1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 */ 28 29/* e1000_hw.c 30 * Shared functions for accessing and configuring the MAC 31 */ 32 33#include "e1000.h" 34 35static s32 e1000_check_downshift(struct e1000_hw *hw); 36static s32 e1000_check_polarity(struct e1000_hw *hw, 37 e1000_rev_polarity *polarity); 38static void e1000_clear_hw_cntrs(struct e1000_hw *hw); 39static void e1000_clear_vfta(struct e1000_hw *hw); 40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, 41 bool link_up); 42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); 43static s32 e1000_detect_gig_phy(struct e1000_hw *hw); 44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); 45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 46 u16 *max_length); 47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); 48static s32 e1000_id_led_init(struct e1000_hw *hw); 49static void e1000_init_rx_addrs(struct e1000_hw *hw); 50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 51 struct e1000_phy_info *phy_info); 52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 53 struct e1000_phy_info *phy_info); 54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); 55static s32 e1000_wait_autoneg(struct e1000_hw *hw); 56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); 57static s32 e1000_set_phy_type(struct e1000_hw *hw); 58static void e1000_phy_init_script(struct e1000_hw *hw); 59static s32 e1000_setup_copper_link(struct e1000_hw *hw); 60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw); 61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw); 62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); 67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 70 u16 words, u16 *data); 71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 72 u16 words, u16 *data); 73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd); 75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); 76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 78 u16 phy_data); 79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 80 u16 *phy_data); 81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 82static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 83static void e1000_release_eeprom(struct e1000_hw *hw); 84static void e1000_standby_eeprom(struct e1000_hw *hw); 85static s32 e1000_set_vco_speed(struct e1000_hw *hw); 86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 87static s32 e1000_set_phy_mode(struct e1000_hw *hw); 88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 89 u16 *data); 90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 91 u16 *data); 92 93/* IGP cable length table */ 94static const 95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { 96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 102 100, 103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 104 110, 110, 105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 106 120, 120 107}; 108 109static DEFINE_SPINLOCK(e1000_eeprom_lock); 110static DEFINE_SPINLOCK(e1000_phy_lock); 111 112/** 113 * e1000_set_phy_type - Set the phy type member in the hw struct. 114 * @hw: Struct containing variables accessed by shared code 115 */ 116static s32 e1000_set_phy_type(struct e1000_hw *hw) 117{ 118 if (hw->mac_type == e1000_undefined) 119 return -E1000_ERR_PHY_TYPE; 120 121 switch (hw->phy_id) { 122 case M88E1000_E_PHY_ID: 123 case M88E1000_I_PHY_ID: 124 case M88E1011_I_PHY_ID: 125 case M88E1111_I_PHY_ID: 126 case M88E1118_E_PHY_ID: 127 hw->phy_type = e1000_phy_m88; 128 break; 129 case IGP01E1000_I_PHY_ID: 130 if (hw->mac_type == e1000_82541 || 131 hw->mac_type == e1000_82541_rev_2 || 132 hw->mac_type == e1000_82547 || 133 hw->mac_type == e1000_82547_rev_2) 134 hw->phy_type = e1000_phy_igp; 135 break; 136 case RTL8211B_PHY_ID: 137 hw->phy_type = e1000_phy_8211; 138 break; 139 case RTL8201N_PHY_ID: 140 hw->phy_type = e1000_phy_8201; 141 break; 142 default: 143 /* Should never have loaded on this device */ 144 hw->phy_type = e1000_phy_undefined; 145 return -E1000_ERR_PHY_TYPE; 146 } 147 148 return E1000_SUCCESS; 149} 150 151/** 152 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY 153 * @hw: Struct containing variables accessed by shared code 154 */ 155static void e1000_phy_init_script(struct e1000_hw *hw) 156{ 157 u32 ret_val; 158 u16 phy_saved_data; 159 160 if (hw->phy_init_script) { 161 msleep(20); 162 163 /* Save off the current value of register 0x2F5B to be restored 164 * at the end of this routine. 165 */ 166 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 167 168 /* Disabled the PHY transmitter */ 169 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 170 msleep(20); 171 172 e1000_write_phy_reg(hw, 0x0000, 0x0140); 173 msleep(5); 174 175 switch (hw->mac_type) { 176 case e1000_82541: 177 case e1000_82547: 178 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 179 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); 180 e1000_write_phy_reg(hw, 0x1F79, 0x0018); 181 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 182 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 183 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 184 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 185 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 186 e1000_write_phy_reg(hw, 0x2010, 0x0008); 187 break; 188 189 case e1000_82541_rev_2: 190 case e1000_82547_rev_2: 191 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 192 break; 193 default: 194 break; 195 } 196 197 e1000_write_phy_reg(hw, 0x0000, 0x3300); 198 msleep(20); 199 200 /* Now enable the transmitter */ 201 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 202 203 if (hw->mac_type == e1000_82547) { 204 u16 fused, fine, coarse; 205 206 /* Move to analog registers page */ 207 e1000_read_phy_reg(hw, 208 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 209 &fused); 210 211 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 212 e1000_read_phy_reg(hw, 213 IGP01E1000_ANALOG_FUSE_STATUS, 214 &fused); 215 216 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 217 coarse = 218 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 219 220 if (coarse > 221 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 222 coarse -= 223 IGP01E1000_ANALOG_FUSE_COARSE_10; 224 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 225 } else if (coarse == 226 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 227 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 228 229 fused = 230 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 231 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 232 (coarse & 233 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 234 235 e1000_write_phy_reg(hw, 236 IGP01E1000_ANALOG_FUSE_CONTROL, 237 fused); 238 e1000_write_phy_reg(hw, 239 IGP01E1000_ANALOG_FUSE_BYPASS, 240 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 241 } 242 } 243 } 244} 245 246/** 247 * e1000_set_mac_type - Set the mac type member in the hw struct. 248 * @hw: Struct containing variables accessed by shared code 249 */ 250s32 e1000_set_mac_type(struct e1000_hw *hw) 251{ 252 switch (hw->device_id) { 253 case E1000_DEV_ID_82542: 254 switch (hw->revision_id) { 255 case E1000_82542_2_0_REV_ID: 256 hw->mac_type = e1000_82542_rev2_0; 257 break; 258 case E1000_82542_2_1_REV_ID: 259 hw->mac_type = e1000_82542_rev2_1; 260 break; 261 default: 262 /* Invalid 82542 revision ID */ 263 return -E1000_ERR_MAC_TYPE; 264 } 265 break; 266 case E1000_DEV_ID_82543GC_FIBER: 267 case E1000_DEV_ID_82543GC_COPPER: 268 hw->mac_type = e1000_82543; 269 break; 270 case E1000_DEV_ID_82544EI_COPPER: 271 case E1000_DEV_ID_82544EI_FIBER: 272 case E1000_DEV_ID_82544GC_COPPER: 273 case E1000_DEV_ID_82544GC_LOM: 274 hw->mac_type = e1000_82544; 275 break; 276 case E1000_DEV_ID_82540EM: 277 case E1000_DEV_ID_82540EM_LOM: 278 case E1000_DEV_ID_82540EP: 279 case E1000_DEV_ID_82540EP_LOM: 280 case E1000_DEV_ID_82540EP_LP: 281 hw->mac_type = e1000_82540; 282 break; 283 case E1000_DEV_ID_82545EM_COPPER: 284 case E1000_DEV_ID_82545EM_FIBER: 285 hw->mac_type = e1000_82545; 286 break; 287 case E1000_DEV_ID_82545GM_COPPER: 288 case E1000_DEV_ID_82545GM_FIBER: 289 case E1000_DEV_ID_82545GM_SERDES: 290 hw->mac_type = e1000_82545_rev_3; 291 break; 292 case E1000_DEV_ID_82546EB_COPPER: 293 case E1000_DEV_ID_82546EB_FIBER: 294 case E1000_DEV_ID_82546EB_QUAD_COPPER: 295 hw->mac_type = e1000_82546; 296 break; 297 case E1000_DEV_ID_82546GB_COPPER: 298 case E1000_DEV_ID_82546GB_FIBER: 299 case E1000_DEV_ID_82546GB_SERDES: 300 case E1000_DEV_ID_82546GB_PCIE: 301 case E1000_DEV_ID_82546GB_QUAD_COPPER: 302 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 303 hw->mac_type = e1000_82546_rev_3; 304 break; 305 case E1000_DEV_ID_82541EI: 306 case E1000_DEV_ID_82541EI_MOBILE: 307 case E1000_DEV_ID_82541ER_LOM: 308 hw->mac_type = e1000_82541; 309 break; 310 case E1000_DEV_ID_82541ER: 311 case E1000_DEV_ID_82541GI: 312 case E1000_DEV_ID_82541GI_LF: 313 case E1000_DEV_ID_82541GI_MOBILE: 314 hw->mac_type = e1000_82541_rev_2; 315 break; 316 case E1000_DEV_ID_82547EI: 317 case E1000_DEV_ID_82547EI_MOBILE: 318 hw->mac_type = e1000_82547; 319 break; 320 case E1000_DEV_ID_82547GI: 321 hw->mac_type = e1000_82547_rev_2; 322 break; 323 case E1000_DEV_ID_INTEL_CE4100_GBE: 324 hw->mac_type = e1000_ce4100; 325 break; 326 default: 327 /* Should never have loaded on this device */ 328 return -E1000_ERR_MAC_TYPE; 329 } 330 331 switch (hw->mac_type) { 332 case e1000_82541: 333 case e1000_82547: 334 case e1000_82541_rev_2: 335 case e1000_82547_rev_2: 336 hw->asf_firmware_present = true; 337 break; 338 default: 339 break; 340 } 341 342 /* The 82543 chip does not count tx_carrier_errors properly in 343 * FD mode 344 */ 345 if (hw->mac_type == e1000_82543) 346 hw->bad_tx_carr_stats_fd = true; 347 348 if (hw->mac_type > e1000_82544) 349 hw->has_smbus = true; 350 351 return E1000_SUCCESS; 352} 353 354/** 355 * e1000_set_media_type - Set media type and TBI compatibility. 356 * @hw: Struct containing variables accessed by shared code 357 */ 358void e1000_set_media_type(struct e1000_hw *hw) 359{ 360 u32 status; 361 362 if (hw->mac_type != e1000_82543) { 363 /* tbi_compatibility is only valid on 82543 */ 364 hw->tbi_compatibility_en = false; 365 } 366 367 switch (hw->device_id) { 368 case E1000_DEV_ID_82545GM_SERDES: 369 case E1000_DEV_ID_82546GB_SERDES: 370 hw->media_type = e1000_media_type_internal_serdes; 371 break; 372 default: 373 switch (hw->mac_type) { 374 case e1000_82542_rev2_0: 375 case e1000_82542_rev2_1: 376 hw->media_type = e1000_media_type_fiber; 377 break; 378 case e1000_ce4100: 379 hw->media_type = e1000_media_type_copper; 380 break; 381 default: 382 status = er32(STATUS); 383 if (status & E1000_STATUS_TBIMODE) { 384 hw->media_type = e1000_media_type_fiber; 385 /* tbi_compatibility not valid on fiber */ 386 hw->tbi_compatibility_en = false; 387 } else { 388 hw->media_type = e1000_media_type_copper; 389 } 390 break; 391 } 392 } 393} 394 395/** 396 * e1000_reset_hw - reset the hardware completely 397 * @hw: Struct containing variables accessed by shared code 398 * 399 * Reset the transmit and receive units; mask and clear all interrupts. 400 */ 401s32 e1000_reset_hw(struct e1000_hw *hw) 402{ 403 u32 ctrl; 404 u32 ctrl_ext; 405 u32 icr; 406 u32 manc; 407 u32 led_ctrl; 408 s32 ret_val; 409 410 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 411 if (hw->mac_type == e1000_82542_rev2_0) { 412 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 413 e1000_pci_clear_mwi(hw); 414 } 415 416 /* Clear interrupt mask to stop board from generating interrupts */ 417 e_dbg("Masking off all interrupts\n"); 418 ew32(IMC, 0xffffffff); 419 420 /* Disable the Transmit and Receive units. Then delay to allow 421 * any pending transactions to complete before we hit the MAC with 422 * the global reset. 423 */ 424 ew32(RCTL, 0); 425 ew32(TCTL, E1000_TCTL_PSP); 426 E1000_WRITE_FLUSH(); 427 428 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 429 hw->tbi_compatibility_on = false; 430 431 /* Delay to allow any outstanding PCI transactions to complete before 432 * resetting the device 433 */ 434 msleep(10); 435 436 ctrl = er32(CTRL); 437 438 /* Must reset the PHY before resetting the MAC */ 439 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 440 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 441 E1000_WRITE_FLUSH(); 442 msleep(5); 443 } 444 445 /* Issue a global reset to the MAC. This will reset the chip's 446 * transmit, receive, DMA, and link units. It will not effect 447 * the current PCI configuration. The global reset bit is self- 448 * clearing, and should clear within a microsecond. 449 */ 450 e_dbg("Issuing a global reset to MAC\n"); 451 452 switch (hw->mac_type) { 453 case e1000_82544: 454 case e1000_82540: 455 case e1000_82545: 456 case e1000_82546: 457 case e1000_82541: 458 case e1000_82541_rev_2: 459 /* These controllers can't ack the 64-bit write when issuing the 460 * reset, so use IO-mapping as a workaround to issue the reset 461 */ 462 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 463 break; 464 case e1000_82545_rev_3: 465 case e1000_82546_rev_3: 466 /* Reset is performed on a shadow of the control register */ 467 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 468 break; 469 case e1000_ce4100: 470 default: 471 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 472 break; 473 } 474 475 /* After MAC reset, force reload of EEPROM to restore power-on settings 476 * to device. Later controllers reload the EEPROM automatically, so 477 * just wait for reload to complete. 478 */ 479 switch (hw->mac_type) { 480 case e1000_82542_rev2_0: 481 case e1000_82542_rev2_1: 482 case e1000_82543: 483 case e1000_82544: 484 /* Wait for reset to complete */ 485 udelay(10); 486 ctrl_ext = er32(CTRL_EXT); 487 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 488 ew32(CTRL_EXT, ctrl_ext); 489 E1000_WRITE_FLUSH(); 490 /* Wait for EEPROM reload */ 491 msleep(2); 492 break; 493 case e1000_82541: 494 case e1000_82541_rev_2: 495 case e1000_82547: 496 case e1000_82547_rev_2: 497 /* Wait for EEPROM reload */ 498 msleep(20); 499 break; 500 default: 501 /* Auto read done will delay 5ms or poll based on mac type */ 502 ret_val = e1000_get_auto_rd_done(hw); 503 if (ret_val) 504 return ret_val; 505 break; 506 } 507 508 /* Disable HW ARPs on ASF enabled adapters */ 509 if (hw->mac_type >= e1000_82540) { 510 manc = er32(MANC); 511 manc &= ~(E1000_MANC_ARP_EN); 512 ew32(MANC, manc); 513 } 514 515 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 516 e1000_phy_init_script(hw); 517 518 /* Configure activity LED after PHY reset */ 519 led_ctrl = er32(LEDCTL); 520 led_ctrl &= IGP_ACTIVITY_LED_MASK; 521 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 522 ew32(LEDCTL, led_ctrl); 523 } 524 525 /* Clear interrupt mask to stop board from generating interrupts */ 526 e_dbg("Masking off all interrupts\n"); 527 ew32(IMC, 0xffffffff); 528 529 /* Clear any pending interrupt events. */ 530 icr = er32(ICR); 531 532 /* If MWI was previously enabled, reenable it. */ 533 if (hw->mac_type == e1000_82542_rev2_0) { 534 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 535 e1000_pci_set_mwi(hw); 536 } 537 538 return E1000_SUCCESS; 539} 540 541/** 542 * e1000_init_hw - Performs basic configuration of the adapter. 543 * @hw: Struct containing variables accessed by shared code 544 * 545 * Assumes that the controller has previously been reset and is in a 546 * post-reset uninitialized state. Initializes the receive address registers, 547 * multicast table, and VLAN filter table. Calls routines to setup link 548 * configuration and flow control settings. Clears all on-chip counters. Leaves 549 * the transmit and receive units disabled and uninitialized. 550 */ 551s32 e1000_init_hw(struct e1000_hw *hw) 552{ 553 u32 ctrl; 554 u32 i; 555 s32 ret_val; 556 u32 mta_size; 557 u32 ctrl_ext; 558 559 /* Initialize Identification LED */ 560 ret_val = e1000_id_led_init(hw); 561 if (ret_val) { 562 e_dbg("Error Initializing Identification LED\n"); 563 return ret_val; 564 } 565 566 /* Set the media type and TBI compatibility */ 567 e1000_set_media_type(hw); 568 569 /* Disabling VLAN filtering. */ 570 e_dbg("Initializing the IEEE VLAN\n"); 571 if (hw->mac_type < e1000_82545_rev_3) 572 ew32(VET, 0); 573 e1000_clear_vfta(hw); 574 575 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 576 if (hw->mac_type == e1000_82542_rev2_0) { 577 e_dbg("Disabling MWI on 82542 rev 2.0\n"); 578 e1000_pci_clear_mwi(hw); 579 ew32(RCTL, E1000_RCTL_RST); 580 E1000_WRITE_FLUSH(); 581 msleep(5); 582 } 583 584 /* Setup the receive address. This involves initializing all of the 585 * Receive Address Registers (RARs 0 - 15). 586 */ 587 e1000_init_rx_addrs(hw); 588 589 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 590 if (hw->mac_type == e1000_82542_rev2_0) { 591 ew32(RCTL, 0); 592 E1000_WRITE_FLUSH(); 593 msleep(1); 594 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 595 e1000_pci_set_mwi(hw); 596 } 597 598 /* Zero out the Multicast HASH table */ 599 e_dbg("Zeroing the MTA\n"); 600 mta_size = E1000_MC_TBL_SIZE; 601 for (i = 0; i < mta_size; i++) { 602 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 603 /* use write flush to prevent Memory Write Block (MWB) from 604 * occurring when accessing our register space 605 */ 606 E1000_WRITE_FLUSH(); 607 } 608 609 /* Set the PCI priority bit correctly in the CTRL register. This 610 * determines if the adapter gives priority to receives, or if it 611 * gives equal priority to transmits and receives. Valid only on 612 * 82542 and 82543 silicon. 613 */ 614 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 615 ctrl = er32(CTRL); 616 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 617 } 618 619 switch (hw->mac_type) { 620 case e1000_82545_rev_3: 621 case e1000_82546_rev_3: 622 break; 623 default: 624 /* Workaround for PCI-X problem when BIOS sets MMRBC 625 * incorrectly. 626 */ 627 if (hw->bus_type == e1000_bus_type_pcix 628 && e1000_pcix_get_mmrbc(hw) > 2048) 629 e1000_pcix_set_mmrbc(hw, 2048); 630 break; 631 } 632 633 /* Call a subroutine to configure the link and setup flow control. */ 634 ret_val = e1000_setup_link(hw); 635 636 /* Set the transmit descriptor write-back policy */ 637 if (hw->mac_type > e1000_82544) { 638 ctrl = er32(TXDCTL); 639 ctrl = 640 (ctrl & ~E1000_TXDCTL_WTHRESH) | 641 E1000_TXDCTL_FULL_TX_DESC_WB; 642 ew32(TXDCTL, ctrl); 643 } 644 645 /* Clear all of the statistics registers (clear on read). It is 646 * important that we do this after we have tried to establish link 647 * because the symbol error count will increment wildly if there 648 * is no link. 649 */ 650 e1000_clear_hw_cntrs(hw); 651 652 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 653 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 654 ctrl_ext = er32(CTRL_EXT); 655 /* Relaxed ordering must be disabled to avoid a parity 656 * error crash in a PCI slot. 657 */ 658 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 659 ew32(CTRL_EXT, ctrl_ext); 660 } 661 662 return ret_val; 663} 664 665/** 666 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. 667 * @hw: Struct containing variables accessed by shared code. 668 */ 669static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 670{ 671 u16 eeprom_data; 672 s32 ret_val; 673 674 if (hw->media_type != e1000_media_type_internal_serdes) 675 return E1000_SUCCESS; 676 677 switch (hw->mac_type) { 678 case e1000_82545_rev_3: 679 case e1000_82546_rev_3: 680 break; 681 default: 682 return E1000_SUCCESS; 683 } 684 685 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, 686 &eeprom_data); 687 if (ret_val) { 688 return ret_val; 689 } 690 691 if (eeprom_data != EEPROM_RESERVED_WORD) { 692 /* Adjust SERDES output amplitude only. */ 693 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 694 ret_val = 695 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 696 if (ret_val) 697 return ret_val; 698 } 699 700 return E1000_SUCCESS; 701} 702 703/** 704 * e1000_setup_link - Configures flow control and link settings. 705 * @hw: Struct containing variables accessed by shared code 706 * 707 * Determines which flow control settings to use. Calls the appropriate media- 708 * specific link configuration function. Configures the flow control settings. 709 * Assuming the adapter has a valid link partner, a valid link should be 710 * established. Assumes the hardware has previously been reset and the 711 * transmitter and receiver are not enabled. 712 */ 713s32 e1000_setup_link(struct e1000_hw *hw) 714{ 715 u32 ctrl_ext; 716 s32 ret_val; 717 u16 eeprom_data; 718 719 /* Read and store word 0x0F of the EEPROM. This word contains bits 720 * that determine the hardware's default PAUSE (flow control) mode, 721 * a bit that determines whether the HW defaults to enabling or 722 * disabling auto-negotiation, and the direction of the 723 * SW defined pins. If there is no SW over-ride of the flow 724 * control setting, then the variable hw->fc will 725 * be initialized based on a value in the EEPROM. 726 */ 727 if (hw->fc == E1000_FC_DEFAULT) { 728 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 729 1, &eeprom_data); 730 if (ret_val) { 731 e_dbg("EEPROM Read Error\n"); 732 return -E1000_ERR_EEPROM; 733 } 734 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 735 hw->fc = E1000_FC_NONE; 736 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 737 EEPROM_WORD0F_ASM_DIR) 738 hw->fc = E1000_FC_TX_PAUSE; 739 else 740 hw->fc = E1000_FC_FULL; 741 } 742 743 /* We want to save off the original Flow Control configuration just 744 * in case we get disconnected and then reconnected into a different 745 * hub or switch with different Flow Control capabilities. 746 */ 747 if (hw->mac_type == e1000_82542_rev2_0) 748 hw->fc &= (~E1000_FC_TX_PAUSE); 749 750 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 751 hw->fc &= (~E1000_FC_RX_PAUSE); 752 753 hw->original_fc = hw->fc; 754 755 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc); 756 757 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 758 * polarity value for the SW controlled pins, and setup the 759 * Extended Device Control reg with that info. 760 * This is needed because one of the SW controlled pins is used for 761 * signal detection. So this should be done before e1000_setup_pcs_link() 762 * or e1000_phy_setup() is called. 763 */ 764 if (hw->mac_type == e1000_82543) { 765 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 766 1, &eeprom_data); 767 if (ret_val) { 768 e_dbg("EEPROM Read Error\n"); 769 return -E1000_ERR_EEPROM; 770 } 771 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 772 SWDPIO__EXT_SHIFT); 773 ew32(CTRL_EXT, ctrl_ext); 774 } 775 776 /* Call the necessary subroutine to configure the link. */ 777 ret_val = (hw->media_type == e1000_media_type_copper) ? 778 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); 779 780 /* Initialize the flow control address, type, and PAUSE timer 781 * registers to their default values. This is done even if flow 782 * control is disabled, because it does not hurt anything to 783 * initialize these registers. 784 */ 785 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 786 787 ew32(FCT, FLOW_CONTROL_TYPE); 788 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 789 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 790 791 ew32(FCTTV, hw->fc_pause_time); 792 793 /* Set the flow control receive threshold registers. Normally, 794 * these registers will be set to a default threshold that may be 795 * adjusted later by the driver's runtime code. However, if the 796 * ability to transmit pause frames in not enabled, then these 797 * registers will be set to 0. 798 */ 799 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 800 ew32(FCRTL, 0); 801 ew32(FCRTH, 0); 802 } else { 803 /* We need to set up the Receive Threshold high and low water 804 * marks as well as (optionally) enabling the transmission of 805 * XON frames. 806 */ 807 if (hw->fc_send_xon) { 808 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 809 ew32(FCRTH, hw->fc_high_water); 810 } else { 811 ew32(FCRTL, hw->fc_low_water); 812 ew32(FCRTH, hw->fc_high_water); 813 } 814 } 815 return ret_val; 816} 817 818/** 819 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link 820 * @hw: Struct containing variables accessed by shared code 821 * 822 * Manipulates Physical Coding Sublayer functions in order to configure 823 * link. Assumes the hardware has been previously reset and the transmitter 824 * and receiver are not enabled. 825 */ 826static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 827{ 828 u32 ctrl; 829 u32 status; 830 u32 txcw = 0; 831 u32 i; 832 u32 signal = 0; 833 s32 ret_val; 834 835 /* On adapters with a MAC newer than 82544, SWDP 1 will be 836 * set when the optics detect a signal. On older adapters, it will be 837 * cleared when there is a signal. This applies to fiber media only. 838 * If we're on serdes media, adjust the output amplitude to value 839 * set in the EEPROM. 840 */ 841 ctrl = er32(CTRL); 842 if (hw->media_type == e1000_media_type_fiber) 843 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 844 845 ret_val = e1000_adjust_serdes_amplitude(hw); 846 if (ret_val) 847 return ret_val; 848 849 /* Take the link out of reset */ 850 ctrl &= ~(E1000_CTRL_LRST); 851 852 /* Adjust VCO speed to improve BER performance */ 853 ret_val = e1000_set_vco_speed(hw); 854 if (ret_val) 855 return ret_val; 856 857 e1000_config_collision_dist(hw); 858 859 /* Check for a software override of the flow control settings, and setup 860 * the device accordingly. If auto-negotiation is enabled, then 861 * software will have to set the "PAUSE" bits to the correct value in 862 * the Tranmsit Config Word Register (TXCW) and re-start 863 * auto-negotiation. However, if auto-negotiation is disabled, then 864 * software will have to manually configure the two flow control enable 865 * bits in the CTRL register. 866 * 867 * The possible values of the "fc" parameter are: 868 * 0: Flow control is completely disabled 869 * 1: Rx flow control is enabled (we can receive pause frames, but 870 * not send pause frames). 871 * 2: Tx flow control is enabled (we can send pause frames but we do 872 * not support receiving pause frames). 873 * 3: Both Rx and TX flow control (symmetric) are enabled. 874 */ 875 switch (hw->fc) { 876 case E1000_FC_NONE: 877 /* Flow ctrl is completely disabled by a software over-ride */ 878 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 879 break; 880 case E1000_FC_RX_PAUSE: 881 /* Rx Flow control is enabled and Tx Flow control is disabled by 882 * a software over-ride. Since there really isn't a way to 883 * advertise that we are capable of Rx Pause ONLY, we will 884 * advertise that we support both symmetric and asymmetric Rx 885 * PAUSE. Later, we will disable the adapter's ability to send 886 * PAUSE frames. 887 */ 888 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 889 break; 890 case E1000_FC_TX_PAUSE: 891 /* Tx Flow control is enabled, and Rx Flow control is disabled, 892 * by a software over-ride. 893 */ 894 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 895 break; 896 case E1000_FC_FULL: 897 /* Flow control (both Rx and Tx) is enabled by a software 898 * over-ride. 899 */ 900 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 901 break; 902 default: 903 e_dbg("Flow control param set incorrectly\n"); 904 return -E1000_ERR_CONFIG; 905 } 906 907 /* Since auto-negotiation is enabled, take the link out of reset (the 908 * link will be in reset, because we previously reset the chip). This 909 * will restart auto-negotiation. If auto-negotiation is successful 910 * then the link-up status bit will be set and the flow control enable 911 * bits (RFCE and TFCE) will be set according to their negotiated value. 912 */ 913 e_dbg("Auto-negotiation enabled\n"); 914 915 ew32(TXCW, txcw); 916 ew32(CTRL, ctrl); 917 E1000_WRITE_FLUSH(); 918 919 hw->txcw = txcw; 920 msleep(1); 921 922 /* If we have a signal (the cable is plugged in) then poll for a 923 * "Link-Up" indication in the Device Status Register. Time-out if a 924 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should 925 * complete in less than 500 milliseconds even if the other end is doing 926 * it in SW). For internal serdes, we just assume a signal is present, 927 * then poll. 928 */ 929 if (hw->media_type == e1000_media_type_internal_serdes || 930 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 931 e_dbg("Looking for Link\n"); 932 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 933 msleep(10); 934 status = er32(STATUS); 935 if (status & E1000_STATUS_LU) 936 break; 937 } 938 if (i == (LINK_UP_TIMEOUT / 10)) { 939 e_dbg("Never got a valid link from auto-neg!!!\n"); 940 hw->autoneg_failed = 1; 941 /* AutoNeg failed to achieve a link, so we'll call 942 * e1000_check_for_link. This routine will force the 943 * link up if we detect a signal. This will allow us to 944 * communicate with non-autonegotiating link partners. 945 */ 946 ret_val = e1000_check_for_link(hw); 947 if (ret_val) { 948 e_dbg("Error while checking for link\n"); 949 return ret_val; 950 } 951 hw->autoneg_failed = 0; 952 } else { 953 hw->autoneg_failed = 0; 954 e_dbg("Valid Link Found\n"); 955 } 956 } else { 957 e_dbg("No Signal Detected\n"); 958 } 959 return E1000_SUCCESS; 960} 961 962/** 963 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series. 964 * @hw: Struct containing variables accessed by shared code 965 * 966 * Commits changes to PHY configuration by calling e1000_phy_reset(). 967 */ 968static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw) 969{ 970 s32 ret_val; 971 972 /* SW reset the PHY so all changes take effect */ 973 ret_val = e1000_phy_reset(hw); 974 if (ret_val) { 975 e_dbg("Error Resetting the PHY\n"); 976 return ret_val; 977 } 978 979 return E1000_SUCCESS; 980} 981 982static s32 gbe_dhg_phy_setup(struct e1000_hw *hw) 983{ 984 s32 ret_val; 985 u32 ctrl_aux; 986 987 switch (hw->phy_type) { 988 case e1000_phy_8211: 989 ret_val = e1000_copper_link_rtl_setup(hw); 990 if (ret_val) { 991 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 992 return ret_val; 993 } 994 break; 995 case e1000_phy_8201: 996 /* Set RMII mode */ 997 ctrl_aux = er32(CTL_AUX); 998 ctrl_aux |= E1000_CTL_AUX_RMII; 999 ew32(CTL_AUX, ctrl_aux); 1000 E1000_WRITE_FLUSH(); 1001 1002 /* Disable the J/K bits required for receive */ 1003 ctrl_aux = er32(CTL_AUX); 1004 ctrl_aux |= 0x4; 1005 ctrl_aux &= ~0x2; 1006 ew32(CTL_AUX, ctrl_aux); 1007 E1000_WRITE_FLUSH(); 1008 ret_val = e1000_copper_link_rtl_setup(hw); 1009 1010 if (ret_val) { 1011 e_dbg("e1000_copper_link_rtl_setup failed!\n"); 1012 return ret_val; 1013 } 1014 break; 1015 default: 1016 e_dbg("Error Resetting the PHY\n"); 1017 return E1000_ERR_PHY_TYPE; 1018 } 1019 1020 return E1000_SUCCESS; 1021} 1022 1023/** 1024 * e1000_copper_link_preconfig - early configuration for copper 1025 * @hw: Struct containing variables accessed by shared code 1026 * 1027 * Make sure we have a valid PHY and change PHY mode before link setup. 1028 */ 1029static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 1030{ 1031 u32 ctrl; 1032 s32 ret_val; 1033 u16 phy_data; 1034 1035 ctrl = er32(CTRL); 1036 /* With 82543, we need to force speed and duplex on the MAC equal to 1037 * what the PHY speed and duplex configuration is. In addition, we need 1038 * to perform a hardware reset on the PHY to take it out of reset. 1039 */ 1040 if (hw->mac_type > e1000_82543) { 1041 ctrl |= E1000_CTRL_SLU; 1042 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1043 ew32(CTRL, ctrl); 1044 } else { 1045 ctrl |= 1046 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1047 ew32(CTRL, ctrl); 1048 ret_val = e1000_phy_hw_reset(hw); 1049 if (ret_val) 1050 return ret_val; 1051 } 1052 1053 /* Make sure we have a valid PHY */ 1054 ret_val = e1000_detect_gig_phy(hw); 1055 if (ret_val) { 1056 e_dbg("Error, did not detect valid phy.\n"); 1057 return ret_val; 1058 } 1059 e_dbg("Phy ID = %x\n", hw->phy_id); 1060 1061 /* Set PHY to class A mode (if necessary) */ 1062 ret_val = e1000_set_phy_mode(hw); 1063 if (ret_val) 1064 return ret_val; 1065 1066 if ((hw->mac_type == e1000_82545_rev_3) || 1067 (hw->mac_type == e1000_82546_rev_3)) { 1068 ret_val = 1069 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1070 phy_data |= 0x00000008; 1071 ret_val = 1072 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1073 } 1074 1075 if (hw->mac_type <= e1000_82543 || 1076 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1077 hw->mac_type == e1000_82541_rev_2 1078 || hw->mac_type == e1000_82547_rev_2) 1079 hw->phy_reset_disable = false; 1080 1081 return E1000_SUCCESS; 1082} 1083 1084/** 1085 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. 1086 * @hw: Struct containing variables accessed by shared code 1087 */ 1088static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 1089{ 1090 u32 led_ctrl; 1091 s32 ret_val; 1092 u16 phy_data; 1093 1094 if (hw->phy_reset_disable) 1095 return E1000_SUCCESS; 1096 1097 ret_val = e1000_phy_reset(hw); 1098 if (ret_val) { 1099 e_dbg("Error Resetting the PHY\n"); 1100 return ret_val; 1101 } 1102 1103 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1104 msleep(15); 1105 /* Configure activity LED after PHY reset */ 1106 led_ctrl = er32(LEDCTL); 1107 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1108 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1109 ew32(LEDCTL, led_ctrl); 1110 1111 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1112 if (hw->phy_type == e1000_phy_igp) { 1113 /* disable lplu d3 during driver init */ 1114 ret_val = e1000_set_d3_lplu_state(hw, false); 1115 if (ret_val) { 1116 e_dbg("Error Disabling LPLU D3\n"); 1117 return ret_val; 1118 } 1119 } 1120 1121 /* Configure mdi-mdix settings */ 1122 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1123 if (ret_val) 1124 return ret_val; 1125 1126 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1127 hw->dsp_config_state = e1000_dsp_config_disabled; 1128 /* Force MDI for earlier revs of the IGP PHY */ 1129 phy_data &= 1130 ~(IGP01E1000_PSCR_AUTO_MDIX | 1131 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1132 hw->mdix = 1; 1133 1134 } else { 1135 hw->dsp_config_state = e1000_dsp_config_enabled; 1136 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1137 1138 switch (hw->mdix) { 1139 case 1: 1140 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1141 break; 1142 case 2: 1143 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1144 break; 1145 case 0: 1146 default: 1147 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1148 break; 1149 } 1150 } 1151 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1152 if (ret_val) 1153 return ret_val; 1154 1155 /* set auto-master slave resolution settings */ 1156 if (hw->autoneg) { 1157 e1000_ms_type phy_ms_setting = hw->master_slave; 1158 1159 if (hw->ffe_config_state == e1000_ffe_config_active) 1160 hw->ffe_config_state = e1000_ffe_config_enabled; 1161 1162 if (hw->dsp_config_state == e1000_dsp_config_activated) 1163 hw->dsp_config_state = e1000_dsp_config_enabled; 1164 1165 /* when autonegotiation advertisement is only 1000Mbps then we 1166 * should disable SmartSpeed and enable Auto MasterSlave 1167 * resolution as hardware default. 1168 */ 1169 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1170 /* Disable SmartSpeed */ 1171 ret_val = 1172 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1173 &phy_data); 1174 if (ret_val) 1175 return ret_val; 1176 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1177 ret_val = 1178 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1179 phy_data); 1180 if (ret_val) 1181 return ret_val; 1182 /* Set auto Master/Slave resolution process */ 1183 ret_val = 1184 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1185 if (ret_val) 1186 return ret_val; 1187 phy_data &= ~CR_1000T_MS_ENABLE; 1188 ret_val = 1189 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1190 if (ret_val) 1191 return ret_val; 1192 } 1193 1194 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1195 if (ret_val) 1196 return ret_val; 1197 1198 /* load defaults for future use */ 1199 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1200 ((phy_data & CR_1000T_MS_VALUE) ? 1201 e1000_ms_force_master : 1202 e1000_ms_force_slave) : e1000_ms_auto; 1203 1204 switch (phy_ms_setting) { 1205 case e1000_ms_force_master: 1206 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1207 break; 1208 case e1000_ms_force_slave: 1209 phy_data |= CR_1000T_MS_ENABLE; 1210 phy_data &= ~(CR_1000T_MS_VALUE); 1211 break; 1212 case e1000_ms_auto: 1213 phy_data &= ~CR_1000T_MS_ENABLE; 1214 default: 1215 break; 1216 } 1217 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1218 if (ret_val) 1219 return ret_val; 1220 } 1221 1222 return E1000_SUCCESS; 1223} 1224 1225/** 1226 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. 1227 * @hw: Struct containing variables accessed by shared code 1228 */ 1229static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1230{ 1231 s32 ret_val; 1232 u16 phy_data; 1233 1234 if (hw->phy_reset_disable) 1235 return E1000_SUCCESS; 1236 1237 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1238 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1239 if (ret_val) 1240 return ret_val; 1241 1242 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1243 1244 /* Options: 1245 * MDI/MDI-X = 0 (default) 1246 * 0 - Auto for all speeds 1247 * 1 - MDI mode 1248 * 2 - MDI-X mode 1249 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1250 */ 1251 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1252 1253 switch (hw->mdix) { 1254 case 1: 1255 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1256 break; 1257 case 2: 1258 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1259 break; 1260 case 3: 1261 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1262 break; 1263 case 0: 1264 default: 1265 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1266 break; 1267 } 1268 1269 /* Options: 1270 * disable_polarity_correction = 0 (default) 1271 * Automatic Correction for Reversed Cable Polarity 1272 * 0 - Disabled 1273 * 1 - Enabled 1274 */ 1275 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1276 if (hw->disable_polarity_correction == 1) 1277 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1278 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1279 if (ret_val) 1280 return ret_val; 1281 1282 if (hw->phy_revision < M88E1011_I_REV_4) { 1283 /* Force TX_CLK in the Extended PHY Specific Control Register 1284 * to 25MHz clock. 1285 */ 1286 ret_val = 1287 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1288 &phy_data); 1289 if (ret_val) 1290 return ret_val; 1291 1292 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1293 1294 if ((hw->phy_revision == E1000_REVISION_2) && 1295 (hw->phy_id == M88E1111_I_PHY_ID)) { 1296 /* Vidalia Phy, set the downshift counter to 5x */ 1297 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1298 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1299 ret_val = e1000_write_phy_reg(hw, 1300 M88E1000_EXT_PHY_SPEC_CTRL, 1301 phy_data); 1302 if (ret_val) 1303 return ret_val; 1304 } else { 1305 /* Configure Master and Slave downshift values */ 1306 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1307 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1308 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1309 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1310 ret_val = e1000_write_phy_reg(hw, 1311 M88E1000_EXT_PHY_SPEC_CTRL, 1312 phy_data); 1313 if (ret_val) 1314 return ret_val; 1315 } 1316 } 1317 1318 /* SW Reset the PHY so all changes take effect */ 1319 ret_val = e1000_phy_reset(hw); 1320 if (ret_val) { 1321 e_dbg("Error Resetting the PHY\n"); 1322 return ret_val; 1323 } 1324 1325 return E1000_SUCCESS; 1326} 1327 1328/** 1329 * e1000_copper_link_autoneg - setup auto-neg 1330 * @hw: Struct containing variables accessed by shared code 1331 * 1332 * Setup auto-negotiation and flow control advertisements, 1333 * and then perform auto-negotiation. 1334 */ 1335static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1336{ 1337 s32 ret_val; 1338 u16 phy_data; 1339 1340 /* Perform some bounds checking on the hw->autoneg_advertised 1341 * parameter. If this variable is zero, then set it to the default. 1342 */ 1343 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1344 1345 /* If autoneg_advertised is zero, we assume it was not defaulted 1346 * by the calling code so we set to advertise full capability. 1347 */ 1348 if (hw->autoneg_advertised == 0) 1349 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1350 1351 /* IFE/RTL8201N PHY only supports 10/100 */ 1352 if (hw->phy_type == e1000_phy_8201) 1353 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 1354 1355 e_dbg("Reconfiguring auto-neg advertisement params\n"); 1356 ret_val = e1000_phy_setup_autoneg(hw); 1357 if (ret_val) { 1358 e_dbg("Error Setting up Auto-Negotiation\n"); 1359 return ret_val; 1360 } 1361 e_dbg("Restarting Auto-Neg\n"); 1362 1363 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1364 * the Auto Neg Restart bit in the PHY control register. 1365 */ 1366 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1367 if (ret_val) 1368 return ret_val; 1369 1370 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1371 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1372 if (ret_val) 1373 return ret_val; 1374 1375 /* Does the user want to wait for Auto-Neg to complete here, or 1376 * check at a later time (for example, callback routine). 1377 */ 1378 if (hw->wait_autoneg_complete) { 1379 ret_val = e1000_wait_autoneg(hw); 1380 if (ret_val) { 1381 e_dbg 1382 ("Error while waiting for autoneg to complete\n"); 1383 return ret_val; 1384 } 1385 } 1386 1387 hw->get_link_status = true; 1388 1389 return E1000_SUCCESS; 1390} 1391 1392/** 1393 * e1000_copper_link_postconfig - post link setup 1394 * @hw: Struct containing variables accessed by shared code 1395 * 1396 * Config the MAC and the PHY after link is up. 1397 * 1) Set up the MAC to the current PHY speed/duplex 1398 * if we are on 82543. If we 1399 * are on newer silicon, we only need to configure 1400 * collision distance in the Transmit Control Register. 1401 * 2) Set up flow control on the MAC to that established with 1402 * the link partner. 1403 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1404 */ 1405static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1406{ 1407 s32 ret_val; 1408 1409 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) { 1410 e1000_config_collision_dist(hw); 1411 } else { 1412 ret_val = e1000_config_mac_to_phy(hw); 1413 if (ret_val) { 1414 e_dbg("Error configuring MAC to PHY settings\n"); 1415 return ret_val; 1416 } 1417 } 1418 ret_val = e1000_config_fc_after_link_up(hw); 1419 if (ret_val) { 1420 e_dbg("Error Configuring Flow Control\n"); 1421 return ret_val; 1422 } 1423 1424 /* Config DSP to improve Giga link quality */ 1425 if (hw->phy_type == e1000_phy_igp) { 1426 ret_val = e1000_config_dsp_after_link_change(hw, true); 1427 if (ret_val) { 1428 e_dbg("Error Configuring DSP after link up\n"); 1429 return ret_val; 1430 } 1431 } 1432 1433 return E1000_SUCCESS; 1434} 1435 1436/** 1437 * e1000_setup_copper_link - phy/speed/duplex setting 1438 * @hw: Struct containing variables accessed by shared code 1439 * 1440 * Detects which PHY is present and sets up the speed and duplex 1441 */ 1442static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1443{ 1444 s32 ret_val; 1445 u16 i; 1446 u16 phy_data; 1447 1448 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1449 ret_val = e1000_copper_link_preconfig(hw); 1450 if (ret_val) 1451 return ret_val; 1452 1453 if (hw->phy_type == e1000_phy_igp) { 1454 ret_val = e1000_copper_link_igp_setup(hw); 1455 if (ret_val) 1456 return ret_val; 1457 } else if (hw->phy_type == e1000_phy_m88) { 1458 ret_val = e1000_copper_link_mgp_setup(hw); 1459 if (ret_val) 1460 return ret_val; 1461 } else { 1462 ret_val = gbe_dhg_phy_setup(hw); 1463 if (ret_val) { 1464 e_dbg("gbe_dhg_phy_setup failed!\n"); 1465 return ret_val; 1466 } 1467 } 1468 1469 if (hw->autoneg) { 1470 /* Setup autoneg and flow control advertisement 1471 * and perform autonegotiation 1472 */ 1473 ret_val = e1000_copper_link_autoneg(hw); 1474 if (ret_val) 1475 return ret_val; 1476 } else { 1477 /* PHY will be set to 10H, 10F, 100H,or 100F 1478 * depending on value from forced_speed_duplex. 1479 */ 1480 e_dbg("Forcing speed and duplex\n"); 1481 ret_val = e1000_phy_force_speed_duplex(hw); 1482 if (ret_val) { 1483 e_dbg("Error Forcing Speed and Duplex\n"); 1484 return ret_val; 1485 } 1486 } 1487 1488 /* Check link status. Wait up to 100 microseconds for link to become 1489 * valid. 1490 */ 1491 for (i = 0; i < 10; i++) { 1492 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1493 if (ret_val) 1494 return ret_val; 1495 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1496 if (ret_val) 1497 return ret_val; 1498 1499 if (phy_data & MII_SR_LINK_STATUS) { 1500 /* Config the MAC and PHY after link is up */ 1501 ret_val = e1000_copper_link_postconfig(hw); 1502 if (ret_val) 1503 return ret_val; 1504 1505 e_dbg("Valid link established!!!\n"); 1506 return E1000_SUCCESS; 1507 } 1508 udelay(10); 1509 } 1510 1511 e_dbg("Unable to establish link!!!\n"); 1512 return E1000_SUCCESS; 1513} 1514 1515/** 1516 * e1000_phy_setup_autoneg - phy settings 1517 * @hw: Struct containing variables accessed by shared code 1518 * 1519 * Configures PHY autoneg and flow control advertisement settings 1520 */ 1521s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1522{ 1523 s32 ret_val; 1524 u16 mii_autoneg_adv_reg; 1525 u16 mii_1000t_ctrl_reg; 1526 1527 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1528 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1529 if (ret_val) 1530 return ret_val; 1531 1532 /* Read the MII 1000Base-T Control Register (Address 9). */ 1533 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1534 if (ret_val) 1535 return ret_val; 1536 else if (hw->phy_type == e1000_phy_8201) 1537 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1538 1539 /* Need to parse both autoneg_advertised and fc and set up 1540 * the appropriate PHY registers. First we will parse for 1541 * autoneg_advertised software override. Since we can advertise 1542 * a plethora of combinations, we need to check each bit 1543 * individually. 1544 */ 1545 1546 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1547 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1548 * the 1000Base-T Control Register (Address 9). 1549 */ 1550 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1551 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1552 1553 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised); 1554 1555 /* Do we want to advertise 10 Mb Half Duplex? */ 1556 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1557 e_dbg("Advertise 10mb Half duplex\n"); 1558 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1559 } 1560 1561 /* Do we want to advertise 10 Mb Full Duplex? */ 1562 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1563 e_dbg("Advertise 10mb Full duplex\n"); 1564 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1565 } 1566 1567 /* Do we want to advertise 100 Mb Half Duplex? */ 1568 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1569 e_dbg("Advertise 100mb Half duplex\n"); 1570 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1571 } 1572 1573 /* Do we want to advertise 100 Mb Full Duplex? */ 1574 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1575 e_dbg("Advertise 100mb Full duplex\n"); 1576 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1577 } 1578 1579 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1580 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1581 e_dbg 1582 ("Advertise 1000mb Half duplex requested, request denied!\n"); 1583 } 1584 1585 /* Do we want to advertise 1000 Mb Full Duplex? */ 1586 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1587 e_dbg("Advertise 1000mb Full duplex\n"); 1588 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1589 } 1590 1591 /* Check for a software override of the flow control settings, and 1592 * setup the PHY advertisement registers accordingly. If 1593 * auto-negotiation is enabled, then software will have to set the 1594 * "PAUSE" bits to the correct value in the Auto-Negotiation 1595 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 1596 * auto-negotiation. 1597 * 1598 * The possible values of the "fc" parameter are: 1599 * 0: Flow control is completely disabled 1600 * 1: Rx flow control is enabled (we can receive pause frames 1601 * but not send pause frames). 1602 * 2: Tx flow control is enabled (we can send pause frames 1603 * but we do not support receiving pause frames). 1604 * 3: Both Rx and TX flow control (symmetric) are enabled. 1605 * other: No software override. The flow control configuration 1606 * in the EEPROM is used. 1607 */ 1608 switch (hw->fc) { 1609 case E1000_FC_NONE: /* 0 */ 1610 /* Flow control (RX & TX) is completely disabled by a 1611 * software over-ride. 1612 */ 1613 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1614 break; 1615 case E1000_FC_RX_PAUSE: /* 1 */ 1616 /* RX Flow control is enabled, and TX Flow control is 1617 * disabled, by a software over-ride. 1618 */ 1619 /* Since there really isn't a way to advertise that we are 1620 * capable of RX Pause ONLY, we will advertise that we 1621 * support both symmetric and asymmetric RX PAUSE. Later 1622 * (in e1000_config_fc_after_link_up) we will disable the 1623 * hw's ability to send PAUSE frames. 1624 */ 1625 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1626 break; 1627 case E1000_FC_TX_PAUSE: /* 2 */ 1628 /* TX Flow control is enabled, and RX Flow control is 1629 * disabled, by a software over-ride. 1630 */ 1631 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1632 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1633 break; 1634 case E1000_FC_FULL: /* 3 */ 1635 /* Flow control (both RX and TX) is enabled by a software 1636 * over-ride. 1637 */ 1638 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1639 break; 1640 default: 1641 e_dbg("Flow control param set incorrectly\n"); 1642 return -E1000_ERR_CONFIG; 1643 } 1644 1645 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1646 if (ret_val) 1647 return ret_val; 1648 1649 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1650 1651 if (hw->phy_type == e1000_phy_8201) { 1652 mii_1000t_ctrl_reg = 0; 1653 } else { 1654 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, 1655 mii_1000t_ctrl_reg); 1656 if (ret_val) 1657 return ret_val; 1658 } 1659 1660 return E1000_SUCCESS; 1661} 1662 1663/** 1664 * e1000_phy_force_speed_duplex - force link settings 1665 * @hw: Struct containing variables accessed by shared code 1666 * 1667 * Force PHY speed and duplex settings to hw->forced_speed_duplex 1668 */ 1669static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1670{ 1671 u32 ctrl; 1672 s32 ret_val; 1673 u16 mii_ctrl_reg; 1674 u16 mii_status_reg; 1675 u16 phy_data; 1676 u16 i; 1677 1678 /* Turn off Flow control if we are forcing speed and duplex. */ 1679 hw->fc = E1000_FC_NONE; 1680 1681 e_dbg("hw->fc = %d\n", hw->fc); 1682 1683 /* Read the Device Control Register. */ 1684 ctrl = er32(CTRL); 1685 1686 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1687 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1688 ctrl &= ~(DEVICE_SPEED_MASK); 1689 1690 /* Clear the Auto Speed Detect Enable bit. */ 1691 ctrl &= ~E1000_CTRL_ASDE; 1692 1693 /* Read the MII Control Register. */ 1694 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1695 if (ret_val) 1696 return ret_val; 1697 1698 /* We need to disable autoneg in order to force link and duplex. */ 1699 1700 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1701 1702 /* Are we forcing Full or Half Duplex? */ 1703 if (hw->forced_speed_duplex == e1000_100_full || 1704 hw->forced_speed_duplex == e1000_10_full) { 1705 /* We want to force full duplex so we SET the full duplex bits 1706 * in the Device and MII Control Registers. 1707 */ 1708 ctrl |= E1000_CTRL_FD; 1709 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1710 e_dbg("Full Duplex\n"); 1711 } else { 1712 /* We want to force half duplex so we CLEAR the full duplex bits 1713 * in the Device and MII Control Registers. 1714 */ 1715 ctrl &= ~E1000_CTRL_FD; 1716 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1717 e_dbg("Half Duplex\n"); 1718 } 1719 1720 /* Are we forcing 100Mbps??? */ 1721 if (hw->forced_speed_duplex == e1000_100_full || 1722 hw->forced_speed_duplex == e1000_100_half) { 1723 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1724 ctrl |= E1000_CTRL_SPD_100; 1725 mii_ctrl_reg |= MII_CR_SPEED_100; 1726 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1727 e_dbg("Forcing 100mb "); 1728 } else { 1729 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1730 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1731 mii_ctrl_reg |= MII_CR_SPEED_10; 1732 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1733 e_dbg("Forcing 10mb "); 1734 } 1735 1736 e1000_config_collision_dist(hw); 1737 1738 /* Write the configured values back to the Device Control Reg. */ 1739 ew32(CTRL, ctrl); 1740 1741 if (hw->phy_type == e1000_phy_m88) { 1742 ret_val = 1743 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1744 if (ret_val) 1745 return ret_val; 1746 1747 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires 1748 * MDI forced whenever speed are duplex are forced. 1749 */ 1750 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1751 ret_val = 1752 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1753 if (ret_val) 1754 return ret_val; 1755 1756 e_dbg("M88E1000 PSCR: %x\n", phy_data); 1757 1758 /* Need to reset the PHY or these changes will be ignored */ 1759 mii_ctrl_reg |= MII_CR_RESET; 1760 1761 /* Disable MDI-X support for 10/100 */ 1762 } else { 1763 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1764 * forced whenever speed or duplex are forced. 1765 */ 1766 ret_val = 1767 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1768 if (ret_val) 1769 return ret_val; 1770 1771 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1772 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1773 1774 ret_val = 1775 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1776 if (ret_val) 1777 return ret_val; 1778 } 1779 1780 /* Write back the modified PHY MII control register. */ 1781 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1782 if (ret_val) 1783 return ret_val; 1784 1785 udelay(1); 1786 1787 /* The wait_autoneg_complete flag may be a little misleading here. 1788 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1789 * But we do want to delay for a period while forcing only so we 1790 * don't generate false No Link messages. So we will wait here 1791 * only if the user has set wait_autoneg_complete to 1, which is 1792 * the default. 1793 */ 1794 if (hw->wait_autoneg_complete) { 1795 /* We will wait for autoneg to complete. */ 1796 e_dbg("Waiting for forced speed/duplex link.\n"); 1797 mii_status_reg = 0; 1798 1799 /* Wait for autoneg to complete or 4.5 seconds to expire */ 1800 for (i = PHY_FORCE_TIME; i > 0; i--) { 1801 /* Read the MII Status Register and wait for Auto-Neg 1802 * Complete bit to be set. 1803 */ 1804 ret_val = 1805 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1806 if (ret_val) 1807 return ret_val; 1808 1809 ret_val = 1810 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1811 if (ret_val) 1812 return ret_val; 1813 1814 if (mii_status_reg & MII_SR_LINK_STATUS) 1815 break; 1816 msleep(100); 1817 } 1818 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { 1819 /* We didn't get link. Reset the DSP and wait again 1820 * for link. 1821 */ 1822 ret_val = e1000_phy_reset_dsp(hw); 1823 if (ret_val) { 1824 e_dbg("Error Resetting PHY DSP\n"); 1825 return ret_val; 1826 } 1827 } 1828 /* This loop will early-out if the link condition has been 1829 * met 1830 */ 1831 for (i = PHY_FORCE_TIME; i > 0; i--) { 1832 if (mii_status_reg & MII_SR_LINK_STATUS) 1833 break; 1834 msleep(100); 1835 /* Read the MII Status Register and wait for Auto-Neg 1836 * Complete bit to be set. 1837 */ 1838 ret_val = 1839 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1840 if (ret_val) 1841 return ret_val; 1842 1843 ret_val = 1844 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1845 if (ret_val) 1846 return ret_val; 1847 } 1848 } 1849 1850 if (hw->phy_type == e1000_phy_m88) { 1851 /* Because we reset the PHY above, we need to re-force TX_CLK in 1852 * the Extended PHY Specific Control Register to 25MHz clock. 1853 * This value defaults back to a 2.5MHz clock when the PHY is 1854 * reset. 1855 */ 1856 ret_val = 1857 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1858 &phy_data); 1859 if (ret_val) 1860 return ret_val; 1861 1862 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1863 ret_val = 1864 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1865 phy_data); 1866 if (ret_val) 1867 return ret_val; 1868 1869 /* In addition, because of the s/w reset above, we need to 1870 * enable CRS on Tx. This must be set for both full and half 1871 * duplex operation. 1872 */ 1873 ret_val = 1874 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1875 if (ret_val) 1876 return ret_val; 1877 1878 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1879 ret_val = 1880 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1881 if (ret_val) 1882 return ret_val; 1883 1884 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) 1885 && (!hw->autoneg) 1886 && (hw->forced_speed_duplex == e1000_10_full 1887 || hw->forced_speed_duplex == e1000_10_half)) { 1888 ret_val = e1000_polarity_reversal_workaround(hw); 1889 if (ret_val) 1890 return ret_val; 1891 } 1892 } 1893 return E1000_SUCCESS; 1894} 1895 1896/** 1897 * e1000_config_collision_dist - set collision distance register 1898 * @hw: Struct containing variables accessed by shared code 1899 * 1900 * Sets the collision distance in the Transmit Control register. 1901 * Link should have been established previously. Reads the speed and duplex 1902 * information from the Device Status register. 1903 */ 1904void e1000_config_collision_dist(struct e1000_hw *hw) 1905{ 1906 u32 tctl, coll_dist; 1907 1908 if (hw->mac_type < e1000_82543) 1909 coll_dist = E1000_COLLISION_DISTANCE_82542; 1910 else 1911 coll_dist = E1000_COLLISION_DISTANCE; 1912 1913 tctl = er32(TCTL); 1914 1915 tctl &= ~E1000_TCTL_COLD; 1916 tctl |= coll_dist << E1000_COLD_SHIFT; 1917 1918 ew32(TCTL, tctl); 1919 E1000_WRITE_FLUSH(); 1920} 1921 1922/** 1923 * e1000_config_mac_to_phy - sync phy and mac settings 1924 * @hw: Struct containing variables accessed by shared code 1925 * @mii_reg: data to write to the MII control register 1926 * 1927 * Sets MAC speed and duplex settings to reflect the those in the PHY 1928 * The contents of the PHY register containing the needed information need to 1929 * be passed in. 1930 */ 1931static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1932{ 1933 u32 ctrl; 1934 s32 ret_val; 1935 u16 phy_data; 1936 1937 /* 82544 or newer MAC, Auto Speed Detection takes care of 1938 * MAC speed/duplex configuration. 1939 */ 1940 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) 1941 return E1000_SUCCESS; 1942 1943 /* Read the Device Control Register and set the bits to Force Speed 1944 * and Duplex. 1945 */ 1946 ctrl = er32(CTRL); 1947 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1948 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1949 1950 switch (hw->phy_type) { 1951 case e1000_phy_8201: 1952 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1953 if (ret_val) 1954 return ret_val; 1955 1956 if (phy_data & RTL_PHY_CTRL_FD) 1957 ctrl |= E1000_CTRL_FD; 1958 else 1959 ctrl &= ~E1000_CTRL_FD; 1960 1961 if (phy_data & RTL_PHY_CTRL_SPD_100) 1962 ctrl |= E1000_CTRL_SPD_100; 1963 else 1964 ctrl |= E1000_CTRL_SPD_10; 1965 1966 e1000_config_collision_dist(hw); 1967 break; 1968 default: 1969 /* Set up duplex in the Device Control and Transmit Control 1970 * registers depending on negotiated values. 1971 */ 1972 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 1973 &phy_data); 1974 if (ret_val) 1975 return ret_val; 1976 1977 if (phy_data & M88E1000_PSSR_DPLX) 1978 ctrl |= E1000_CTRL_FD; 1979 else 1980 ctrl &= ~E1000_CTRL_FD; 1981 1982 e1000_config_collision_dist(hw); 1983 1984 /* Set up speed in the Device Control register depending on 1985 * negotiated values. 1986 */ 1987 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1988 ctrl |= E1000_CTRL_SPD_1000; 1989 else if ((phy_data & M88E1000_PSSR_SPEED) == 1990 M88E1000_PSSR_100MBS) 1991 ctrl |= E1000_CTRL_SPD_100; 1992 } 1993 1994 /* Write the configured values back to the Device Control Reg. */ 1995 ew32(CTRL, ctrl); 1996 return E1000_SUCCESS; 1997} 1998 1999/** 2000 * e1000_force_mac_fc - force flow control settings 2001 * @hw: Struct containing variables accessed by shared code 2002 * 2003 * Forces the MAC's flow control settings. 2004 * Sets the TFCE and RFCE bits in the device control register to reflect 2005 * the adapter settings. TFCE and RFCE need to be explicitly set by 2006 * software when a Copper PHY is used because autonegotiation is managed 2007 * by the PHY rather than the MAC. Software must also configure these 2008 * bits when link is forced on a fiber connection. 2009 */ 2010s32 e1000_force_mac_fc(struct e1000_hw *hw) 2011{ 2012 u32 ctrl; 2013 2014 /* Get the current configuration of the Device Control Register */ 2015 ctrl = er32(CTRL); 2016 2017 /* Because we didn't get link via the internal auto-negotiation 2018 * mechanism (we either forced link or we got link via PHY 2019 * auto-neg), we have to manually enable/disable transmit an 2020 * receive flow control. 2021 * 2022 * The "Case" statement below enables/disable flow control 2023 * according to the "hw->fc" parameter. 2024 * 2025 * The possible values of the "fc" parameter are: 2026 * 0: Flow control is completely disabled 2027 * 1: Rx flow control is enabled (we can receive pause 2028 * frames but not send pause frames). 2029 * 2: Tx flow control is enabled (we can send pause frames 2030 * frames but we do not receive pause frames). 2031 * 3: Both Rx and TX flow control (symmetric) is enabled. 2032 * other: No other values should be possible at this point. 2033 */ 2034 2035 switch (hw->fc) { 2036 case E1000_FC_NONE: 2037 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2038 break; 2039 case E1000_FC_RX_PAUSE: 2040 ctrl &= (~E1000_CTRL_TFCE); 2041 ctrl |= E1000_CTRL_RFCE; 2042 break; 2043 case E1000_FC_TX_PAUSE: 2044 ctrl &= (~E1000_CTRL_RFCE); 2045 ctrl |= E1000_CTRL_TFCE; 2046 break; 2047 case E1000_FC_FULL: 2048 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2049 break; 2050 default: 2051 e_dbg("Flow control param set incorrectly\n"); 2052 return -E1000_ERR_CONFIG; 2053 } 2054 2055 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2056 if (hw->mac_type == e1000_82542_rev2_0) 2057 ctrl &= (~E1000_CTRL_TFCE); 2058 2059 ew32(CTRL, ctrl); 2060 return E1000_SUCCESS; 2061} 2062 2063/** 2064 * e1000_config_fc_after_link_up - configure flow control after autoneg 2065 * @hw: Struct containing variables accessed by shared code 2066 * 2067 * Configures flow control settings after link is established 2068 * Should be called immediately after a valid link has been established. 2069 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 2070 * and autonegotiation is enabled, the MAC flow control settings will be set 2071 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 2072 * and RFCE bits will be automatically set to the negotiated flow control mode. 2073 */ 2074static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 2075{ 2076 s32 ret_val; 2077 u16 mii_status_reg; 2078 u16 mii_nway_adv_reg; 2079 u16 mii_nway_lp_ability_reg; 2080 u16 speed; 2081 u16 duplex; 2082 2083 /* Check for the case where we have fiber media and auto-neg failed 2084 * so we had to force link. In this case, we need to force the 2085 * configuration of the MAC to match the "fc" parameter. 2086 */ 2087 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) 2088 || ((hw->media_type == e1000_media_type_internal_serdes) 2089 && (hw->autoneg_failed)) 2090 || ((hw->media_type == e1000_media_type_copper) 2091 && (!hw->autoneg))) { 2092 ret_val = e1000_force_mac_fc(hw); 2093 if (ret_val) { 2094 e_dbg("Error forcing flow control settings\n"); 2095 return ret_val; 2096 } 2097 } 2098 2099 /* Check for the case where we have copper media and auto-neg is 2100 * enabled. In this case, we need to check and see if Auto-Neg 2101 * has completed, and if so, how the PHY and link partner has 2102 * flow control configured. 2103 */ 2104 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2105 /* Read the MII Status Register and check to see if AutoNeg 2106 * has completed. We read this twice because this reg has 2107 * some "sticky" (latched) bits. 2108 */ 2109 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2110 if (ret_val) 2111 return ret_val; 2112 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2113 if (ret_val) 2114 return ret_val; 2115 2116 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2117 /* The AutoNeg process has completed, so we now need to 2118 * read both the Auto Negotiation Advertisement Register 2119 * (Address 4) and the Auto_Negotiation Base Page 2120 * Ability Register (Address 5) to determine how flow 2121 * control was negotiated. 2122 */ 2123 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2124 &mii_nway_adv_reg); 2125 if (ret_val) 2126 return ret_val; 2127 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2128 &mii_nway_lp_ability_reg); 2129 if (ret_val) 2130 return ret_val; 2131 2132 /* Two bits in the Auto Negotiation Advertisement 2133 * Register (Address 4) and two bits in the Auto 2134 * Negotiation Base Page Ability Register (Address 5) 2135 * determine flow control for both the PHY and the link 2136 * partner. The following table, taken out of the IEEE 2137 * 802.3ab/D6.0 dated March 25, 1999, describes these 2138 * PAUSE resolution bits and how flow control is 2139 * determined based upon these settings. 2140 * NOTE: DC = Don't Care 2141 * 2142 * LOCAL DEVICE | LINK PARTNER 2143 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2144 *-------|---------|-------|---------|------------------ 2145 * 0 | 0 | DC | DC | E1000_FC_NONE 2146 * 0 | 1 | 0 | DC | E1000_FC_NONE 2147 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2148 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2149 * 1 | 0 | 0 | DC | E1000_FC_NONE 2150 * 1 | DC | 1 | DC | E1000_FC_FULL 2151 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2152 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2153 * 2154 */ 2155 /* Are both PAUSE bits set to 1? If so, this implies 2156 * Symmetric Flow Control is enabled at both ends. The 2157 * ASM_DIR bits are irrelevant per the spec. 2158 * 2159 * For Symmetric Flow Control: 2160 * 2161 * LOCAL DEVICE | LINK PARTNER 2162 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2163 *-------|---------|-------|---------|------------------ 2164 * 1 | DC | 1 | DC | E1000_FC_FULL 2165 * 2166 */ 2167 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2168 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2169 /* Now we need to check if the user selected Rx 2170 * ONLY of pause frames. In this case, we had 2171 * to advertise FULL flow control because we 2172 * could not advertise Rx ONLY. Hence, we must 2173 * now check to see if we need to turn OFF the 2174 * TRANSMISSION of PAUSE frames. 2175 */ 2176 if (hw->original_fc == E1000_FC_FULL) { 2177 hw->fc = E1000_FC_FULL; 2178 e_dbg("Flow Control = FULL.\n"); 2179 } else { 2180 hw->fc = E1000_FC_RX_PAUSE; 2181 e_dbg 2182 ("Flow Control = RX PAUSE frames only.\n"); 2183 } 2184 } 2185 /* For receiving PAUSE frames ONLY. 2186 * 2187 * LOCAL DEVICE | LINK PARTNER 2188 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2189 *-------|---------|-------|---------|------------------ 2190 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2191 * 2192 */ 2193 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2194 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2195 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2196 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2197 { 2198 hw->fc = E1000_FC_TX_PAUSE; 2199 e_dbg 2200 ("Flow Control = TX PAUSE frames only.\n"); 2201 } 2202 /* For transmitting PAUSE frames ONLY. 2203 * 2204 * LOCAL DEVICE | LINK PARTNER 2205 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2206 *-------|---------|-------|---------|------------------ 2207 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2208 * 2209 */ 2210 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2211 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2212 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2213 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) 2214 { 2215 hw->fc = E1000_FC_RX_PAUSE; 2216 e_dbg 2217 ("Flow Control = RX PAUSE frames only.\n"); 2218 } 2219 /* Per the IEEE spec, at this point flow control should 2220 * be disabled. However, we want to consider that we 2221 * could be connected to a legacy switch that doesn't 2222 * advertise desired flow control, but can be forced on 2223 * the link partner. So if we advertised no flow 2224 * control, that is what we will resolve to. If we 2225 * advertised some kind of receive capability (Rx Pause 2226 * Only or Full Flow Control) and the link partner 2227 * advertised none, we will configure ourselves to 2228 * enable Rx Flow Control only. We can do this safely 2229 * for two reasons: If the link partner really 2230 * didn't want flow control enabled, and we enable Rx, 2231 * no harm done since we won't be receiving any PAUSE 2232 * frames anyway. If the intent on the link partner was 2233 * to have flow control enabled, then by us enabling Rx 2234 * only, we can at least receive pause frames and 2235 * process them. This is a good idea because in most 2236 * cases, since we are predominantly a server NIC, more 2237 * times than not we will be asked to delay transmission 2238 * of packets than asking our link partner to pause 2239 * transmission of frames. 2240 */ 2241 else if ((hw->original_fc == E1000_FC_NONE || 2242 hw->original_fc == E1000_FC_TX_PAUSE) || 2243 hw->fc_strict_ieee) { 2244 hw->fc = E1000_FC_NONE; 2245 e_dbg("Flow Control = NONE.\n"); 2246 } else { 2247 hw->fc = E1000_FC_RX_PAUSE; 2248 e_dbg 2249 ("Flow Control = RX PAUSE frames only.\n"); 2250 } 2251 2252 /* Now we need to do one last check... If we auto- 2253 * negotiated to HALF DUPLEX, flow control should not be 2254 * enabled per IEEE 802.3 spec. 2255 */ 2256 ret_val = 2257 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2258 if (ret_val) { 2259 e_dbg 2260 ("Error getting link speed and duplex\n"); 2261 return ret_val; 2262 } 2263 2264 if (duplex == HALF_DUPLEX) 2265 hw->fc = E1000_FC_NONE; 2266 2267 /* Now we call a subroutine to actually force the MAC 2268 * controller to use the correct flow control settings. 2269 */ 2270 ret_val = e1000_force_mac_fc(hw); 2271 if (ret_val) { 2272 e_dbg 2273 ("Error forcing flow control settings\n"); 2274 return ret_val; 2275 } 2276 } else { 2277 e_dbg 2278 ("Copper PHY and Auto Neg has not completed.\n"); 2279 } 2280 } 2281 return E1000_SUCCESS; 2282} 2283 2284/** 2285 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 2286 * @hw: pointer to the HW structure 2287 * 2288 * Checks for link up on the hardware. If link is not up and we have 2289 * a signal, then we need to force link up. 2290 */ 2291static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 2292{ 2293 u32 rxcw; 2294 u32 ctrl; 2295 u32 status; 2296 s32 ret_val = E1000_SUCCESS; 2297 2298 ctrl = er32(CTRL); 2299 status = er32(STATUS); 2300 rxcw = er32(RXCW); 2301 2302 /* If we don't have link (auto-negotiation failed or link partner 2303 * cannot auto-negotiate), and our link partner is not trying to 2304 * auto-negotiate with us (we are receiving idles or data), 2305 * we need to force link up. We also need to give auto-negotiation 2306 * time to complete. 2307 */ 2308 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 2309 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 2310 if (hw->autoneg_failed == 0) { 2311 hw->autoneg_failed = 1; 2312 goto out; 2313 } 2314 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 2315 2316 /* Disable auto-negotiation in the TXCW register */ 2317 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 2318 2319 /* Force link-up and also force full-duplex. */ 2320 ctrl = er32(CTRL); 2321 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 2322 ew32(CTRL, ctrl); 2323 2324 /* Configure Flow Control after forcing link up. */ 2325 ret_val = e1000_config_fc_after_link_up(hw); 2326 if (ret_val) { 2327 e_dbg("Error configuring flow control\n"); 2328 goto out; 2329 } 2330 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2331 /* If we are forcing link and we are receiving /C/ ordered 2332 * sets, re-enable auto-negotiation in the TXCW register 2333 * and disable forced link in the Device Control register 2334 * in an attempt to auto-negotiate with our link partner. 2335 */ 2336 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2337 ew32(TXCW, hw->txcw); 2338 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 2339 2340 hw->serdes_has_link = true; 2341 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 2342 /* If we force link for non-auto-negotiation switch, check 2343 * link status based on MAC synchronization for internal 2344 * serdes media type. 2345 */ 2346 /* SYNCH bit and IV bit are sticky. */ 2347 udelay(10); 2348 rxcw = er32(RXCW); 2349 if (rxcw & E1000_RXCW_SYNCH) { 2350 if (!(rxcw & E1000_RXCW_IV)) { 2351 hw->serdes_has_link = true; 2352 e_dbg("SERDES: Link up - forced.\n"); 2353 } 2354 } else { 2355 hw->serdes_has_link = false; 2356 e_dbg("SERDES: Link down - force failed.\n"); 2357 } 2358 } 2359 2360 if (E1000_TXCW_ANE & er32(TXCW)) { 2361 status = er32(STATUS); 2362 if (status & E1000_STATUS_LU) { 2363 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 2364 udelay(10); 2365 rxcw = er32(RXCW); 2366 if (rxcw & E1000_RXCW_SYNCH) { 2367 if (!(rxcw & E1000_RXCW_IV)) { 2368 hw->serdes_has_link = true; 2369 e_dbg("SERDES: Link up - autoneg " 2370 "completed successfully.\n"); 2371 } else { 2372 hw->serdes_has_link = false; 2373 e_dbg("SERDES: Link down - invalid" 2374 "codewords detected in autoneg.\n"); 2375 } 2376 } else { 2377 hw->serdes_has_link = false; 2378 e_dbg("SERDES: Link down - no sync.\n"); 2379 } 2380 } else { 2381 hw->serdes_has_link = false; 2382 e_dbg("SERDES: Link down - autoneg failed\n"); 2383 } 2384 } 2385 2386 out: 2387 return ret_val; 2388} 2389 2390/** 2391 * e1000_check_for_link 2392 * @hw: Struct containing variables accessed by shared code 2393 * 2394 * Checks to see if the link status of the hardware has changed. 2395 * Called by any function that needs to check the link status of the adapter. 2396 */ 2397s32 e1000_check_for_link(struct e1000_hw *hw) 2398{ 2399 u32 rxcw = 0; 2400 u32 ctrl; 2401 u32 status; 2402 u32 rctl; 2403 u32 icr; 2404 u32 signal = 0; 2405 s32 ret_val; 2406 u16 phy_data; 2407 2408 ctrl = er32(CTRL); 2409 status = er32(STATUS); 2410 2411 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be 2412 * set when the optics detect a signal. On older adapters, it will be 2413 * cleared when there is a signal. This applies to fiber media only. 2414 */ 2415 if ((hw->media_type == e1000_media_type_fiber) || 2416 (hw->media_type == e1000_media_type_internal_serdes)) { 2417 rxcw = er32(RXCW); 2418 2419 if (hw->media_type == e1000_media_type_fiber) { 2420 signal = 2421 (hw->mac_type > 2422 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2423 if (status & E1000_STATUS_LU) 2424 hw->get_link_status = false; 2425 } 2426 } 2427 2428 /* If we have a copper PHY then we only want to go out to the PHY 2429 * registers to see if Auto-Neg has completed and/or if our link 2430 * status has changed. The get_link_status flag will be set if we 2431 * receive a Link Status Change interrupt or we have Rx Sequence 2432 * Errors. 2433 */ 2434 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2435 /* First we want to see if the MII Status Register reports 2436 * link. If so, then we want to get the current speed/duplex 2437 * of the PHY. 2438 * Read the register twice since the link bit is sticky. 2439 */ 2440 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2441 if (ret_val) 2442 return ret_val; 2443 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2444 if (ret_val) 2445 return ret_val; 2446 2447 if (phy_data & MII_SR_LINK_STATUS) { 2448 hw->get_link_status = false; 2449 /* Check if there was DownShift, must be checked 2450 * immediately after link-up 2451 */ 2452 e1000_check_downshift(hw); 2453 2454 /* If we are on 82544 or 82543 silicon and speed/duplex 2455 * are forced to 10H or 10F, then we will implement the 2456 * polarity reversal workaround. We disable interrupts 2457 * first, and upon returning, place the devices 2458 * interrupt state to its previous value except for the 2459 * link status change interrupt which will 2460 * happen due to the execution of this workaround. 2461 */ 2462 2463 if ((hw->mac_type == e1000_82544 2464 || hw->mac_type == e1000_82543) && (!hw->autoneg) 2465 && (hw->forced_speed_duplex == e1000_10_full 2466 || hw->forced_speed_duplex == e1000_10_half)) { 2467 ew32(IMC, 0xffffffff); 2468 ret_val = 2469 e1000_polarity_reversal_workaround(hw); 2470 icr = er32(ICR); 2471 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2472 ew32(IMS, IMS_ENABLE_MASK); 2473 } 2474 2475 } else { 2476 /* No link detected */ 2477 e1000_config_dsp_after_link_change(hw, false); 2478 return 0; 2479 } 2480 2481 /* If we are forcing speed/duplex, then we simply return since 2482 * we have already determined whether we have link or not. 2483 */ 2484 if (!hw->autoneg) 2485 return -E1000_ERR_CONFIG; 2486 2487 /* optimize the dsp settings for the igp phy */ 2488 e1000_config_dsp_after_link_change(hw, true); 2489 2490 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2491 * have Si on board that is 82544 or newer, Auto 2492 * Speed Detection takes care of MAC speed/duplex 2493 * configuration. So we only need to configure Collision 2494 * Distance in the MAC. Otherwise, we need to force 2495 * speed/duplex on the MAC to the current PHY speed/duplex 2496 * settings. 2497 */ 2498 if ((hw->mac_type >= e1000_82544) && 2499 (hw->mac_type != e1000_ce4100)) 2500 e1000_config_collision_dist(hw); 2501 else { 2502 ret_val = e1000_config_mac_to_phy(hw); 2503 if (ret_val) { 2504 e_dbg 2505 ("Error configuring MAC to PHY settings\n"); 2506 return ret_val; 2507 } 2508 } 2509 2510 /* Configure Flow Control now that Auto-Neg has completed. 2511 * First, we need to restore the desired flow control settings 2512 * because we may have had to re-autoneg with a different link 2513 * partner. 2514 */ 2515 ret_val = e1000_config_fc_after_link_up(hw); 2516 if (ret_val) { 2517 e_dbg("Error configuring flow control\n"); 2518 return ret_val; 2519 } 2520 2521 /* At this point we know that we are on copper and we have 2522 * auto-negotiated link. These are conditions for checking the 2523 * link partner capability register. We use the link speed to 2524 * determine if TBI compatibility needs to be turned on or off. 2525 * If the link is not at gigabit speed, then TBI compatibility 2526 * is not needed. If we are at gigabit speed, we turn on TBI 2527 * compatibility. 2528 */ 2529 if (hw->tbi_compatibility_en) { 2530 u16 speed, duplex; 2531 ret_val = 2532 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2533 if (ret_val) { 2534 e_dbg 2535 ("Error getting link speed and duplex\n"); 2536 return ret_val; 2537 } 2538 if (speed != SPEED_1000) { 2539 /* If link speed is not set to gigabit speed, we 2540 * do not need to enable TBI compatibility. 2541 */ 2542 if (hw->tbi_compatibility_on) { 2543 /* If we previously were in the mode, 2544 * turn it off. 2545 */ 2546 rctl = er32(RCTL); 2547 rctl &= ~E1000_RCTL_SBP; 2548 ew32(RCTL, rctl); 2549 hw->tbi_compatibility_on = false; 2550 } 2551 } else { 2552 /* If TBI compatibility is was previously off, 2553 * turn it on. For compatibility with a TBI link 2554 * partner, we will store bad packets. Some 2555 * frames have an additional byte on the end and 2556 * will look like CRC errors to to the hardware. 2557 */ 2558 if (!hw->tbi_compatibility_on) { 2559 hw->tbi_compatibility_on = true; 2560 rctl = er32(RCTL); 2561 rctl |= E1000_RCTL_SBP; 2562 ew32(RCTL, rctl); 2563 } 2564 } 2565 } 2566 } 2567 2568 if ((hw->media_type == e1000_media_type_fiber) || 2569 (hw->media_type == e1000_media_type_internal_serdes)) 2570 e1000_check_for_serdes_link_generic(hw); 2571 2572 return E1000_SUCCESS; 2573} 2574 2575/** 2576 * e1000_get_speed_and_duplex 2577 * @hw: Struct containing variables accessed by shared code 2578 * @speed: Speed of the connection 2579 * @duplex: Duplex setting of the connection 2580 * 2581 * Detects the current speed and duplex settings of the hardware. 2582 */ 2583s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2584{ 2585 u32 status; 2586 s32 ret_val; 2587 u16 phy_data; 2588 2589 if (hw->mac_type >= e1000_82543) { 2590 status = er32(STATUS); 2591 if (status & E1000_STATUS_SPEED_1000) { 2592 *speed = SPEED_1000; 2593 e_dbg("1000 Mbs, "); 2594 } else if (status & E1000_STATUS_SPEED_100) { 2595 *speed = SPEED_100; 2596 e_dbg("100 Mbs, "); 2597 } else { 2598 *speed = SPEED_10; 2599 e_dbg("10 Mbs, "); 2600 } 2601 2602 if (status & E1000_STATUS_FD) { 2603 *duplex = FULL_DUPLEX; 2604 e_dbg("Full Duplex\n"); 2605 } else { 2606 *duplex = HALF_DUPLEX; 2607 e_dbg(" Half Duplex\n"); 2608 } 2609 } else { 2610 e_dbg("1000 Mbs, Full Duplex\n"); 2611 *speed = SPEED_1000; 2612 *duplex = FULL_DUPLEX; 2613 } 2614 2615 /* IGP01 PHY may advertise full duplex operation after speed downgrade 2616 * even if it is operating at half duplex. Here we set the duplex 2617 * settings to match the duplex in the link partner's capabilities. 2618 */ 2619 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2620 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2621 if (ret_val) 2622 return ret_val; 2623 2624 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2625 *duplex = HALF_DUPLEX; 2626 else { 2627 ret_val = 2628 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2629 if (ret_val) 2630 return ret_val; 2631 if ((*speed == SPEED_100 2632 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) 2633 || (*speed == SPEED_10 2634 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2635 *duplex = HALF_DUPLEX; 2636 } 2637 } 2638 2639 return E1000_SUCCESS; 2640} 2641 2642/** 2643 * e1000_wait_autoneg 2644 * @hw: Struct containing variables accessed by shared code 2645 * 2646 * Blocks until autoneg completes or times out (~4.5 seconds) 2647 */ 2648static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2649{ 2650 s32 ret_val; 2651 u16 i; 2652 u16 phy_data; 2653 2654 e_dbg("Waiting for Auto-Neg to complete.\n"); 2655 2656 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2657 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2658 /* Read the MII Status Register and wait for Auto-Neg 2659 * Complete bit to be set. 2660 */ 2661 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2662 if (ret_val) 2663 return ret_val; 2664 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2665 if (ret_val) 2666 return ret_val; 2667 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2668 return E1000_SUCCESS; 2669 } 2670 msleep(100); 2671 } 2672 return E1000_SUCCESS; 2673} 2674 2675/** 2676 * e1000_raise_mdi_clk - Raises the Management Data Clock 2677 * @hw: Struct containing variables accessed by shared code 2678 * @ctrl: Device control register's current value 2679 */ 2680static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2681{ 2682 /* Raise the clock input to the Management Data Clock (by setting the 2683 * MDC bit), and then delay 10 microseconds. 2684 */ 2685 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2686 E1000_WRITE_FLUSH(); 2687 udelay(10); 2688} 2689 2690/** 2691 * e1000_lower_mdi_clk - Lowers the Management Data Clock 2692 * @hw: Struct containing variables accessed by shared code 2693 * @ctrl: Device control register's current value 2694 */ 2695static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2696{ 2697 /* Lower the clock input to the Management Data Clock (by clearing the 2698 * MDC bit), and then delay 10 microseconds. 2699 */ 2700 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2701 E1000_WRITE_FLUSH(); 2702 udelay(10); 2703} 2704 2705/** 2706 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY 2707 * @hw: Struct containing variables accessed by shared code 2708 * @data: Data to send out to the PHY 2709 * @count: Number of bits to shift out 2710 * 2711 * Bits are shifted out in MSB to LSB order. 2712 */ 2713static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2714{ 2715 u32 ctrl; 2716 u32 mask; 2717 2718 /* We need to shift "count" number of bits out to the PHY. So, the value 2719 * in the "data" parameter will be shifted out to the PHY one bit at a 2720 * time. In order to do this, "data" must be broken down into bits. 2721 */ 2722 mask = 0x01; 2723 mask <<= (count - 1); 2724 2725 ctrl = er32(CTRL); 2726 2727 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2728 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2729 2730 while (mask) { 2731 /* A "1" is shifted out to the PHY by setting the MDIO bit to 2732 * "1" and then raising and lowering the Management Data Clock. 2733 * A "0" is shifted out to the PHY by setting the MDIO bit to 2734 * "0" and then raising and lowering the clock. 2735 */ 2736 if (data & mask) 2737 ctrl |= E1000_CTRL_MDIO; 2738 else 2739 ctrl &= ~E1000_CTRL_MDIO; 2740 2741 ew32(CTRL, ctrl); 2742 E1000_WRITE_FLUSH(); 2743 2744 udelay(10); 2745 2746 e1000_raise_mdi_clk(hw, &ctrl); 2747 e1000_lower_mdi_clk(hw, &ctrl); 2748 2749 mask = mask >> 1; 2750 } 2751} 2752 2753/** 2754 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY 2755 * @hw: Struct containing variables accessed by shared code 2756 * 2757 * Bits are shifted in in MSB to LSB order. 2758 */ 2759static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2760{ 2761 u32 ctrl; 2762 u16 data = 0; 2763 u8 i; 2764 2765 /* In order to read a register from the PHY, we need to shift in a total 2766 * of 18 bits from the PHY. The first two bit (turnaround) times are 2767 * used to avoid contention on the MDIO pin when a read operation is 2768 * performed. These two bits are ignored by us and thrown away. Bits are 2769 * "shifted in" by raising the input to the Management Data Clock 2770 * (setting the MDC bit), and then reading the value of the MDIO bit. 2771 */ 2772 ctrl = er32(CTRL); 2773 2774 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 2775 * input. 2776 */ 2777 ctrl &= ~E1000_CTRL_MDIO_DIR; 2778 ctrl &= ~E1000_CTRL_MDIO; 2779 2780 ew32(CTRL, ctrl); 2781 E1000_WRITE_FLUSH(); 2782 2783 /* Raise and Lower the clock before reading in the data. This accounts 2784 * for the turnaround bits. The first clock occurred when we clocked out 2785 * the last bit of the Register Address. 2786 */ 2787 e1000_raise_mdi_clk(hw, &ctrl); 2788 e1000_lower_mdi_clk(hw, &ctrl); 2789 2790 for (data = 0, i = 0; i < 16; i++) { 2791 data = data << 1; 2792 e1000_raise_mdi_clk(hw, &ctrl); 2793 ctrl = er32(CTRL); 2794 /* Check to see if we shifted in a "1". */ 2795 if (ctrl & E1000_CTRL_MDIO) 2796 data |= 1; 2797 e1000_lower_mdi_clk(hw, &ctrl); 2798 } 2799 2800 e1000_raise_mdi_clk(hw, &ctrl); 2801 e1000_lower_mdi_clk(hw, &ctrl); 2802 2803 return data; 2804} 2805 2806 2807/** 2808 * e1000_read_phy_reg - read a phy register 2809 * @hw: Struct containing variables accessed by shared code 2810 * @reg_addr: address of the PHY register to read 2811 * 2812 * Reads the value from a PHY register, if the value is on a specific non zero 2813 * page, sets the page first. 2814 */ 2815s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2816{ 2817 u32 ret_val; 2818 unsigned long flags; 2819 2820 spin_lock_irqsave(&e1000_phy_lock, flags); 2821 2822 if ((hw->phy_type == e1000_phy_igp) && 2823 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2824 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2825 (u16) reg_addr); 2826 if (ret_val) { 2827 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2828 return ret_val; 2829 } 2830 } 2831 2832 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2833 phy_data); 2834 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2835 2836 return ret_val; 2837} 2838 2839static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2840 u16 *phy_data) 2841{ 2842 u32 i; 2843 u32 mdic = 0; 2844 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2845 2846 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2847 e_dbg("PHY Address %d is out of range\n", reg_addr); 2848 return -E1000_ERR_PARAM; 2849 } 2850 2851 if (hw->mac_type > e1000_82543) { 2852 /* Set up Op-code, Phy Address, and register address in the MDI 2853 * Control register. The MAC will take care of interfacing with 2854 * the PHY to retrieve the desired data. 2855 */ 2856 if (hw->mac_type == e1000_ce4100) { 2857 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2858 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2859 (INTEL_CE_GBE_MDIC_OP_READ) | 2860 (INTEL_CE_GBE_MDIC_GO)); 2861 2862 writel(mdic, E1000_MDIO_CMD); 2863 2864 /* Poll the ready bit to see if the MDI read 2865 * completed 2866 */ 2867 for (i = 0; i < 64; i++) { 2868 udelay(50); 2869 mdic = readl(E1000_MDIO_CMD); 2870 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 2871 break; 2872 } 2873 2874 if (mdic & INTEL_CE_GBE_MDIC_GO) { 2875 e_dbg("MDI Read did not complete\n"); 2876 return -E1000_ERR_PHY; 2877 } 2878 2879 mdic = readl(E1000_MDIO_STS); 2880 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) { 2881 e_dbg("MDI Read Error\n"); 2882 return -E1000_ERR_PHY; 2883 } 2884 *phy_data = (u16) mdic; 2885 } else { 2886 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2887 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2888 (E1000_MDIC_OP_READ)); 2889 2890 ew32(MDIC, mdic); 2891 2892 /* Poll the ready bit to see if the MDI read 2893 * completed 2894 */ 2895 for (i = 0; i < 64; i++) { 2896 udelay(50); 2897 mdic = er32(MDIC); 2898 if (mdic & E1000_MDIC_READY) 2899 break; 2900 } 2901 if (!(mdic & E1000_MDIC_READY)) { 2902 e_dbg("MDI Read did not complete\n"); 2903 return -E1000_ERR_PHY; 2904 } 2905 if (mdic & E1000_MDIC_ERROR) { 2906 e_dbg("MDI Error\n"); 2907 return -E1000_ERR_PHY; 2908 } 2909 *phy_data = (u16) mdic; 2910 } 2911 } else { 2912 /* We must first send a preamble through the MDIO pin to signal 2913 * the beginning of an MII instruction. This is done by sending 2914 * 32 consecutive "1" bits. 2915 */ 2916 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2917 2918 /* Now combine the next few fields that are required for a read 2919 * operation. We use this method instead of calling the 2920 * e1000_shift_out_mdi_bits routine five different times. The 2921 * format of a MII read instruction consists of a shift out of 2922 * 14 bits and is defined as follows: 2923 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2924 * followed by a shift in of 18 bits. This first two bits 2925 * shifted in are TurnAround bits used to avoid contention on 2926 * the MDIO pin when a READ operation is performed. These two 2927 * bits are thrown away followed by a shift in of 16 bits which 2928 * contains the desired data. 2929 */ 2930 mdic = ((reg_addr) | (phy_addr << 5) | 2931 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2932 2933 e1000_shift_out_mdi_bits(hw, mdic, 14); 2934 2935 /* Now that we've shifted out the read command to the MII, we 2936 * need to "shift in" the 16-bit value (18 total bits) of the 2937 * requested PHY register address. 2938 */ 2939 *phy_data = e1000_shift_in_mdi_bits(hw); 2940 } 2941 return E1000_SUCCESS; 2942} 2943 2944/** 2945 * e1000_write_phy_reg - write a phy register 2946 * 2947 * @hw: Struct containing variables accessed by shared code 2948 * @reg_addr: address of the PHY register to write 2949 * @data: data to write to the PHY 2950 * 2951 * Writes a value to a PHY register 2952 */ 2953s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2954{ 2955 u32 ret_val; 2956 unsigned long flags; 2957 2958 spin_lock_irqsave(&e1000_phy_lock, flags); 2959 2960 if ((hw->phy_type == e1000_phy_igp) && 2961 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2962 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2963 (u16) reg_addr); 2964 if (ret_val) { 2965 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2966 return ret_val; 2967 } 2968 } 2969 2970 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2971 phy_data); 2972 spin_unlock_irqrestore(&e1000_phy_lock, flags); 2973 2974 return ret_val; 2975} 2976 2977static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2978 u16 phy_data) 2979{ 2980 u32 i; 2981 u32 mdic = 0; 2982 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1; 2983 2984 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2985 e_dbg("PHY Address %d is out of range\n", reg_addr); 2986 return -E1000_ERR_PARAM; 2987 } 2988 2989 if (hw->mac_type > e1000_82543) { 2990 /* Set up Op-code, Phy Address, register address, and data 2991 * intended for the PHY register in the MDI Control register. 2992 * The MAC will take care of interfacing with the PHY to send 2993 * the desired data. 2994 */ 2995 if (hw->mac_type == e1000_ce4100) { 2996 mdic = (((u32) phy_data) | 2997 (reg_addr << E1000_MDIC_REG_SHIFT) | 2998 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2999 (INTEL_CE_GBE_MDIC_OP_WRITE) | 3000 (INTEL_CE_GBE_MDIC_GO)); 3001 3002 writel(mdic, E1000_MDIO_CMD); 3003 3004 /* Poll the ready bit to see if the MDI read 3005 * completed 3006 */ 3007 for (i = 0; i < 640; i++) { 3008 udelay(5); 3009 mdic = readl(E1000_MDIO_CMD); 3010 if (!(mdic & INTEL_CE_GBE_MDIC_GO)) 3011 break; 3012 } 3013 if (mdic & INTEL_CE_GBE_MDIC_GO) { 3014 e_dbg("MDI Write did not complete\n"); 3015 return -E1000_ERR_PHY; 3016 } 3017 } else { 3018 mdic = (((u32) phy_data) | 3019 (reg_addr << E1000_MDIC_REG_SHIFT) | 3020 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3021 (E1000_MDIC_OP_WRITE)); 3022 3023 ew32(MDIC, mdic); 3024 3025 /* Poll the ready bit to see if the MDI read 3026 * completed 3027 */ 3028 for (i = 0; i < 641; i++) { 3029 udelay(5); 3030 mdic = er32(MDIC); 3031 if (mdic & E1000_MDIC_READY) 3032 break; 3033 } 3034 if (!(mdic & E1000_MDIC_READY)) { 3035 e_dbg("MDI Write did not complete\n"); 3036 return -E1000_ERR_PHY; 3037 } 3038 } 3039 } else { 3040 /* We'll need to use the SW defined pins to shift the write 3041 * command out to the PHY. We first send a preamble to the PHY 3042 * to signal the beginning of the MII instruction. This is done 3043 * by sending 32 consecutive "1" bits. 3044 */ 3045 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 3046 3047 /* Now combine the remaining required fields that will indicate 3048 * a write operation. We use this method instead of calling the 3049 * e1000_shift_out_mdi_bits routine for each field in the 3050 * command. The format of a MII write instruction is as follows: 3051 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>. 3052 */ 3053 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 3054 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 3055 mdic <<= 16; 3056 mdic |= (u32) phy_data; 3057 3058 e1000_shift_out_mdi_bits(hw, mdic, 32); 3059 } 3060 3061 return E1000_SUCCESS; 3062} 3063 3064/** 3065 * e1000_phy_hw_reset - reset the phy, hardware style 3066 * @hw: Struct containing variables accessed by shared code 3067 * 3068 * Returns the PHY to the power-on reset state 3069 */ 3070s32 e1000_phy_hw_reset(struct e1000_hw *hw) 3071{ 3072 u32 ctrl, ctrl_ext; 3073 u32 led_ctrl; 3074 3075 e_dbg("Resetting Phy...\n"); 3076 3077 if (hw->mac_type > e1000_82543) { 3078 /* Read the device control register and assert the 3079 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. 3080 * For e1000 hardware, we delay for 10ms between the assert 3081 * and de-assert. 3082 */ 3083 ctrl = er32(CTRL); 3084 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 3085 E1000_WRITE_FLUSH(); 3086 3087 msleep(10); 3088 3089 ew32(CTRL, ctrl); 3090 E1000_WRITE_FLUSH(); 3091 3092 } else { 3093 /* Read the Extended Device Control Register, assert the 3094 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 3095 * out of reset. 3096 */ 3097 ctrl_ext = er32(CTRL_EXT); 3098 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3099 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3100 ew32(CTRL_EXT, ctrl_ext); 3101 E1000_WRITE_FLUSH(); 3102 msleep(10); 3103 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3104 ew32(CTRL_EXT, ctrl_ext); 3105 E1000_WRITE_FLUSH(); 3106 } 3107 udelay(150); 3108 3109 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3110 /* Configure activity LED after PHY reset */ 3111 led_ctrl = er32(LEDCTL); 3112 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3113 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3114 ew32(LEDCTL, led_ctrl); 3115 } 3116 3117 /* Wait for FW to finish PHY configuration. */ 3118 return e1000_get_phy_cfg_done(hw); 3119} 3120 3121/** 3122 * e1000_phy_reset - reset the phy to commit settings 3123 * @hw: Struct containing variables accessed by shared code 3124 * 3125 * Resets the PHY 3126 * Sets bit 15 of the MII Control register 3127 */ 3128s32 e1000_phy_reset(struct e1000_hw *hw) 3129{ 3130 s32 ret_val; 3131 u16 phy_data; 3132 3133 switch (hw->phy_type) { 3134 case e1000_phy_igp: 3135 ret_val = e1000_phy_hw_reset(hw); 3136 if (ret_val) 3137 return ret_val; 3138 break; 3139 default: 3140 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3141 if (ret_val) 3142 return ret_val; 3143 3144 phy_data |= MII_CR_RESET; 3145 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3146 if (ret_val) 3147 return ret_val; 3148 3149 udelay(1); 3150 break; 3151 } 3152 3153 if (hw->phy_type == e1000_phy_igp) 3154 e1000_phy_init_script(hw); 3155 3156 return E1000_SUCCESS; 3157} 3158 3159/** 3160 * e1000_detect_gig_phy - check the phy type 3161 * @hw: Struct containing variables accessed by shared code 3162 * 3163 * Probes the expected PHY address for known PHY IDs 3164 */ 3165static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3166{ 3167 s32 phy_init_status, ret_val; 3168 u16 phy_id_high, phy_id_low; 3169 bool match = false; 3170 3171 if (hw->phy_id != 0) 3172 return E1000_SUCCESS; 3173 3174 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3175 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3176 if (ret_val) 3177 return ret_val; 3178 3179 hw->phy_id = (u32) (phy_id_high << 16); 3180 udelay(20); 3181 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3182 if (ret_val) 3183 return ret_val; 3184 3185 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); 3186 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; 3187 3188 switch (hw->mac_type) { 3189 case e1000_82543: 3190 if (hw->phy_id == M88E1000_E_PHY_ID) 3191 match = true; 3192 break; 3193 case e1000_82544: 3194 if (hw->phy_id == M88E1000_I_PHY_ID) 3195 match = true; 3196 break; 3197 case e1000_82540: 3198 case e1000_82545: 3199 case e1000_82545_rev_3: 3200 case e1000_82546: 3201 case e1000_82546_rev_3: 3202 if (hw->phy_id == M88E1011_I_PHY_ID) 3203 match = true; 3204 break; 3205 case e1000_ce4100: 3206 if ((hw->phy_id == RTL8211B_PHY_ID) || 3207 (hw->phy_id == RTL8201N_PHY_ID) || 3208 (hw->phy_id == M88E1118_E_PHY_ID)) 3209 match = true; 3210 break; 3211 case e1000_82541: 3212 case e1000_82541_rev_2: 3213 case e1000_82547: 3214 case e1000_82547_rev_2: 3215 if (hw->phy_id == IGP01E1000_I_PHY_ID) 3216 match = true; 3217 break; 3218 default: 3219 e_dbg("Invalid MAC type %d\n", hw->mac_type); 3220 return -E1000_ERR_CONFIG; 3221 } 3222 phy_init_status = e1000_set_phy_type(hw); 3223 3224 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3225 e_dbg("PHY ID 0x%X detected\n", hw->phy_id); 3226 return E1000_SUCCESS; 3227 } 3228 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id); 3229 return -E1000_ERR_PHY; 3230} 3231 3232/** 3233 * e1000_phy_reset_dsp - reset DSP 3234 * @hw: Struct containing variables accessed by shared code 3235 * 3236 * Resets the PHY's DSP 3237 */ 3238static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3239{ 3240 s32 ret_val; 3241 3242 do { 3243 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3244 if (ret_val) 3245 break; 3246 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3247 if (ret_val) 3248 break; 3249 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3250 if (ret_val) 3251 break; 3252 ret_val = E1000_SUCCESS; 3253 } while (0); 3254 3255 return ret_val; 3256} 3257 3258/** 3259 * e1000_phy_igp_get_info - get igp specific registers 3260 * @hw: Struct containing variables accessed by shared code 3261 * @phy_info: PHY information structure 3262 * 3263 * Get PHY information from various PHY registers for igp PHY only. 3264 */ 3265static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3266 struct e1000_phy_info *phy_info) 3267{ 3268 s32 ret_val; 3269 u16 phy_data, min_length, max_length, average; 3270 e1000_rev_polarity polarity; 3271 3272 /* The downshift status is checked only once, after link is established, 3273 * and it stored in the hw->speed_downgraded parameter. 3274 */ 3275 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3276 3277 /* IGP01E1000 does not need to support it. */ 3278 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3279 3280 /* IGP01E1000 always correct polarity reversal */ 3281 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3282 3283 /* Check polarity status */ 3284 ret_val = e1000_check_polarity(hw, &polarity); 3285 if (ret_val) 3286 return ret_val; 3287 3288 phy_info->cable_polarity = polarity; 3289 3290 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3291 if (ret_val) 3292 return ret_val; 3293 3294 phy_info->mdix_mode = 3295 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> 3296 IGP01E1000_PSSR_MDIX_SHIFT); 3297 3298 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3299 IGP01E1000_PSSR_SPEED_1000MBPS) { 3300 /* Local/Remote Receiver Information are only valid @ 1000 3301 * Mbps 3302 */ 3303 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3304 if (ret_val) 3305 return ret_val; 3306 3307 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3308 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3309 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3310 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3311 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3312 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3313 3314 /* Get cable length */ 3315 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3316 if (ret_val) 3317 return ret_val; 3318 3319 /* Translate to old method */ 3320 average = (max_length + min_length) / 2; 3321 3322 if (average <= e1000_igp_cable_length_50) 3323 phy_info->cable_length = e1000_cable_length_50; 3324 else if (average <= e1000_igp_cable_length_80) 3325 phy_info->cable_length = e1000_cable_length_50_80; 3326 else if (average <= e1000_igp_cable_length_110) 3327 phy_info->cable_length = e1000_cable_length_80_110; 3328 else if (average <= e1000_igp_cable_length_140) 3329 phy_info->cable_length = e1000_cable_length_110_140; 3330 else 3331 phy_info->cable_length = e1000_cable_length_140; 3332 } 3333 3334 return E1000_SUCCESS; 3335} 3336 3337/** 3338 * e1000_phy_m88_get_info - get m88 specific registers 3339 * @hw: Struct containing variables accessed by shared code 3340 * @phy_info: PHY information structure 3341 * 3342 * Get PHY information from various PHY registers for m88 PHY only. 3343 */ 3344static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3345 struct e1000_phy_info *phy_info) 3346{ 3347 s32 ret_val; 3348 u16 phy_data; 3349 e1000_rev_polarity polarity; 3350 3351 /* The downshift status is checked only once, after link is established, 3352 * and it stored in the hw->speed_downgraded parameter. 3353 */ 3354 phy_info->downshift = (e1000_downshift) hw->speed_downgraded; 3355 3356 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3357 if (ret_val) 3358 return ret_val; 3359 3360 phy_info->extended_10bt_distance = 3361 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3362 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3363 e1000_10bt_ext_dist_enable_lower : 3364 e1000_10bt_ext_dist_enable_normal; 3365 3366 phy_info->polarity_correction = 3367 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3368 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3369 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3370 3371 /* Check polarity status */ 3372 ret_val = e1000_check_polarity(hw, &polarity); 3373 if (ret_val) 3374 return ret_val; 3375 phy_info->cable_polarity = polarity; 3376 3377 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3378 if (ret_val) 3379 return ret_val; 3380 3381 phy_info->mdix_mode = 3382 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> 3383 M88E1000_PSSR_MDIX_SHIFT); 3384 3385 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3386 /* Cable Length Estimation and Local/Remote Receiver Information 3387 * are only valid at 1000 Mbps. 3388 */ 3389 phy_info->cable_length = 3390 (e1000_cable_length) ((phy_data & 3391 M88E1000_PSSR_CABLE_LENGTH) >> 3392 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3393 3394 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3395 if (ret_val) 3396 return ret_val; 3397 3398 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3399 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3400 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3401 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3402 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3403 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3404 3405 } 3406 3407 return E1000_SUCCESS; 3408} 3409 3410/** 3411 * e1000_phy_get_info - request phy info 3412 * @hw: Struct containing variables accessed by shared code 3413 * @phy_info: PHY information structure 3414 * 3415 * Get PHY information from various PHY registers 3416 */ 3417s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3418{ 3419 s32 ret_val; 3420 u16 phy_data; 3421 3422 phy_info->cable_length = e1000_cable_length_undefined; 3423 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3424 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3425 phy_info->downshift = e1000_downshift_undefined; 3426 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3427 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3428 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3429 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3430 3431 if (hw->media_type != e1000_media_type_copper) { 3432 e_dbg("PHY info is only valid for copper media\n"); 3433 return -E1000_ERR_CONFIG; 3434 } 3435 3436 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3437 if (ret_val) 3438 return ret_val; 3439 3440 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3441 if (ret_val) 3442 return ret_val; 3443 3444 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3445 e_dbg("PHY info is only valid if link is up\n"); 3446 return -E1000_ERR_CONFIG; 3447 } 3448 3449 if (hw->phy_type == e1000_phy_igp) 3450 return e1000_phy_igp_get_info(hw, phy_info); 3451 else if ((hw->phy_type == e1000_phy_8211) || 3452 (hw->phy_type == e1000_phy_8201)) 3453 return E1000_SUCCESS; 3454 else 3455 return e1000_phy_m88_get_info(hw, phy_info); 3456} 3457 3458s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3459{ 3460 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 3461 e_dbg("Invalid MDI setting detected\n"); 3462 hw->mdix = 1; 3463 return -E1000_ERR_CONFIG; 3464 } 3465 return E1000_SUCCESS; 3466} 3467 3468/** 3469 * e1000_init_eeprom_params - initialize sw eeprom vars 3470 * @hw: Struct containing variables accessed by shared code 3471 * 3472 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3473 * is configured. 3474 */ 3475s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3476{ 3477 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3478 u32 eecd = er32(EECD); 3479 s32 ret_val = E1000_SUCCESS; 3480 u16 eeprom_size; 3481 3482 switch (hw->mac_type) { 3483 case e1000_82542_rev2_0: 3484 case e1000_82542_rev2_1: 3485 case e1000_82543: 3486 case e1000_82544: 3487 eeprom->type = e1000_eeprom_microwire; 3488 eeprom->word_size = 64; 3489 eeprom->opcode_bits = 3; 3490 eeprom->address_bits = 6; 3491 eeprom->delay_usec = 50; 3492 break; 3493 case e1000_82540: 3494 case e1000_82545: 3495 case e1000_82545_rev_3: 3496 case e1000_82546: 3497 case e1000_82546_rev_3: 3498 eeprom->type = e1000_eeprom_microwire; 3499 eeprom->opcode_bits = 3; 3500 eeprom->delay_usec = 50; 3501 if (eecd & E1000_EECD_SIZE) { 3502 eeprom->word_size = 256; 3503 eeprom->address_bits = 8; 3504 } else { 3505 eeprom->word_size = 64; 3506 eeprom->address_bits = 6; 3507 } 3508 break; 3509 case e1000_82541: 3510 case e1000_82541_rev_2: 3511 case e1000_82547: 3512 case e1000_82547_rev_2: 3513 if (eecd & E1000_EECD_TYPE) { 3514 eeprom->type = e1000_eeprom_spi; 3515 eeprom->opcode_bits = 8; 3516 eeprom->delay_usec = 1; 3517 if (eecd & E1000_EECD_ADDR_BITS) { 3518 eeprom->page_size = 32; 3519 eeprom->address_bits = 16; 3520 } else { 3521 eeprom->page_size = 8; 3522 eeprom->address_bits = 8; 3523 } 3524 } else { 3525 eeprom->type = e1000_eeprom_microwire; 3526 eeprom->opcode_bits = 3; 3527 eeprom->delay_usec = 50; 3528 if (eecd & E1000_EECD_ADDR_BITS) { 3529 eeprom->word_size = 256; 3530 eeprom->address_bits = 8; 3531 } else { 3532 eeprom->word_size = 64; 3533 eeprom->address_bits = 6; 3534 } 3535 } 3536 break; 3537 default: 3538 break; 3539 } 3540 3541 if (eeprom->type == e1000_eeprom_spi) { 3542 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 3543 * 128B to 32KB (incremented by powers of 2). 3544 */ 3545 /* Set to default value for initial eeprom read. */ 3546 eeprom->word_size = 64; 3547 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3548 if (ret_val) 3549 return ret_val; 3550 eeprom_size = 3551 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3552 /* 256B eeprom size was not supported in earlier hardware, so we 3553 * bump eeprom_size up one to ensure that "1" (which maps to 3554 * 256B) is never the result used in the shifting logic below. 3555 */ 3556 if (eeprom_size) 3557 eeprom_size++; 3558 3559 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3560 } 3561 return ret_val; 3562} 3563 3564/** 3565 * e1000_raise_ee_clk - Raises the EEPROM's clock input. 3566 * @hw: Struct containing variables accessed by shared code 3567 * @eecd: EECD's current value 3568 */ 3569static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3570{ 3571 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3572 * wait <delay> microseconds. 3573 */ 3574 *eecd = *eecd | E1000_EECD_SK; 3575 ew32(EECD, *eecd); 3576 E1000_WRITE_FLUSH(); 3577 udelay(hw->eeprom.delay_usec); 3578} 3579 3580/** 3581 * e1000_lower_ee_clk - Lowers the EEPROM's clock input. 3582 * @hw: Struct containing variables accessed by shared code 3583 * @eecd: EECD's current value 3584 */ 3585static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3586{ 3587 /* Lower the clock input to the EEPROM (by clearing the SK bit), and 3588 * then wait 50 microseconds. 3589 */ 3590 *eecd = *eecd & ~E1000_EECD_SK; 3591 ew32(EECD, *eecd); 3592 E1000_WRITE_FLUSH(); 3593 udelay(hw->eeprom.delay_usec); 3594} 3595 3596/** 3597 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. 3598 * @hw: Struct containing variables accessed by shared code 3599 * @data: data to send to the EEPROM 3600 * @count: number of bits to shift out 3601 */ 3602static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3603{ 3604 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3605 u32 eecd; 3606 u32 mask; 3607 3608 /* We need to shift "count" bits out to the EEPROM. So, value in the 3609 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3610 * In order to do this, "data" must be broken down into bits. 3611 */ 3612 mask = 0x01 << (count - 1); 3613 eecd = er32(EECD); 3614 if (eeprom->type == e1000_eeprom_microwire) { 3615 eecd &= ~E1000_EECD_DO; 3616 } else if (eeprom->type == e1000_eeprom_spi) { 3617 eecd |= E1000_EECD_DO; 3618 } 3619 do { 3620 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a 3621 * "1", and then raising and then lowering the clock (the SK bit 3622 * controls the clock input to the EEPROM). A "0" is shifted 3623 * out to the EEPROM by setting "DI" to "0" and then raising and 3624 * then lowering the clock. 3625 */ 3626 eecd &= ~E1000_EECD_DI; 3627 3628 if (data & mask) 3629 eecd |= E1000_EECD_DI; 3630 3631 ew32(EECD, eecd); 3632 E1000_WRITE_FLUSH(); 3633 3634 udelay(eeprom->delay_usec); 3635 3636 e1000_raise_ee_clk(hw, &eecd); 3637 e1000_lower_ee_clk(hw, &eecd); 3638 3639 mask = mask >> 1; 3640 3641 } while (mask); 3642 3643 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3644 eecd &= ~E1000_EECD_DI; 3645 ew32(EECD, eecd); 3646} 3647 3648/** 3649 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM 3650 * @hw: Struct containing variables accessed by shared code 3651 * @count: number of bits to shift in 3652 */ 3653static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3654{ 3655 u32 eecd; 3656 u32 i; 3657 u16 data; 3658 3659 /* In order to read a register from the EEPROM, we need to shift 'count' 3660 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3661 * input to the EEPROM (setting the SK bit), and then reading the value 3662 * of the "DO" bit. During this "shifting in" process the "DI" bit 3663 * should always be clear. 3664 */ 3665 3666 eecd = er32(EECD); 3667 3668 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3669 data = 0; 3670 3671 for (i = 0; i < count; i++) { 3672 data = data << 1; 3673 e1000_raise_ee_clk(hw, &eecd); 3674 3675 eecd = er32(EECD); 3676 3677 eecd &= ~(E1000_EECD_DI); 3678 if (eecd & E1000_EECD_DO) 3679 data |= 1; 3680 3681 e1000_lower_ee_clk(hw, &eecd); 3682 } 3683 3684 return data; 3685} 3686 3687/** 3688 * e1000_acquire_eeprom - Prepares EEPROM for access 3689 * @hw: Struct containing variables accessed by shared code 3690 * 3691 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3692 * function should be called before issuing a command to the EEPROM. 3693 */ 3694static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3695{ 3696 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3697 u32 eecd, i = 0; 3698 3699 eecd = er32(EECD); 3700 3701 /* Request EEPROM Access */ 3702 if (hw->mac_type > e1000_82544) { 3703 eecd |= E1000_EECD_REQ; 3704 ew32(EECD, eecd); 3705 eecd = er32(EECD); 3706 while ((!(eecd & E1000_EECD_GNT)) && 3707 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3708 i++; 3709 udelay(5); 3710 eecd = er32(EECD); 3711 } 3712 if (!(eecd & E1000_EECD_GNT)) { 3713 eecd &= ~E1000_EECD_REQ; 3714 ew32(EECD, eecd); 3715 e_dbg("Could not acquire EEPROM grant\n"); 3716 return -E1000_ERR_EEPROM; 3717 } 3718 } 3719 3720 /* Setup EEPROM for Read/Write */ 3721 3722 if (eeprom->type == e1000_eeprom_microwire) { 3723 /* Clear SK and DI */ 3724 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3725 ew32(EECD, eecd); 3726 3727 /* Set CS */ 3728 eecd |= E1000_EECD_CS; 3729 ew32(EECD, eecd); 3730 } else if (eeprom->type == e1000_eeprom_spi) { 3731 /* Clear SK and CS */ 3732 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3733 ew32(EECD, eecd); 3734 E1000_WRITE_FLUSH(); 3735 udelay(1); 3736 } 3737 3738 return E1000_SUCCESS; 3739} 3740 3741/** 3742 * e1000_standby_eeprom - Returns EEPROM to a "standby" state 3743 * @hw: Struct containing variables accessed by shared code 3744 */ 3745static void e1000_standby_eeprom(struct e1000_hw *hw) 3746{ 3747 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3748 u32 eecd; 3749 3750 eecd = er32(EECD); 3751 3752 if (eeprom->type == e1000_eeprom_microwire) { 3753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3754 ew32(EECD, eecd); 3755 E1000_WRITE_FLUSH(); 3756 udelay(eeprom->delay_usec); 3757 3758 /* Clock high */ 3759 eecd |= E1000_EECD_SK; 3760 ew32(EECD, eecd); 3761 E1000_WRITE_FLUSH(); 3762 udelay(eeprom->delay_usec); 3763 3764 /* Select EEPROM */ 3765 eecd |= E1000_EECD_CS; 3766 ew32(EECD, eecd); 3767 E1000_WRITE_FLUSH(); 3768 udelay(eeprom->delay_usec); 3769 3770 /* Clock low */ 3771 eecd &= ~E1000_EECD_SK; 3772 ew32(EECD, eecd); 3773 E1000_WRITE_FLUSH(); 3774 udelay(eeprom->delay_usec); 3775 } else if (eeprom->type == e1000_eeprom_spi) { 3776 /* Toggle CS to flush commands */ 3777 eecd |= E1000_EECD_CS; 3778 ew32(EECD, eecd); 3779 E1000_WRITE_FLUSH(); 3780 udelay(eeprom->delay_usec); 3781 eecd &= ~E1000_EECD_CS; 3782 ew32(EECD, eecd); 3783 E1000_WRITE_FLUSH(); 3784 udelay(eeprom->delay_usec); 3785 } 3786} 3787 3788/** 3789 * e1000_release_eeprom - drop chip select 3790 * @hw: Struct containing variables accessed by shared code 3791 * 3792 * Terminates a command by inverting the EEPROM's chip select pin 3793 */ 3794static void e1000_release_eeprom(struct e1000_hw *hw) 3795{ 3796 u32 eecd; 3797 3798 eecd = er32(EECD); 3799 3800 if (hw->eeprom.type == e1000_eeprom_spi) { 3801 eecd |= E1000_EECD_CS; /* Pull CS high */ 3802 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3803 3804 ew32(EECD, eecd); 3805 E1000_WRITE_FLUSH(); 3806 3807 udelay(hw->eeprom.delay_usec); 3808 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 3809 /* cleanup eeprom */ 3810 3811 /* CS on Microwire is active-high */ 3812 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3813 3814 ew32(EECD, eecd); 3815 3816 /* Rising edge of clock */ 3817 eecd |= E1000_EECD_SK; 3818 ew32(EECD, eecd); 3819 E1000_WRITE_FLUSH(); 3820 udelay(hw->eeprom.delay_usec); 3821 3822 /* Falling edge of clock */ 3823 eecd &= ~E1000_EECD_SK; 3824 ew32(EECD, eecd); 3825 E1000_WRITE_FLUSH(); 3826 udelay(hw->eeprom.delay_usec); 3827 } 3828 3829 /* Stop requesting EEPROM access */ 3830 if (hw->mac_type > e1000_82544) { 3831 eecd &= ~E1000_EECD_REQ; 3832 ew32(EECD, eecd); 3833 } 3834} 3835 3836/** 3837 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. 3838 * @hw: Struct containing variables accessed by shared code 3839 */ 3840static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3841{ 3842 u16 retry_count = 0; 3843 u8 spi_stat_reg; 3844 3845 /* Read "Status Register" repeatedly until the LSB is cleared. The 3846 * EEPROM will signal that the command has been completed by clearing 3847 * bit 0 of the internal status register. If it's not cleared within 3848 * 5 milliseconds, then error out. 3849 */ 3850 retry_count = 0; 3851 do { 3852 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3853 hw->eeprom.opcode_bits); 3854 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); 3855 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3856 break; 3857 3858 udelay(5); 3859 retry_count += 5; 3860 3861 e1000_standby_eeprom(hw); 3862 } while (retry_count < EEPROM_MAX_RETRY_SPI); 3863 3864 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3865 * only 0-5mSec on 5V devices) 3866 */ 3867 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3868 e_dbg("SPI EEPROM Status error\n"); 3869 return -E1000_ERR_EEPROM; 3870 } 3871 3872 return E1000_SUCCESS; 3873} 3874 3875/** 3876 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. 3877 * @hw: Struct containing variables accessed by shared code 3878 * @offset: offset of word in the EEPROM to read 3879 * @data: word read from the EEPROM 3880 * @words: number of words to read 3881 */ 3882s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3883{ 3884 s32 ret; 3885 spin_lock(&e1000_eeprom_lock); 3886 ret = e1000_do_read_eeprom(hw, offset, words, data); 3887 spin_unlock(&e1000_eeprom_lock); 3888 return ret; 3889} 3890 3891static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 3892 u16 *data) 3893{ 3894 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3895 u32 i = 0; 3896 3897 if (hw->mac_type == e1000_ce4100) { 3898 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words, 3899 data); 3900 return E1000_SUCCESS; 3901 } 3902 3903 /* If eeprom is not yet detected, do so now */ 3904 if (eeprom->word_size == 0) 3905 e1000_init_eeprom_params(hw); 3906 3907 /* A check for invalid values: offset too large, too many words, and 3908 * not enough words. 3909 */ 3910 if ((offset >= eeprom->word_size) 3911 || (words > eeprom->word_size - offset) || (words == 0)) { 3912 e_dbg("\"words\" parameter out of bounds. Words = %d," 3913 "size = %d\n", offset, eeprom->word_size); 3914 return -E1000_ERR_EEPROM; 3915 } 3916 3917 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 3918 * directly. In this case, we need to acquire the EEPROM so that 3919 * FW or other port software does not interrupt. 3920 */ 3921 /* Prepare the EEPROM for bit-bang reading */ 3922 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3923 return -E1000_ERR_EEPROM; 3924 3925 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3926 * acquired the EEPROM at this point, so any returns should release it 3927 */ 3928 if (eeprom->type == e1000_eeprom_spi) { 3929 u16 word_in; 3930 u8 read_opcode = EEPROM_READ_OPCODE_SPI; 3931 3932 if (e1000_spi_eeprom_ready(hw)) { 3933 e1000_release_eeprom(hw); 3934 return -E1000_ERR_EEPROM; 3935 } 3936 3937 e1000_standby_eeprom(hw); 3938 3939 /* Some SPI eeproms use the 8th address bit embedded in the 3940 * opcode 3941 */ 3942 if ((eeprom->address_bits == 8) && (offset >= 128)) 3943 read_opcode |= EEPROM_A8_OPCODE_SPI; 3944 3945 /* Send the READ command (opcode + addr) */ 3946 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3947 e1000_shift_out_ee_bits(hw, (u16) (offset * 2), 3948 eeprom->address_bits); 3949 3950 /* Read the data. The address of the eeprom internally 3951 * increments with each byte (spi) being read, saving on the 3952 * overhead of eeprom setup and tear-down. The address counter 3953 * will roll over if reading beyond the size of the eeprom, thus 3954 * allowing the entire memory to be read starting from any 3955 * offset. 3956 */ 3957 for (i = 0; i < words; i++) { 3958 word_in = e1000_shift_in_ee_bits(hw, 16); 3959 data[i] = (word_in >> 8) | (word_in << 8); 3960 } 3961 } else if (eeprom->type == e1000_eeprom_microwire) { 3962 for (i = 0; i < words; i++) { 3963 /* Send the READ command (opcode + addr) */ 3964 e1000_shift_out_ee_bits(hw, 3965 EEPROM_READ_OPCODE_MICROWIRE, 3966 eeprom->opcode_bits); 3967 e1000_shift_out_ee_bits(hw, (u16) (offset + i), 3968 eeprom->address_bits); 3969 3970 /* Read the data. For microwire, each word requires the 3971 * overhead of eeprom setup and tear-down. 3972 */ 3973 data[i] = e1000_shift_in_ee_bits(hw, 16); 3974 e1000_standby_eeprom(hw); 3975 } 3976 } 3977 3978 /* End this read operation */ 3979 e1000_release_eeprom(hw); 3980 3981 return E1000_SUCCESS; 3982} 3983 3984/** 3985 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum 3986 * @hw: Struct containing variables accessed by shared code 3987 * 3988 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3989 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3990 * valid. 3991 */ 3992s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 3993{ 3994 u16 checksum = 0; 3995 u16 i, eeprom_data; 3996 3997 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3998 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3999 e_dbg("EEPROM Read Error\n"); 4000 return -E1000_ERR_EEPROM; 4001 } 4002 checksum += eeprom_data; 4003 } 4004 4005#ifdef CONFIG_PARISC 4006 /* This is a signature and not a checksum on HP c8000 */ 4007 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) 4008 return E1000_SUCCESS; 4009 4010#endif 4011 if (checksum == (u16) EEPROM_SUM) 4012 return E1000_SUCCESS; 4013 else { 4014 e_dbg("EEPROM Checksum Invalid\n"); 4015 return -E1000_ERR_EEPROM; 4016 } 4017} 4018 4019/** 4020 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum 4021 * @hw: Struct containing variables accessed by shared code 4022 * 4023 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 4024 * Writes the difference to word offset 63 of the EEPROM. 4025 */ 4026s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 4027{ 4028 u16 checksum = 0; 4029 u16 i, eeprom_data; 4030 4031 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 4032 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 4033 e_dbg("EEPROM Read Error\n"); 4034 return -E1000_ERR_EEPROM; 4035 } 4036 checksum += eeprom_data; 4037 } 4038 checksum = (u16) EEPROM_SUM - checksum; 4039 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4040 e_dbg("EEPROM Write Error\n"); 4041 return -E1000_ERR_EEPROM; 4042 } 4043 return E1000_SUCCESS; 4044} 4045 4046/** 4047 * e1000_write_eeprom - write words to the different EEPROM types. 4048 * @hw: Struct containing variables accessed by shared code 4049 * @offset: offset within the EEPROM to be written to 4050 * @words: number of words to write 4051 * @data: 16 bit word to be written to the EEPROM 4052 * 4053 * If e1000_update_eeprom_checksum is not called after this function, the 4054 * EEPROM will most likely contain an invalid checksum. 4055 */ 4056s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 4057{ 4058 s32 ret; 4059 spin_lock(&e1000_eeprom_lock); 4060 ret = e1000_do_write_eeprom(hw, offset, words, data); 4061 spin_unlock(&e1000_eeprom_lock); 4062 return ret; 4063} 4064 4065static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, 4066 u16 *data) 4067{ 4068 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4069 s32 status = 0; 4070 4071 if (hw->mac_type == e1000_ce4100) { 4072 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words, 4073 data); 4074 return E1000_SUCCESS; 4075 } 4076 4077 /* If eeprom is not yet detected, do so now */ 4078 if (eeprom->word_size == 0) 4079 e1000_init_eeprom_params(hw); 4080 4081 /* A check for invalid values: offset too large, too many words, and 4082 * not enough words. 4083 */ 4084 if ((offset >= eeprom->word_size) 4085 || (words > eeprom->word_size - offset) || (words == 0)) { 4086 e_dbg("\"words\" parameter out of bounds\n"); 4087 return -E1000_ERR_EEPROM; 4088 } 4089 4090 /* Prepare the EEPROM for writing */ 4091 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4092 return -E1000_ERR_EEPROM; 4093 4094 if (eeprom->type == e1000_eeprom_microwire) { 4095 status = e1000_write_eeprom_microwire(hw, offset, words, data); 4096 } else { 4097 status = e1000_write_eeprom_spi(hw, offset, words, data); 4098 msleep(10); 4099 } 4100 4101 /* Done with writing */ 4102 e1000_release_eeprom(hw); 4103 4104 return status; 4105} 4106 4107/** 4108 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. 4109 * @hw: Struct containing variables accessed by shared code 4110 * @offset: offset within the EEPROM to be written to 4111 * @words: number of words to write 4112 * @data: pointer to array of 8 bit words to be written to the EEPROM 4113 */ 4114static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 4115 u16 *data) 4116{ 4117 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4118 u16 widx = 0; 4119 4120 while (widx < words) { 4121 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 4122 4123 if (e1000_spi_eeprom_ready(hw)) 4124 return -E1000_ERR_EEPROM; 4125 4126 e1000_standby_eeprom(hw); 4127 4128 /* Send the WRITE ENABLE command (8 bit opcode ) */ 4129 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 4130 eeprom->opcode_bits); 4131 4132 e1000_standby_eeprom(hw); 4133 4134 /* Some SPI eeproms use the 8th address bit embedded in the 4135 * opcode 4136 */ 4137 if ((eeprom->address_bits == 8) && (offset >= 128)) 4138 write_opcode |= EEPROM_A8_OPCODE_SPI; 4139 4140 /* Send the Write command (8-bit opcode + addr) */ 4141 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 4142 4143 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), 4144 eeprom->address_bits); 4145 4146 /* Send the data */ 4147 4148 /* Loop to allow for up to whole page write (32 bytes) of 4149 * eeprom 4150 */ 4151 while (widx < words) { 4152 u16 word_out = data[widx]; 4153 word_out = (word_out >> 8) | (word_out << 8); 4154 e1000_shift_out_ee_bits(hw, word_out, 16); 4155 widx++; 4156 4157 /* Some larger eeprom sizes are capable of a 32-byte 4158 * PAGE WRITE operation, while the smaller eeproms are 4159 * capable of an 8-byte PAGE WRITE operation. Break the 4160 * inner loop to pass new address 4161 */ 4162 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 4163 e1000_standby_eeprom(hw); 4164 break; 4165 } 4166 } 4167 } 4168 4169 return E1000_SUCCESS; 4170} 4171 4172/** 4173 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. 4174 * @hw: Struct containing variables accessed by shared code 4175 * @offset: offset within the EEPROM to be written to 4176 * @words: number of words to write 4177 * @data: pointer to array of 8 bit words to be written to the EEPROM 4178 */ 4179static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 4180 u16 words, u16 *data) 4181{ 4182 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4183 u32 eecd; 4184 u16 words_written = 0; 4185 u16 i = 0; 4186 4187 /* Send the write enable command to the EEPROM (3-bit opcode plus 4188 * 6/8-bit dummy address beginning with 11). It's less work to include 4189 * the 11 of the dummy address as part of the opcode than it is to shift 4190 * it over the correct number of bits for the address. This puts the 4191 * EEPROM into write/erase mode. 4192 */ 4193 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 4194 (u16) (eeprom->opcode_bits + 2)); 4195 4196 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4197 4198 /* Prepare the EEPROM */ 4199 e1000_standby_eeprom(hw); 4200 4201 while (words_written < words) { 4202 /* Send the Write command (3-bit opcode + addr) */ 4203 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 4204 eeprom->opcode_bits); 4205 4206 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), 4207 eeprom->address_bits); 4208 4209 /* Send the data */ 4210 e1000_shift_out_ee_bits(hw, data[words_written], 16); 4211 4212 /* Toggle the CS line. This in effect tells the EEPROM to 4213 * execute the previous command. 4214 */ 4215 e1000_standby_eeprom(hw); 4216 4217 /* Read DO repeatedly until it is high (equal to '1'). The 4218 * EEPROM will signal that the command has been completed by 4219 * raising the DO signal. If DO does not go high in 10 4220 * milliseconds, then error out. 4221 */ 4222 for (i = 0; i < 200; i++) { 4223 eecd = er32(EECD); 4224 if (eecd & E1000_EECD_DO) 4225 break; 4226 udelay(50); 4227 } 4228 if (i == 200) { 4229 e_dbg("EEPROM Write did not complete\n"); 4230 return -E1000_ERR_EEPROM; 4231 } 4232 4233 /* Recover from write */ 4234 e1000_standby_eeprom(hw); 4235 4236 words_written++; 4237 } 4238 4239 /* Send the write disable command to the EEPROM (3-bit opcode plus 4240 * 6/8-bit dummy address beginning with 10). It's less work to include 4241 * the 10 of the dummy address as part of the opcode than it is to shift 4242 * it over the correct number of bits for the address. This takes the 4243 * EEPROM out of write/erase mode. 4244 */ 4245 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 4246 (u16) (eeprom->opcode_bits + 2)); 4247 4248 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); 4249 4250 return E1000_SUCCESS; 4251} 4252 4253/** 4254 * e1000_read_mac_addr - read the adapters MAC from eeprom 4255 * @hw: Struct containing variables accessed by shared code 4256 * 4257 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4258 * second function of dual function devices 4259 */ 4260s32 e1000_read_mac_addr(struct e1000_hw *hw) 4261{ 4262 u16 offset; 4263 u16 eeprom_data, i; 4264 4265 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4266 offset = i >> 1; 4267 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4268 e_dbg("EEPROM Read Error\n"); 4269 return -E1000_ERR_EEPROM; 4270 } 4271 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); 4272 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); 4273 } 4274 4275 switch (hw->mac_type) { 4276 default: 4277 break; 4278 case e1000_82546: 4279 case e1000_82546_rev_3: 4280 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4281 hw->perm_mac_addr[5] ^= 0x01; 4282 break; 4283 } 4284 4285 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4286 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4287 return E1000_SUCCESS; 4288} 4289 4290/** 4291 * e1000_init_rx_addrs - Initializes receive address filters. 4292 * @hw: Struct containing variables accessed by shared code 4293 * 4294 * Places the MAC address in receive address register 0 and clears the rest 4295 * of the receive address registers. Clears the multicast table. Assumes 4296 * the receiver is in reset when the routine is called. 4297 */ 4298static void e1000_init_rx_addrs(struct e1000_hw *hw) 4299{ 4300 u32 i; 4301 u32 rar_num; 4302 4303 /* Setup the receive address. */ 4304 e_dbg("Programming MAC Address into RAR[0]\n"); 4305 4306 e1000_rar_set(hw, hw->mac_addr, 0); 4307 4308 rar_num = E1000_RAR_ENTRIES; 4309 4310 /* Zero out the other 15 receive addresses. */ 4311 e_dbg("Clearing RAR[1-15]\n"); 4312 for (i = 1; i < rar_num; i++) { 4313 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4314 E1000_WRITE_FLUSH(); 4315 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4316 E1000_WRITE_FLUSH(); 4317 } 4318} 4319 4320/** 4321 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table 4322 * @hw: Struct containing variables accessed by shared code 4323 * @mc_addr: the multicast address to hash 4324 */ 4325u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4326{ 4327 u32 hash_value = 0; 4328 4329 /* The portion of the address that is used for the hash table is 4330 * determined by the mc_filter_type setting. 4331 */ 4332 switch (hw->mc_filter_type) { 4333 /* [0] [1] [2] [3] [4] [5] 4334 * 01 AA 00 12 34 56 4335 * LSB MSB 4336 */ 4337 case 0: 4338 /* [47:36] i.e. 0x563 for above example address */ 4339 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); 4340 break; 4341 case 1: 4342 /* [46:35] i.e. 0xAC6 for above example address */ 4343 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); 4344 break; 4345 case 2: 4346 /* [45:34] i.e. 0x5D8 for above example address */ 4347 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); 4348 break; 4349 case 3: 4350 /* [43:32] i.e. 0x634 for above example address */ 4351 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); 4352 break; 4353 } 4354 4355 hash_value &= 0xFFF; 4356 return hash_value; 4357} 4358 4359/** 4360 * e1000_rar_set - Puts an ethernet address into a receive address register. 4361 * @hw: Struct containing variables accessed by shared code 4362 * @addr: Address to put into receive address register 4363 * @index: Receive address register to write 4364 */ 4365void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4366{ 4367 u32 rar_low, rar_high; 4368 4369 /* HW expects these in little endian so we reverse the byte order 4370 * from network order (big endian) to little endian 4371 */ 4372 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 4373 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 4374 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 4375 4376 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 4377 * unit hang. 4378 * 4379 * Description: 4380 * If there are any Rx frames queued up or otherwise present in the HW 4381 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 4382 * hang. To work around this issue, we have to disable receives and 4383 * flush out all Rx frames before we enable RSS. To do so, we modify we 4384 * redirect all Rx traffic to manageability and then reset the HW. 4385 * This flushes away Rx frames, and (since the redirections to 4386 * manageability persists across resets) keeps new ones from coming in 4387 * while we work. Then, we clear the Address Valid AV bit for all MAC 4388 * addresses and undo the re-direction to manageability. 4389 * Now, frames are coming in again, but the MAC won't accept them, so 4390 * far so good. We now proceed to initialize RSS (if necessary) and 4391 * configure the Rx unit. Last, we re-enable the AV bits and continue 4392 * on our merry way. 4393 */ 4394 switch (hw->mac_type) { 4395 default: 4396 /* Indicate to hardware the Address is Valid. */ 4397 rar_high |= E1000_RAH_AV; 4398 break; 4399 } 4400 4401 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 4402 E1000_WRITE_FLUSH(); 4403 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 4404 E1000_WRITE_FLUSH(); 4405} 4406 4407/** 4408 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. 4409 * @hw: Struct containing variables accessed by shared code 4410 * @offset: Offset in VLAN filer table to write 4411 * @value: Value to write into VLAN filter table 4412 */ 4413void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4414{ 4415 u32 temp; 4416 4417 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4418 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4419 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4420 E1000_WRITE_FLUSH(); 4421 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4422 E1000_WRITE_FLUSH(); 4423 } else { 4424 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4425 E1000_WRITE_FLUSH(); 4426 } 4427} 4428 4429/** 4430 * e1000_clear_vfta - Clears the VLAN filer table 4431 * @hw: Struct containing variables accessed by shared code 4432 */ 4433static void e1000_clear_vfta(struct e1000_hw *hw) 4434{ 4435 u32 offset; 4436 u32 vfta_value = 0; 4437 u32 vfta_offset = 0; 4438 u32 vfta_bit_in_reg = 0; 4439 4440 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4441 /* If the offset we want to clear is the same offset of the 4442 * manageability VLAN ID, then clear all bits except that of the 4443 * manageability unit 4444 */ 4445 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 4446 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 4447 E1000_WRITE_FLUSH(); 4448 } 4449} 4450 4451static s32 e1000_id_led_init(struct e1000_hw *hw) 4452{ 4453 u32 ledctl; 4454 const u32 ledctl_mask = 0x000000FF; 4455 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4456 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4457 u16 eeprom_data, i, temp; 4458 const u16 led_mask = 0x0F; 4459 4460 if (hw->mac_type < e1000_82540) { 4461 /* Nothing to do */ 4462 return E1000_SUCCESS; 4463 } 4464 4465 ledctl = er32(LEDCTL); 4466 hw->ledctl_default = ledctl; 4467 hw->ledctl_mode1 = hw->ledctl_default; 4468 hw->ledctl_mode2 = hw->ledctl_default; 4469 4470 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4471 e_dbg("EEPROM Read Error\n"); 4472 return -E1000_ERR_EEPROM; 4473 } 4474 4475 if ((eeprom_data == ID_LED_RESERVED_0000) || 4476 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4477 eeprom_data = ID_LED_DEFAULT; 4478 } 4479 4480 for (i = 0; i < 4; i++) { 4481 temp = (eeprom_data >> (i << 2)) & led_mask; 4482 switch (temp) { 4483 case ID_LED_ON1_DEF2: 4484 case ID_LED_ON1_ON2: 4485 case ID_LED_ON1_OFF2: 4486 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4487 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4488 break; 4489 case ID_LED_OFF1_DEF2: 4490 case ID_LED_OFF1_ON2: 4491 case ID_LED_OFF1_OFF2: 4492 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4493 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4494 break; 4495 default: 4496 /* Do nothing */ 4497 break; 4498 } 4499 switch (temp) { 4500 case ID_LED_DEF1_ON2: 4501 case ID_LED_ON1_ON2: 4502 case ID_LED_OFF1_ON2: 4503 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4504 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4505 break; 4506 case ID_LED_DEF1_OFF2: 4507 case ID_LED_ON1_OFF2: 4508 case ID_LED_OFF1_OFF2: 4509 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4510 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4511 break; 4512 default: 4513 /* Do nothing */ 4514 break; 4515 } 4516 } 4517 return E1000_SUCCESS; 4518} 4519 4520/** 4521 * e1000_setup_led 4522 * @hw: Struct containing variables accessed by shared code 4523 * 4524 * Prepares SW controlable LED for use and saves the current state of the LED. 4525 */ 4526s32 e1000_setup_led(struct e1000_hw *hw) 4527{ 4528 u32 ledctl; 4529 s32 ret_val = E1000_SUCCESS; 4530 4531 switch (hw->mac_type) { 4532 case e1000_82542_rev2_0: 4533 case e1000_82542_rev2_1: 4534 case e1000_82543: 4535 case e1000_82544: 4536 /* No setup necessary */ 4537 break; 4538 case e1000_82541: 4539 case e1000_82547: 4540 case e1000_82541_rev_2: 4541 case e1000_82547_rev_2: 4542 /* Turn off PHY Smart Power Down (if enabled) */ 4543 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 4544 &hw->phy_spd_default); 4545 if (ret_val) 4546 return ret_val; 4547 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4548 (u16) (hw->phy_spd_default & 4549 ~IGP01E1000_GMII_SPD)); 4550 if (ret_val) 4551 return ret_val; 4552 /* Fall Through */ 4553 default: 4554 if (hw->media_type == e1000_media_type_fiber) { 4555 ledctl = er32(LEDCTL); 4556 /* Save current LEDCTL settings */ 4557 hw->ledctl_default = ledctl; 4558 /* Turn off LED0 */ 4559 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 4560 E1000_LEDCTL_LED0_BLINK | 4561 E1000_LEDCTL_LED0_MODE_MASK); 4562 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 4563 E1000_LEDCTL_LED0_MODE_SHIFT); 4564 ew32(LEDCTL, ledctl); 4565 } else if (hw->media_type == e1000_media_type_copper) 4566 ew32(LEDCTL, hw->ledctl_mode1); 4567 break; 4568 } 4569 4570 return E1000_SUCCESS; 4571} 4572 4573/** 4574 * e1000_cleanup_led - Restores the saved state of the SW controlable LED. 4575 * @hw: Struct containing variables accessed by shared code 4576 */ 4577s32 e1000_cleanup_led(struct e1000_hw *hw) 4578{ 4579 s32 ret_val = E1000_SUCCESS; 4580 4581 switch (hw->mac_type) { 4582 case e1000_82542_rev2_0: 4583 case e1000_82542_rev2_1: 4584 case e1000_82543: 4585 case e1000_82544: 4586 /* No cleanup necessary */ 4587 break; 4588 case e1000_82541: 4589 case e1000_82547: 4590 case e1000_82541_rev_2: 4591 case e1000_82547_rev_2: 4592 /* Turn on PHY Smart Power Down (if previously enabled) */ 4593 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4594 hw->phy_spd_default); 4595 if (ret_val) 4596 return ret_val; 4597 /* Fall Through */ 4598 default: 4599 /* Restore LEDCTL settings */ 4600 ew32(LEDCTL, hw->ledctl_default); 4601 break; 4602 } 4603 4604 return E1000_SUCCESS; 4605} 4606 4607/** 4608 * e1000_led_on - Turns on the software controllable LED 4609 * @hw: Struct containing variables accessed by shared code 4610 */ 4611s32 e1000_led_on(struct e1000_hw *hw) 4612{ 4613 u32 ctrl = er32(CTRL); 4614 4615 switch (hw->mac_type) { 4616 case e1000_82542_rev2_0: 4617 case e1000_82542_rev2_1: 4618 case e1000_82543: 4619 /* Set SW Defineable Pin 0 to turn on the LED */ 4620 ctrl |= E1000_CTRL_SWDPIN0; 4621 ctrl |= E1000_CTRL_SWDPIO0; 4622 break; 4623 case e1000_82544: 4624 if (hw->media_type == e1000_media_type_fiber) { 4625 /* Set SW Defineable Pin 0 to turn on the LED */ 4626 ctrl |= E1000_CTRL_SWDPIN0; 4627 ctrl |= E1000_CTRL_SWDPIO0; 4628 } else { 4629 /* Clear SW Defineable Pin 0 to turn on the LED */ 4630 ctrl &= ~E1000_CTRL_SWDPIN0; 4631 ctrl |= E1000_CTRL_SWDPIO0; 4632 } 4633 break; 4634 default: 4635 if (hw->media_type == e1000_media_type_fiber) { 4636 /* Clear SW Defineable Pin 0 to turn on the LED */ 4637 ctrl &= ~E1000_CTRL_SWDPIN0; 4638 ctrl |= E1000_CTRL_SWDPIO0; 4639 } else if (hw->media_type == e1000_media_type_copper) { 4640 ew32(LEDCTL, hw->ledctl_mode2); 4641 return E1000_SUCCESS; 4642 } 4643 break; 4644 } 4645 4646 ew32(CTRL, ctrl); 4647 4648 return E1000_SUCCESS; 4649} 4650 4651/** 4652 * e1000_led_off - Turns off the software controllable LED 4653 * @hw: Struct containing variables accessed by shared code 4654 */ 4655s32 e1000_led_off(struct e1000_hw *hw) 4656{ 4657 u32 ctrl = er32(CTRL); 4658 4659 switch (hw->mac_type) { 4660 case e1000_82542_rev2_0: 4661 case e1000_82542_rev2_1: 4662 case e1000_82543: 4663 /* Clear SW Defineable Pin 0 to turn off the LED */ 4664 ctrl &= ~E1000_CTRL_SWDPIN0; 4665 ctrl |= E1000_CTRL_SWDPIO0; 4666 break; 4667 case e1000_82544: 4668 if (hw->media_type == e1000_media_type_fiber) { 4669 /* Clear SW Defineable Pin 0 to turn off the LED */ 4670 ctrl &= ~E1000_CTRL_SWDPIN0; 4671 ctrl |= E1000_CTRL_SWDPIO0; 4672 } else { 4673 /* Set SW Defineable Pin 0 to turn off the LED */ 4674 ctrl |= E1000_CTRL_SWDPIN0; 4675 ctrl |= E1000_CTRL_SWDPIO0; 4676 } 4677 break; 4678 default: 4679 if (hw->media_type == e1000_media_type_fiber) { 4680 /* Set SW Defineable Pin 0 to turn off the LED */ 4681 ctrl |= E1000_CTRL_SWDPIN0; 4682 ctrl |= E1000_CTRL_SWDPIO0; 4683 } else if (hw->media_type == e1000_media_type_copper) { 4684 ew32(LEDCTL, hw->ledctl_mode1); 4685 return E1000_SUCCESS; 4686 } 4687 break; 4688 } 4689 4690 ew32(CTRL, ctrl); 4691 4692 return E1000_SUCCESS; 4693} 4694 4695/** 4696 * e1000_clear_hw_cntrs - Clears all hardware statistics counters. 4697 * @hw: Struct containing variables accessed by shared code 4698 */ 4699static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4700{ 4701 volatile u32 temp; 4702 4703 temp = er32(CRCERRS); 4704 temp = er32(SYMERRS); 4705 temp = er32(MPC); 4706 temp = er32(SCC); 4707 temp = er32(ECOL); 4708 temp = er32(MCC); 4709 temp = er32(LATECOL); 4710 temp = er32(COLC); 4711 temp = er32(DC); 4712 temp = er32(SEC); 4713 temp = er32(RLEC); 4714 temp = er32(XONRXC); 4715 temp = er32(XONTXC); 4716 temp = er32(XOFFRXC); 4717 temp = er32(XOFFTXC); 4718 temp = er32(FCRUC); 4719 4720 temp = er32(PRC64); 4721 temp = er32(PRC127); 4722 temp = er32(PRC255); 4723 temp = er32(PRC511); 4724 temp = er32(PRC1023); 4725 temp = er32(PRC1522); 4726 4727 temp = er32(GPRC); 4728 temp = er32(BPRC); 4729 temp = er32(MPRC); 4730 temp = er32(GPTC); 4731 temp = er32(GORCL); 4732 temp = er32(GORCH); 4733 temp = er32(GOTCL); 4734 temp = er32(GOTCH); 4735 temp = er32(RNBC); 4736 temp = er32(RUC); 4737 temp = er32(RFC); 4738 temp = er32(ROC); 4739 temp = er32(RJC); 4740 temp = er32(TORL); 4741 temp = er32(TORH); 4742 temp = er32(TOTL); 4743 temp = er32(TOTH); 4744 temp = er32(TPR); 4745 temp = er32(TPT); 4746 4747 temp = er32(PTC64); 4748 temp = er32(PTC127); 4749 temp = er32(PTC255); 4750 temp = er32(PTC511); 4751 temp = er32(PTC1023); 4752 temp = er32(PTC1522); 4753 4754 temp = er32(MPTC); 4755 temp = er32(BPTC); 4756 4757 if (hw->mac_type < e1000_82543) 4758 return; 4759 4760 temp = er32(ALGNERRC); 4761 temp = er32(RXERRC); 4762 temp = er32(TNCRS); 4763 temp = er32(CEXTERR); 4764 temp = er32(TSCTC); 4765 temp = er32(TSCTFC); 4766 4767 if (hw->mac_type <= e1000_82544) 4768 return; 4769 4770 temp = er32(MGTPRC); 4771 temp = er32(MGTPDC); 4772 temp = er32(MGTPTC); 4773} 4774 4775/** 4776 * e1000_reset_adaptive - Resets Adaptive IFS to its default state. 4777 * @hw: Struct containing variables accessed by shared code 4778 * 4779 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4780 * hw->ifs_params_forced to true. However, you must initialize hw-> 4781 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4782 * before calling this function. 4783 */ 4784void e1000_reset_adaptive(struct e1000_hw *hw) 4785{ 4786 if (hw->adaptive_ifs) { 4787 if (!hw->ifs_params_forced) { 4788 hw->current_ifs_val = 0; 4789 hw->ifs_min_val = IFS_MIN; 4790 hw->ifs_max_val = IFS_MAX; 4791 hw->ifs_step_size = IFS_STEP; 4792 hw->ifs_ratio = IFS_RATIO; 4793 } 4794 hw->in_ifs_mode = false; 4795 ew32(AIT, 0); 4796 } else { 4797 e_dbg("Not in Adaptive IFS mode!\n"); 4798 } 4799} 4800 4801/** 4802 * e1000_update_adaptive - update adaptive IFS 4803 * @hw: Struct containing variables accessed by shared code 4804 * @tx_packets: Number of transmits since last callback 4805 * @total_collisions: Number of collisions since last callback 4806 * 4807 * Called during the callback/watchdog routine to update IFS value based on 4808 * the ratio of transmits to collisions. 4809 */ 4810void e1000_update_adaptive(struct e1000_hw *hw) 4811{ 4812 if (hw->adaptive_ifs) { 4813 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { 4814 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4815 hw->in_ifs_mode = true; 4816 if (hw->current_ifs_val < hw->ifs_max_val) { 4817 if (hw->current_ifs_val == 0) 4818 hw->current_ifs_val = 4819 hw->ifs_min_val; 4820 else 4821 hw->current_ifs_val += 4822 hw->ifs_step_size; 4823 ew32(AIT, hw->current_ifs_val); 4824 } 4825 } 4826 } else { 4827 if (hw->in_ifs_mode 4828 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4829 hw->current_ifs_val = 0; 4830 hw->in_ifs_mode = false; 4831 ew32(AIT, 0); 4832 } 4833 } 4834 } else { 4835 e_dbg("Not in Adaptive IFS mode!\n"); 4836 } 4837} 4838 4839/** 4840 * e1000_get_bus_info 4841 * @hw: Struct containing variables accessed by shared code 4842 * 4843 * Gets the current PCI bus type, speed, and width of the hardware 4844 */ 4845void e1000_get_bus_info(struct e1000_hw *hw) 4846{ 4847 u32 status; 4848 4849 switch (hw->mac_type) { 4850 case e1000_82542_rev2_0: 4851 case e1000_82542_rev2_1: 4852 hw->bus_type = e1000_bus_type_pci; 4853 hw->bus_speed = e1000_bus_speed_unknown; 4854 hw->bus_width = e1000_bus_width_unknown; 4855 break; 4856 default: 4857 status = er32(STATUS); 4858 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4859 e1000_bus_type_pcix : e1000_bus_type_pci; 4860 4861 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4862 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4863 e1000_bus_speed_66 : e1000_bus_speed_120; 4864 } else if (hw->bus_type == e1000_bus_type_pci) { 4865 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 4866 e1000_bus_speed_66 : e1000_bus_speed_33; 4867 } else { 4868 switch (status & E1000_STATUS_PCIX_SPEED) { 4869 case E1000_STATUS_PCIX_SPEED_66: 4870 hw->bus_speed = e1000_bus_speed_66; 4871 break; 4872 case E1000_STATUS_PCIX_SPEED_100: 4873 hw->bus_speed = e1000_bus_speed_100; 4874 break; 4875 case E1000_STATUS_PCIX_SPEED_133: 4876 hw->bus_speed = e1000_bus_speed_133; 4877 break; 4878 default: 4879 hw->bus_speed = e1000_bus_speed_reserved; 4880 break; 4881 } 4882 } 4883 hw->bus_width = (status & E1000_STATUS_BUS64) ? 4884 e1000_bus_width_64 : e1000_bus_width_32; 4885 break; 4886 } 4887} 4888 4889/** 4890 * e1000_write_reg_io 4891 * @hw: Struct containing variables accessed by shared code 4892 * @offset: offset to write to 4893 * @value: value to write 4894 * 4895 * Writes a value to one of the devices registers using port I/O (as opposed to 4896 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4897 */ 4898static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 4899{ 4900 unsigned long io_addr = hw->io_base; 4901 unsigned long io_data = hw->io_base + 4; 4902 4903 e1000_io_write(hw, io_addr, offset); 4904 e1000_io_write(hw, io_data, value); 4905} 4906 4907/** 4908 * e1000_get_cable_length - Estimates the cable length. 4909 * @hw: Struct containing variables accessed by shared code 4910 * @min_length: The estimated minimum length 4911 * @max_length: The estimated maximum length 4912 * 4913 * returns: - E1000_ERR_XXX 4914 * E1000_SUCCESS 4915 * 4916 * This function always returns a ranged length (minimum & maximum). 4917 * So for M88 phy's, this function interprets the one value returned from the 4918 * register to the minimum and maximum range. 4919 * For IGP phy's, the function calculates the range by the AGC registers. 4920 */ 4921static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 4922 u16 *max_length) 4923{ 4924 s32 ret_val; 4925 u16 agc_value = 0; 4926 u16 i, phy_data; 4927 u16 cable_length; 4928 4929 *min_length = *max_length = 0; 4930 4931 /* Use old method for Phy older than IGP */ 4932 if (hw->phy_type == e1000_phy_m88) { 4933 4934 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4935 &phy_data); 4936 if (ret_val) 4937 return ret_val; 4938 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4939 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 4940 4941 /* Convert the enum value to ranged values */ 4942 switch (cable_length) { 4943 case e1000_cable_length_50: 4944 *min_length = 0; 4945 *max_length = e1000_igp_cable_length_50; 4946 break; 4947 case e1000_cable_length_50_80: 4948 *min_length = e1000_igp_cable_length_50; 4949 *max_length = e1000_igp_cable_length_80; 4950 break; 4951 case e1000_cable_length_80_110: 4952 *min_length = e1000_igp_cable_length_80; 4953 *max_length = e1000_igp_cable_length_110; 4954 break; 4955 case e1000_cable_length_110_140: 4956 *min_length = e1000_igp_cable_length_110; 4957 *max_length = e1000_igp_cable_length_140; 4958 break; 4959 case e1000_cable_length_140: 4960 *min_length = e1000_igp_cable_length_140; 4961 *max_length = e1000_igp_cable_length_170; 4962 break; 4963 default: 4964 return -E1000_ERR_PHY; 4965 } 4966 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 4967 u16 cur_agc_value; 4968 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 4969 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 4970 IGP01E1000_PHY_AGC_A, 4971 IGP01E1000_PHY_AGC_B, 4972 IGP01E1000_PHY_AGC_C, 4973 IGP01E1000_PHY_AGC_D 4974 }; 4975 /* Read the AGC registers for all channels */ 4976 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 4977 4978 ret_val = 4979 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 4980 if (ret_val) 4981 return ret_val; 4982 4983 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 4984 4985 /* Value bound check. */ 4986 if ((cur_agc_value >= 4987 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) 4988 || (cur_agc_value == 0)) 4989 return -E1000_ERR_PHY; 4990 4991 agc_value += cur_agc_value; 4992 4993 /* Update minimal AGC value. */ 4994 if (min_agc_value > cur_agc_value) 4995 min_agc_value = cur_agc_value; 4996 } 4997 4998 /* Remove the minimal AGC result for length < 50m */ 4999 if (agc_value < 5000 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 5001 agc_value -= min_agc_value; 5002 5003 /* Get the average length of the remaining 3 channels */ 5004 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 5005 } else { 5006 /* Get the average length of all the 4 channels. */ 5007 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 5008 } 5009 5010 /* Set the range of the calculated length. */ 5011 *min_length = ((e1000_igp_cable_length_table[agc_value] - 5012 IGP01E1000_AGC_RANGE) > 0) ? 5013 (e1000_igp_cable_length_table[agc_value] - 5014 IGP01E1000_AGC_RANGE) : 0; 5015 *max_length = e1000_igp_cable_length_table[agc_value] + 5016 IGP01E1000_AGC_RANGE; 5017 } 5018 5019 return E1000_SUCCESS; 5020} 5021 5022/** 5023 * e1000_check_polarity - Check the cable polarity 5024 * @hw: Struct containing variables accessed by shared code 5025 * @polarity: output parameter : 0 - Polarity is not reversed 5026 * 1 - Polarity is reversed. 5027 * 5028 * returns: - E1000_ERR_XXX 5029 * E1000_SUCCESS 5030 * 5031 * For phy's older than IGP, this function simply reads the polarity bit in the 5032 * Phy Status register. For IGP phy's, this bit is valid only if link speed is 5033 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 5034 * return 0. If the link speed is 1000 Mbps the polarity status is in the 5035 * IGP01E1000_PHY_PCS_INIT_REG. 5036 */ 5037static s32 e1000_check_polarity(struct e1000_hw *hw, 5038 e1000_rev_polarity *polarity) 5039{ 5040 s32 ret_val; 5041 u16 phy_data; 5042 5043 if (hw->phy_type == e1000_phy_m88) { 5044 /* return the Polarity bit in the Status register. */ 5045 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5046 &phy_data); 5047 if (ret_val) 5048 return ret_val; 5049 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 5050 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5051 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5052 5053 } else if (hw->phy_type == e1000_phy_igp) { 5054 /* Read the Status register to check the speed */ 5055 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5056 &phy_data); 5057 if (ret_val) 5058 return ret_val; 5059 5060 /* If speed is 1000 Mbps, must read the 5061 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status 5062 */ 5063 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 5064 IGP01E1000_PSSR_SPEED_1000MBPS) { 5065 5066 /* Read the GIG initialization PCS register (0x00B4) */ 5067 ret_val = 5068 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 5069 &phy_data); 5070 if (ret_val) 5071 return ret_val; 5072 5073 /* Check the polarity bits */ 5074 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 5075 e1000_rev_polarity_reversed : 5076 e1000_rev_polarity_normal; 5077 } else { 5078 /* For 10 Mbps, read the polarity bit in the status 5079 * register. (for 100 Mbps this bit is always 0) 5080 */ 5081 *polarity = 5082 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5083 e1000_rev_polarity_reversed : 5084 e1000_rev_polarity_normal; 5085 } 5086 } 5087 return E1000_SUCCESS; 5088} 5089 5090/** 5091 * e1000_check_downshift - Check if Downshift occurred 5092 * @hw: Struct containing variables accessed by shared code 5093 * @downshift: output parameter : 0 - No Downshift occurred. 5094 * 1 - Downshift occurred. 5095 * 5096 * returns: - E1000_ERR_XXX 5097 * E1000_SUCCESS 5098 * 5099 * For phy's older than IGP, this function reads the Downshift bit in the Phy 5100 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 5101 * Link Health register. In IGP this bit is latched high, so the driver must 5102 * read it immediately after link is established. 5103 */ 5104static s32 e1000_check_downshift(struct e1000_hw *hw) 5105{ 5106 s32 ret_val; 5107 u16 phy_data; 5108 5109 if (hw->phy_type == e1000_phy_igp) { 5110 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5111 &phy_data); 5112 if (ret_val) 5113 return ret_val; 5114 5115 hw->speed_downgraded = 5116 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5117 } else if (hw->phy_type == e1000_phy_m88) { 5118 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5119 &phy_data); 5120 if (ret_val) 5121 return ret_val; 5122 5123 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5124 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5125 } 5126 5127 return E1000_SUCCESS; 5128} 5129 5130static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 5131 IGP01E1000_PHY_AGC_PARAM_A, 5132 IGP01E1000_PHY_AGC_PARAM_B, 5133 IGP01E1000_PHY_AGC_PARAM_C, 5134 IGP01E1000_PHY_AGC_PARAM_D 5135}; 5136 5137static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw) 5138{ 5139 u16 min_length, max_length; 5140 u16 phy_data, i; 5141 s32 ret_val; 5142 5143 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 5144 if (ret_val) 5145 return ret_val; 5146 5147 if (hw->dsp_config_state != e1000_dsp_config_enabled) 5148 return 0; 5149 5150 if (min_length >= e1000_igp_cable_length_50) { 5151 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5152 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 5153 &phy_data); 5154 if (ret_val) 5155 return ret_val; 5156 5157 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5158 5159 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 5160 phy_data); 5161 if (ret_val) 5162 return ret_val; 5163 } 5164 hw->dsp_config_state = e1000_dsp_config_activated; 5165 } else { 5166 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 5167 u32 idle_errs = 0; 5168 5169 /* clear previous idle error counts */ 5170 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 5171 if (ret_val) 5172 return ret_val; 5173 5174 for (i = 0; i < ffe_idle_err_timeout; i++) { 5175 udelay(1000); 5176 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5177 &phy_data); 5178 if (ret_val) 5179 return ret_val; 5180 5181 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 5182 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 5183 hw->ffe_config_state = e1000_ffe_config_active; 5184 5185 ret_val = e1000_write_phy_reg(hw, 5186 IGP01E1000_PHY_DSP_FFE, 5187 IGP01E1000_PHY_DSP_FFE_CM_CP); 5188 if (ret_val) 5189 return ret_val; 5190 break; 5191 } 5192 5193 if (idle_errs) 5194 ffe_idle_err_timeout = 5195 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 5196 } 5197 } 5198 5199 return 0; 5200} 5201 5202/** 5203 * e1000_config_dsp_after_link_change 5204 * @hw: Struct containing variables accessed by shared code 5205 * @link_up: was link up at the time this was called 5206 * 5207 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5208 * E1000_SUCCESS at any other case. 5209 * 5210 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 5211 * gigabit link is achieved to improve link quality. 5212 */ 5213 5214static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5215{ 5216 s32 ret_val; 5217 u16 phy_data, phy_saved_data, speed, duplex, i; 5218 5219 if (hw->phy_type != e1000_phy_igp) 5220 return E1000_SUCCESS; 5221 5222 if (link_up) { 5223 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5224 if (ret_val) { 5225 e_dbg("Error getting link speed and duplex\n"); 5226 return ret_val; 5227 } 5228 5229 if (speed == SPEED_1000) { 5230 ret_val = e1000_1000Mb_check_cable_length(hw); 5231 if (ret_val) 5232 return ret_val; 5233 } 5234 } else { 5235 if (hw->dsp_config_state == e1000_dsp_config_activated) { 5236 /* Save off the current value of register 0x2F5B to be 5237 * restored at the end of the routines. 5238 */ 5239 ret_val = 5240 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5241 5242 if (ret_val) 5243 return ret_val; 5244 5245 /* Disable the PHY transmitter */ 5246 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5247 5248 if (ret_val) 5249 return ret_val; 5250 5251 msleep(20); 5252 5253 ret_val = e1000_write_phy_reg(hw, 0x0000, 5254 IGP01E1000_IEEE_FORCE_GIGA); 5255 if (ret_val) 5256 return ret_val; 5257 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5258 ret_val = 5259 e1000_read_phy_reg(hw, dsp_reg_array[i], 5260 &phy_data); 5261 if (ret_val) 5262 return ret_val; 5263 5264 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5265 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 5266 5267 ret_val = 5268 e1000_write_phy_reg(hw, dsp_reg_array[i], 5269 phy_data); 5270 if (ret_val) 5271 return ret_val; 5272 } 5273 5274 ret_val = e1000_write_phy_reg(hw, 0x0000, 5275 IGP01E1000_IEEE_RESTART_AUTONEG); 5276 if (ret_val) 5277 return ret_val; 5278 5279 msleep(20); 5280 5281 /* Now enable the transmitter */ 5282 ret_val = 5283 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5284 5285 if (ret_val) 5286 return ret_val; 5287 5288 hw->dsp_config_state = e1000_dsp_config_enabled; 5289 } 5290 5291 if (hw->ffe_config_state == e1000_ffe_config_active) { 5292 /* Save off the current value of register 0x2F5B to be 5293 * restored at the end of the routines. 5294 */ 5295 ret_val = 5296 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5297 5298 if (ret_val) 5299 return ret_val; 5300 5301 /* Disable the PHY transmitter */ 5302 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5303 5304 if (ret_val) 5305 return ret_val; 5306 5307 msleep(20); 5308 5309 ret_val = e1000_write_phy_reg(hw, 0x0000, 5310 IGP01E1000_IEEE_FORCE_GIGA); 5311 if (ret_val) 5312 return ret_val; 5313 ret_val = 5314 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 5315 IGP01E1000_PHY_DSP_FFE_DEFAULT); 5316 if (ret_val) 5317 return ret_val; 5318 5319 ret_val = e1000_write_phy_reg(hw, 0x0000, 5320 IGP01E1000_IEEE_RESTART_AUTONEG); 5321 if (ret_val) 5322 return ret_val; 5323 5324 msleep(20); 5325 5326 /* Now enable the transmitter */ 5327 ret_val = 5328 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5329 5330 if (ret_val) 5331 return ret_val; 5332 5333 hw->ffe_config_state = e1000_ffe_config_enabled; 5334 } 5335 } 5336 return E1000_SUCCESS; 5337} 5338 5339/** 5340 * e1000_set_phy_mode - Set PHY to class A mode 5341 * @hw: Struct containing variables accessed by shared code 5342 * 5343 * Assumes the following operations will follow to enable the new class mode. 5344 * 1. Do a PHY soft reset 5345 * 2. Restart auto-negotiation or force link. 5346 */ 5347static s32 e1000_set_phy_mode(struct e1000_hw *hw) 5348{ 5349 s32 ret_val; 5350 u16 eeprom_data; 5351 5352 if ((hw->mac_type == e1000_82545_rev_3) && 5353 (hw->media_type == e1000_media_type_copper)) { 5354 ret_val = 5355 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 5356 &eeprom_data); 5357 if (ret_val) { 5358 return ret_val; 5359 } 5360 5361 if ((eeprom_data != EEPROM_RESERVED_WORD) && 5362 (eeprom_data & EEPROM_PHY_CLASS_A)) { 5363 ret_val = 5364 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 5365 0x000B); 5366 if (ret_val) 5367 return ret_val; 5368 ret_val = 5369 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 5370 0x8104); 5371 if (ret_val) 5372 return ret_val; 5373 5374 hw->phy_reset_disable = false; 5375 } 5376 } 5377 5378 return E1000_SUCCESS; 5379} 5380 5381/** 5382 * e1000_set_d3_lplu_state - set d3 link power state 5383 * @hw: Struct containing variables accessed by shared code 5384 * @active: true to enable lplu false to disable lplu. 5385 * 5386 * This function sets the lplu state according to the active flag. When 5387 * activating lplu this function also disables smart speed and vise versa. 5388 * lplu will not be activated unless the device autonegotiation advertisement 5389 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 5390 * 5391 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5392 * E1000_SUCCESS at any other case. 5393 */ 5394static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5395{ 5396 s32 ret_val; 5397 u16 phy_data; 5398 5399 if (hw->phy_type != e1000_phy_igp) 5400 return E1000_SUCCESS; 5401 5402 /* During driver activity LPLU should not be used or it will attain link 5403 * from the lowest speeds starting from 10Mbps. The capability is used 5404 * for Dx transitions and states 5405 */ 5406 if (hw->mac_type == e1000_82541_rev_2 5407 || hw->mac_type == e1000_82547_rev_2) { 5408 ret_val = 5409 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5410 if (ret_val) 5411 return ret_val; 5412 } 5413 5414 if (!active) { 5415 if (hw->mac_type == e1000_82541_rev_2 || 5416 hw->mac_type == e1000_82547_rev_2) { 5417 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 5418 ret_val = 5419 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5420 phy_data); 5421 if (ret_val) 5422 return ret_val; 5423 } 5424 5425 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 5426 * during Dx states where the power conservation is most 5427 * important. During driver activity we should enable 5428 * SmartSpeed, so performance is maintained. 5429 */ 5430 if (hw->smart_speed == e1000_smart_speed_on) { 5431 ret_val = 5432 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5433 &phy_data); 5434 if (ret_val) 5435 return ret_val; 5436 5437 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 5438 ret_val = 5439 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5440 phy_data); 5441 if (ret_val) 5442 return ret_val; 5443 } else if (hw->smart_speed == e1000_smart_speed_off) { 5444 ret_val = 5445 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5446 &phy_data); 5447 if (ret_val) 5448 return ret_val; 5449 5450 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5451 ret_val = 5452 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5453 phy_data); 5454 if (ret_val) 5455 return ret_val; 5456 } 5457 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 5458 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) 5459 || (hw->autoneg_advertised == 5460 AUTONEG_ADVERTISE_10_100_ALL)) { 5461 5462 if (hw->mac_type == e1000_82541_rev_2 || 5463 hw->mac_type == e1000_82547_rev_2) { 5464 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5465 ret_val = 5466 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 5467 phy_data); 5468 if (ret_val) 5469 return ret_val; 5470 } 5471 5472 /* When LPLU is enabled we should disable SmartSpeed */ 5473 ret_val = 5474 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5475 &phy_data); 5476 if (ret_val) 5477 return ret_val; 5478 5479 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5480 ret_val = 5481 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5482 phy_data); 5483 if (ret_val) 5484 return ret_val; 5485 5486 } 5487 return E1000_SUCCESS; 5488} 5489 5490/** 5491 * e1000_set_vco_speed 5492 * @hw: Struct containing variables accessed by shared code 5493 * 5494 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 5495 */ 5496static s32 e1000_set_vco_speed(struct e1000_hw *hw) 5497{ 5498 s32 ret_val; 5499 u16 default_page = 0; 5500 u16 phy_data; 5501 5502 switch (hw->mac_type) { 5503 case e1000_82545_rev_3: 5504 case e1000_82546_rev_3: 5505 break; 5506 default: 5507 return E1000_SUCCESS; 5508 } 5509 5510 /* Set PHY register 30, page 5, bit 8 to 0 */ 5511 5512 ret_val = 5513 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5514 if (ret_val) 5515 return ret_val; 5516 5517 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5518 if (ret_val) 5519 return ret_val; 5520 5521 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5522 if (ret_val) 5523 return ret_val; 5524 5525 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5526 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5527 if (ret_val) 5528 return ret_val; 5529 5530 /* Set PHY register 30, page 4, bit 11 to 1 */ 5531 5532 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5533 if (ret_val) 5534 return ret_val; 5535 5536 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5537 if (ret_val) 5538 return ret_val; 5539 5540 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5541 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5542 if (ret_val) 5543 return ret_val; 5544 5545 ret_val = 5546 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5547 if (ret_val) 5548 return ret_val; 5549 5550 return E1000_SUCCESS; 5551} 5552 5553 5554/** 5555 * e1000_enable_mng_pass_thru - check for bmc pass through 5556 * @hw: Struct containing variables accessed by shared code 5557 * 5558 * Verifies the hardware needs to allow ARPs to be processed by the host 5559 * returns: - true/false 5560 */ 5561u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5562{ 5563 u32 manc; 5564 5565 if (hw->asf_firmware_present) { 5566 manc = er32(MANC); 5567 5568 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5569 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5570 return false; 5571 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 5572 return true; 5573 } 5574 return false; 5575} 5576 5577static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5578{ 5579 s32 ret_val; 5580 u16 mii_status_reg; 5581 u16 i; 5582 5583 /* Polarity reversal workaround for forced 10F/10H links. */ 5584 5585 /* Disable the transmitter on the PHY */ 5586 5587 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5588 if (ret_val) 5589 return ret_val; 5590 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 5591 if (ret_val) 5592 return ret_val; 5593 5594 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5595 if (ret_val) 5596 return ret_val; 5597 5598 /* This loop will early-out if the NO link condition has been met. */ 5599 for (i = PHY_FORCE_TIME; i > 0; i--) { 5600 /* Read the MII Status Register and wait for Link Status bit 5601 * to be clear. 5602 */ 5603 5604 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5605 if (ret_val) 5606 return ret_val; 5607 5608 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5609 if (ret_val) 5610 return ret_val; 5611 5612 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 5613 break; 5614 msleep(100); 5615 } 5616 5617 /* Recommended delay time after link has been lost */ 5618 msleep(1000); 5619 5620 /* Now we will re-enable th transmitter on the PHY */ 5621 5622 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5623 if (ret_val) 5624 return ret_val; 5625 msleep(50); 5626 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 5627 if (ret_val) 5628 return ret_val; 5629 msleep(50); 5630 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 5631 if (ret_val) 5632 return ret_val; 5633 msleep(50); 5634 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 5635 if (ret_val) 5636 return ret_val; 5637 5638 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5639 if (ret_val) 5640 return ret_val; 5641 5642 /* This loop will early-out if the link condition has been met. */ 5643 for (i = PHY_FORCE_TIME; i > 0; i--) { 5644 /* Read the MII Status Register and wait for Link Status bit 5645 * to be set. 5646 */ 5647 5648 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5649 if (ret_val) 5650 return ret_val; 5651 5652 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5653 if (ret_val) 5654 return ret_val; 5655 5656 if (mii_status_reg & MII_SR_LINK_STATUS) 5657 break; 5658 msleep(100); 5659 } 5660 return E1000_SUCCESS; 5661} 5662 5663/** 5664 * e1000_get_auto_rd_done 5665 * @hw: Struct containing variables accessed by shared code 5666 * 5667 * Check for EEPROM Auto Read bit done. 5668 * returns: - E1000_ERR_RESET if fail to reset MAC 5669 * E1000_SUCCESS at any other case. 5670 */ 5671static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5672{ 5673 msleep(5); 5674 return E1000_SUCCESS; 5675} 5676 5677/** 5678 * e1000_get_phy_cfg_done 5679 * @hw: Struct containing variables accessed by shared code 5680 * 5681 * Checks if the PHY configuration is done 5682 * returns: - E1000_ERR_RESET if fail to reset MAC 5683 * E1000_SUCCESS at any other case. 5684 */ 5685static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5686{ 5687 msleep(10); 5688 return E1000_SUCCESS; 5689} 5690