1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_TXRX_H_ 28#define _I40E_TXRX_H_ 29 30/* Interrupt Throttling and Rate Limiting Goodies */ 31 32#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33#define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */ 34#define I40E_ITR_100K 0x0005 35#define I40E_ITR_20K 0x0019 36#define I40E_ITR_8K 0x003E 37#define I40E_ITR_4K 0x007A 38#define I40E_ITR_RX_DEF I40E_ITR_8K 39#define I40E_ITR_TX_DEF I40E_ITR_4K 40#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 41#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 42#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 43#define I40E_DEFAULT_IRQ_WORK 256 44#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 45#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 46#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 47 48#define I40E_QUEUE_END_OF_LIST 0x7FF 49 50/* this enum matches hardware bits and is meant to be used by DYN_CTLN 51 * registers and QINT registers or more generally anywhere in the manual 52 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 53 * register but instead is a special value meaning "don't update" ITR0/1/2. 54 */ 55enum i40e_dyn_idx_t { 56 I40E_IDX_ITR0 = 0, 57 I40E_IDX_ITR1 = 1, 58 I40E_IDX_ITR2 = 2, 59 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 60}; 61 62/* these are indexes into ITRN registers */ 63#define I40E_RX_ITR I40E_IDX_ITR0 64#define I40E_TX_ITR I40E_IDX_ITR1 65#define I40E_PE_ITR I40E_IDX_ITR2 66 67/* Supported RSS offloads */ 68#define I40E_DEFAULT_RSS_HENA ( \ 69 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 70 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 71 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 72 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 73 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 74 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 75 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 76 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 77 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 78 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 79 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 80 81/* Supported Rx Buffer Sizes */ 82#define I40E_RXBUFFER_512 512 /* Used for packet split */ 83#define I40E_RXBUFFER_2048 2048 84#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ 85#define I40E_RXBUFFER_4096 4096 86#define I40E_RXBUFFER_8192 8192 87#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 88 89/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 90 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 91 * this adds up to 512 bytes of extra data meaning the smallest allocation 92 * we could have is 1K. 93 * i.e. RXBUFFER_512 --> size-1024 slab 94 */ 95#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 96 97/* How many Rx Buffers do we bundle into one write to the hardware ? */ 98#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 99#define I40E_RX_INCREMENT(r, i) \ 100 do { \ 101 (i)++; \ 102 if ((i) == (r)->count) \ 103 i = 0; \ 104 r->next_to_clean = i; \ 105 } while (0) 106 107#define I40E_RX_NEXT_DESC(r, i, n) \ 108 do { \ 109 (i)++; \ 110 if ((i) == (r)->count) \ 111 i = 0; \ 112 (n) = I40E_RX_DESC((r), (i)); \ 113 } while (0) 114 115#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 116 do { \ 117 I40E_RX_NEXT_DESC((r), (i), (n)); \ 118 prefetch((n)); \ 119 } while (0) 120 121#define i40e_rx_desc i40e_32byte_rx_desc 122 123#define I40E_MAX_BUFFER_TXD 8 124#define I40E_MIN_TX_LEN 17 125#define I40E_MAX_DATA_PER_TXD 8192 126 127/* Tx Descriptors needed, worst case */ 128#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) 129#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 130#define I40E_MIN_DESC_PENDING 4 131 132#define I40E_TX_FLAGS_CSUM (u32)(1) 133#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) 134#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) 135#define I40E_TX_FLAGS_TSO (u32)(1 << 3) 136#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) 137#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) 138#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) 139#define I40E_TX_FLAGS_FSO (u32)(1 << 7) 140#define I40E_TX_FLAGS_TSYN (u32)(1 << 8) 141#define I40E_TX_FLAGS_FD_SB (u32)(1 << 9) 142#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 143#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 144#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 145#define I40E_TX_FLAGS_VLAN_SHIFT 16 146 147struct i40e_tx_buffer { 148 struct i40e_tx_desc *next_to_watch; 149 unsigned long time_stamp; 150 union { 151 struct sk_buff *skb; 152 void *raw_buf; 153 }; 154 unsigned int bytecount; 155 unsigned short gso_segs; 156 DEFINE_DMA_UNMAP_ADDR(dma); 157 DEFINE_DMA_UNMAP_LEN(len); 158 u32 tx_flags; 159}; 160 161struct i40e_rx_buffer { 162 struct sk_buff *skb; 163 void *hdr_buf; 164 dma_addr_t dma; 165 struct page *page; 166 dma_addr_t page_dma; 167 unsigned int page_offset; 168}; 169 170struct i40e_queue_stats { 171 u64 packets; 172 u64 bytes; 173}; 174 175struct i40e_tx_queue_stats { 176 u64 restart_queue; 177 u64 tx_busy; 178 u64 tx_done_old; 179}; 180 181struct i40e_rx_queue_stats { 182 u64 non_eop_descs; 183 u64 alloc_page_failed; 184 u64 alloc_buff_failed; 185}; 186 187enum i40e_ring_state_t { 188 __I40E_TX_FDIR_INIT_DONE, 189 __I40E_TX_XPS_INIT_DONE, 190 __I40E_TX_DETECT_HANG, 191 __I40E_HANG_CHECK_ARMED, 192 __I40E_RX_PS_ENABLED, 193 __I40E_RX_16BYTE_DESC_ENABLED, 194}; 195 196#define ring_is_ps_enabled(ring) \ 197 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 198#define set_ring_ps_enabled(ring) \ 199 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 200#define clear_ring_ps_enabled(ring) \ 201 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 202#define check_for_tx_hang(ring) \ 203 test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 204#define set_check_for_tx_hang(ring) \ 205 set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 206#define clear_check_for_tx_hang(ring) \ 207 clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 208#define ring_is_16byte_desc_enabled(ring) \ 209 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 210#define set_ring_16byte_desc_enabled(ring) \ 211 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 212#define clear_ring_16byte_desc_enabled(ring) \ 213 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 214 215/* struct that defines a descriptor ring, associated with a VSI */ 216struct i40e_ring { 217 struct i40e_ring *next; /* pointer to next ring in q_vector */ 218 void *desc; /* Descriptor ring memory */ 219 struct device *dev; /* Used for DMA mapping */ 220 struct net_device *netdev; /* netdev ring maps to */ 221 union { 222 struct i40e_tx_buffer *tx_bi; 223 struct i40e_rx_buffer *rx_bi; 224 }; 225 unsigned long state; 226 u16 queue_index; /* Queue number of ring */ 227 u8 dcb_tc; /* Traffic class of ring */ 228 u8 __iomem *tail; 229 230 u16 count; /* Number of descriptors */ 231 u16 reg_idx; /* HW register index of the ring */ 232 u16 rx_hdr_len; 233 u16 rx_buf_len; 234 u8 dtype; 235#define I40E_RX_DTYPE_NO_SPLIT 0 236#define I40E_RX_DTYPE_HEADER_SPLIT 1 237#define I40E_RX_DTYPE_SPLIT_ALWAYS 2 238 u8 hsplit; 239#define I40E_RX_SPLIT_L2 0x1 240#define I40E_RX_SPLIT_IP 0x2 241#define I40E_RX_SPLIT_TCP_UDP 0x4 242#define I40E_RX_SPLIT_SCTP 0x8 243 244 /* used in interrupt processing */ 245 u16 next_to_use; 246 u16 next_to_clean; 247 248 u8 atr_sample_rate; 249 u8 atr_count; 250 251 unsigned long last_rx_timestamp; 252 253 bool ring_active; /* is ring online or not */ 254 bool arm_wb; /* do something to arm write back */ 255 256 /* stats structs */ 257 struct i40e_queue_stats stats; 258 struct u64_stats_sync syncp; 259 union { 260 struct i40e_tx_queue_stats tx_stats; 261 struct i40e_rx_queue_stats rx_stats; 262 }; 263 264 unsigned int size; /* length of descriptor ring in bytes */ 265 dma_addr_t dma; /* physical address of ring */ 266 267 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 268 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 269 270 struct rcu_head rcu; /* to avoid race on free */ 271} ____cacheline_internodealigned_in_smp; 272 273enum i40e_latency_range { 274 I40E_LOWEST_LATENCY = 0, 275 I40E_LOW_LATENCY = 1, 276 I40E_BULK_LATENCY = 2, 277}; 278 279struct i40e_ring_container { 280 /* array of pointers to rings */ 281 struct i40e_ring *ring; 282 unsigned int total_bytes; /* total bytes processed this int */ 283 unsigned int total_packets; /* total packets processed this int */ 284 u16 count; 285 enum i40e_latency_range latency_range; 286 u16 itr; 287}; 288 289/* iterator for handling rings in ring container */ 290#define i40e_for_each_ring(pos, head) \ 291 for (pos = (head).ring; pos != NULL; pos = pos->next) 292 293void i40e_alloc_rx_buffers_ps(struct i40e_ring *rxr, u16 cleaned_count); 294void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rxr, u16 cleaned_count); 295void i40e_alloc_rx_headers(struct i40e_ring *rxr); 296netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 297void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 298void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 299int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 300int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 301void i40e_free_tx_resources(struct i40e_ring *tx_ring); 302void i40e_free_rx_resources(struct i40e_ring *rx_ring); 303int i40e_napi_poll(struct napi_struct *napi, int budget); 304#ifdef I40E_FCOE 305void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 306 struct i40e_tx_buffer *first, u32 tx_flags, 307 const u8 hdr_len, u32 td_cmd, u32 td_offset); 308int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); 309int i40e_xmit_descriptor_count(struct sk_buff *skb, struct i40e_ring *tx_ring); 310int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 311 struct i40e_ring *tx_ring, u32 *flags); 312#endif 313#endif /* _I40E_TXRX_H_ */ 314