1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_ADMINQ_CMD_H_ 28#define _I40E_ADMINQ_CMD_H_ 29 30/* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36#define I40E_FW_API_VERSION_MAJOR 0x0001 37#define I40E_FW_API_VERSION_MINOR 0x0002 38#define I40E_FW_API_VERSION_A0_MINOR 0x0000 39 40struct i40e_aq_desc { 41 __le16 flags; 42 __le16 opcode; 43 __le16 datalen; 44 __le16 retval; 45 __le32 cookie_high; 46 __le32 cookie_low; 47 union { 48 struct { 49 __le32 param0; 50 __le32 param1; 51 __le32 param2; 52 __le32 param3; 53 } internal; 54 struct { 55 __le32 param0; 56 __le32 param1; 57 __le32 addr_high; 58 __le32 addr_low; 59 } external; 60 u8 raw[16]; 61 } params; 62}; 63 64/* Flags sub-structure 65 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 66 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 67 */ 68 69/* command flags and offsets*/ 70#define I40E_AQ_FLAG_DD_SHIFT 0 71#define I40E_AQ_FLAG_CMP_SHIFT 1 72#define I40E_AQ_FLAG_ERR_SHIFT 2 73#define I40E_AQ_FLAG_VFE_SHIFT 3 74#define I40E_AQ_FLAG_LB_SHIFT 9 75#define I40E_AQ_FLAG_RD_SHIFT 10 76#define I40E_AQ_FLAG_VFC_SHIFT 11 77#define I40E_AQ_FLAG_BUF_SHIFT 12 78#define I40E_AQ_FLAG_SI_SHIFT 13 79#define I40E_AQ_FLAG_EI_SHIFT 14 80#define I40E_AQ_FLAG_FE_SHIFT 15 81 82#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 83#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 84#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 85#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 86#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 87#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 88#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 89#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 90#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 91#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 92#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 93 94/* error codes */ 95enum i40e_admin_queue_err { 96 I40E_AQ_RC_OK = 0, /* success */ 97 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 98 I40E_AQ_RC_ENOENT = 2, /* No such element */ 99 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 100 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 101 I40E_AQ_RC_EIO = 5, /* I/O error */ 102 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 103 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 104 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 105 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 106 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 107 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 108 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 109 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 110 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 111 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 112 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 113 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 114 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 115 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 116 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 117 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 118 I40E_AQ_RC_EFBIG = 22, /* File too large */ 119}; 120 121/* Admin Queue command opcodes */ 122enum i40e_admin_queue_opc { 123 /* aq commands */ 124 i40e_aqc_opc_get_version = 0x0001, 125 i40e_aqc_opc_driver_version = 0x0002, 126 i40e_aqc_opc_queue_shutdown = 0x0003, 127 i40e_aqc_opc_set_pf_context = 0x0004, 128 129 /* resource ownership */ 130 i40e_aqc_opc_request_resource = 0x0008, 131 i40e_aqc_opc_release_resource = 0x0009, 132 133 i40e_aqc_opc_list_func_capabilities = 0x000A, 134 i40e_aqc_opc_list_dev_capabilities = 0x000B, 135 136 i40e_aqc_opc_set_cppm_configuration = 0x0103, 137 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 138 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 139 140 /* LAA */ 141 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 142 i40e_aqc_opc_mac_address_read = 0x0107, 143 i40e_aqc_opc_mac_address_write = 0x0108, 144 145 /* PXE */ 146 i40e_aqc_opc_clear_pxe_mode = 0x0110, 147 148 /* internal switch commands */ 149 i40e_aqc_opc_get_switch_config = 0x0200, 150 i40e_aqc_opc_add_statistics = 0x0201, 151 i40e_aqc_opc_remove_statistics = 0x0202, 152 i40e_aqc_opc_set_port_parameters = 0x0203, 153 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 154 155 i40e_aqc_opc_add_vsi = 0x0210, 156 i40e_aqc_opc_update_vsi_parameters = 0x0211, 157 i40e_aqc_opc_get_vsi_parameters = 0x0212, 158 159 i40e_aqc_opc_add_pv = 0x0220, 160 i40e_aqc_opc_update_pv_parameters = 0x0221, 161 i40e_aqc_opc_get_pv_parameters = 0x0222, 162 163 i40e_aqc_opc_add_veb = 0x0230, 164 i40e_aqc_opc_update_veb_parameters = 0x0231, 165 i40e_aqc_opc_get_veb_parameters = 0x0232, 166 167 i40e_aqc_opc_delete_element = 0x0243, 168 169 i40e_aqc_opc_add_macvlan = 0x0250, 170 i40e_aqc_opc_remove_macvlan = 0x0251, 171 i40e_aqc_opc_add_vlan = 0x0252, 172 i40e_aqc_opc_remove_vlan = 0x0253, 173 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 174 i40e_aqc_opc_add_tag = 0x0255, 175 i40e_aqc_opc_remove_tag = 0x0256, 176 i40e_aqc_opc_add_multicast_etag = 0x0257, 177 i40e_aqc_opc_remove_multicast_etag = 0x0258, 178 i40e_aqc_opc_update_tag = 0x0259, 179 i40e_aqc_opc_add_control_packet_filter = 0x025A, 180 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 181 i40e_aqc_opc_add_cloud_filters = 0x025C, 182 i40e_aqc_opc_remove_cloud_filters = 0x025D, 183 184 i40e_aqc_opc_add_mirror_rule = 0x0260, 185 i40e_aqc_opc_delete_mirror_rule = 0x0261, 186 187 /* DCB commands */ 188 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 189 i40e_aqc_opc_dcb_updated = 0x0302, 190 191 /* TX scheduler */ 192 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 193 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 194 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 195 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 196 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 197 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 198 199 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 200 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 201 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 202 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 203 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 204 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 205 i40e_aqc_opc_query_port_ets_config = 0x0419, 206 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 207 i40e_aqc_opc_suspend_port_tx = 0x041B, 208 i40e_aqc_opc_resume_port_tx = 0x041C, 209 i40e_aqc_opc_configure_partition_bw = 0x041D, 210 211 /* hmc */ 212 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 213 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 214 215 /* phy commands*/ 216 i40e_aqc_opc_get_phy_abilities = 0x0600, 217 i40e_aqc_opc_set_phy_config = 0x0601, 218 i40e_aqc_opc_set_mac_config = 0x0603, 219 i40e_aqc_opc_set_link_restart_an = 0x0605, 220 i40e_aqc_opc_get_link_status = 0x0607, 221 i40e_aqc_opc_set_phy_int_mask = 0x0613, 222 i40e_aqc_opc_get_local_advt_reg = 0x0614, 223 i40e_aqc_opc_set_local_advt_reg = 0x0615, 224 i40e_aqc_opc_get_partner_advt = 0x0616, 225 i40e_aqc_opc_set_lb_modes = 0x0618, 226 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 227 i40e_aqc_opc_set_phy_debug = 0x0622, 228 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 229 230 /* NVM commands */ 231 i40e_aqc_opc_nvm_read = 0x0701, 232 i40e_aqc_opc_nvm_erase = 0x0702, 233 i40e_aqc_opc_nvm_update = 0x0703, 234 i40e_aqc_opc_nvm_config_read = 0x0704, 235 i40e_aqc_opc_nvm_config_write = 0x0705, 236 237 /* virtualization commands */ 238 i40e_aqc_opc_send_msg_to_pf = 0x0801, 239 i40e_aqc_opc_send_msg_to_vf = 0x0802, 240 i40e_aqc_opc_send_msg_to_peer = 0x0803, 241 242 /* alternate structure */ 243 i40e_aqc_opc_alternate_write = 0x0900, 244 i40e_aqc_opc_alternate_write_indirect = 0x0901, 245 i40e_aqc_opc_alternate_read = 0x0902, 246 i40e_aqc_opc_alternate_read_indirect = 0x0903, 247 i40e_aqc_opc_alternate_write_done = 0x0904, 248 i40e_aqc_opc_alternate_set_mode = 0x0905, 249 i40e_aqc_opc_alternate_clear_port = 0x0906, 250 251 /* LLDP commands */ 252 i40e_aqc_opc_lldp_get_mib = 0x0A00, 253 i40e_aqc_opc_lldp_update_mib = 0x0A01, 254 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 255 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 256 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 257 i40e_aqc_opc_lldp_stop = 0x0A05, 258 i40e_aqc_opc_lldp_start = 0x0A06, 259 260 /* Tunnel commands */ 261 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 262 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 263 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 264 265 /* Async Events */ 266 i40e_aqc_opc_event_lan_overflow = 0x1001, 267 268 /* OEM commands */ 269 i40e_aqc_opc_oem_parameter_change = 0xFE00, 270 i40e_aqc_opc_oem_device_status_change = 0xFE01, 271 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 272 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 273 274 /* debug commands */ 275 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 276 i40e_aqc_opc_debug_set_mode = 0xFF01, 277 i40e_aqc_opc_debug_read_reg = 0xFF03, 278 i40e_aqc_opc_debug_write_reg = 0xFF04, 279 i40e_aqc_opc_debug_modify_reg = 0xFF07, 280 i40e_aqc_opc_debug_dump_internals = 0xFF08, 281}; 282 283/* command structures and indirect data structures */ 284 285/* Structure naming conventions: 286 * - no suffix for direct command descriptor structures 287 * - _data for indirect sent data 288 * - _resp for indirect return data (data which is both will use _data) 289 * - _completion for direct return data 290 * - _element_ for repeated elements (may also be _data or _resp) 291 * 292 * Command structures are expected to overlay the params.raw member of the basic 293 * descriptor, and as such cannot exceed 16 bytes in length. 294 */ 295 296/* This macro is used to generate a compilation error if a structure 297 * is not exactly the correct length. It gives a divide by zero error if the 298 * structure is not of the correct size, otherwise it creates an enum that is 299 * never used. 300 */ 301#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 302 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 303 304/* This macro is used extensively to ensure that command structures are 16 305 * bytes in length as they have to map to the raw array of that size. 306 */ 307#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 308 309/* internal (0x00XX) commands */ 310 311/* Get version (direct 0x0001) */ 312struct i40e_aqc_get_version { 313 __le32 rom_ver; 314 __le32 fw_build; 315 __le16 fw_major; 316 __le16 fw_minor; 317 __le16 api_major; 318 __le16 api_minor; 319}; 320 321I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 322 323/* Send driver version (indirect 0x0002) */ 324struct i40e_aqc_driver_version { 325 u8 driver_major_ver; 326 u8 driver_minor_ver; 327 u8 driver_build_ver; 328 u8 driver_subbuild_ver; 329 u8 reserved[4]; 330 __le32 address_high; 331 __le32 address_low; 332}; 333 334I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 335 336/* Queue Shutdown (direct 0x0003) */ 337struct i40e_aqc_queue_shutdown { 338 __le32 driver_unloading; 339#define I40E_AQ_DRIVER_UNLOADING 0x1 340 u8 reserved[12]; 341}; 342 343I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 344 345/* Set PF context (0x0004, direct) */ 346struct i40e_aqc_set_pf_context { 347 u8 pf_id; 348 u8 reserved[15]; 349}; 350 351I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 352 353/* Request resource ownership (direct 0x0008) 354 * Release resource ownership (direct 0x0009) 355 */ 356#define I40E_AQ_RESOURCE_NVM 1 357#define I40E_AQ_RESOURCE_SDP 2 358#define I40E_AQ_RESOURCE_ACCESS_READ 1 359#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 360#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 361#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 362 363struct i40e_aqc_request_resource { 364 __le16 resource_id; 365 __le16 access_type; 366 __le32 timeout; 367 __le32 resource_number; 368 u8 reserved[4]; 369}; 370 371I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 372 373/* Get function capabilities (indirect 0x000A) 374 * Get device capabilities (indirect 0x000B) 375 */ 376struct i40e_aqc_list_capabilites { 377 u8 command_flags; 378#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 379 u8 pf_index; 380 u8 reserved[2]; 381 __le32 count; 382 __le32 addr_high; 383 __le32 addr_low; 384}; 385 386I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 387 388struct i40e_aqc_list_capabilities_element_resp { 389 __le16 id; 390 u8 major_rev; 391 u8 minor_rev; 392 __le32 number; 393 __le32 logical_id; 394 __le32 phys_id; 395 u8 reserved[16]; 396}; 397 398/* list of caps */ 399 400#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 401#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 402#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 403#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 404#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 405#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 406#define I40E_AQ_CAP_ID_SRIOV 0x0012 407#define I40E_AQ_CAP_ID_VF 0x0013 408#define I40E_AQ_CAP_ID_VMDQ 0x0014 409#define I40E_AQ_CAP_ID_8021QBG 0x0015 410#define I40E_AQ_CAP_ID_8021QBR 0x0016 411#define I40E_AQ_CAP_ID_VSI 0x0017 412#define I40E_AQ_CAP_ID_DCB 0x0018 413#define I40E_AQ_CAP_ID_FCOE 0x0021 414#define I40E_AQ_CAP_ID_ISCSI 0x0022 415#define I40E_AQ_CAP_ID_RSS 0x0040 416#define I40E_AQ_CAP_ID_RXQ 0x0041 417#define I40E_AQ_CAP_ID_TXQ 0x0042 418#define I40E_AQ_CAP_ID_MSIX 0x0043 419#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 420#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 421#define I40E_AQ_CAP_ID_1588 0x0046 422#define I40E_AQ_CAP_ID_IWARP 0x0051 423#define I40E_AQ_CAP_ID_LED 0x0061 424#define I40E_AQ_CAP_ID_SDP 0x0062 425#define I40E_AQ_CAP_ID_MDIO 0x0063 426#define I40E_AQ_CAP_ID_FLEX10 0x00F1 427#define I40E_AQ_CAP_ID_CEM 0x00F2 428 429/* Set CPPM Configuration (direct 0x0103) */ 430struct i40e_aqc_cppm_configuration { 431 __le16 command_flags; 432#define I40E_AQ_CPPM_EN_LTRC 0x0800 433#define I40E_AQ_CPPM_EN_DMCTH 0x1000 434#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 435#define I40E_AQ_CPPM_EN_HPTC 0x4000 436#define I40E_AQ_CPPM_EN_DMARC 0x8000 437 __le16 ttlx; 438 __le32 dmacr; 439 __le16 dmcth; 440 u8 hptc; 441 u8 reserved; 442 __le32 pfltrc; 443}; 444 445I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 446 447/* Set ARP Proxy command / response (indirect 0x0104) */ 448struct i40e_aqc_arp_proxy_data { 449 __le16 command_flags; 450#define I40E_AQ_ARP_INIT_IPV4 0x0008 451#define I40E_AQ_ARP_UNSUP_CTL 0x0010 452#define I40E_AQ_ARP_ENA 0x0020 453#define I40E_AQ_ARP_ADD_IPV4 0x0040 454#define I40E_AQ_ARP_DEL_IPV4 0x0080 455 __le16 table_id; 456 __le32 pfpm_proxyfc; 457 __le32 ip_addr; 458 u8 mac_addr[6]; 459 u8 reserved[2]; 460}; 461 462I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 463 464/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 465struct i40e_aqc_ns_proxy_data { 466 __le16 table_idx_mac_addr_0; 467 __le16 table_idx_mac_addr_1; 468 __le16 table_idx_ipv6_0; 469 __le16 table_idx_ipv6_1; 470 __le16 control; 471#define I40E_AQ_NS_PROXY_ADD_0 0x0100 472#define I40E_AQ_NS_PROXY_DEL_0 0x0200 473#define I40E_AQ_NS_PROXY_ADD_1 0x0400 474#define I40E_AQ_NS_PROXY_DEL_1 0x0800 475#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 476#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 477#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 478#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 479#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 480#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 481#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 482 u8 mac_addr_0[6]; 483 u8 mac_addr_1[6]; 484 u8 local_mac_addr[6]; 485 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 486 u8 ipv6_addr_1[16]; 487}; 488 489I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 490 491/* Manage LAA Command (0x0106) - obsolete */ 492struct i40e_aqc_mng_laa { 493 __le16 command_flags; 494#define I40E_AQ_LAA_FLAG_WR 0x8000 495 u8 reserved[2]; 496 __le32 sal; 497 __le16 sah; 498 u8 reserved2[6]; 499}; 500 501I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 502 503/* Manage MAC Address Read Command (indirect 0x0107) */ 504struct i40e_aqc_mac_address_read { 505 __le16 command_flags; 506#define I40E_AQC_LAN_ADDR_VALID 0x10 507#define I40E_AQC_SAN_ADDR_VALID 0x20 508#define I40E_AQC_PORT_ADDR_VALID 0x40 509#define I40E_AQC_WOL_ADDR_VALID 0x80 510#define I40E_AQC_ADDR_VALID_MASK 0xf0 511 u8 reserved[6]; 512 __le32 addr_high; 513 __le32 addr_low; 514}; 515 516I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 517 518struct i40e_aqc_mac_address_read_data { 519 u8 pf_lan_mac[6]; 520 u8 pf_san_mac[6]; 521 u8 port_mac[6]; 522 u8 pf_wol_mac[6]; 523}; 524 525I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 526 527/* Manage MAC Address Write Command (0x0108) */ 528struct i40e_aqc_mac_address_write { 529 __le16 command_flags; 530#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 531#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 532#define I40E_AQC_WRITE_TYPE_PORT 0x8000 533#define I40E_AQC_WRITE_TYPE_MASK 0xc000 534 __le16 mac_sah; 535 __le32 mac_sal; 536 u8 reserved[8]; 537}; 538 539I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 540 541/* PXE commands (0x011x) */ 542 543/* Clear PXE Command and response (direct 0x0110) */ 544struct i40e_aqc_clear_pxe { 545 u8 rx_cnt; 546 u8 reserved[15]; 547}; 548 549I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 550 551/* Switch configuration commands (0x02xx) */ 552 553/* Used by many indirect commands that only pass an seid and a buffer in the 554 * command 555 */ 556struct i40e_aqc_switch_seid { 557 __le16 seid; 558 u8 reserved[6]; 559 __le32 addr_high; 560 __le32 addr_low; 561}; 562 563I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 564 565/* Get Switch Configuration command (indirect 0x0200) 566 * uses i40e_aqc_switch_seid for the descriptor 567 */ 568struct i40e_aqc_get_switch_config_header_resp { 569 __le16 num_reported; 570 __le16 num_total; 571 u8 reserved[12]; 572}; 573 574I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 575 576struct i40e_aqc_switch_config_element_resp { 577 u8 element_type; 578#define I40E_AQ_SW_ELEM_TYPE_MAC 1 579#define I40E_AQ_SW_ELEM_TYPE_PF 2 580#define I40E_AQ_SW_ELEM_TYPE_VF 3 581#define I40E_AQ_SW_ELEM_TYPE_EMP 4 582#define I40E_AQ_SW_ELEM_TYPE_BMC 5 583#define I40E_AQ_SW_ELEM_TYPE_PV 16 584#define I40E_AQ_SW_ELEM_TYPE_VEB 17 585#define I40E_AQ_SW_ELEM_TYPE_PA 18 586#define I40E_AQ_SW_ELEM_TYPE_VSI 19 587 u8 revision; 588#define I40E_AQ_SW_ELEM_REV_1 1 589 __le16 seid; 590 __le16 uplink_seid; 591 __le16 downlink_seid; 592 u8 reserved[3]; 593 u8 connection_type; 594#define I40E_AQ_CONN_TYPE_REGULAR 0x1 595#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 596#define I40E_AQ_CONN_TYPE_CASCADED 0x3 597 __le16 scheduler_id; 598 __le16 element_info; 599}; 600 601I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 602 603/* Get Switch Configuration (indirect 0x0200) 604 * an array of elements are returned in the response buffer 605 * the first in the array is the header, remainder are elements 606 */ 607struct i40e_aqc_get_switch_config_resp { 608 struct i40e_aqc_get_switch_config_header_resp header; 609 struct i40e_aqc_switch_config_element_resp element[1]; 610}; 611 612I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 613 614/* Add Statistics (direct 0x0201) 615 * Remove Statistics (direct 0x0202) 616 */ 617struct i40e_aqc_add_remove_statistics { 618 __le16 seid; 619 __le16 vlan; 620 __le16 stat_index; 621 u8 reserved[10]; 622}; 623 624I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 625 626/* Set Port Parameters command (direct 0x0203) */ 627struct i40e_aqc_set_port_parameters { 628 __le16 command_flags; 629#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 630#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 631#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 632 __le16 bad_frame_vsi; 633 __le16 default_seid; /* reserved for command */ 634 u8 reserved[10]; 635}; 636 637I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 638 639/* Get Switch Resource Allocation (indirect 0x0204) */ 640struct i40e_aqc_get_switch_resource_alloc { 641 u8 num_entries; /* reserved for command */ 642 u8 reserved[7]; 643 __le32 addr_high; 644 __le32 addr_low; 645}; 646 647I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 648 649/* expect an array of these structs in the response buffer */ 650struct i40e_aqc_switch_resource_alloc_element_resp { 651 u8 resource_type; 652#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 653#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 654#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 655#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 656#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 657#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 658#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 659#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 660#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 661#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 662#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 663#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 664#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 665#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 666#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 667#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 668#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 669#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 670#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 671 u8 reserved1; 672 __le16 guaranteed; 673 __le16 total; 674 __le16 used; 675 __le16 total_unalloced; 676 u8 reserved2[6]; 677}; 678 679I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 680 681/* Add VSI (indirect 0x0210) 682 * this indirect command uses struct i40e_aqc_vsi_properties_data 683 * as the indirect buffer (128 bytes) 684 * 685 * Update VSI (indirect 0x211) 686 * uses the same data structure as Add VSI 687 * 688 * Get VSI (indirect 0x0212) 689 * uses the same completion and data structure as Add VSI 690 */ 691struct i40e_aqc_add_get_update_vsi { 692 __le16 uplink_seid; 693 u8 connection_type; 694#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 695#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 696#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 697 u8 reserved1; 698 u8 vf_id; 699 u8 reserved2; 700 __le16 vsi_flags; 701#define I40E_AQ_VSI_TYPE_SHIFT 0x0 702#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 703#define I40E_AQ_VSI_TYPE_VF 0x0 704#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 705#define I40E_AQ_VSI_TYPE_PF 0x2 706#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 707#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 708 __le32 addr_high; 709 __le32 addr_low; 710}; 711 712I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 713 714struct i40e_aqc_add_get_update_vsi_completion { 715 __le16 seid; 716 __le16 vsi_number; 717 __le16 vsi_used; 718 __le16 vsi_free; 719 __le32 addr_high; 720 __le32 addr_low; 721}; 722 723I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 724 725struct i40e_aqc_vsi_properties_data { 726 /* first 96 byte are written by SW */ 727 __le16 valid_sections; 728#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 729#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 730#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 731#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 732#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 733#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 734#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 735#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 736#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 737#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 738 /* switch section */ 739 __le16 switch_id; /* 12bit id combined with flags below */ 740#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 741#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 742#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 743#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 744#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 745 u8 sw_reserved[2]; 746 /* security section */ 747 u8 sec_flags; 748#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 749#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 750#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 751 u8 sec_reserved; 752 /* VLAN section */ 753 __le16 pvid; /* VLANS include priority bits */ 754 __le16 fcoe_pvid; 755 u8 port_vlan_flags; 756#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 757#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 758 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 759#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 760#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 761#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 762#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 763#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 764#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 765 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 766#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 767#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 768#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 769#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 770 u8 pvlan_reserved[3]; 771 /* ingress egress up sections */ 772 __le32 ingress_table; /* bitmap, 3 bits per up */ 773#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 774#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 775 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 776#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 777#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 778 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 779#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 780#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 781 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 782#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 783#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 784 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 785#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 786#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 787 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 788#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 789#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 790 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 791#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 792#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 793 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 794#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 795#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 796 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 797 __le32 egress_table; /* same defines as for ingress table */ 798 /* cascaded PV section */ 799 __le16 cas_pv_tag; 800 u8 cas_pv_flags; 801#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 802#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 803 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 804#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 805#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 806#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 807#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 808#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 809#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 810 u8 cas_pv_reserved; 811 /* queue mapping section */ 812 __le16 mapping_flags; 813#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 814#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 815 __le16 queue_mapping[16]; 816#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 817#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 818 __le16 tc_mapping[8]; 819#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 820#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 821 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 822#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 823#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 824 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 825 /* queueing option section */ 826 u8 queueing_opt_flags; 827#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 828#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 829 u8 queueing_opt_reserved[3]; 830 /* scheduler section */ 831 u8 up_enable_bits; 832 u8 sched_reserved; 833 /* outer up section */ 834 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 835 u8 cmd_reserved[8]; 836 /* last 32 bytes are written by FW */ 837 __le16 qs_handle[8]; 838#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 839 __le16 stat_counter_idx; 840 __le16 sched_id; 841 u8 resp_reserved[12]; 842}; 843 844I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 845 846/* Add Port Virtualizer (direct 0x0220) 847 * also used for update PV (direct 0x0221) but only flags are used 848 * (IS_CTRL_PORT only works on add PV) 849 */ 850struct i40e_aqc_add_update_pv { 851 __le16 command_flags; 852#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 853#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 854#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 855#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 856 __le16 uplink_seid; 857 __le16 connected_seid; 858 u8 reserved[10]; 859}; 860 861I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 862 863struct i40e_aqc_add_update_pv_completion { 864 /* reserved for update; for add also encodes error if rc == ENOSPC */ 865 __le16 pv_seid; 866#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 867#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 868#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 869#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 870 u8 reserved[14]; 871}; 872 873I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 874 875/* Get PV Params (direct 0x0222) 876 * uses i40e_aqc_switch_seid for the descriptor 877 */ 878 879struct i40e_aqc_get_pv_params_completion { 880 __le16 seid; 881 __le16 default_stag; 882 __le16 pv_flags; /* same flags as add_pv */ 883#define I40E_AQC_GET_PV_PV_TYPE 0x1 884#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 885#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 886 u8 reserved[8]; 887 __le16 default_port_seid; 888}; 889 890I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 891 892/* Add VEB (direct 0x0230) */ 893struct i40e_aqc_add_veb { 894 __le16 uplink_seid; 895 __le16 downlink_seid; 896 __le16 veb_flags; 897#define I40E_AQC_ADD_VEB_FLOATING 0x1 898#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 899#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 900 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 901#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 902#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 903#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 904 u8 enable_tcs; 905 u8 reserved[9]; 906}; 907 908I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 909 910struct i40e_aqc_add_veb_completion { 911 u8 reserved[6]; 912 __le16 switch_seid; 913 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 914 __le16 veb_seid; 915#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 916#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 917#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 918#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 919 __le16 statistic_index; 920 __le16 vebs_used; 921 __le16 vebs_free; 922}; 923 924I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 925 926/* Get VEB Parameters (direct 0x0232) 927 * uses i40e_aqc_switch_seid for the descriptor 928 */ 929struct i40e_aqc_get_veb_parameters_completion { 930 __le16 seid; 931 __le16 switch_id; 932 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 933 __le16 statistic_index; 934 __le16 vebs_used; 935 __le16 vebs_free; 936 u8 reserved[4]; 937}; 938 939I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 940 941/* Delete Element (direct 0x0243) 942 * uses the generic i40e_aqc_switch_seid 943 */ 944 945/* Add MAC-VLAN (indirect 0x0250) */ 946 947/* used for the command for most vlan commands */ 948struct i40e_aqc_macvlan { 949 __le16 num_addresses; 950 __le16 seid[3]; 951#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 952#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 953 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 954#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 955 __le32 addr_high; 956 __le32 addr_low; 957}; 958 959I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 960 961/* indirect data for command and response */ 962struct i40e_aqc_add_macvlan_element_data { 963 u8 mac_addr[6]; 964 __le16 vlan_tag; 965 __le16 flags; 966#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 967#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 968#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 969#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 970 __le16 queue_number; 971#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 972#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 973 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 974 /* response section */ 975 u8 match_method; 976#define I40E_AQC_MM_PERFECT_MATCH 0x01 977#define I40E_AQC_MM_HASH_MATCH 0x02 978#define I40E_AQC_MM_ERR_NO_RES 0xFF 979 u8 reserved1[3]; 980}; 981 982struct i40e_aqc_add_remove_macvlan_completion { 983 __le16 perfect_mac_used; 984 __le16 perfect_mac_free; 985 __le16 unicast_hash_free; 986 __le16 multicast_hash_free; 987 __le32 addr_high; 988 __le32 addr_low; 989}; 990 991I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 992 993/* Remove MAC-VLAN (indirect 0x0251) 994 * uses i40e_aqc_macvlan for the descriptor 995 * data points to an array of num_addresses of elements 996 */ 997 998struct i40e_aqc_remove_macvlan_element_data { 999 u8 mac_addr[6]; 1000 __le16 vlan_tag; 1001 u8 flags; 1002#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1003#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1004#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1005#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1006 u8 reserved[3]; 1007 /* reply section */ 1008 u8 error_code; 1009#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1010#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1011 u8 reply_reserved[3]; 1012}; 1013 1014/* Add VLAN (indirect 0x0252) 1015 * Remove VLAN (indirect 0x0253) 1016 * use the generic i40e_aqc_macvlan for the command 1017 */ 1018struct i40e_aqc_add_remove_vlan_element_data { 1019 __le16 vlan_tag; 1020 u8 vlan_flags; 1021/* flags for add VLAN */ 1022#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1023#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1024#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1025#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1026#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1027#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1028#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1029#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1030#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1031#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1032#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1033#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1034/* flags for remove VLAN */ 1035#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1036 u8 reserved; 1037 u8 result; 1038/* flags for add VLAN */ 1039#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1040#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1041#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1042/* flags for remove VLAN */ 1043#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1044#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1045 u8 reserved1[3]; 1046}; 1047 1048struct i40e_aqc_add_remove_vlan_completion { 1049 u8 reserved[4]; 1050 __le16 vlans_used; 1051 __le16 vlans_free; 1052 __le32 addr_high; 1053 __le32 addr_low; 1054}; 1055 1056/* Set VSI Promiscuous Modes (direct 0x0254) */ 1057struct i40e_aqc_set_vsi_promiscuous_modes { 1058 __le16 promiscuous_flags; 1059 __le16 valid_flags; 1060/* flags used for both fields above */ 1061#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1062#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1063#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1064#define I40E_AQC_SET_VSI_DEFAULT 0x08 1065#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1066 __le16 seid; 1067#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1068 __le16 vlan_tag; 1069#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1070 u8 reserved[8]; 1071}; 1072 1073I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1074 1075/* Add S/E-tag command (direct 0x0255) 1076 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1077 */ 1078struct i40e_aqc_add_tag { 1079 __le16 flags; 1080#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1081 __le16 seid; 1082#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1083#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1084 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1085 __le16 tag; 1086 __le16 queue_number; 1087 u8 reserved[8]; 1088}; 1089 1090I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1091 1092struct i40e_aqc_add_remove_tag_completion { 1093 u8 reserved[12]; 1094 __le16 tags_used; 1095 __le16 tags_free; 1096}; 1097 1098I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1099 1100/* Remove S/E-tag command (direct 0x0256) 1101 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1102 */ 1103struct i40e_aqc_remove_tag { 1104 __le16 seid; 1105#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1106#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1107 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1108 __le16 tag; 1109 u8 reserved[12]; 1110}; 1111 1112I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1113 1114/* Add multicast E-Tag (direct 0x0257) 1115 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1116 * and no external data 1117 */ 1118struct i40e_aqc_add_remove_mcast_etag { 1119 __le16 pv_seid; 1120 __le16 etag; 1121 u8 num_unicast_etags; 1122 u8 reserved[3]; 1123 __le32 addr_high; /* address of array of 2-byte s-tags */ 1124 __le32 addr_low; 1125}; 1126 1127I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1128 1129struct i40e_aqc_add_remove_mcast_etag_completion { 1130 u8 reserved[4]; 1131 __le16 mcast_etags_used; 1132 __le16 mcast_etags_free; 1133 __le32 addr_high; 1134 __le32 addr_low; 1135 1136}; 1137 1138I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1139 1140/* Update S/E-Tag (direct 0x0259) */ 1141struct i40e_aqc_update_tag { 1142 __le16 seid; 1143#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1144#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1145 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1146 __le16 old_tag; 1147 __le16 new_tag; 1148 u8 reserved[10]; 1149}; 1150 1151I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1152 1153struct i40e_aqc_update_tag_completion { 1154 u8 reserved[12]; 1155 __le16 tags_used; 1156 __le16 tags_free; 1157}; 1158 1159I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1160 1161/* Add Control Packet filter (direct 0x025A) 1162 * Remove Control Packet filter (direct 0x025B) 1163 * uses the i40e_aqc_add_oveb_cloud, 1164 * and the generic direct completion structure 1165 */ 1166struct i40e_aqc_add_remove_control_packet_filter { 1167 u8 mac[6]; 1168 __le16 etype; 1169 __le16 flags; 1170#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1171#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1172#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1173#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1174#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1175 __le16 seid; 1176#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1177#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1178 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1179 __le16 queue; 1180 u8 reserved[2]; 1181}; 1182 1183I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1184 1185struct i40e_aqc_add_remove_control_packet_filter_completion { 1186 __le16 mac_etype_used; 1187 __le16 etype_used; 1188 __le16 mac_etype_free; 1189 __le16 etype_free; 1190 u8 reserved[8]; 1191}; 1192 1193I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1194 1195/* Add Cloud filters (indirect 0x025C) 1196 * Remove Cloud filters (indirect 0x025D) 1197 * uses the i40e_aqc_add_remove_cloud_filters, 1198 * and the generic indirect completion structure 1199 */ 1200struct i40e_aqc_add_remove_cloud_filters { 1201 u8 num_filters; 1202 u8 reserved; 1203 __le16 seid; 1204#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1205#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1206 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1207 u8 reserved2[4]; 1208 __le32 addr_high; 1209 __le32 addr_low; 1210}; 1211 1212I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1213 1214struct i40e_aqc_add_remove_cloud_filters_element_data { 1215 u8 outer_mac[6]; 1216 u8 inner_mac[6]; 1217 __le16 inner_vlan; 1218 union { 1219 struct { 1220 u8 reserved[12]; 1221 u8 data[4]; 1222 } v4; 1223 struct { 1224 u8 data[16]; 1225 } v6; 1226 } ipaddr; 1227 __le16 flags; 1228#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1229#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1230 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1231/* 0x0000 reserved */ 1232#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1233/* 0x0002 reserved */ 1234#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1235#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1236/* 0x0005 reserved */ 1237#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1238/* 0x0007 reserved */ 1239/* 0x0008 reserved */ 1240#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1241#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1242#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1243#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1244 1245#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1246#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1247#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1248#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1249#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1250 1251#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1252#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1253#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1254#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1255#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1256#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1257 1258 __le32 tenant_id; 1259 u8 reserved[4]; 1260 __le16 queue_number; 1261#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1262#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1263 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1264 u8 reserved2[14]; 1265 /* response section */ 1266 u8 allocation_result; 1267#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1268#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1269 u8 response_reserved[7]; 1270}; 1271 1272struct i40e_aqc_remove_cloud_filters_completion { 1273 __le16 perfect_ovlan_used; 1274 __le16 perfect_ovlan_free; 1275 __le16 vlan_used; 1276 __le16 vlan_free; 1277 __le32 addr_high; 1278 __le32 addr_low; 1279}; 1280 1281I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1282 1283/* Add Mirror Rule (indirect or direct 0x0260) 1284 * Delete Mirror Rule (indirect or direct 0x0261) 1285 * note: some rule types (4,5) do not use an external buffer. 1286 * take care to set the flags correctly. 1287 */ 1288struct i40e_aqc_add_delete_mirror_rule { 1289 __le16 seid; 1290 __le16 rule_type; 1291#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1292#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1293 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1294#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1295#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1296#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1297#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1298#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1299 __le16 num_entries; 1300 __le16 destination; /* VSI for add, rule id for delete */ 1301 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1302 __le32 addr_low; 1303}; 1304 1305I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1306 1307struct i40e_aqc_add_delete_mirror_rule_completion { 1308 u8 reserved[2]; 1309 __le16 rule_id; /* only used on add */ 1310 __le16 mirror_rules_used; 1311 __le16 mirror_rules_free; 1312 __le32 addr_high; 1313 __le32 addr_low; 1314}; 1315 1316I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1317 1318/* DCB 0x03xx*/ 1319 1320/* PFC Ignore (direct 0x0301) 1321 * the command and response use the same descriptor structure 1322 */ 1323struct i40e_aqc_pfc_ignore { 1324 u8 tc_bitmap; 1325 u8 command_flags; /* unused on response */ 1326#define I40E_AQC_PFC_IGNORE_SET 0x80 1327#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1328 u8 reserved[14]; 1329}; 1330 1331I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1332 1333/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1334 * with no parameters 1335 */ 1336 1337/* TX scheduler 0x04xx */ 1338 1339/* Almost all the indirect commands use 1340 * this generic struct to pass the SEID in param0 1341 */ 1342struct i40e_aqc_tx_sched_ind { 1343 __le16 vsi_seid; 1344 u8 reserved[6]; 1345 __le32 addr_high; 1346 __le32 addr_low; 1347}; 1348 1349I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1350 1351/* Several commands respond with a set of queue set handles */ 1352struct i40e_aqc_qs_handles_resp { 1353 __le16 qs_handles[8]; 1354}; 1355 1356/* Configure VSI BW limits (direct 0x0400) */ 1357struct i40e_aqc_configure_vsi_bw_limit { 1358 __le16 vsi_seid; 1359 u8 reserved[2]; 1360 __le16 credit; 1361 u8 reserved1[2]; 1362 u8 max_credit; /* 0-3, limit = 2^max */ 1363 u8 reserved2[7]; 1364}; 1365 1366I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1367 1368/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1369 * responds with i40e_aqc_qs_handles_resp 1370 */ 1371struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1372 u8 tc_valid_bits; 1373 u8 reserved[15]; 1374 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1375 1376 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1377 __le16 tc_bw_max[2]; 1378 u8 reserved1[28]; 1379}; 1380 1381I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1382 1383/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1384 * responds with i40e_aqc_qs_handles_resp 1385 */ 1386struct i40e_aqc_configure_vsi_tc_bw_data { 1387 u8 tc_valid_bits; 1388 u8 reserved[3]; 1389 u8 tc_bw_credits[8]; 1390 u8 reserved1[4]; 1391 __le16 qs_handles[8]; 1392}; 1393 1394I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1395 1396/* Query vsi bw configuration (indirect 0x0408) */ 1397struct i40e_aqc_query_vsi_bw_config_resp { 1398 u8 tc_valid_bits; 1399 u8 tc_suspended_bits; 1400 u8 reserved[14]; 1401 __le16 qs_handles[8]; 1402 u8 reserved1[4]; 1403 __le16 port_bw_limit; 1404 u8 reserved2[2]; 1405 u8 max_bw; /* 0-3, limit = 2^max */ 1406 u8 reserved3[23]; 1407}; 1408 1409I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1410 1411/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1412struct i40e_aqc_query_vsi_ets_sla_config_resp { 1413 u8 tc_valid_bits; 1414 u8 reserved[3]; 1415 u8 share_credits[8]; 1416 __le16 credits[8]; 1417 1418 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1419 __le16 tc_bw_max[2]; 1420}; 1421 1422I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1423 1424/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1425struct i40e_aqc_configure_switching_comp_bw_limit { 1426 __le16 seid; 1427 u8 reserved[2]; 1428 __le16 credit; 1429 u8 reserved1[2]; 1430 u8 max_bw; /* 0-3, limit = 2^max */ 1431 u8 reserved2[7]; 1432}; 1433 1434I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1435 1436/* Enable Physical Port ETS (indirect 0x0413) 1437 * Modify Physical Port ETS (indirect 0x0414) 1438 * Disable Physical Port ETS (indirect 0x0415) 1439 */ 1440struct i40e_aqc_configure_switching_comp_ets_data { 1441 u8 reserved[4]; 1442 u8 tc_valid_bits; 1443 u8 seepage; 1444#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1445 u8 tc_strict_priority_flags; 1446 u8 reserved1[17]; 1447 u8 tc_bw_share_credits[8]; 1448 u8 reserved2[96]; 1449}; 1450 1451I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1452 1453/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1454struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1455 u8 tc_valid_bits; 1456 u8 reserved[15]; 1457 __le16 tc_bw_credit[8]; 1458 1459 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1460 __le16 tc_bw_max[2]; 1461 u8 reserved1[28]; 1462}; 1463 1464I40E_CHECK_STRUCT_LEN(0x40, 1465 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1466 1467/* Configure Switching Component Bandwidth Allocation per Tc 1468 * (indirect 0x0417) 1469 */ 1470struct i40e_aqc_configure_switching_comp_bw_config_data { 1471 u8 tc_valid_bits; 1472 u8 reserved[2]; 1473 u8 absolute_credits; /* bool */ 1474 u8 tc_bw_share_credits[8]; 1475 u8 reserved1[20]; 1476}; 1477 1478I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1479 1480/* Query Switching Component Configuration (indirect 0x0418) */ 1481struct i40e_aqc_query_switching_comp_ets_config_resp { 1482 u8 tc_valid_bits; 1483 u8 reserved[35]; 1484 __le16 port_bw_limit; 1485 u8 reserved1[2]; 1486 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1487 u8 reserved2[23]; 1488}; 1489 1490I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1491 1492/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1493struct i40e_aqc_query_port_ets_config_resp { 1494 u8 reserved[4]; 1495 u8 tc_valid_bits; 1496 u8 reserved1; 1497 u8 tc_strict_priority_bits; 1498 u8 reserved2; 1499 u8 tc_bw_share_credits[8]; 1500 __le16 tc_bw_limits[8]; 1501 1502 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1503 __le16 tc_bw_max[2]; 1504 u8 reserved3[32]; 1505}; 1506 1507I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1508 1509/* Query Switching Component Bandwidth Allocation per Traffic Type 1510 * (indirect 0x041A) 1511 */ 1512struct i40e_aqc_query_switching_comp_bw_config_resp { 1513 u8 tc_valid_bits; 1514 u8 reserved[2]; 1515 u8 absolute_credits_enable; /* bool */ 1516 u8 tc_bw_share_credits[8]; 1517 __le16 tc_bw_limits[8]; 1518 1519 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1520 __le16 tc_bw_max[2]; 1521}; 1522 1523I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1524 1525/* Suspend/resume port TX traffic 1526 * (direct 0x041B and 0x041C) uses the generic SEID struct 1527 */ 1528 1529/* Configure partition BW 1530 * (indirect 0x041D) 1531 */ 1532struct i40e_aqc_configure_partition_bw_data { 1533 __le16 pf_valid_bits; 1534 u8 min_bw[16]; /* guaranteed bandwidth */ 1535 u8 max_bw[16]; /* bandwidth limit */ 1536}; 1537 1538I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1539 1540/* Get and set the active HMC resource profile and status. 1541 * (direct 0x0500) and (direct 0x0501) 1542 */ 1543struct i40e_aq_get_set_hmc_resource_profile { 1544 u8 pm_profile; 1545 u8 pe_vf_enabled; 1546 u8 reserved[14]; 1547}; 1548 1549I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1550 1551enum i40e_aq_hmc_profile { 1552 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1553 I40E_HMC_PROFILE_DEFAULT = 1, 1554 I40E_HMC_PROFILE_FAVOR_VF = 2, 1555 I40E_HMC_PROFILE_EQUAL = 3, 1556}; 1557 1558#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1559#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1560 1561/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1562 1563/* set in param0 for get phy abilities to report qualified modules */ 1564#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1565#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1566 1567enum i40e_aq_phy_type { 1568 I40E_PHY_TYPE_SGMII = 0x0, 1569 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1570 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1571 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1572 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1573 I40E_PHY_TYPE_XAUI = 0x5, 1574 I40E_PHY_TYPE_XFI = 0x6, 1575 I40E_PHY_TYPE_SFI = 0x7, 1576 I40E_PHY_TYPE_XLAUI = 0x8, 1577 I40E_PHY_TYPE_XLPPI = 0x9, 1578 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1579 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1580 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1581 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1582 I40E_PHY_TYPE_100BASE_TX = 0x11, 1583 I40E_PHY_TYPE_1000BASE_T = 0x12, 1584 I40E_PHY_TYPE_10GBASE_T = 0x13, 1585 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1586 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1587 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1588 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1589 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1590 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1591 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1592 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1593 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1594 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1595 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1596 I40E_PHY_TYPE_MAX 1597}; 1598 1599#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1600#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1601#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1602#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1603#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1604 1605enum i40e_aq_link_speed { 1606 I40E_LINK_SPEED_UNKNOWN = 0, 1607 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1608 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1609 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1610 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1611 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1612}; 1613 1614struct i40e_aqc_module_desc { 1615 u8 oui[3]; 1616 u8 reserved1; 1617 u8 part_number[16]; 1618 u8 revision[4]; 1619 u8 reserved2[8]; 1620}; 1621 1622I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1623 1624struct i40e_aq_get_phy_abilities_resp { 1625 __le32 phy_type; /* bitmap using the above enum for offsets */ 1626 u8 link_speed; /* bitmap using the above enum bit patterns */ 1627 u8 abilities; 1628#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1629#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1630#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1631#define I40E_AQ_PHY_LINK_ENABLED 0x08 1632#define I40E_AQ_PHY_AN_ENABLED 0x10 1633#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1634 __le16 eee_capability; 1635#define I40E_AQ_EEE_100BASE_TX 0x0002 1636#define I40E_AQ_EEE_1000BASE_T 0x0004 1637#define I40E_AQ_EEE_10GBASE_T 0x0008 1638#define I40E_AQ_EEE_1000BASE_KX 0x0010 1639#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1640#define I40E_AQ_EEE_10GBASE_KR 0x0040 1641 __le32 eeer_val; 1642 u8 d3_lpan; 1643#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1644 u8 reserved[3]; 1645 u8 phy_id[4]; 1646 u8 module_type[3]; 1647 u8 qualified_module_count; 1648#define I40E_AQ_PHY_MAX_QMS 16 1649 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1650}; 1651 1652I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1653 1654/* Set PHY Config (direct 0x0601) */ 1655struct i40e_aq_set_phy_config { /* same bits as above in all */ 1656 __le32 phy_type; 1657 u8 link_speed; 1658 u8 abilities; 1659/* bits 0-2 use the values from get_phy_abilities_resp */ 1660#define I40E_AQ_PHY_ENABLE_LINK 0x08 1661#define I40E_AQ_PHY_ENABLE_AN 0x10 1662#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1663 __le16 eee_capability; 1664 __le32 eeer; 1665 u8 low_power_ctrl; 1666 u8 reserved[3]; 1667}; 1668 1669I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1670 1671/* Set MAC Config command data structure (direct 0x0603) */ 1672struct i40e_aq_set_mac_config { 1673 __le16 max_frame_size; 1674 u8 params; 1675#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1676#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1677#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1678#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1679#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1680#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1681#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1682#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1683#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1684#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1685#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1686#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1687#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1688#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1689 u8 tx_timer_priority; /* bitmap */ 1690 __le16 tx_timer_value; 1691 __le16 fc_refresh_threshold; 1692 u8 reserved[8]; 1693}; 1694 1695I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1696 1697/* Restart Auto-Negotiation (direct 0x605) */ 1698struct i40e_aqc_set_link_restart_an { 1699 u8 command; 1700#define I40E_AQ_PHY_RESTART_AN 0x02 1701#define I40E_AQ_PHY_LINK_ENABLE 0x04 1702 u8 reserved[15]; 1703}; 1704 1705I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1706 1707/* Get Link Status cmd & response data structure (direct 0x0607) */ 1708struct i40e_aqc_get_link_status { 1709 __le16 command_flags; /* only field set on command */ 1710#define I40E_AQ_LSE_MASK 0x3 1711#define I40E_AQ_LSE_NOP 0x0 1712#define I40E_AQ_LSE_DISABLE 0x2 1713#define I40E_AQ_LSE_ENABLE 0x3 1714/* only response uses this flag */ 1715#define I40E_AQ_LSE_IS_ENABLED 0x1 1716 u8 phy_type; /* i40e_aq_phy_type */ 1717 u8 link_speed; /* i40e_aq_link_speed */ 1718 u8 link_info; 1719#define I40E_AQ_LINK_UP 0x01 1720#define I40E_AQ_LINK_FAULT 0x02 1721#define I40E_AQ_LINK_FAULT_TX 0x04 1722#define I40E_AQ_LINK_FAULT_RX 0x08 1723#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1724#define I40E_AQ_MEDIA_AVAILABLE 0x40 1725#define I40E_AQ_SIGNAL_DETECT 0x80 1726 u8 an_info; 1727#define I40E_AQ_AN_COMPLETED 0x01 1728#define I40E_AQ_LP_AN_ABILITY 0x02 1729#define I40E_AQ_PD_FAULT 0x04 1730#define I40E_AQ_FEC_EN 0x08 1731#define I40E_AQ_PHY_LOW_POWER 0x10 1732#define I40E_AQ_LINK_PAUSE_TX 0x20 1733#define I40E_AQ_LINK_PAUSE_RX 0x40 1734#define I40E_AQ_QUALIFIED_MODULE 0x80 1735 u8 ext_info; 1736#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1737#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1738#define I40E_AQ_LINK_TX_SHIFT 0x02 1739#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1740#define I40E_AQ_LINK_TX_ACTIVE 0x00 1741#define I40E_AQ_LINK_TX_DRAINED 0x01 1742#define I40E_AQ_LINK_TX_FLUSHED 0x03 1743#define I40E_AQ_LINK_FORCED_40G 0x10 1744 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1745 __le16 max_frame_size; 1746 u8 config; 1747#define I40E_AQ_CONFIG_CRC_ENA 0x04 1748#define I40E_AQ_CONFIG_PACING_MASK 0x78 1749 u8 reserved[5]; 1750}; 1751 1752I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1753 1754/* Set event mask command (direct 0x613) */ 1755struct i40e_aqc_set_phy_int_mask { 1756 u8 reserved[8]; 1757 __le16 event_mask; 1758#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1759#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1760#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1761#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1762#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1763#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1764#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1765#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1766#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1767 u8 reserved1[6]; 1768}; 1769 1770I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1771 1772/* Get Local AN advt register (direct 0x0614) 1773 * Set Local AN advt register (direct 0x0615) 1774 * Get Link Partner AN advt register (direct 0x0616) 1775 */ 1776struct i40e_aqc_an_advt_reg { 1777 __le32 local_an_reg0; 1778 __le16 local_an_reg1; 1779 u8 reserved[10]; 1780}; 1781 1782I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1783 1784/* Set Loopback mode (0x0618) */ 1785struct i40e_aqc_set_lb_mode { 1786 __le16 lb_mode; 1787#define I40E_AQ_LB_PHY_LOCAL 0x01 1788#define I40E_AQ_LB_PHY_REMOTE 0x02 1789#define I40E_AQ_LB_MAC_LOCAL 0x04 1790 u8 reserved[14]; 1791}; 1792 1793I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1794 1795/* Set PHY Debug command (0x0622) */ 1796struct i40e_aqc_set_phy_debug { 1797 u8 command_flags; 1798#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1799#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1800#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1801 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1802#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1803#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1804#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1805#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1806 u8 reserved[15]; 1807}; 1808 1809I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1810 1811enum i40e_aq_phy_reg_type { 1812 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1813 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1814 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1815}; 1816 1817/* NVM Read command (indirect 0x0701) 1818 * NVM Erase commands (direct 0x0702) 1819 * NVM Update commands (indirect 0x0703) 1820 */ 1821struct i40e_aqc_nvm_update { 1822 u8 command_flags; 1823#define I40E_AQ_NVM_LAST_CMD 0x01 1824#define I40E_AQ_NVM_FLASH_ONLY 0x80 1825 u8 module_pointer; 1826 __le16 length; 1827 __le32 offset; 1828 __le32 addr_high; 1829 __le32 addr_low; 1830}; 1831 1832I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1833 1834/* NVM Config Read (indirect 0x0704) */ 1835struct i40e_aqc_nvm_config_read { 1836 __le16 cmd_flags; 1837#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1838#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1839#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1840 __le16 element_count; 1841 __le16 element_id; /* Feature/field ID */ 1842 __le16 element_id_msw; /* MSWord of field ID */ 1843 __le32 address_high; 1844 __le32 address_low; 1845}; 1846 1847I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1848 1849/* NVM Config Write (indirect 0x0705) */ 1850struct i40e_aqc_nvm_config_write { 1851 __le16 cmd_flags; 1852 __le16 element_count; 1853 u8 reserved[4]; 1854 __le32 address_high; 1855 __le32 address_low; 1856}; 1857 1858I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1859 1860/* Used for 0x0704 as well as for 0x0705 commands */ 1861#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1862#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1863 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1864#define I40E_AQ_ANVM_FEATURE 0 1865#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1866struct i40e_aqc_nvm_config_data_feature { 1867 __le16 feature_id; 1868#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1869#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1870#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1871 __le16 feature_options; 1872 __le16 feature_selection; 1873}; 1874 1875I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1876 1877struct i40e_aqc_nvm_config_data_immediate_field { 1878 __le32 field_id; 1879 __le32 field_value; 1880 __le16 field_options; 1881 __le16 reserved; 1882}; 1883 1884I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1885 1886/* Send to PF command (indirect 0x0801) id is only used by PF 1887 * Send to VF command (indirect 0x0802) id is only used by PF 1888 * Send to Peer PF command (indirect 0x0803) 1889 */ 1890struct i40e_aqc_pf_vf_message { 1891 __le32 id; 1892 u8 reserved[4]; 1893 __le32 addr_high; 1894 __le32 addr_low; 1895}; 1896 1897I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1898 1899/* Alternate structure */ 1900 1901/* Direct write (direct 0x0900) 1902 * Direct read (direct 0x0902) 1903 */ 1904struct i40e_aqc_alternate_write { 1905 __le32 address0; 1906 __le32 data0; 1907 __le32 address1; 1908 __le32 data1; 1909}; 1910 1911I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1912 1913/* Indirect write (indirect 0x0901) 1914 * Indirect read (indirect 0x0903) 1915 */ 1916 1917struct i40e_aqc_alternate_ind_write { 1918 __le32 address; 1919 __le32 length; 1920 __le32 addr_high; 1921 __le32 addr_low; 1922}; 1923 1924I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1925 1926/* Done alternate write (direct 0x0904) 1927 * uses i40e_aq_desc 1928 */ 1929struct i40e_aqc_alternate_write_done { 1930 __le16 cmd_flags; 1931#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1932#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1933#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1934#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1935 u8 reserved[14]; 1936}; 1937 1938I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1939 1940/* Set OEM mode (direct 0x0905) */ 1941struct i40e_aqc_alternate_set_mode { 1942 __le32 mode; 1943#define I40E_AQ_ALTERNATE_MODE_NONE 0 1944#define I40E_AQ_ALTERNATE_MODE_OEM 1 1945 u8 reserved[12]; 1946}; 1947 1948I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1949 1950/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1951 1952/* async events 0x10xx */ 1953 1954/* Lan Queue Overflow Event (direct, 0x1001) */ 1955struct i40e_aqc_lan_overflow { 1956 __le32 prtdcb_rupto; 1957 __le32 otx_ctl; 1958 u8 reserved[8]; 1959}; 1960 1961I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1962 1963/* Get LLDP MIB (indirect 0x0A00) */ 1964struct i40e_aqc_lldp_get_mib { 1965 u8 type; 1966 u8 reserved1; 1967#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1968#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1969#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1970#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1971#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1972#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1973#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1974#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1975#define I40E_AQ_LLDP_TX_SHIFT 0x4 1976#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1977/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1978 __le16 local_len; 1979 __le16 remote_len; 1980 u8 reserved2[2]; 1981 __le32 addr_high; 1982 __le32 addr_low; 1983}; 1984 1985I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1986 1987/* Configure LLDP MIB Change Event (direct 0x0A01) 1988 * also used for the event (with type in the command field) 1989 */ 1990struct i40e_aqc_lldp_update_mib { 1991 u8 command; 1992#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1993#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1994 u8 reserved[7]; 1995 __le32 addr_high; 1996 __le32 addr_low; 1997}; 1998 1999I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2000 2001/* Add LLDP TLV (indirect 0x0A02) 2002 * Delete LLDP TLV (indirect 0x0A04) 2003 */ 2004struct i40e_aqc_lldp_add_tlv { 2005 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2006 u8 reserved1[1]; 2007 __le16 len; 2008 u8 reserved2[4]; 2009 __le32 addr_high; 2010 __le32 addr_low; 2011}; 2012 2013I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2014 2015/* Update LLDP TLV (indirect 0x0A03) */ 2016struct i40e_aqc_lldp_update_tlv { 2017 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2018 u8 reserved; 2019 __le16 old_len; 2020 __le16 new_offset; 2021 __le16 new_len; 2022 __le32 addr_high; 2023 __le32 addr_low; 2024}; 2025 2026I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2027 2028/* Stop LLDP (direct 0x0A05) */ 2029struct i40e_aqc_lldp_stop { 2030 u8 command; 2031#define I40E_AQ_LLDP_AGENT_STOP 0x0 2032#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2033 u8 reserved[15]; 2034}; 2035 2036I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2037 2038/* Start LLDP (direct 0x0A06) */ 2039 2040struct i40e_aqc_lldp_start { 2041 u8 command; 2042#define I40E_AQ_LLDP_AGENT_START 0x1 2043 u8 reserved[15]; 2044}; 2045 2046I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2047 2048/* Apply MIB changes (0x0A07) 2049 * uses the generic struc as it contains no data 2050 */ 2051 2052/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2053struct i40e_aqc_add_udp_tunnel { 2054 __le16 udp_port; 2055 u8 reserved0[3]; 2056 u8 protocol_type; 2057#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2058#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2059#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2060 u8 reserved1[10]; 2061}; 2062 2063I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2064 2065struct i40e_aqc_add_udp_tunnel_completion { 2066 __le16 udp_port; 2067 u8 filter_entry_index; 2068 u8 multiple_pfs; 2069#define I40E_AQC_SINGLE_PF 0x0 2070#define I40E_AQC_MULTIPLE_PFS 0x1 2071 u8 total_filters; 2072 u8 reserved[11]; 2073}; 2074 2075I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2076 2077/* remove UDP Tunnel command (0x0B01) */ 2078struct i40e_aqc_remove_udp_tunnel { 2079 u8 reserved[2]; 2080 u8 index; /* 0 to 15 */ 2081 u8 reserved2[13]; 2082}; 2083 2084I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2085 2086struct i40e_aqc_del_udp_tunnel_completion { 2087 __le16 udp_port; 2088 u8 index; /* 0 to 15 */ 2089 u8 multiple_pfs; 2090 u8 total_filters_used; 2091 u8 reserved1[11]; 2092}; 2093 2094I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2095 2096/* tunnel key structure 0x0B10 */ 2097 2098struct i40e_aqc_tunnel_key_structure_A0 { 2099 __le16 key1_off; 2100 __le16 key1_len; 2101 __le16 key2_off; 2102 __le16 key2_len; 2103 __le16 flags; 2104#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2105/* response flags */ 2106#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2107#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2108#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2109 u8 resreved[6]; 2110}; 2111 2112I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); 2113 2114struct i40e_aqc_tunnel_key_structure { 2115 u8 key1_off; 2116 u8 key2_off; 2117 u8 key1_len; /* 0 to 15 */ 2118 u8 key2_len; /* 0 to 15 */ 2119 u8 flags; 2120#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2121/* response flags */ 2122#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2123#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2124#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2125 u8 network_key_index; 2126#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2127#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2128#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2129#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2130 u8 reserved[10]; 2131}; 2132 2133I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2134 2135/* OEM mode commands (direct 0xFE0x) */ 2136struct i40e_aqc_oem_param_change { 2137 __le32 param_type; 2138#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2139#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2140#define I40E_AQ_OEM_PARAM_MAC 2 2141 __le32 param_value1; 2142 __le16 param_value2; 2143 u8 reserved[6]; 2144}; 2145 2146I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2147 2148struct i40e_aqc_oem_state_change { 2149 __le32 state; 2150#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2151#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2152 u8 reserved[12]; 2153}; 2154 2155I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2156 2157/* Initialize OCSD (0xFE02, direct) */ 2158struct i40e_aqc_opc_oem_ocsd_initialize { 2159 u8 type_status; 2160 u8 reserved1[3]; 2161 __le32 ocsd_memory_block_addr_high; 2162 __le32 ocsd_memory_block_addr_low; 2163 __le32 requested_update_interval; 2164}; 2165 2166I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2167 2168/* Initialize OCBB (0xFE03, direct) */ 2169struct i40e_aqc_opc_oem_ocbb_initialize { 2170 u8 type_status; 2171 u8 reserved1[3]; 2172 __le32 ocbb_memory_block_addr_high; 2173 __le32 ocbb_memory_block_addr_low; 2174 u8 reserved2[4]; 2175}; 2176 2177I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2178 2179/* debug commands */ 2180 2181/* get device id (0xFF00) uses the generic structure */ 2182 2183/* set test more (0xFF01, internal) */ 2184 2185struct i40e_acq_set_test_mode { 2186 u8 mode; 2187#define I40E_AQ_TEST_PARTIAL 0 2188#define I40E_AQ_TEST_FULL 1 2189#define I40E_AQ_TEST_NVM 2 2190 u8 reserved[3]; 2191 u8 command; 2192#define I40E_AQ_TEST_OPEN 0 2193#define I40E_AQ_TEST_CLOSE 1 2194#define I40E_AQ_TEST_INC 2 2195 u8 reserved2[3]; 2196 __le32 address_high; 2197 __le32 address_low; 2198}; 2199 2200I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2201 2202/* Debug Read Register command (0xFF03) 2203 * Debug Write Register command (0xFF04) 2204 */ 2205struct i40e_aqc_debug_reg_read_write { 2206 __le32 reserved; 2207 __le32 address; 2208 __le32 value_high; 2209 __le32 value_low; 2210}; 2211 2212I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2213 2214/* Scatter/gather Reg Read (indirect 0xFF05) 2215 * Scatter/gather Reg Write (indirect 0xFF06) 2216 */ 2217 2218/* i40e_aq_desc is used for the command */ 2219struct i40e_aqc_debug_reg_sg_element_data { 2220 __le32 address; 2221 __le32 value; 2222}; 2223 2224/* Debug Modify register (direct 0xFF07) */ 2225struct i40e_aqc_debug_modify_reg { 2226 __le32 address; 2227 __le32 value; 2228 __le32 clear_mask; 2229 __le32 set_mask; 2230}; 2231 2232I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2233 2234/* dump internal data (0xFF08, indirect) */ 2235 2236#define I40E_AQ_CLUSTER_ID_AUX 0 2237#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2238#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2239#define I40E_AQ_CLUSTER_ID_HMC 3 2240#define I40E_AQ_CLUSTER_ID_MAC0 4 2241#define I40E_AQ_CLUSTER_ID_MAC1 5 2242#define I40E_AQ_CLUSTER_ID_MAC2 6 2243#define I40E_AQ_CLUSTER_ID_MAC3 7 2244#define I40E_AQ_CLUSTER_ID_DCB 8 2245#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2246#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2247#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2248 2249struct i40e_aqc_debug_dump_internals { 2250 u8 cluster_id; 2251 u8 table_id; 2252 __le16 data_size; 2253 __le32 idx; 2254 __le32 address_high; 2255 __le32 address_low; 2256}; 2257 2258I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2259 2260struct i40e_aqc_debug_modify_internals { 2261 u8 cluster_id; 2262 u8 cluster_specific_params[7]; 2263 __le32 address_high; 2264 __le32 address_low; 2265}; 2266 2267I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2268 2269#endif 2270