1/* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8#ifndef _QLCNIC_H_ 9#define _QLCNIC_H_ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/types.h> 14#include <linux/ioport.h> 15#include <linux/pci.h> 16#include <linux/netdevice.h> 17#include <linux/etherdevice.h> 18#include <linux/ip.h> 19#include <linux/in.h> 20#include <linux/tcp.h> 21#include <linux/skbuff.h> 22#include <linux/firmware.h> 23#include <linux/ethtool.h> 24#include <linux/mii.h> 25#include <linux/timer.h> 26#include <linux/irq.h> 27 28#include <linux/vmalloc.h> 29 30#include <linux/io.h> 31#include <asm/byteorder.h> 32#include <linux/bitops.h> 33#include <linux/if_vlan.h> 34 35#include "qlcnic_hdr.h" 36#include "qlcnic_hw.h" 37#include "qlcnic_83xx_hw.h" 38#include "qlcnic_dcb.h" 39 40#define _QLCNIC_LINUX_MAJOR 5 41#define _QLCNIC_LINUX_MINOR 3 42#define _QLCNIC_LINUX_SUBVERSION 62 43#define QLCNIC_LINUX_VERSIONID "5.3.62" 44#define QLCNIC_DRV_IDC_VER 0x01 45#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 46 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 47 48#define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 49#define _major(v) (((v) >> 24) & 0xff) 50#define _minor(v) (((v) >> 16) & 0xff) 51#define _build(v) ((v) & 0xffff) 52 53/* version in image has weird encoding: 54 * 7:0 - major 55 * 15:8 - minor 56 * 31:16 - build (little endian) 57 */ 58#define QLCNIC_DECODE_VERSION(v) \ 59 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 60 61#define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 62#define QLCNIC_NUM_FLASH_SECTORS (64) 63#define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 64#define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 65 * QLCNIC_FLASH_SECTOR_SIZE) 66 67#define RCV_DESC_RINGSIZE(rds_ring) \ 68 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 69#define RCV_BUFF_RINGSIZE(rds_ring) \ 70 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 71#define STATUS_DESC_RINGSIZE(sds_ring) \ 72 (sizeof(struct status_desc) * (sds_ring)->num_desc) 73#define TX_BUFF_RINGSIZE(tx_ring) \ 74 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 75#define TX_DESC_RINGSIZE(tx_ring) \ 76 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 77 78#define QLCNIC_P3P_A0 0x50 79#define QLCNIC_P3P_C0 0x58 80 81#define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 82 83#define FIRST_PAGE_GROUP_START 0 84#define FIRST_PAGE_GROUP_END 0x100000 85 86#define P3P_MAX_MTU (9600) 87#define P3P_MIN_MTU (68) 88#define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 89 90#define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 91#define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 92#define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 93#define QLCNIC_LRO_BUFFER_EXTRA 2048 94 95/* Tx defines */ 96#define QLCNIC_MAX_FRAGS_PER_TX 14 97#define MAX_TSO_HEADER_DESC 2 98#define MGMT_CMD_DESC_RESV 4 99#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 100 + MGMT_CMD_DESC_RESV) 101#define QLCNIC_MAX_TX_TIMEOUTS 2 102 103/* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */ 104#define QLCNIC_SINGLE_RING 1 105#define QLCNIC_DEF_SDS_RINGS 4 106#define QLCNIC_DEF_TX_RINGS 4 107#define QLCNIC_MAX_VNIC_TX_RINGS 4 108#define QLCNIC_MAX_VNIC_SDS_RINGS 4 109#define QLCNIC_83XX_MINIMUM_VECTOR 3 110#define QLCNIC_82XX_MINIMUM_VECTOR 2 111 112enum qlcnic_queue_type { 113 QLCNIC_TX_QUEUE = 1, 114 QLCNIC_RX_QUEUE, 115}; 116 117/* Operational mode for driver */ 118#define QLCNIC_VNIC_MODE 0xFF 119#define QLCNIC_DEFAULT_MODE 0x0 120 121/* Virtual NIC function count */ 122#define QLC_DEFAULT_VNIC_COUNT 8 123#define QLC_84XX_VNIC_COUNT 16 124 125/* 126 * Following are the states of the Phantom. Phantom will set them and 127 * Host will read to check if the fields are correct. 128 */ 129#define PHAN_INITIALIZE_FAILED 0xffff 130#define PHAN_INITIALIZE_COMPLETE 0xff01 131 132/* Host writes the following to notify that it has done the init-handshake */ 133#define PHAN_INITIALIZE_ACK 0xf00f 134#define PHAN_PEG_RCV_INITIALIZED 0xff01 135 136#define NUM_RCV_DESC_RINGS 3 137 138#define RCV_RING_NORMAL 0 139#define RCV_RING_JUMBO 1 140 141#define MIN_CMD_DESCRIPTORS 64 142#define MIN_RCV_DESCRIPTORS 64 143#define MIN_JUMBO_DESCRIPTORS 32 144 145#define MAX_CMD_DESCRIPTORS 1024 146#define MAX_RCV_DESCRIPTORS_1G 4096 147#define MAX_RCV_DESCRIPTORS_10G 8192 148#define MAX_RCV_DESCRIPTORS_VF 2048 149#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 150#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 151 152#define DEFAULT_RCV_DESCRIPTORS_1G 2048 153#define DEFAULT_RCV_DESCRIPTORS_10G 4096 154#define DEFAULT_RCV_DESCRIPTORS_VF 1024 155#define MAX_RDS_RINGS 2 156 157#define get_next_index(index, length) \ 158 (((index) + 1) & ((length) - 1)) 159 160/* 161 * Following data structures describe the descriptors that will be used. 162 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 163 * we are doing LSO (above the 1500 size packet) only. 164 */ 165struct cmd_desc_type0 { 166 u8 tcp_hdr_offset; /* For LSO only */ 167 u8 ip_hdr_offset; /* For LSO only */ 168 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 169 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 170 171 __le64 addr_buffer2; 172 173 __le16 encap_descr; /* 15:10 offset of outer L3 header, 174 * 9:6 number of 32bit words in outer L3 header, 175 * 5 offload outer L4 checksum, 176 * 4 offload outer L3 checksum, 177 * 3 Inner L4 type, TCP=0, UDP=1, 178 * 2 Inner L3 type, IPv4=0, IPv6=1, 179 * 1 Outer L3 type,IPv4=0, IPv6=1, 180 * 0 type of encapsulation, GRE=0, VXLAN=1 181 */ 182 __le16 mss; 183 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 184 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 185 u8 outer_hdr_length; /* Encapsulation only */ 186 u8 rsvd1; 187 188 __le64 addr_buffer3; 189 __le64 addr_buffer1; 190 191 __le16 buffer_length[4]; 192 193 __le64 addr_buffer4; 194 195 u8 eth_addr[ETH_ALEN]; 196 __le16 vlan_TCI; /* In case of encapsulation, 197 * this is for outer VLAN 198 */ 199 200} __attribute__ ((aligned(64))); 201 202/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 203struct rcv_desc { 204 __le16 reference_handle; 205 __le16 reserved; 206 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 207 __le64 addr_buffer; 208} __packed; 209 210struct status_desc { 211 __le64 status_desc_data[2]; 212} __attribute__ ((aligned(16))); 213 214/* UNIFIED ROMIMAGE */ 215#define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 216#define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 217#define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 218#define QLCNIC_UNI_DIR_SECT_FW 0x7 219 220/*Offsets */ 221#define QLCNIC_UNI_CHIP_REV_OFF 10 222#define QLCNIC_UNI_FLAGS_OFF 11 223#define QLCNIC_UNI_BIOS_VERSION_OFF 12 224#define QLCNIC_UNI_BOOTLD_IDX_OFF 27 225#define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 226 227struct uni_table_desc{ 228 __le32 findex; 229 __le32 num_entries; 230 __le32 entry_size; 231 __le32 reserved[5]; 232}; 233 234struct uni_data_desc{ 235 __le32 findex; 236 __le32 size; 237 __le32 reserved[5]; 238}; 239 240/* Flash Defines and Structures */ 241#define QLCNIC_FLT_LOCATION 0x3F1000 242#define QLCNIC_FDT_LOCATION 0x3F0000 243#define QLCNIC_B0_FW_IMAGE_REGION 0x74 244#define QLCNIC_C0_FW_IMAGE_REGION 0x97 245#define QLCNIC_BOOTLD_REGION 0X72 246struct qlcnic_flt_header { 247 u16 version; 248 u16 len; 249 u16 checksum; 250 u16 reserved; 251}; 252 253struct qlcnic_flt_entry { 254 u8 region; 255 u8 reserved0; 256 u8 attrib; 257 u8 reserved1; 258 u32 size; 259 u32 start_addr; 260 u32 end_addr; 261}; 262 263/* Flash Descriptor Table */ 264struct qlcnic_fdt { 265 u32 valid; 266 u16 ver; 267 u16 len; 268 u16 cksum; 269 u16 unused; 270 u8 model[16]; 271 u8 mfg_id; 272 u16 id; 273 u8 flag; 274 u8 erase_cmd; 275 u8 alt_erase_cmd; 276 u8 write_enable_cmd; 277 u8 write_enable_bits; 278 u8 write_statusreg_cmd; 279 u8 unprotected_sec_cmd; 280 u8 read_manuf_cmd; 281 u32 block_size; 282 u32 alt_block_size; 283 u32 flash_size; 284 u32 write_enable_data; 285 u8 readid_addr_len; 286 u8 write_disable_bits; 287 u8 read_dev_id_len; 288 u8 chip_erase_cmd; 289 u16 read_timeo; 290 u8 protected_sec_cmd; 291 u8 resvd[65]; 292}; 293/* Magic number to let user know flash is programmed */ 294#define QLCNIC_BDINFO_MAGIC 0x12345678 295 296#define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 297#define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 298#define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 299#define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 300#define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 301#define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 302#define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 303#define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 304#define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 305#define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 306#define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 307#define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 308#define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 309#define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 310 311#define QLCNIC_MSIX_TABLE_OFFSET 0x44 312 313/* Flash memory map */ 314#define QLCNIC_BRDCFG_START 0x4000 /* board config */ 315#define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 316#define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 317#define QLCNIC_USER_START 0x3E8000 /* Firmware info */ 318 319#define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 320#define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 321#define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 322#define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 323 324#define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 325#define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 326 327#define QLCNIC_FW_MIN_SIZE (0x3fffff) 328#define QLCNIC_UNIFIED_ROMIMAGE 0 329#define QLCNIC_FLASH_ROMIMAGE 1 330#define QLCNIC_UNKNOWN_ROMIMAGE 0xff 331 332#define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 333#define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 334 335extern char qlcnic_driver_name[]; 336 337extern int qlcnic_use_msi; 338extern int qlcnic_use_msi_x; 339extern int qlcnic_auto_fw_reset; 340extern int qlcnic_load_fw_file; 341 342/* Number of status descriptors to handle per interrupt */ 343#define MAX_STATUS_HANDLE (64) 344 345/* 346 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 347 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 348 */ 349struct qlcnic_skb_frag { 350 u64 dma; 351 u64 length; 352}; 353 354/* Following defines are for the state of the buffers */ 355#define QLCNIC_BUFFER_FREE 0 356#define QLCNIC_BUFFER_BUSY 1 357 358/* 359 * There will be one qlcnic_buffer per skb packet. These will be 360 * used to save the dma info for pci_unmap_page() 361 */ 362struct qlcnic_cmd_buffer { 363 struct sk_buff *skb; 364 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 365 u32 frag_count; 366}; 367 368/* In rx_buffer, we do not need multiple fragments as is a single buffer */ 369struct qlcnic_rx_buffer { 370 u16 ref_handle; 371 struct sk_buff *skb; 372 struct list_head list; 373 u64 dma; 374}; 375 376/* Board types */ 377#define QLCNIC_GBE 0x01 378#define QLCNIC_XGBE 0x02 379 380/* 381 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 382 * adjusted based on configured MTU. 383 */ 384#define QLCNIC_INTR_COAL_TYPE_RX 1 385#define QLCNIC_INTR_COAL_TYPE_TX 2 386#define QLCNIC_INTR_COAL_TYPE_RX_TX 3 387 388#define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 389#define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 390 391#define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 392#define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 393 394#define QLCNIC_INTR_DEFAULT 0x04 395#define QLCNIC_CONFIG_INTR_COALESCE 3 396#define QLCNIC_DEV_INFO_SIZE 2 397 398struct qlcnic_nic_intr_coalesce { 399 u8 type; 400 u8 sts_ring_mask; 401 u16 rx_packets; 402 u16 rx_time_us; 403 u16 tx_packets; 404 u16 tx_time_us; 405 u16 flag; 406 u32 timer_out; 407}; 408 409struct qlcnic_83xx_dump_template_hdr { 410 u32 type; 411 u32 offset; 412 u32 size; 413 u32 cap_mask; 414 u32 num_entries; 415 u32 version; 416 u32 timestamp; 417 u32 checksum; 418 u32 drv_cap_mask; 419 u32 sys_info[3]; 420 u32 saved_state[16]; 421 u32 cap_sizes[8]; 422 u32 ocm_wnd_reg[16]; 423 u32 rsvd[0]; 424}; 425 426struct qlcnic_82xx_dump_template_hdr { 427 u32 type; 428 u32 offset; 429 u32 size; 430 u32 cap_mask; 431 u32 num_entries; 432 u32 version; 433 u32 timestamp; 434 u32 checksum; 435 u32 drv_cap_mask; 436 u32 sys_info[3]; 437 u32 saved_state[16]; 438 u32 cap_sizes[8]; 439 u32 rsvd[7]; 440 u32 capabilities; 441 u32 rsvd1[0]; 442}; 443 444#define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16) 445 446struct qlcnic_fw_dump { 447 u8 clr; /* flag to indicate if dump is cleared */ 448 bool enable; /* enable/disable dump */ 449 u32 size; /* total size of the dump */ 450 u32 cap_mask; /* Current capture mask */ 451 void *data; /* dump data area */ 452 void *tmpl_hdr; 453 dma_addr_t phys_addr; 454 void *dma_buffer; 455 bool use_pex_dma; 456 /* Read only elements which are common between 82xx and 83xx 457 * template header. Update these values immediately after we read 458 * template header from Firmware 459 */ 460 u32 tmpl_hdr_size; 461 u32 version; 462 u32 num_entries; 463 u32 offset; 464}; 465 466/* 467 * One hardware_context{} per adapter 468 * contains interrupt info as well shared hardware info. 469 */ 470struct qlcnic_hardware_context { 471 void __iomem *pci_base0; 472 void __iomem *ocm_win_crb; 473 474 unsigned long pci_len0; 475 476 rwlock_t crb_lock; 477 struct mutex mem_lock; 478 479 u8 revision_id; 480 u8 pci_func; 481 u8 linkup; 482 u8 loopback_state; 483 u8 beacon_state; 484 u8 has_link_events; 485 u8 fw_type; 486 u8 physical_port; 487 u8 reset_context; 488 u8 msix_supported; 489 u8 max_mac_filters; 490 u8 mc_enabled; 491 u8 max_mc_count; 492 u8 diag_test; 493 u8 num_msix; 494 u8 nic_mode; 495 int diag_cnt; 496 497 u16 max_uc_count; 498 u16 port_type; 499 u16 board_type; 500 u16 supported_type; 501 502 u16 link_speed; 503 u16 link_duplex; 504 u16 link_autoneg; 505 u16 module_type; 506 507 u16 op_mode; 508 u16 switch_mode; 509 u16 max_tx_ques; 510 u16 max_rx_ques; 511 u16 max_mtu; 512 u32 msg_enable; 513 u16 total_nic_func; 514 u16 max_pci_func; 515 u32 max_vnic_func; 516 u32 total_pci_func; 517 518 u32 capabilities; 519 u32 extra_capability[3]; 520 u32 temp; 521 u32 int_vec_bit; 522 u32 fw_hal_version; 523 u32 port_config; 524 struct qlcnic_hardware_ops *hw_ops; 525 struct qlcnic_nic_intr_coalesce coal; 526 struct qlcnic_fw_dump fw_dump; 527 struct qlcnic_fdt fdt; 528 struct qlc_83xx_reset reset; 529 struct qlc_83xx_idc idc; 530 struct qlc_83xx_fw_info *fw_info; 531 struct qlcnic_intrpt_config *intr_tbl; 532 struct qlcnic_sriov *sriov; 533 u32 *reg_tbl; 534 u32 *ext_reg_tbl; 535 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; 536 u32 mbox_reg[4]; 537 struct qlcnic_mailbox *mailbox; 538 u8 extend_lb_time; 539 u8 phys_port_id[ETH_ALEN]; 540 u8 lb_mode; 541 u16 vxlan_port; 542 struct device *hwmon_dev; 543 u32 post_mode; 544 bool run_post; 545}; 546 547struct qlcnic_adapter_stats { 548 u64 xmitcalled; 549 u64 xmitfinished; 550 u64 rxdropped; 551 u64 txdropped; 552 u64 csummed; 553 u64 rx_pkts; 554 u64 lro_pkts; 555 u64 rxbytes; 556 u64 txbytes; 557 u64 lrobytes; 558 u64 lso_frames; 559 u64 encap_lso_frames; 560 u64 encap_tx_csummed; 561 u64 encap_rx_csummed; 562 u64 xmit_on; 563 u64 xmit_off; 564 u64 skb_alloc_failure; 565 u64 null_rxbuf; 566 u64 rx_dma_map_error; 567 u64 tx_dma_map_error; 568 u64 spurious_intr; 569 u64 mac_filter_limit_overrun; 570}; 571 572/* 573 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 574 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 575 */ 576struct qlcnic_host_rds_ring { 577 void __iomem *crb_rcv_producer; 578 struct rcv_desc *desc_head; 579 struct qlcnic_rx_buffer *rx_buf_arr; 580 u32 num_desc; 581 u32 producer; 582 u32 dma_size; 583 u32 skb_size; 584 u32 flags; 585 struct list_head free_list; 586 spinlock_t lock; 587 dma_addr_t phys_addr; 588} ____cacheline_internodealigned_in_smp; 589 590struct qlcnic_host_sds_ring { 591 u32 consumer; 592 u32 num_desc; 593 void __iomem *crb_sts_consumer; 594 595 struct qlcnic_host_tx_ring *tx_ring; 596 struct status_desc *desc_head; 597 struct qlcnic_adapter *adapter; 598 struct napi_struct napi; 599 struct list_head free_list[NUM_RCV_DESC_RINGS]; 600 601 void __iomem *crb_intr_mask; 602 int irq; 603 604 dma_addr_t phys_addr; 605 char name[IFNAMSIZ + 12]; 606} ____cacheline_internodealigned_in_smp; 607 608struct qlcnic_tx_queue_stats { 609 u64 xmit_on; 610 u64 xmit_off; 611 u64 xmit_called; 612 u64 xmit_finished; 613 u64 tx_bytes; 614}; 615 616struct qlcnic_host_tx_ring { 617 int irq; 618 void __iomem *crb_intr_mask; 619 char name[IFNAMSIZ + 12]; 620 u16 ctx_id; 621 622 u32 state; 623 u32 producer; 624 u32 sw_consumer; 625 u32 num_desc; 626 627 struct qlcnic_tx_queue_stats tx_stats; 628 629 void __iomem *crb_cmd_producer; 630 struct cmd_desc_type0 *desc_head; 631 struct qlcnic_adapter *adapter; 632 struct napi_struct napi; 633 struct qlcnic_cmd_buffer *cmd_buf_arr; 634 __le32 *hw_consumer; 635 636 dma_addr_t phys_addr; 637 dma_addr_t hw_cons_phys_addr; 638 struct netdev_queue *txq; 639 /* Lock to protect Tx descriptors cleanup */ 640 spinlock_t tx_clean_lock; 641} ____cacheline_internodealigned_in_smp; 642 643/* 644 * Receive context. There is one such structure per instance of the 645 * receive processing. Any state information that is relevant to 646 * the receive, and is must be in this structure. The global data may be 647 * present elsewhere. 648 */ 649struct qlcnic_recv_context { 650 struct qlcnic_host_rds_ring *rds_rings; 651 struct qlcnic_host_sds_ring *sds_rings; 652 u32 state; 653 u16 context_id; 654 u16 virt_port; 655}; 656 657/* HW context creation */ 658 659#define QLCNIC_OS_CRB_RETRY_COUNT 4000 660 661#define QLCNIC_CDRP_CMD_BIT 0x80000000 662 663/* 664 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 665 * in the crb QLCNIC_CDRP_CRB_OFFSET. 666 */ 667#define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 668#define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 669 670#define QLCNIC_CDRP_RSP_OK 0x00000001 671#define QLCNIC_CDRP_RSP_FAIL 0x00000002 672#define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 673 674/* 675 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 676 * the crb QLCNIC_CDRP_CRB_OFFSET. 677 */ 678#define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 679 680#define QLCNIC_RCODE_SUCCESS 0 681#define QLCNIC_RCODE_INVALID_ARGS 6 682#define QLCNIC_RCODE_NOT_SUPPORTED 9 683#define QLCNIC_RCODE_NOT_PERMITTED 10 684#define QLCNIC_RCODE_NOT_IMPL 15 685#define QLCNIC_RCODE_INVALID 16 686#define QLCNIC_RCODE_TIMEOUT 17 687#define QLCNIC_DESTROY_CTX_RESET 0 688 689/* 690 * Capabilities Announced 691 */ 692#define QLCNIC_CAP0_LEGACY_CONTEXT (1) 693#define QLCNIC_CAP0_LEGACY_MN (1 << 2) 694#define QLCNIC_CAP0_LSO (1 << 6) 695#define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 696#define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 697#define QLCNIC_CAP0_VALIDOFF (1 << 11) 698#define QLCNIC_CAP0_LRO_MSS (1 << 21) 699#define QLCNIC_CAP0_TX_MULTI (1 << 22) 700 701/* 702 * Context state 703 */ 704#define QLCNIC_HOST_CTX_STATE_FREED 0 705#define QLCNIC_HOST_CTX_STATE_ACTIVE 2 706 707/* 708 * Rx context 709 */ 710 711struct qlcnic_hostrq_sds_ring { 712 __le64 host_phys_addr; /* Ring base addr */ 713 __le32 ring_size; /* Ring entries */ 714 __le16 msi_index; 715 __le16 rsvd; /* Padding */ 716} __packed; 717 718struct qlcnic_hostrq_rds_ring { 719 __le64 host_phys_addr; /* Ring base addr */ 720 __le64 buff_size; /* Packet buffer size */ 721 __le32 ring_size; /* Ring entries */ 722 __le32 ring_kind; /* Class of ring */ 723} __packed; 724 725struct qlcnic_hostrq_rx_ctx { 726 __le64 host_rsp_dma_addr; /* Response dma'd here */ 727 __le32 capabilities[4]; /* Flag bit vector */ 728 __le32 host_int_crb_mode; /* Interrupt crb usage */ 729 __le32 host_rds_crb_mode; /* RDS crb usage */ 730 /* These ring offsets are relative to data[0] below */ 731 __le32 rds_ring_offset; /* Offset to RDS config */ 732 __le32 sds_ring_offset; /* Offset to SDS config */ 733 __le16 num_rds_rings; /* Count of RDS rings */ 734 __le16 num_sds_rings; /* Count of SDS rings */ 735 __le16 valid_field_offset; 736 u8 txrx_sds_binding; 737 u8 msix_handler; 738 u8 reserved[128]; /* reserve space for future expansion*/ 739 /* MUST BE 64-bit aligned. 740 The following is packed: 741 - N hostrq_rds_rings 742 - N hostrq_sds_rings */ 743 char data[0]; 744} __packed; 745 746struct qlcnic_cardrsp_rds_ring{ 747 __le32 host_producer_crb; /* Crb to use */ 748 __le32 rsvd1; /* Padding */ 749} __packed; 750 751struct qlcnic_cardrsp_sds_ring { 752 __le32 host_consumer_crb; /* Crb to use */ 753 __le32 interrupt_crb; /* Crb to use */ 754} __packed; 755 756struct qlcnic_cardrsp_rx_ctx { 757 /* These ring offsets are relative to data[0] below */ 758 __le32 rds_ring_offset; /* Offset to RDS config */ 759 __le32 sds_ring_offset; /* Offset to SDS config */ 760 __le32 host_ctx_state; /* Starting State */ 761 __le32 num_fn_per_port; /* How many PCI fn share the port */ 762 __le16 num_rds_rings; /* Count of RDS rings */ 763 __le16 num_sds_rings; /* Count of SDS rings */ 764 __le16 context_id; /* Handle for context */ 765 u8 phys_port; /* Physical id of port */ 766 u8 virt_port; /* Virtual/Logical id of port */ 767 u8 reserved[128]; /* save space for future expansion */ 768 /* MUST BE 64-bit aligned. 769 The following is packed: 770 - N cardrsp_rds_rings 771 - N cardrs_sds_rings */ 772 char data[0]; 773} __packed; 774 775#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 776 (sizeof(HOSTRQ_RX) + \ 777 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 778 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 779 780#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 781 (sizeof(CARDRSP_RX) + \ 782 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 783 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 784 785/* 786 * Tx context 787 */ 788 789struct qlcnic_hostrq_cds_ring { 790 __le64 host_phys_addr; /* Ring base addr */ 791 __le32 ring_size; /* Ring entries */ 792 __le32 rsvd; /* Padding */ 793} __packed; 794 795struct qlcnic_hostrq_tx_ctx { 796 __le64 host_rsp_dma_addr; /* Response dma'd here */ 797 __le64 cmd_cons_dma_addr; /* */ 798 __le64 dummy_dma_addr; /* */ 799 __le32 capabilities[4]; /* Flag bit vector */ 800 __le32 host_int_crb_mode; /* Interrupt crb usage */ 801 __le32 rsvd1; /* Padding */ 802 __le16 rsvd2; /* Padding */ 803 __le16 interrupt_ctl; 804 __le16 msi_index; 805 __le16 rsvd3; /* Padding */ 806 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 807 u8 reserved[128]; /* future expansion */ 808} __packed; 809 810struct qlcnic_cardrsp_cds_ring { 811 __le32 host_producer_crb; /* Crb to use */ 812 __le32 interrupt_crb; /* Crb to use */ 813} __packed; 814 815struct qlcnic_cardrsp_tx_ctx { 816 __le32 host_ctx_state; /* Starting state */ 817 __le16 context_id; /* Handle for context */ 818 u8 phys_port; /* Physical id of port */ 819 u8 virt_port; /* Virtual/Logical id of port */ 820 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 821 u8 reserved[128]; /* future expansion */ 822} __packed; 823 824#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 825#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 826 827/* CRB */ 828 829#define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 830#define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 831#define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 832#define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 833 834#define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 835#define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 836#define QLCNIC_HOST_INT_CRB_MODE_NORX 2 837#define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 838#define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 839 840 841/* MAC */ 842 843#define MC_COUNT_P3P 38 844 845#define QLCNIC_MAC_NOOP 0 846#define QLCNIC_MAC_ADD 1 847#define QLCNIC_MAC_DEL 2 848#define QLCNIC_MAC_VLAN_ADD 3 849#define QLCNIC_MAC_VLAN_DEL 4 850 851enum qlcnic_mac_type { 852 QLCNIC_UNICAST_MAC, 853 QLCNIC_MULTICAST_MAC, 854 QLCNIC_BROADCAST_MAC, 855}; 856 857struct qlcnic_mac_vlan_list { 858 struct list_head list; 859 uint8_t mac_addr[ETH_ALEN+2]; 860 u16 vlan_id; 861 enum qlcnic_mac_type mac_type; 862}; 863 864/* MAC Learn */ 865#define NO_MAC_LEARN 0 866#define DRV_MAC_LEARN 1 867#define FDB_MAC_LEARN 2 868 869#define QLCNIC_HOST_REQUEST 0x13 870#define QLCNIC_REQUEST 0x14 871 872#define QLCNIC_MAC_EVENT 0x1 873 874#define QLCNIC_IP_UP 2 875#define QLCNIC_IP_DOWN 3 876 877#define QLCNIC_ILB_MODE 0x1 878#define QLCNIC_ELB_MODE 0x2 879#define QLCNIC_LB_MODE_MASK 0x3 880 881#define QLCNIC_LINKEVENT 0x1 882#define QLCNIC_LB_RESPONSE 0x2 883#define QLCNIC_IS_LB_CONFIGURED(VAL) \ 884 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 885 886/* 887 * Driver --> Firmware 888 */ 889#define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 890#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 891#define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 892#define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 893#define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 894#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 895 896#define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 897#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 898#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 899#define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 900 901/* 902 * Firmware --> Driver 903 */ 904 905#define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 906#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D 907#define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 908 909#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 910#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 911#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 912 913#define QLCNIC_LRO_REQUEST_CLEANUP 4 914 915/* Capabilites received */ 916#define QLCNIC_FW_CAPABILITY_TSO BIT_1 917#define QLCNIC_FW_CAPABILITY_BDG BIT_8 918#define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 919#define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 920#define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 921#define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 922#define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 923 924#define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 925#define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 926#define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 927#define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 928#define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9 929 930#define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0 931#define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1 932#define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4 933 934/* module types */ 935#define LINKEVENT_MODULE_NOT_PRESENT 1 936#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 937#define LINKEVENT_MODULE_OPTICAL_SRLR 3 938#define LINKEVENT_MODULE_OPTICAL_LRM 4 939#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 940#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 941#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 942#define LINKEVENT_MODULE_TWINAX 8 943 944#define LINKSPEED_10GBPS 10000 945#define LINKSPEED_1GBPS 1000 946#define LINKSPEED_100MBPS 100 947#define LINKSPEED_10MBPS 10 948 949#define LINKSPEED_ENCODED_10MBPS 0 950#define LINKSPEED_ENCODED_100MBPS 1 951#define LINKSPEED_ENCODED_1GBPS 2 952 953#define LINKEVENT_AUTONEG_DISABLED 0 954#define LINKEVENT_AUTONEG_ENABLED 1 955 956#define LINKEVENT_HALF_DUPLEX 0 957#define LINKEVENT_FULL_DUPLEX 1 958 959#define LINKEVENT_LINKSPEED_MBPS 0 960#define LINKEVENT_LINKSPEED_ENCODED 1 961 962/* firmware response header: 963 * 63:58 - message type 964 * 57:56 - owner 965 * 55:53 - desc count 966 * 52:48 - reserved 967 * 47:40 - completion id 968 * 39:32 - opcode 969 * 31:16 - error code 970 * 15:00 - reserved 971 */ 972#define qlcnic_get_nic_msg_opcode(msg_hdr) \ 973 ((msg_hdr >> 32) & 0xFF) 974 975struct qlcnic_fw_msg { 976 union { 977 struct { 978 u64 hdr; 979 u64 body[7]; 980 }; 981 u64 words[8]; 982 }; 983}; 984 985struct qlcnic_nic_req { 986 __le64 qhdr; 987 __le64 req_hdr; 988 __le64 words[6]; 989} __packed; 990 991struct qlcnic_mac_req { 992 u8 op; 993 u8 tag; 994 u8 mac_addr[6]; 995}; 996 997struct qlcnic_vlan_req { 998 __le16 vlan_id; 999 __le16 rsvd[3]; 1000} __packed; 1001 1002struct qlcnic_ipaddr { 1003 __be32 ipv4; 1004 __be32 ipv6[4]; 1005}; 1006 1007#define QLCNIC_MSI_ENABLED 0x02 1008#define QLCNIC_MSIX_ENABLED 0x04 1009#define QLCNIC_LRO_ENABLED 0x01 1010#define QLCNIC_LRO_DISABLED 0x00 1011#define QLCNIC_BRIDGE_ENABLED 0X10 1012#define QLCNIC_DIAG_ENABLED 0x20 1013#define QLCNIC_ESWITCH_ENABLED 0x40 1014#define QLCNIC_ADAPTER_INITIALIZED 0x80 1015#define QLCNIC_TAGGING_ENABLED 0x100 1016#define QLCNIC_MACSPOOF 0x200 1017#define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 1018#define QLCNIC_PROMISC_DISABLED 0x800 1019#define QLCNIC_NEED_FLR 0x1000 1020#define QLCNIC_FW_RESET_OWNER 0x2000 1021#define QLCNIC_FW_HANG 0x4000 1022#define QLCNIC_FW_LRO_MSS_CAP 0x8000 1023#define QLCNIC_TX_INTR_SHARED 0x10000 1024#define QLCNIC_APP_CHANGED_FLAGS 0x20000 1025#define QLCNIC_HAS_PHYS_PORT_ID 0x40000 1026#define QLCNIC_TSS_RSS 0x80000 1027 1028#ifdef CONFIG_QLCNIC_VXLAN 1029#define QLCNIC_ADD_VXLAN_PORT 0x100000 1030#define QLCNIC_DEL_VXLAN_PORT 0x200000 1031#endif 1032 1033#define QLCNIC_VLAN_FILTERING 0x800000 1034 1035#define QLCNIC_IS_MSI_FAMILY(adapter) \ 1036 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 1037#define QLCNIC_IS_TSO_CAPABLE(adapter) \ 1038 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) 1039 1040#define QLCNIC_BEACON_EANBLE 0xC 1041#define QLCNIC_BEACON_DISABLE 0xD 1042 1043#define QLCNIC_BEACON_ON 2 1044#define QLCNIC_BEACON_OFF 0 1045 1046#define QLCNIC_MSIX_TBL_SPACE 8192 1047#define QLCNIC_PCI_REG_MSIX_TBL 0x44 1048#define QLCNIC_MSIX_TBL_PGSIZE 4096 1049 1050#define QLCNIC_ADAPTER_UP_MAGIC 777 1051 1052#define __QLCNIC_FW_ATTACHED 0 1053#define __QLCNIC_DEV_UP 1 1054#define __QLCNIC_RESETTING 2 1055#define __QLCNIC_START_FW 4 1056#define __QLCNIC_AER 5 1057#define __QLCNIC_DIAG_RES_ALLOC 6 1058#define __QLCNIC_LED_ENABLE 7 1059#define __QLCNIC_ELB_INPROGRESS 8 1060#define __QLCNIC_MULTI_TX_UNIQUE 9 1061#define __QLCNIC_SRIOV_ENABLE 10 1062#define __QLCNIC_SRIOV_CAPABLE 11 1063#define __QLCNIC_MBX_POLL_ENABLE 12 1064#define __QLCNIC_DIAG_MODE 13 1065#define __QLCNIC_MAINTENANCE_MODE 16 1066 1067#define QLCNIC_INTERRUPT_TEST 1 1068#define QLCNIC_LOOPBACK_TEST 2 1069#define QLCNIC_LED_TEST 3 1070 1071#define QLCNIC_FILTER_AGE 80 1072#define QLCNIC_READD_AGE 20 1073#define QLCNIC_LB_MAX_FILTERS 64 1074#define QLCNIC_LB_BUCKET_SIZE 32 1075#define QLCNIC_ILB_MAX_RCV_LOOP 10 1076 1077struct qlcnic_filter { 1078 struct hlist_node fnode; 1079 u8 faddr[ETH_ALEN]; 1080 u16 vlan_id; 1081 unsigned long ftime; 1082}; 1083 1084struct qlcnic_filter_hash { 1085 struct hlist_head *fhead; 1086 u8 fnum; 1087 u16 fmax; 1088 u16 fbucket_size; 1089}; 1090 1091/* Mailbox specific data structures */ 1092struct qlcnic_mailbox { 1093 struct workqueue_struct *work_q; 1094 struct qlcnic_adapter *adapter; 1095 struct qlcnic_mbx_ops *ops; 1096 struct work_struct work; 1097 struct completion completion; 1098 struct list_head cmd_q; 1099 unsigned long status; 1100 spinlock_t queue_lock; /* Mailbox queue lock */ 1101 spinlock_t aen_lock; /* Mailbox response/AEN lock */ 1102 atomic_t rsp_status; 1103 u32 num_cmds; 1104}; 1105 1106struct qlcnic_adapter { 1107 struct qlcnic_hardware_context *ahw; 1108 struct qlcnic_recv_context *recv_ctx; 1109 struct qlcnic_host_tx_ring *tx_ring; 1110 struct net_device *netdev; 1111 struct pci_dev *pdev; 1112 1113 unsigned long state; 1114 u32 flags; 1115 1116 u16 num_txd; 1117 u16 num_rxd; 1118 u16 num_jumbo_rxd; 1119 u16 max_rxd; 1120 u16 max_jumbo_rxd; 1121 1122 u8 max_rds_rings; 1123 1124 u8 max_sds_rings; /* max sds rings supported by adapter */ 1125 u8 max_tx_rings; /* max tx rings supported by adapter */ 1126 1127 u8 drv_tx_rings; /* max tx rings supported by driver */ 1128 u8 drv_sds_rings; /* max sds rings supported by driver */ 1129 1130 u8 drv_tss_rings; /* tss ring input */ 1131 u8 drv_rss_rings; /* rss ring input */ 1132 1133 u8 rx_csum; 1134 u8 portnum; 1135 1136 u8 fw_wait_cnt; 1137 u8 fw_fail_cnt; 1138 u8 tx_timeo_cnt; 1139 u8 need_fw_reset; 1140 u8 reset_ctx_cnt; 1141 1142 u16 is_up; 1143 u16 rx_pvid; 1144 u16 tx_pvid; 1145 1146 u32 irq; 1147 u32 heartbeat; 1148 1149 u8 dev_state; 1150 u8 reset_ack_timeo; 1151 u8 dev_init_timeo; 1152 1153 u8 mac_addr[ETH_ALEN]; 1154 1155 u64 dev_rst_time; 1156 bool drv_mac_learn; 1157 bool fdb_mac_learn; 1158 bool rx_mac_learn; 1159 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1160 u8 flash_mfg_id; 1161 struct qlcnic_npar_info *npars; 1162 struct qlcnic_eswitch *eswitch; 1163 struct qlcnic_nic_template *nic_ops; 1164 1165 struct qlcnic_adapter_stats stats; 1166 struct list_head mac_list; 1167 1168 void __iomem *tgt_mask_reg; 1169 void __iomem *tgt_status_reg; 1170 void __iomem *crb_int_state_reg; 1171 void __iomem *isr_int_vec; 1172 1173 struct msix_entry *msix_entries; 1174 struct workqueue_struct *qlcnic_wq; 1175 struct delayed_work fw_work; 1176 struct delayed_work idc_aen_work; 1177 struct delayed_work mbx_poll_work; 1178 struct qlcnic_dcb *dcb; 1179 1180 struct qlcnic_filter_hash fhash; 1181 struct qlcnic_filter_hash rx_fhash; 1182 struct list_head vf_mc_list; 1183 1184 spinlock_t mac_learn_lock; 1185 /* spinlock for catching rcv filters for eswitch traffic */ 1186 spinlock_t rx_mac_learn_lock; 1187 u32 file_prd_off; /*File fw product offset*/ 1188 u32 fw_version; 1189 u32 offload_flags; 1190 const struct firmware *fw; 1191}; 1192 1193struct qlcnic_info_le { 1194 __le16 pci_func; 1195 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1196 __le16 phys_port; 1197 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1198 1199 __le32 capabilities; 1200 u8 max_mac_filters; 1201 u8 reserved1; 1202 __le16 max_mtu; 1203 1204 __le16 max_tx_ques; 1205 __le16 max_rx_ques; 1206 __le16 min_tx_bw; 1207 __le16 max_tx_bw; 1208 __le32 op_type; 1209 __le16 max_bw_reg_offset; 1210 __le16 max_linkspeed_reg_offset; 1211 __le32 capability1; 1212 __le32 capability2; 1213 __le32 capability3; 1214 __le16 max_tx_mac_filters; 1215 __le16 max_rx_mcast_mac_filters; 1216 __le16 max_rx_ucast_mac_filters; 1217 __le16 max_rx_ip_addr; 1218 __le16 max_rx_lro_flow; 1219 __le16 max_rx_status_rings; 1220 __le16 max_rx_buf_rings; 1221 __le16 max_tx_vlan_keys; 1222 u8 total_pf; 1223 u8 total_rss_engines; 1224 __le16 max_vports; 1225 __le16 linkstate_reg_offset; 1226 __le16 bit_offsets; 1227 __le16 max_local_ipv6_addrs; 1228 __le16 max_remote_ipv6_addrs; 1229 u8 reserved2[56]; 1230} __packed; 1231 1232struct qlcnic_info { 1233 u16 pci_func; 1234 u16 op_mode; 1235 u16 phys_port; 1236 u16 switch_mode; 1237 u32 capabilities; 1238 u8 max_mac_filters; 1239 u16 max_mtu; 1240 u16 max_tx_ques; 1241 u16 max_rx_ques; 1242 u16 min_tx_bw; 1243 u16 max_tx_bw; 1244 u32 op_type; 1245 u16 max_bw_reg_offset; 1246 u16 max_linkspeed_reg_offset; 1247 u32 capability1; 1248 u32 capability2; 1249 u32 capability3; 1250 u16 max_tx_mac_filters; 1251 u16 max_rx_mcast_mac_filters; 1252 u16 max_rx_ucast_mac_filters; 1253 u16 max_rx_ip_addr; 1254 u16 max_rx_lro_flow; 1255 u16 max_rx_status_rings; 1256 u16 max_rx_buf_rings; 1257 u16 max_tx_vlan_keys; 1258 u8 total_pf; 1259 u8 total_rss_engines; 1260 u16 max_vports; 1261 u16 linkstate_reg_offset; 1262 u16 bit_offsets; 1263 u16 max_local_ipv6_addrs; 1264 u16 max_remote_ipv6_addrs; 1265}; 1266 1267struct qlcnic_pci_info_le { 1268 __le16 id; /* pci function id */ 1269 __le16 active; /* 1 = Enabled */ 1270 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1271 __le16 default_port; /* default port number */ 1272 1273 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1274 __le16 tx_max_bw; 1275 __le16 reserved1[2]; 1276 1277 u8 mac[ETH_ALEN]; 1278 __le16 func_count; 1279 u8 reserved2[104]; 1280 1281} __packed; 1282 1283struct qlcnic_pci_info { 1284 u16 id; 1285 u16 active; 1286 u16 type; 1287 u16 default_port; 1288 u16 tx_min_bw; 1289 u16 tx_max_bw; 1290 u8 mac[ETH_ALEN]; 1291 u16 func_count; 1292}; 1293 1294struct qlcnic_npar_info { 1295 bool eswitch_status; 1296 u16 pvid; 1297 u16 min_bw; 1298 u16 max_bw; 1299 u8 phy_port; 1300 u8 type; 1301 u8 active; 1302 u8 enable_pm; 1303 u8 dest_npar; 1304 u8 discard_tagged; 1305 u8 mac_override; 1306 u8 mac_anti_spoof; 1307 u8 promisc_mode; 1308 u8 offload_flags; 1309 u8 pci_func; 1310 u8 mac[ETH_ALEN]; 1311}; 1312 1313struct qlcnic_eswitch { 1314 u8 port; 1315 u8 active_vports; 1316 u8 active_vlans; 1317 u8 active_ucast_filters; 1318 u8 max_ucast_filters; 1319 u8 max_active_vlans; 1320 1321 u32 flags; 1322#define QLCNIC_SWITCH_ENABLE BIT_1 1323#define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1324#define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1325#define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1326}; 1327 1328 1329/* Return codes for Error handling */ 1330#define QL_STATUS_INVALID_PARAM -1 1331 1332#define MAX_BW 100 /* % of link speed */ 1333#define MIN_BW 1 /* % of link speed */ 1334#define MAX_VLAN_ID 4095 1335#define MIN_VLAN_ID 2 1336#define DEFAULT_MAC_LEARN 1 1337 1338#define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1339#define IS_VALID_BW(bw) (bw <= MAX_BW) 1340 1341struct qlcnic_pci_func_cfg { 1342 u16 func_type; 1343 u16 min_bw; 1344 u16 max_bw; 1345 u16 port_num; 1346 u8 pci_func; 1347 u8 func_state; 1348 u8 def_mac_addr[ETH_ALEN]; 1349}; 1350 1351struct qlcnic_npar_func_cfg { 1352 u32 fw_capab; 1353 u16 port_num; 1354 u16 min_bw; 1355 u16 max_bw; 1356 u16 max_tx_queues; 1357 u16 max_rx_queues; 1358 u8 pci_func; 1359 u8 op_mode; 1360}; 1361 1362struct qlcnic_pm_func_cfg { 1363 u8 pci_func; 1364 u8 action; 1365 u8 dest_npar; 1366 u8 reserved[5]; 1367}; 1368 1369struct qlcnic_esw_func_cfg { 1370 u16 vlan_id; 1371 u8 op_mode; 1372 u8 op_type; 1373 u8 pci_func; 1374 u8 host_vlan_tag; 1375 u8 promisc_mode; 1376 u8 discard_tagged; 1377 u8 mac_override; 1378 u8 mac_anti_spoof; 1379 u8 offload_flags; 1380 u8 reserved[5]; 1381}; 1382 1383#define QLCNIC_STATS_VERSION 1 1384#define QLCNIC_STATS_PORT 1 1385#define QLCNIC_STATS_ESWITCH 2 1386#define QLCNIC_QUERY_RX_COUNTER 0 1387#define QLCNIC_QUERY_TX_COUNTER 1 1388#define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL 1389#define QLCNIC_FILL_STATS(VAL1) \ 1390 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) 1391#define QLCNIC_MAC_STATS 1 1392#define QLCNIC_ESW_STATS 2 1393 1394#define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1395do { \ 1396 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ 1397 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1398 (VAL1) = (VAL2); \ 1399 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ 1400 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1401 (VAL1) += (VAL2); \ 1402} while (0) 1403 1404struct qlcnic_mac_statistics_le { 1405 __le64 mac_tx_frames; 1406 __le64 mac_tx_bytes; 1407 __le64 mac_tx_mcast_pkts; 1408 __le64 mac_tx_bcast_pkts; 1409 __le64 mac_tx_pause_cnt; 1410 __le64 mac_tx_ctrl_pkt; 1411 __le64 mac_tx_lt_64b_pkts; 1412 __le64 mac_tx_lt_127b_pkts; 1413 __le64 mac_tx_lt_255b_pkts; 1414 __le64 mac_tx_lt_511b_pkts; 1415 __le64 mac_tx_lt_1023b_pkts; 1416 __le64 mac_tx_lt_1518b_pkts; 1417 __le64 mac_tx_gt_1518b_pkts; 1418 __le64 rsvd1[3]; 1419 1420 __le64 mac_rx_frames; 1421 __le64 mac_rx_bytes; 1422 __le64 mac_rx_mcast_pkts; 1423 __le64 mac_rx_bcast_pkts; 1424 __le64 mac_rx_pause_cnt; 1425 __le64 mac_rx_ctrl_pkt; 1426 __le64 mac_rx_lt_64b_pkts; 1427 __le64 mac_rx_lt_127b_pkts; 1428 __le64 mac_rx_lt_255b_pkts; 1429 __le64 mac_rx_lt_511b_pkts; 1430 __le64 mac_rx_lt_1023b_pkts; 1431 __le64 mac_rx_lt_1518b_pkts; 1432 __le64 mac_rx_gt_1518b_pkts; 1433 __le64 rsvd2[3]; 1434 1435 __le64 mac_rx_length_error; 1436 __le64 mac_rx_length_small; 1437 __le64 mac_rx_length_large; 1438 __le64 mac_rx_jabber; 1439 __le64 mac_rx_dropped; 1440 __le64 mac_rx_crc_error; 1441 __le64 mac_align_error; 1442} __packed; 1443 1444struct qlcnic_mac_statistics { 1445 u64 mac_tx_frames; 1446 u64 mac_tx_bytes; 1447 u64 mac_tx_mcast_pkts; 1448 u64 mac_tx_bcast_pkts; 1449 u64 mac_tx_pause_cnt; 1450 u64 mac_tx_ctrl_pkt; 1451 u64 mac_tx_lt_64b_pkts; 1452 u64 mac_tx_lt_127b_pkts; 1453 u64 mac_tx_lt_255b_pkts; 1454 u64 mac_tx_lt_511b_pkts; 1455 u64 mac_tx_lt_1023b_pkts; 1456 u64 mac_tx_lt_1518b_pkts; 1457 u64 mac_tx_gt_1518b_pkts; 1458 u64 rsvd1[3]; 1459 u64 mac_rx_frames; 1460 u64 mac_rx_bytes; 1461 u64 mac_rx_mcast_pkts; 1462 u64 mac_rx_bcast_pkts; 1463 u64 mac_rx_pause_cnt; 1464 u64 mac_rx_ctrl_pkt; 1465 u64 mac_rx_lt_64b_pkts; 1466 u64 mac_rx_lt_127b_pkts; 1467 u64 mac_rx_lt_255b_pkts; 1468 u64 mac_rx_lt_511b_pkts; 1469 u64 mac_rx_lt_1023b_pkts; 1470 u64 mac_rx_lt_1518b_pkts; 1471 u64 mac_rx_gt_1518b_pkts; 1472 u64 rsvd2[3]; 1473 u64 mac_rx_length_error; 1474 u64 mac_rx_length_small; 1475 u64 mac_rx_length_large; 1476 u64 mac_rx_jabber; 1477 u64 mac_rx_dropped; 1478 u64 mac_rx_crc_error; 1479 u64 mac_align_error; 1480}; 1481 1482struct qlcnic_esw_stats_le { 1483 __le16 context_id; 1484 __le16 version; 1485 __le16 size; 1486 __le16 unused; 1487 __le64 unicast_frames; 1488 __le64 multicast_frames; 1489 __le64 broadcast_frames; 1490 __le64 dropped_frames; 1491 __le64 errors; 1492 __le64 local_frames; 1493 __le64 numbytes; 1494 __le64 rsvd[3]; 1495} __packed; 1496 1497struct __qlcnic_esw_statistics { 1498 u16 context_id; 1499 u16 version; 1500 u16 size; 1501 u16 unused; 1502 u64 unicast_frames; 1503 u64 multicast_frames; 1504 u64 broadcast_frames; 1505 u64 dropped_frames; 1506 u64 errors; 1507 u64 local_frames; 1508 u64 numbytes; 1509 u64 rsvd[3]; 1510}; 1511 1512struct qlcnic_esw_statistics { 1513 struct __qlcnic_esw_statistics rx; 1514 struct __qlcnic_esw_statistics tx; 1515}; 1516 1517#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1518#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1519#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1520#define QLCNIC_FORCE_FW_RESET 0xdeaddead 1521#define QLCNIC_SET_QUIESCENT 0xadd00010 1522#define QLCNIC_RESET_QUIESCENT 0xadd00020 1523 1524struct _cdrp_cmd { 1525 u32 num; 1526 u32 *arg; 1527}; 1528 1529struct qlcnic_cmd_args { 1530 struct completion completion; 1531 struct list_head list; 1532 struct _cdrp_cmd req; 1533 struct _cdrp_cmd rsp; 1534 atomic_t rsp_status; 1535 int pay_size; 1536 u32 rsp_opcode; 1537 u32 total_cmds; 1538 u32 op_type; 1539 u32 type; 1540 u32 cmd_op; 1541 u32 *hdr; /* Back channel message header */ 1542 u32 *pay; /* Back channel message payload */ 1543 u8 func_num; 1544}; 1545 1546int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1547int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1548int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1549int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1550 1551#define ADDR_IN_RANGE(addr, low, high) \ 1552 (((addr) < (high)) && ((addr) >= (low))) 1553 1554#define QLCRD32(adapter, off, err) \ 1555 (adapter->ahw->hw_ops->read_reg)(adapter, off, err) 1556 1557#define QLCWR32(adapter, off, val) \ 1558 adapter->ahw->hw_ops->write_reg(adapter, off, val) 1559 1560int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1561void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1562 1563#define qlcnic_rom_lock(a) \ 1564 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1565#define qlcnic_rom_unlock(a) \ 1566 qlcnic_pcie_sem_unlock((a), 2) 1567#define qlcnic_phy_lock(a) \ 1568 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1569#define qlcnic_phy_unlock(a) \ 1570 qlcnic_pcie_sem_unlock((a), 3) 1571#define qlcnic_sw_lock(a) \ 1572 qlcnic_pcie_sem_lock((a), 6, 0) 1573#define qlcnic_sw_unlock(a) \ 1574 qlcnic_pcie_sem_unlock((a), 6) 1575#define crb_win_lock(a) \ 1576 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1577#define crb_win_unlock(a) \ 1578 qlcnic_pcie_sem_unlock((a), 7) 1579 1580#define __QLCNIC_MAX_LED_RATE 0xf 1581#define __QLCNIC_MAX_LED_STATE 0x2 1582 1583#define MAX_CTL_CHECK 1000 1584 1585void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1586void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1587int qlcnic_dump_fw(struct qlcnic_adapter *); 1588int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); 1589bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); 1590 1591/* Functions from qlcnic_init.c */ 1592void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); 1593int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1594int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1595void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1596void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1597int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1598int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1599int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1600 1601int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1602int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1603 u8 *bytes, size_t size); 1604int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1605void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1606 1607void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); 1608 1609int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1610void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1611 1612int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1613void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1614 1615void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1616void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1617void qlcnic_release_tx_buffers(struct qlcnic_adapter *, 1618 struct qlcnic_host_tx_ring *); 1619 1620int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1621void qlcnic_watchdog_task(struct work_struct *work); 1622void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1623 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); 1624void qlcnic_set_multi(struct net_device *netdev); 1625void qlcnic_flush_mcast_mac(struct qlcnic_adapter *); 1626int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16, 1627 enum qlcnic_mac_type); 1628int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); 1629void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); 1630int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); 1631 1632int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1633int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); 1634int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1635netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1636 netdev_features_t features); 1637int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1638int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1639void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); 1640 1641/* Functions from qlcnic_ethtool.c */ 1642int qlcnic_check_loopback_buff(unsigned char *, u8 []); 1643int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); 1644 1645/* Functions from qlcnic_main.c */ 1646int qlcnic_reset_context(struct qlcnic_adapter *); 1647void qlcnic_diag_free_res(struct net_device *netdev, int); 1648int qlcnic_diag_alloc_res(struct net_device *netdev, int); 1649netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *); 1650void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8); 1651void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8); 1652int qlcnic_setup_rings(struct qlcnic_adapter *); 1653int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int); 1654void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1655int qlcnic_enable_msix(struct qlcnic_adapter *, u32); 1656void qlcnic_set_drv_version(struct qlcnic_adapter *); 1657 1658/* eSwitch management functions */ 1659int qlcnic_config_switch_port(struct qlcnic_adapter *, 1660 struct qlcnic_esw_func_cfg *); 1661 1662int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1663 struct qlcnic_esw_func_cfg *); 1664int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1665int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1666 struct __qlcnic_esw_statistics *); 1667int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1668 struct __qlcnic_esw_statistics *); 1669int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1670int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1671 1672void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); 1673 1674int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); 1675void qlcnic_free_sds_rings(struct qlcnic_recv_context *); 1676void qlcnic_advert_link_change(struct qlcnic_adapter *, int); 1677void qlcnic_free_tx_rings(struct qlcnic_adapter *); 1678int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); 1679void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1680 1681void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); 1682void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); 1683void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); 1684void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); 1685 1686int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); 1687int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); 1688void qlcnic_set_vlan_config(struct qlcnic_adapter *, 1689 struct qlcnic_esw_func_cfg *); 1690void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, 1691 struct qlcnic_esw_func_cfg *); 1692int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *); 1693void qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1694int qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1695void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1696void qlcnic_detach(struct qlcnic_adapter *); 1697void qlcnic_teardown_intr(struct qlcnic_adapter *); 1698int qlcnic_attach(struct qlcnic_adapter *); 1699int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1700void qlcnic_restore_indev_addr(struct net_device *, unsigned long); 1701 1702int qlcnic_check_temp(struct qlcnic_adapter *); 1703int qlcnic_init_pci_info(struct qlcnic_adapter *); 1704int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); 1705int qlcnic_reset_npar_config(struct qlcnic_adapter *); 1706int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); 1707int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); 1708int qlcnic_read_mac_addr(struct qlcnic_adapter *); 1709int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); 1710void qlcnic_set_netdev_features(struct qlcnic_adapter *, 1711 struct qlcnic_esw_func_cfg *); 1712void qlcnic_sriov_vf_set_multi(struct net_device *); 1713int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8); 1714int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *, 1715 u16 *); 1716 1717/* 1718 * QLOGIC Board information 1719 */ 1720 1721#define QLCNIC_MAX_BOARD_NAME_LEN 100 1722struct qlcnic_board_info { 1723 unsigned short vendor; 1724 unsigned short device; 1725 unsigned short sub_vendor; 1726 unsigned short sub_device; 1727 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1728}; 1729 1730static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1731{ 1732 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1733 return tx_ring->sw_consumer - tx_ring->producer; 1734 else 1735 return tx_ring->sw_consumer + tx_ring->num_desc - 1736 tx_ring->producer; 1737} 1738 1739struct qlcnic_nic_template { 1740 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1741 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1742 int (*start_firmware) (struct qlcnic_adapter *); 1743 int (*init_driver) (struct qlcnic_adapter *); 1744 void (*request_reset) (struct qlcnic_adapter *, u32); 1745 void (*cancel_idc_work) (struct qlcnic_adapter *); 1746 int (*napi_add)(struct qlcnic_adapter *, struct net_device *); 1747 void (*napi_del)(struct qlcnic_adapter *); 1748 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); 1749 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); 1750 int (*shutdown)(struct pci_dev *); 1751 int (*resume)(struct qlcnic_adapter *); 1752}; 1753 1754struct qlcnic_mbx_ops { 1755 int (*enqueue_cmd) (struct qlcnic_adapter *, 1756 struct qlcnic_cmd_args *, unsigned long *); 1757 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1758 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1759 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1760 void (*nofity_fw) (struct qlcnic_adapter *, u8); 1761}; 1762 1763int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); 1764void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); 1765void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); 1766void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); 1767void qlcnic_update_stats(struct qlcnic_adapter *); 1768 1769/* Adapter hardware abstraction */ 1770struct qlcnic_hardware_ops { 1771 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1772 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1773 int (*read_reg) (struct qlcnic_adapter *, ulong, int *); 1774 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); 1775 void (*get_ocm_win) (struct qlcnic_hardware_context *); 1776 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); 1777 int (*setup_intr) (struct qlcnic_adapter *); 1778 int (*alloc_mbx_args)(struct qlcnic_cmd_args *, 1779 struct qlcnic_adapter *, u32); 1780 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1781 void (*get_func_no) (struct qlcnic_adapter *); 1782 int (*api_lock) (struct qlcnic_adapter *); 1783 void (*api_unlock) (struct qlcnic_adapter *); 1784 void (*add_sysfs) (struct qlcnic_adapter *); 1785 void (*remove_sysfs) (struct qlcnic_adapter *); 1786 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); 1787 int (*create_rx_ctx) (struct qlcnic_adapter *); 1788 int (*create_tx_ctx) (struct qlcnic_adapter *, 1789 struct qlcnic_host_tx_ring *, int); 1790 void (*del_rx_ctx) (struct qlcnic_adapter *); 1791 void (*del_tx_ctx) (struct qlcnic_adapter *, 1792 struct qlcnic_host_tx_ring *); 1793 int (*setup_link_event) (struct qlcnic_adapter *, int); 1794 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); 1795 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); 1796 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); 1797 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); 1798 void (*napi_enable) (struct qlcnic_adapter *); 1799 void (*napi_disable) (struct qlcnic_adapter *); 1800 int (*config_intr_coal) (struct qlcnic_adapter *, 1801 struct ethtool_coalesce *); 1802 int (*config_rss) (struct qlcnic_adapter *, int); 1803 int (*config_hw_lro) (struct qlcnic_adapter *, int); 1804 int (*config_loopback) (struct qlcnic_adapter *, u8); 1805 int (*clear_loopback) (struct qlcnic_adapter *, u8); 1806 int (*config_promisc_mode) (struct qlcnic_adapter *, u32); 1807 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); 1808 int (*get_board_info) (struct qlcnic_adapter *); 1809 void (*set_mac_filter_count) (struct qlcnic_adapter *); 1810 void (*free_mac_list) (struct qlcnic_adapter *); 1811 int (*read_phys_port_id) (struct qlcnic_adapter *); 1812 pci_ers_result_t (*io_error_detected) (struct pci_dev *, 1813 pci_channel_state_t); 1814 pci_ers_result_t (*io_slot_reset) (struct pci_dev *); 1815 void (*io_resume) (struct pci_dev *); 1816 void (*get_beacon_state)(struct qlcnic_adapter *); 1817 void (*enable_sds_intr) (struct qlcnic_adapter *, 1818 struct qlcnic_host_sds_ring *); 1819 void (*disable_sds_intr) (struct qlcnic_adapter *, 1820 struct qlcnic_host_sds_ring *); 1821 void (*enable_tx_intr) (struct qlcnic_adapter *, 1822 struct qlcnic_host_tx_ring *); 1823 void (*disable_tx_intr) (struct qlcnic_adapter *, 1824 struct qlcnic_host_tx_ring *); 1825 u32 (*get_saved_state)(void *, u32); 1826 void (*set_saved_state)(void *, u32, u32); 1827 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *); 1828 u32 (*get_cap_size)(void *, int); 1829 void (*set_sys_info)(void *, int, u32); 1830 void (*store_cap_mask)(void *, u32); 1831}; 1832 1833extern struct qlcnic_nic_template qlcnic_vf_ops; 1834 1835static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter) 1836{ 1837 return adapter->ahw->extra_capability[0] & 1838 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD; 1839} 1840 1841static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter) 1842{ 1843 return adapter->ahw->extra_capability[0] & 1844 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD; 1845} 1846 1847static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) 1848{ 1849 return adapter->nic_ops->start_firmware(adapter); 1850} 1851 1852static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, 1853 loff_t offset, size_t size) 1854{ 1855 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); 1856} 1857 1858static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, 1859 loff_t offset, size_t size) 1860{ 1861 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); 1862} 1863 1864static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, 1865 ulong off, u32 data) 1866{ 1867 return adapter->ahw->hw_ops->write_reg(adapter, off, data); 1868} 1869 1870static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, 1871 u8 *mac, u8 function) 1872{ 1873 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); 1874} 1875 1876static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter) 1877{ 1878 return adapter->ahw->hw_ops->setup_intr(adapter); 1879} 1880 1881static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 1882 struct qlcnic_adapter *adapter, u32 arg) 1883{ 1884 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); 1885} 1886 1887static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, 1888 struct qlcnic_cmd_args *cmd) 1889{ 1890 if (adapter->ahw->hw_ops->mbx_cmd) 1891 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); 1892 1893 return -EIO; 1894} 1895 1896static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) 1897{ 1898 adapter->ahw->hw_ops->get_func_no(adapter); 1899} 1900 1901static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) 1902{ 1903 return adapter->ahw->hw_ops->api_lock(adapter); 1904} 1905 1906static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) 1907{ 1908 adapter->ahw->hw_ops->api_unlock(adapter); 1909} 1910 1911static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) 1912{ 1913 if (adapter->ahw->hw_ops->add_sysfs) 1914 adapter->ahw->hw_ops->add_sysfs(adapter); 1915} 1916 1917static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) 1918{ 1919 if (adapter->ahw->hw_ops->remove_sysfs) 1920 adapter->ahw->hw_ops->remove_sysfs(adapter); 1921} 1922 1923static inline void 1924qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) 1925{ 1926 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); 1927} 1928 1929static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) 1930{ 1931 return adapter->ahw->hw_ops->create_rx_ctx(adapter); 1932} 1933 1934static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, 1935 struct qlcnic_host_tx_ring *ptr, 1936 int ring) 1937{ 1938 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); 1939} 1940 1941static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) 1942{ 1943 return adapter->ahw->hw_ops->del_rx_ctx(adapter); 1944} 1945 1946static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, 1947 struct qlcnic_host_tx_ring *ptr) 1948{ 1949 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); 1950} 1951 1952static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, 1953 int enable) 1954{ 1955 return adapter->ahw->hw_ops->setup_link_event(adapter, enable); 1956} 1957 1958static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, 1959 struct qlcnic_info *info, u8 id) 1960{ 1961 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); 1962} 1963 1964static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, 1965 struct qlcnic_pci_info *info) 1966{ 1967 return adapter->ahw->hw_ops->get_pci_info(adapter, info); 1968} 1969 1970static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, 1971 struct qlcnic_info *info) 1972{ 1973 return adapter->ahw->hw_ops->set_nic_info(adapter, info); 1974} 1975 1976static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, 1977 u8 *addr, u16 id, u8 cmd) 1978{ 1979 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); 1980} 1981 1982static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, 1983 struct net_device *netdev) 1984{ 1985 return adapter->nic_ops->napi_add(adapter, netdev); 1986} 1987 1988static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) 1989{ 1990 adapter->nic_ops->napi_del(adapter); 1991} 1992 1993static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) 1994{ 1995 adapter->ahw->hw_ops->napi_enable(adapter); 1996} 1997 1998static inline int __qlcnic_shutdown(struct pci_dev *pdev) 1999{ 2000 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 2001 2002 return adapter->nic_ops->shutdown(pdev); 2003} 2004 2005static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) 2006{ 2007 return adapter->nic_ops->resume(adapter); 2008} 2009 2010static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) 2011{ 2012 adapter->ahw->hw_ops->napi_disable(adapter); 2013} 2014 2015static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter, 2016 struct ethtool_coalesce *ethcoal) 2017{ 2018 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal); 2019} 2020 2021static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) 2022{ 2023 return adapter->ahw->hw_ops->config_rss(adapter, enable); 2024} 2025 2026static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, 2027 int enable) 2028{ 2029 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); 2030} 2031 2032static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 2033{ 2034 return adapter->ahw->hw_ops->config_loopback(adapter, mode); 2035} 2036 2037static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 2038{ 2039 return adapter->ahw->hw_ops->clear_loopback(adapter, mode); 2040} 2041 2042static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, 2043 u32 mode) 2044{ 2045 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); 2046} 2047 2048static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, 2049 u64 *addr, u16 id) 2050{ 2051 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); 2052} 2053 2054static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) 2055{ 2056 return adapter->ahw->hw_ops->get_board_info(adapter); 2057} 2058 2059static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) 2060{ 2061 return adapter->ahw->hw_ops->free_mac_list(adapter); 2062} 2063 2064static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) 2065{ 2066 if (adapter->ahw->hw_ops->set_mac_filter_count) 2067 adapter->ahw->hw_ops->set_mac_filter_count(adapter); 2068} 2069 2070static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter) 2071{ 2072 adapter->ahw->hw_ops->get_beacon_state(adapter); 2073} 2074 2075static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) 2076{ 2077 if (adapter->ahw->hw_ops->read_phys_port_id) 2078 adapter->ahw->hw_ops->read_phys_port_id(adapter); 2079} 2080 2081static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter, 2082 void *t_hdr, u32 index) 2083{ 2084 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index); 2085} 2086 2087static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter, 2088 void *t_hdr, u32 index, u32 value) 2089{ 2090 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value); 2091} 2092 2093static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter, 2094 struct qlcnic_fw_dump *fw_dump) 2095{ 2096 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump); 2097} 2098 2099static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter, 2100 void *tmpl_hdr, int index) 2101{ 2102 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index); 2103} 2104 2105static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter, 2106 void *tmpl_hdr, int idx, u32 value) 2107{ 2108 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value); 2109} 2110 2111static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter, 2112 void *tmpl_hdr, u32 mask) 2113{ 2114 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask); 2115} 2116 2117static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, 2118 u32 key) 2119{ 2120 if (adapter->nic_ops->request_reset) 2121 adapter->nic_ops->request_reset(adapter, key); 2122} 2123 2124static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) 2125{ 2126 if (adapter->nic_ops->cancel_idc_work) 2127 adapter->nic_ops->cancel_idc_work(adapter); 2128} 2129 2130static inline irqreturn_t 2131qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) 2132{ 2133 return adapter->nic_ops->clear_legacy_intr(adapter); 2134} 2135 2136static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, 2137 u32 rate) 2138{ 2139 return adapter->nic_ops->config_led(adapter, state, rate); 2140} 2141 2142static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, 2143 __be32 ip, int cmd) 2144{ 2145 adapter->nic_ops->config_ipaddr(adapter, ip, cmd); 2146} 2147 2148static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) 2149{ 2150 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2151} 2152 2153static inline void 2154qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter, 2155 struct qlcnic_host_tx_ring *tx_ring) 2156{ 2157 if (qlcnic_check_multi_tx(adapter) && 2158 !adapter->ahw->diag_test) 2159 writel(0x0, tx_ring->crb_intr_mask); 2160} 2161 2162static inline void 2163qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter, 2164 struct qlcnic_host_tx_ring *tx_ring) 2165{ 2166 if (qlcnic_check_multi_tx(adapter) && 2167 !adapter->ahw->diag_test) 2168 writel(1, tx_ring->crb_intr_mask); 2169} 2170 2171static inline void 2172qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter, 2173 struct qlcnic_host_tx_ring *tx_ring) 2174{ 2175 writel(0, tx_ring->crb_intr_mask); 2176} 2177 2178static inline void 2179qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter, 2180 struct qlcnic_host_tx_ring *tx_ring) 2181{ 2182 writel(1, tx_ring->crb_intr_mask); 2183} 2184 2185/* Enable MSI-x and INT-x interrupts */ 2186static inline void 2187qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter, 2188 struct qlcnic_host_sds_ring *sds_ring) 2189{ 2190 writel(0, sds_ring->crb_intr_mask); 2191} 2192 2193/* Disable MSI-x and INT-x interrupts */ 2194static inline void 2195qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter, 2196 struct qlcnic_host_sds_ring *sds_ring) 2197{ 2198 writel(1, sds_ring->crb_intr_mask); 2199} 2200 2201static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) 2202{ 2203 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2204 adapter->drv_tx_rings = QLCNIC_SINGLE_RING; 2205} 2206 2207/* When operating in a muti tx mode, driver needs to write 0x1 2208 * to src register, instead of 0x0 to disable receiving interrupt. 2209 */ 2210static inline void 2211qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter, 2212 struct qlcnic_host_sds_ring *sds_ring) 2213{ 2214 if (qlcnic_check_multi_tx(adapter) && 2215 !adapter->ahw->diag_test && 2216 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2217 writel(0x1, sds_ring->crb_intr_mask); 2218 else 2219 writel(0, sds_ring->crb_intr_mask); 2220} 2221 2222static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter, 2223 struct qlcnic_host_sds_ring *sds_ring) 2224{ 2225 if (adapter->ahw->hw_ops->enable_sds_intr) 2226 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring); 2227} 2228 2229static inline void 2230qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter, 2231 struct qlcnic_host_sds_ring *sds_ring) 2232{ 2233 if (adapter->ahw->hw_ops->disable_sds_intr) 2234 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring); 2235} 2236 2237static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter, 2238 struct qlcnic_host_tx_ring *tx_ring) 2239{ 2240 if (adapter->ahw->hw_ops->enable_tx_intr) 2241 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring); 2242} 2243 2244static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter, 2245 struct qlcnic_host_tx_ring *tx_ring) 2246{ 2247 if (adapter->ahw->hw_ops->disable_tx_intr) 2248 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring); 2249} 2250 2251/* When operating in a muti tx mode, driver needs to write 0x0 2252 * to src register, instead of 0x1 to enable receiving interrupts. 2253 */ 2254static inline void 2255qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter, 2256 struct qlcnic_host_sds_ring *sds_ring) 2257{ 2258 if (qlcnic_check_multi_tx(adapter) && 2259 !adapter->ahw->diag_test && 2260 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2261 writel(0, sds_ring->crb_intr_mask); 2262 else 2263 writel(0x1, sds_ring->crb_intr_mask); 2264 2265 if (!QLCNIC_IS_MSI_FAMILY(adapter)) 2266 writel(0xfbff, adapter->tgt_mask_reg); 2267} 2268 2269static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) 2270{ 2271 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2272} 2273 2274static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) 2275{ 2276 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2277} 2278 2279static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) 2280{ 2281 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2282} 2283 2284extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; 2285extern const struct ethtool_ops qlcnic_ethtool_ops; 2286extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 2287 2288#define QLCDB(adapter, lvl, _fmt, _args...) do { \ 2289 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ 2290 printk(KERN_INFO "%s: %s: " _fmt, \ 2291 dev_name(&adapter->pdev->dev), \ 2292 __func__, ##_args); \ 2293 } while (0) 2294 2295#define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 2296#define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 2297#define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830 2298#define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 2299#define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 2300#define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 2301 2302static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) 2303{ 2304 unsigned short device = adapter->pdev->device; 2305 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; 2306} 2307 2308static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) 2309{ 2310 unsigned short device = adapter->pdev->device; 2311 2312 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2313 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2314} 2315 2316static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) 2317{ 2318 unsigned short device = adapter->pdev->device; 2319 bool status; 2320 2321 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || 2322 (device == PCI_DEVICE_ID_QLOGIC_QLE8830) || 2323 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2324 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || 2325 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; 2326 2327 return status; 2328} 2329 2330static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) 2331{ 2332 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; 2333} 2334 2335static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) 2336{ 2337 unsigned short device = adapter->pdev->device; 2338 bool status; 2339 2340 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || 2341 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2342 2343 return status; 2344} 2345 2346static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter) 2347{ 2348 unsigned short device = adapter->pdev->device; 2349 2350 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; 2351} 2352 2353static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter) 2354{ 2355 unsigned short device = adapter->pdev->device; 2356 2357 return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false; 2358} 2359 2360static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter) 2361{ 2362 bool status; 2363 2364 status = (qlcnic_sriov_pf_check(adapter) || 2365 qlcnic_sriov_vf_check(adapter)) ? true : false; 2366 2367 return status; 2368} 2369 2370static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter) 2371{ 2372 if (qlcnic_84xx_check(adapter)) 2373 return QLC_84XX_VNIC_COUNT; 2374 else 2375 return QLC_DEFAULT_VNIC_COUNT; 2376} 2377 2378static inline void qlcnic_swap32_buffer(u32 *buffer, int count) 2379{ 2380#if defined(__BIG_ENDIAN) 2381 u32 *tmp = buffer; 2382 int i; 2383 2384 for (i = 0; i < count; i++) { 2385 *tmp = swab32(*tmp); 2386 tmp++; 2387 } 2388#endif 2389} 2390 2391#ifdef CONFIG_QLCNIC_HWMON 2392void qlcnic_register_hwmon_dev(struct qlcnic_adapter *); 2393void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *); 2394#else 2395static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter) 2396{ 2397 return; 2398} 2399static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter) 2400{ 2401 return; 2402} 2403#endif 2404#endif /* __QLCNIC_H_ */ 2405