1/* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8#include "qlcnic.h" 9#include "qlcnic_sriov.h" 10#include <linux/if_vlan.h> 11#include <linux/ipv6.h> 12#include <linux/ethtool.h> 13#include <linux/interrupt.h> 14#include <linux/aer.h> 15 16static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *); 17static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); 18static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, 19 struct qlcnic_cmd_args *); 20static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); 21static irqreturn_t qlcnic_83xx_handle_aen(int, void *); 22static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *, 23 pci_channel_state_t); 24static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); 25static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *); 26static void qlcnic_83xx_io_resume(struct pci_dev *); 27static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); 28static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *); 29static int qlcnic_83xx_resume(struct qlcnic_adapter *); 30static int qlcnic_83xx_shutdown(struct pci_dev *); 31static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *); 32 33#define RSS_HASHTYPE_IP_TCP 0x3 34#define QLC_83XX_FW_MBX_CMD 0 35#define QLC_SKIP_INACTIVE_PCI_REGS 7 36#define QLC_MAX_LEGACY_FUNC_SUPP 8 37 38/* 83xx Module type */ 39#define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */ 40#define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */ 41#define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */ 42#define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP 0x4 /* 10GE passive 43 * copper(compliant) 44 */ 45#define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP 0x5 /* 10GE active limiting 46 * copper(compliant) 47 */ 48#define QLC_83XX_MODULE_DA_10GE_LEGACY_CP 0x6 /* 10GE passive copper 49 * (legacy, best effort) 50 */ 51#define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */ 52#define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */ 53#define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */ 54#define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/ 55#define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP 0xb /* 1GE passive copper 56 * (legacy, best effort) 57 */ 58#define QLC_83XX_MODULE_UNKNOWN 0xf /* Unknown module type */ 59 60/* Port types */ 61#define QLC_83XX_10_CAPABLE BIT_8 62#define QLC_83XX_100_CAPABLE BIT_9 63#define QLC_83XX_1G_CAPABLE BIT_10 64#define QLC_83XX_10G_CAPABLE BIT_11 65#define QLC_83XX_AUTONEG_ENABLE BIT_15 66 67static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = { 68 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1}, 69 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34}, 70 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27}, 71 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1}, 72 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18}, 73 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1}, 74 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1}, 75 {QLCNIC_CMD_INTRPT_TEST, 22, 12}, 76 {QLCNIC_CMD_SET_MTU, 3, 1}, 77 {QLCNIC_CMD_READ_PHY, 4, 2}, 78 {QLCNIC_CMD_WRITE_PHY, 5, 1}, 79 {QLCNIC_CMD_READ_HW_REG, 4, 1}, 80 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2}, 81 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1}, 82 {QLCNIC_CMD_READ_MAX_MTU, 4, 2}, 83 {QLCNIC_CMD_READ_MAX_LRO, 4, 2}, 84 {QLCNIC_CMD_MAC_ADDRESS, 4, 3}, 85 {QLCNIC_CMD_GET_PCI_INFO, 1, 129}, 86 {QLCNIC_CMD_GET_NIC_INFO, 2, 19}, 87 {QLCNIC_CMD_SET_NIC_INFO, 32, 1}, 88 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3}, 89 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1}, 90 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3}, 91 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1}, 92 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1}, 93 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3}, 94 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1}, 95 {QLCNIC_CMD_CONFIG_PORT, 4, 1}, 96 {QLCNIC_CMD_TEMP_SIZE, 1, 4}, 97 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5}, 98 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1}, 99 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3}, 100 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1}, 101 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1}, 102 {QLCNIC_CMD_CONFIGURE_LED, 2, 1}, 103 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1}, 104 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1}, 105 {QLCNIC_CMD_GET_STATISTICS, 2, 80}, 106 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1}, 107 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2}, 108 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4}, 109 {QLCNIC_CMD_IDC_ACK, 5, 1}, 110 {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1}, 111 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1}, 112 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1}, 113 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5}, 114 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1}, 115 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26}, 116 {QLCNIC_CMD_CONFIG_VPORT, 4, 4}, 117 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1}, 118 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2}, 119 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50}, 120 {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1}, 121}; 122 123const u32 qlcnic_83xx_ext_reg_tbl[] = { 124 0x38CC, /* Global Reset */ 125 0x38F0, /* Wildcard */ 126 0x38FC, /* Informant */ 127 0x3038, /* Host MBX ctrl */ 128 0x303C, /* FW MBX ctrl */ 129 0x355C, /* BOOT LOADER ADDRESS REG */ 130 0x3560, /* BOOT LOADER SIZE REG */ 131 0x3564, /* FW IMAGE ADDR REG */ 132 0x1000, /* MBX intr enable */ 133 0x1200, /* Default Intr mask */ 134 0x1204, /* Default Interrupt ID */ 135 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */ 136 0x3784, /* QLC_83XX_IDC_DEV_STATE */ 137 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */ 138 0x378C, /* QLC_83XX_IDC_DRV_ACK */ 139 0x3790, /* QLC_83XX_IDC_CTRL */ 140 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */ 141 0x3798, /* QLC_83XX_IDC_MIN_VERSION */ 142 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */ 143 0x37A0, /* QLC_83XX_IDC_PF_0 */ 144 0x37A4, /* QLC_83XX_IDC_PF_1 */ 145 0x37A8, /* QLC_83XX_IDC_PF_2 */ 146 0x37AC, /* QLC_83XX_IDC_PF_3 */ 147 0x37B0, /* QLC_83XX_IDC_PF_4 */ 148 0x37B4, /* QLC_83XX_IDC_PF_5 */ 149 0x37B8, /* QLC_83XX_IDC_PF_6 */ 150 0x37BC, /* QLC_83XX_IDC_PF_7 */ 151 0x37C0, /* QLC_83XX_IDC_PF_8 */ 152 0x37C4, /* QLC_83XX_IDC_PF_9 */ 153 0x37C8, /* QLC_83XX_IDC_PF_10 */ 154 0x37CC, /* QLC_83XX_IDC_PF_11 */ 155 0x37D0, /* QLC_83XX_IDC_PF_12 */ 156 0x37D4, /* QLC_83XX_IDC_PF_13 */ 157 0x37D8, /* QLC_83XX_IDC_PF_14 */ 158 0x37DC, /* QLC_83XX_IDC_PF_15 */ 159 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */ 160 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */ 161 0x37F0, /* QLC_83XX_DRV_OP_MODE */ 162 0x37F4, /* QLC_83XX_VNIC_STATE */ 163 0x3868, /* QLC_83XX_DRV_LOCK */ 164 0x386C, /* QLC_83XX_DRV_UNLOCK */ 165 0x3504, /* QLC_83XX_DRV_LOCK_ID */ 166 0x34A4, /* QLC_83XX_ASIC_TEMP */ 167}; 168 169const u32 qlcnic_83xx_reg_tbl[] = { 170 0x34A8, /* PEG_HALT_STAT1 */ 171 0x34AC, /* PEG_HALT_STAT2 */ 172 0x34B0, /* FW_HEARTBEAT */ 173 0x3500, /* FLASH LOCK_ID */ 174 0x3528, /* FW_CAPABILITIES */ 175 0x3538, /* Driver active, DRV_REG0 */ 176 0x3540, /* Device state, DRV_REG1 */ 177 0x3544, /* Driver state, DRV_REG2 */ 178 0x3548, /* Driver scratch, DRV_REG3 */ 179 0x354C, /* Device partiton info, DRV_REG4 */ 180 0x3524, /* Driver IDC ver, DRV_REG5 */ 181 0x3550, /* FW_VER_MAJOR */ 182 0x3554, /* FW_VER_MINOR */ 183 0x3558, /* FW_VER_SUB */ 184 0x359C, /* NPAR STATE */ 185 0x35FC, /* FW_IMG_VALID */ 186 0x3650, /* CMD_PEG_STATE */ 187 0x373C, /* RCV_PEG_STATE */ 188 0x37B4, /* ASIC TEMP */ 189 0x356C, /* FW API */ 190 0x3570, /* DRV OP MODE */ 191 0x3850, /* FLASH LOCK */ 192 0x3854, /* FLASH UNLOCK */ 193}; 194 195static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = { 196 .read_crb = qlcnic_83xx_read_crb, 197 .write_crb = qlcnic_83xx_write_crb, 198 .read_reg = qlcnic_83xx_rd_reg_indirect, 199 .write_reg = qlcnic_83xx_wrt_reg_indirect, 200 .get_mac_address = qlcnic_83xx_get_mac_address, 201 .setup_intr = qlcnic_83xx_setup_intr, 202 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args, 203 .mbx_cmd = qlcnic_83xx_issue_cmd, 204 .get_func_no = qlcnic_83xx_get_func_no, 205 .api_lock = qlcnic_83xx_cam_lock, 206 .api_unlock = qlcnic_83xx_cam_unlock, 207 .add_sysfs = qlcnic_83xx_add_sysfs, 208 .remove_sysfs = qlcnic_83xx_remove_sysfs, 209 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag, 210 .create_rx_ctx = qlcnic_83xx_create_rx_ctx, 211 .create_tx_ctx = qlcnic_83xx_create_tx_ctx, 212 .del_rx_ctx = qlcnic_83xx_del_rx_ctx, 213 .del_tx_ctx = qlcnic_83xx_del_tx_ctx, 214 .setup_link_event = qlcnic_83xx_setup_link_event, 215 .get_nic_info = qlcnic_83xx_get_nic_info, 216 .get_pci_info = qlcnic_83xx_get_pci_info, 217 .set_nic_info = qlcnic_83xx_set_nic_info, 218 .change_macvlan = qlcnic_83xx_sre_macaddr_change, 219 .napi_enable = qlcnic_83xx_napi_enable, 220 .napi_disable = qlcnic_83xx_napi_disable, 221 .config_intr_coal = qlcnic_83xx_config_intr_coal, 222 .config_rss = qlcnic_83xx_config_rss, 223 .config_hw_lro = qlcnic_83xx_config_hw_lro, 224 .config_promisc_mode = qlcnic_83xx_nic_set_promisc, 225 .change_l2_filter = qlcnic_83xx_change_l2_filter, 226 .get_board_info = qlcnic_83xx_get_port_info, 227 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count, 228 .free_mac_list = qlcnic_82xx_free_mac_list, 229 .io_error_detected = qlcnic_83xx_io_error_detected, 230 .io_slot_reset = qlcnic_83xx_io_slot_reset, 231 .io_resume = qlcnic_83xx_io_resume, 232 .get_beacon_state = qlcnic_83xx_get_beacon_state, 233 .enable_sds_intr = qlcnic_83xx_enable_sds_intr, 234 .disable_sds_intr = qlcnic_83xx_disable_sds_intr, 235 .enable_tx_intr = qlcnic_83xx_enable_tx_intr, 236 .disable_tx_intr = qlcnic_83xx_disable_tx_intr, 237 .get_saved_state = qlcnic_83xx_get_saved_state, 238 .set_saved_state = qlcnic_83xx_set_saved_state, 239 .cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values, 240 .get_cap_size = qlcnic_83xx_get_cap_size, 241 .set_sys_info = qlcnic_83xx_set_sys_info, 242 .store_cap_mask = qlcnic_83xx_store_cap_mask, 243}; 244 245static struct qlcnic_nic_template qlcnic_83xx_ops = { 246 .config_bridged_mode = qlcnic_config_bridged_mode, 247 .config_led = qlcnic_config_led, 248 .request_reset = qlcnic_83xx_idc_request_reset, 249 .cancel_idc_work = qlcnic_83xx_idc_exit, 250 .napi_add = qlcnic_83xx_napi_add, 251 .napi_del = qlcnic_83xx_napi_del, 252 .config_ipaddr = qlcnic_83xx_config_ipaddr, 253 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr, 254 .shutdown = qlcnic_83xx_shutdown, 255 .resume = qlcnic_83xx_resume, 256}; 257 258void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw) 259{ 260 ahw->hw_ops = &qlcnic_83xx_hw_ops; 261 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; 262 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl; 263} 264 265int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter) 266{ 267 u32 fw_major, fw_minor, fw_build; 268 struct pci_dev *pdev = adapter->pdev; 269 270 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); 271 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); 272 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); 273 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build); 274 275 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n", 276 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build); 277 278 return adapter->fw_version; 279} 280 281static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr) 282{ 283 void __iomem *base; 284 u32 val; 285 286 base = adapter->ahw->pci_base0 + 287 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func); 288 writel(addr, base); 289 val = readl(base); 290 if (val != addr) 291 return -EIO; 292 293 return 0; 294} 295 296int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, 297 int *err) 298{ 299 struct qlcnic_hardware_context *ahw = adapter->ahw; 300 301 *err = __qlcnic_set_win_base(adapter, (u32) addr); 302 if (!*err) { 303 return QLCRDX(ahw, QLCNIC_WILDCARD); 304 } else { 305 dev_err(&adapter->pdev->dev, 306 "%s failed, addr = 0x%lx\n", __func__, addr); 307 return -EIO; 308 } 309} 310 311int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, 312 u32 data) 313{ 314 int err; 315 struct qlcnic_hardware_context *ahw = adapter->ahw; 316 317 err = __qlcnic_set_win_base(adapter, (u32) addr); 318 if (!err) { 319 QLCWRX(ahw, QLCNIC_WILDCARD, data); 320 return 0; 321 } else { 322 dev_err(&adapter->pdev->dev, 323 "%s failed, addr = 0x%x data = 0x%x\n", 324 __func__, (int)addr, data); 325 return err; 326 } 327} 328 329static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter) 330{ 331 struct qlcnic_hardware_context *ahw = adapter->ahw; 332 333 /* MSI-X enablement failed, use legacy interrupt */ 334 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR; 335 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK; 336 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR; 337 adapter->msix_entries[0].vector = adapter->pdev->irq; 338 dev_info(&adapter->pdev->dev, "using legacy interrupt\n"); 339} 340 341static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter) 342{ 343 int num_msix; 344 345 num_msix = adapter->drv_sds_rings; 346 347 /* account for AEN interrupt MSI-X based interrupts */ 348 num_msix += 1; 349 350 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) 351 num_msix += adapter->drv_tx_rings; 352 353 return num_msix; 354} 355 356int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter) 357{ 358 struct qlcnic_hardware_context *ahw = adapter->ahw; 359 int err, i, num_msix; 360 361 if (adapter->flags & QLCNIC_TSS_RSS) { 362 err = qlcnic_setup_tss_rss_intr(adapter); 363 if (err < 0) 364 return err; 365 num_msix = ahw->num_msix; 366 } else { 367 num_msix = qlcnic_83xx_calculate_msix_vector(adapter); 368 369 err = qlcnic_enable_msix(adapter, num_msix); 370 if (err == -ENOMEM) 371 return err; 372 373 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 374 num_msix = ahw->num_msix; 375 } else { 376 if (qlcnic_sriov_vf_check(adapter)) 377 return -EINVAL; 378 num_msix = 1; 379 adapter->drv_sds_rings = QLCNIC_SINGLE_RING; 380 adapter->drv_tx_rings = QLCNIC_SINGLE_RING; 381 } 382 } 383 384 /* setup interrupt mapping table for fw */ 385 ahw->intr_tbl = vzalloc(num_msix * 386 sizeof(struct qlcnic_intrpt_config)); 387 if (!ahw->intr_tbl) 388 return -ENOMEM; 389 390 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) { 391 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) { 392 dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n", 393 ahw->pci_func); 394 return -EOPNOTSUPP; 395 } 396 397 qlcnic_83xx_enable_legacy(adapter); 398 } 399 400 for (i = 0; i < num_msix; i++) { 401 if (adapter->flags & QLCNIC_MSIX_ENABLED) 402 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX; 403 else 404 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX; 405 ahw->intr_tbl[i].id = i; 406 ahw->intr_tbl[i].src = 0; 407 } 408 409 return 0; 410} 411 412static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter) 413{ 414 writel(0, adapter->tgt_mask_reg); 415} 416 417static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter) 418{ 419 if (adapter->tgt_mask_reg) 420 writel(1, adapter->tgt_mask_reg); 421} 422 423static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter 424 *adapter) 425{ 426 u32 mask; 427 428 /* Mailbox in MSI-x mode and Legacy Interrupt share the same 429 * source register. We could be here before contexts are created 430 * and sds_ring->crb_intr_mask has not been initialized, calculate 431 * BAR offset for Interrupt Source Register 432 */ 433 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 434 writel(0, adapter->ahw->pci_base0 + mask); 435} 436 437void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter) 438{ 439 u32 mask; 440 441 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 442 writel(1, adapter->ahw->pci_base0 + mask); 443 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0); 444} 445 446static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter, 447 struct qlcnic_cmd_args *cmd) 448{ 449 int i; 450 451 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) 452 return; 453 454 for (i = 0; i < cmd->rsp.num; i++) 455 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i)); 456} 457 458irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter) 459{ 460 u32 intr_val; 461 struct qlcnic_hardware_context *ahw = adapter->ahw; 462 int retries = 0; 463 464 intr_val = readl(adapter->tgt_status_reg); 465 466 if (!QLC_83XX_VALID_INTX_BIT31(intr_val)) 467 return IRQ_NONE; 468 469 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) { 470 adapter->stats.spurious_intr++; 471 return IRQ_NONE; 472 } 473 /* The barrier is required to ensure writes to the registers */ 474 wmb(); 475 476 /* clear the interrupt trigger control register */ 477 writel(0, adapter->isr_int_vec); 478 intr_val = readl(adapter->isr_int_vec); 479 do { 480 intr_val = readl(adapter->tgt_status_reg); 481 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func) 482 break; 483 retries++; 484 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) && 485 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY)); 486 487 return IRQ_HANDLED; 488} 489 490static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx) 491{ 492 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); 493 complete(&mbx->completion); 494} 495 496static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter) 497{ 498 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; 499 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 500 unsigned long flags; 501 502 spin_lock_irqsave(&mbx->aen_lock, flags); 503 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); 504 if (!(resp & QLCNIC_SET_OWNER)) 505 goto out; 506 507 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); 508 if (event & QLCNIC_MBX_ASYNC_EVENT) { 509 __qlcnic_83xx_process_aen(adapter); 510 } else { 511 if (atomic_read(&mbx->rsp_status) != rsp_status) 512 qlcnic_83xx_notify_mbx_response(mbx); 513 } 514out: 515 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 516 spin_unlock_irqrestore(&mbx->aen_lock, flags); 517} 518 519irqreturn_t qlcnic_83xx_intr(int irq, void *data) 520{ 521 struct qlcnic_adapter *adapter = data; 522 struct qlcnic_host_sds_ring *sds_ring; 523 struct qlcnic_hardware_context *ahw = adapter->ahw; 524 525 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE) 526 return IRQ_NONE; 527 528 qlcnic_83xx_poll_process_aen(adapter); 529 530 if (ahw->diag_test) { 531 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) 532 ahw->diag_cnt++; 533 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 534 return IRQ_HANDLED; 535 } 536 537 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) { 538 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 539 } else { 540 sds_ring = &adapter->recv_ctx->sds_rings[0]; 541 napi_schedule(&sds_ring->napi); 542 } 543 544 return IRQ_HANDLED; 545} 546 547irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data) 548{ 549 struct qlcnic_host_sds_ring *sds_ring = data; 550 struct qlcnic_adapter *adapter = sds_ring->adapter; 551 552 if (adapter->flags & QLCNIC_MSIX_ENABLED) 553 goto done; 554 555 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE) 556 return IRQ_NONE; 557 558done: 559 adapter->ahw->diag_cnt++; 560 qlcnic_enable_sds_intr(adapter, sds_ring); 561 562 return IRQ_HANDLED; 563} 564 565void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter) 566{ 567 u32 num_msix; 568 569 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) 570 qlcnic_83xx_set_legacy_intr_mask(adapter); 571 572 qlcnic_83xx_disable_mbx_intr(adapter); 573 574 if (adapter->flags & QLCNIC_MSIX_ENABLED) 575 num_msix = adapter->ahw->num_msix - 1; 576 else 577 num_msix = 0; 578 579 msleep(20); 580 581 if (adapter->msix_entries) { 582 synchronize_irq(adapter->msix_entries[num_msix].vector); 583 free_irq(adapter->msix_entries[num_msix].vector, adapter); 584 } 585} 586 587int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter) 588{ 589 irq_handler_t handler; 590 u32 val; 591 int err = 0; 592 unsigned long flags = 0; 593 594 if (!(adapter->flags & QLCNIC_MSI_ENABLED) && 595 !(adapter->flags & QLCNIC_MSIX_ENABLED)) 596 flags |= IRQF_SHARED; 597 598 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 599 handler = qlcnic_83xx_handle_aen; 600 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector; 601 err = request_irq(val, handler, flags, "qlcnic-MB", adapter); 602 if (err) { 603 dev_err(&adapter->pdev->dev, 604 "failed to register MBX interrupt\n"); 605 return err; 606 } 607 } else { 608 handler = qlcnic_83xx_intr; 609 val = adapter->msix_entries[0].vector; 610 err = request_irq(val, handler, flags, "qlcnic", adapter); 611 if (err) { 612 dev_err(&adapter->pdev->dev, 613 "failed to register INTx interrupt\n"); 614 return err; 615 } 616 qlcnic_83xx_clear_legacy_intr_mask(adapter); 617 } 618 619 /* Enable mailbox interrupt */ 620 qlcnic_83xx_enable_mbx_interrupt(adapter); 621 622 return err; 623} 624 625void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter) 626{ 627 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT); 628 adapter->ahw->pci_func = (val >> 24) & 0xff; 629} 630 631int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter) 632{ 633 void __iomem *addr; 634 u32 val, limit = 0; 635 636 struct qlcnic_hardware_context *ahw = adapter->ahw; 637 638 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func); 639 do { 640 val = readl(addr); 641 if (val) { 642 /* write the function number to register */ 643 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 644 ahw->pci_func); 645 return 0; 646 } 647 usleep_range(1000, 2000); 648 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT); 649 650 return -EIO; 651} 652 653void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter) 654{ 655 void __iomem *addr; 656 u32 val; 657 struct qlcnic_hardware_context *ahw = adapter->ahw; 658 659 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func); 660 val = readl(addr); 661} 662 663void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, 664 loff_t offset, size_t size) 665{ 666 int ret = 0; 667 u32 data; 668 669 if (qlcnic_api_lock(adapter)) { 670 dev_err(&adapter->pdev->dev, 671 "%s: failed to acquire lock. addr offset 0x%x\n", 672 __func__, (u32)offset); 673 return; 674 } 675 676 data = QLCRD32(adapter, (u32) offset, &ret); 677 qlcnic_api_unlock(adapter); 678 679 if (ret == -EIO) { 680 dev_err(&adapter->pdev->dev, 681 "%s: failed. addr offset 0x%x\n", 682 __func__, (u32)offset); 683 return; 684 } 685 memcpy(buf, &data, size); 686} 687 688void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf, 689 loff_t offset, size_t size) 690{ 691 u32 data; 692 693 memcpy(&data, buf, size); 694 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data); 695} 696 697int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter) 698{ 699 struct qlcnic_hardware_context *ahw = adapter->ahw; 700 int status; 701 702 status = qlcnic_83xx_get_port_config(adapter); 703 if (status) { 704 dev_err(&adapter->pdev->dev, 705 "Get Port Info failed\n"); 706 } else { 707 708 if (ahw->port_config & QLC_83XX_10G_CAPABLE) { 709 ahw->port_type = QLCNIC_XGBE; 710 } else if (ahw->port_config & QLC_83XX_10_CAPABLE || 711 ahw->port_config & QLC_83XX_100_CAPABLE || 712 ahw->port_config & QLC_83XX_1G_CAPABLE) { 713 ahw->port_type = QLCNIC_GBE; 714 } else { 715 ahw->port_type = QLCNIC_XGBE; 716 } 717 718 if (QLC_83XX_AUTONEG(ahw->port_config)) 719 ahw->link_autoneg = AUTONEG_ENABLE; 720 721 } 722 return status; 723} 724 725static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter) 726{ 727 struct qlcnic_hardware_context *ahw = adapter->ahw; 728 u16 act_pci_fn = ahw->total_nic_func; 729 u16 count; 730 731 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT; 732 if (act_pci_fn <= 2) 733 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) / 734 act_pci_fn; 735 else 736 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) / 737 act_pci_fn; 738 ahw->max_uc_count = count; 739} 740 741void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter) 742{ 743 u32 val; 744 745 if (adapter->flags & QLCNIC_MSIX_ENABLED) 746 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); 747 else 748 val = BIT_2; 749 750 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val); 751 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); 752} 753 754void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter, 755 const struct pci_device_id *ent) 756{ 757 u32 op_mode, priv_level; 758 struct qlcnic_hardware_context *ahw = adapter->ahw; 759 760 ahw->fw_hal_version = 2; 761 qlcnic_get_func_no(adapter); 762 763 if (qlcnic_sriov_vf_check(adapter)) { 764 qlcnic_sriov_vf_set_ops(adapter); 765 return; 766 } 767 768 /* Determine function privilege level */ 769 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE); 770 if (op_mode == QLC_83XX_DEFAULT_OPMODE) 771 priv_level = QLCNIC_MGMT_FUNC; 772 else 773 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode, 774 ahw->pci_func); 775 776 if (priv_level == QLCNIC_NON_PRIV_FUNC) { 777 ahw->op_mode = QLCNIC_NON_PRIV_FUNC; 778 dev_info(&adapter->pdev->dev, 779 "HAL Version: %d Non Privileged function\n", 780 ahw->fw_hal_version); 781 adapter->nic_ops = &qlcnic_vf_ops; 782 } else { 783 if (pci_find_ext_capability(adapter->pdev, 784 PCI_EXT_CAP_ID_SRIOV)) 785 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state); 786 adapter->nic_ops = &qlcnic_83xx_ops; 787 } 788} 789 790static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, 791 u32 data[]); 792static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, 793 u32 data[]); 794 795void qlcnic_dump_mbx(struct qlcnic_adapter *adapter, 796 struct qlcnic_cmd_args *cmd) 797{ 798 int i; 799 800 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) 801 return; 802 803 dev_info(&adapter->pdev->dev, 804 "Host MBX regs(%d)\n", cmd->req.num); 805 for (i = 0; i < cmd->req.num; i++) { 806 if (i && !(i % 8)) 807 pr_info("\n"); 808 pr_info("%08x ", cmd->req.arg[i]); 809 } 810 pr_info("\n"); 811 dev_info(&adapter->pdev->dev, 812 "FW MBX regs(%d)\n", cmd->rsp.num); 813 for (i = 0; i < cmd->rsp.num; i++) { 814 if (i && !(i % 8)) 815 pr_info("\n"); 816 pr_info("%08x ", cmd->rsp.arg[i]); 817 } 818 pr_info("\n"); 819} 820 821static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter, 822 struct qlcnic_cmd_args *cmd) 823{ 824 struct qlcnic_hardware_context *ahw = adapter->ahw; 825 int opcode = LSW(cmd->req.arg[0]); 826 unsigned long max_loops; 827 828 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP; 829 830 for (; max_loops; max_loops--) { 831 if (atomic_read(&cmd->rsp_status) == 832 QLC_83XX_MBX_RESPONSE_ARRIVED) 833 return; 834 835 udelay(1); 836 } 837 838 dev_err(&adapter->pdev->dev, 839 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 840 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode); 841 flush_workqueue(ahw->mailbox->work_q); 842 return; 843} 844 845int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter, 846 struct qlcnic_cmd_args *cmd) 847{ 848 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 849 struct qlcnic_hardware_context *ahw = adapter->ahw; 850 int cmd_type, err, opcode; 851 unsigned long timeout; 852 853 if (!mbx) 854 return -EIO; 855 856 opcode = LSW(cmd->req.arg[0]); 857 cmd_type = cmd->type; 858 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout); 859 if (err) { 860 dev_err(&adapter->pdev->dev, 861 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n", 862 __func__, opcode, cmd->type, ahw->pci_func, 863 ahw->op_mode); 864 return err; 865 } 866 867 switch (cmd_type) { 868 case QLC_83XX_MBX_CMD_WAIT: 869 if (!wait_for_completion_timeout(&cmd->completion, timeout)) { 870 dev_err(&adapter->pdev->dev, 871 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 872 __func__, opcode, cmd_type, ahw->pci_func, 873 ahw->op_mode); 874 flush_workqueue(mbx->work_q); 875 } 876 break; 877 case QLC_83XX_MBX_CMD_NO_WAIT: 878 return 0; 879 case QLC_83XX_MBX_CMD_BUSY_WAIT: 880 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd); 881 break; 882 default: 883 dev_err(&adapter->pdev->dev, 884 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 885 __func__, opcode, cmd_type, ahw->pci_func, 886 ahw->op_mode); 887 qlcnic_83xx_detach_mailbox_work(adapter); 888 } 889 890 return cmd->rsp_opcode; 891} 892 893int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 894 struct qlcnic_adapter *adapter, u32 type) 895{ 896 int i, size; 897 u32 temp; 898 const struct qlcnic_mailbox_metadata *mbx_tbl; 899 900 memset(mbx, 0, sizeof(struct qlcnic_cmd_args)); 901 mbx_tbl = qlcnic_83xx_mbx_tbl; 902 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl); 903 for (i = 0; i < size; i++) { 904 if (type == mbx_tbl[i].cmd) { 905 mbx->op_type = QLC_83XX_FW_MBX_CMD; 906 mbx->req.num = mbx_tbl[i].in_args; 907 mbx->rsp.num = mbx_tbl[i].out_args; 908 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32), 909 GFP_ATOMIC); 910 if (!mbx->req.arg) 911 return -ENOMEM; 912 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32), 913 GFP_ATOMIC); 914 if (!mbx->rsp.arg) { 915 kfree(mbx->req.arg); 916 mbx->req.arg = NULL; 917 return -ENOMEM; 918 } 919 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num); 920 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num); 921 temp = adapter->ahw->fw_hal_version << 29; 922 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp); 923 mbx->cmd_op = type; 924 return 0; 925 } 926 } 927 928 dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n", 929 __func__, type); 930 return -EINVAL; 931} 932 933void qlcnic_83xx_idc_aen_work(struct work_struct *work) 934{ 935 struct qlcnic_adapter *adapter; 936 struct qlcnic_cmd_args cmd; 937 int i, err = 0; 938 939 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work); 940 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK); 941 if (err) 942 return; 943 944 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++) 945 cmd.req.arg[i] = adapter->ahw->mbox_aen[i]; 946 947 err = qlcnic_issue_cmd(adapter, &cmd); 948 if (err) 949 dev_info(&adapter->pdev->dev, 950 "%s: Mailbox IDC ACK failed.\n", __func__); 951 qlcnic_free_mbx_args(&cmd); 952} 953 954static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, 955 u32 data[]) 956{ 957 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n", 958 QLCNIC_MBX_RSP(data[0])); 959 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status); 960 return; 961} 962 963static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) 964{ 965 struct qlcnic_hardware_context *ahw = adapter->ahw; 966 u32 event[QLC_83XX_MBX_AEN_CNT]; 967 int i; 968 969 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) 970 event[i] = readl(QLCNIC_MBX_FW(ahw, i)); 971 972 switch (QLCNIC_MBX_RSP(event[0])) { 973 974 case QLCNIC_MBX_LINK_EVENT: 975 qlcnic_83xx_handle_link_aen(adapter, event); 976 break; 977 case QLCNIC_MBX_COMP_EVENT: 978 qlcnic_83xx_handle_idc_comp_aen(adapter, event); 979 break; 980 case QLCNIC_MBX_REQUEST_EVENT: 981 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) 982 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]); 983 queue_delayed_work(adapter->qlcnic_wq, 984 &adapter->idc_aen_work, 0); 985 break; 986 case QLCNIC_MBX_TIME_EXTEND_EVENT: 987 ahw->extend_lb_time = event[1] >> 8 & 0xf; 988 break; 989 case QLCNIC_MBX_BC_EVENT: 990 qlcnic_sriov_handle_bc_event(adapter, event[1]); 991 break; 992 case QLCNIC_MBX_SFP_INSERT_EVENT: 993 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n", 994 QLCNIC_MBX_RSP(event[0])); 995 break; 996 case QLCNIC_MBX_SFP_REMOVE_EVENT: 997 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n", 998 QLCNIC_MBX_RSP(event[0])); 999 break; 1000 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT: 1001 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]); 1002 break; 1003 default: 1004 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n", 1005 QLCNIC_MBX_RSP(event[0])); 1006 break; 1007 } 1008 1009 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); 1010} 1011 1012static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) 1013{ 1014 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; 1015 struct qlcnic_hardware_context *ahw = adapter->ahw; 1016 struct qlcnic_mailbox *mbx = ahw->mailbox; 1017 unsigned long flags; 1018 1019 spin_lock_irqsave(&mbx->aen_lock, flags); 1020 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL); 1021 if (resp & QLCNIC_SET_OWNER) { 1022 event = readl(QLCNIC_MBX_FW(ahw, 0)); 1023 if (event & QLCNIC_MBX_ASYNC_EVENT) { 1024 __qlcnic_83xx_process_aen(adapter); 1025 } else { 1026 if (atomic_read(&mbx->rsp_status) != rsp_status) 1027 qlcnic_83xx_notify_mbx_response(mbx); 1028 } 1029 } 1030 spin_unlock_irqrestore(&mbx->aen_lock, flags); 1031} 1032 1033static void qlcnic_83xx_mbx_poll_work(struct work_struct *work) 1034{ 1035 struct qlcnic_adapter *adapter; 1036 1037 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work); 1038 1039 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 1040 return; 1041 1042 qlcnic_83xx_process_aen(adapter); 1043 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 1044 (HZ / 10)); 1045} 1046 1047void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter) 1048{ 1049 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 1050 return; 1051 1052 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work); 1053 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0); 1054} 1055 1056void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter) 1057{ 1058 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) 1059 return; 1060 cancel_delayed_work_sync(&adapter->mbx_poll_work); 1061} 1062 1063static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter) 1064{ 1065 int index, i, err, sds_mbx_size; 1066 u32 *buf, intrpt_id, intr_mask; 1067 u16 context_id; 1068 u8 num_sds; 1069 struct qlcnic_cmd_args cmd; 1070 struct qlcnic_host_sds_ring *sds; 1071 struct qlcnic_sds_mbx sds_mbx; 1072 struct qlcnic_add_rings_mbx_out *mbx_out; 1073 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1074 struct qlcnic_hardware_context *ahw = adapter->ahw; 1075 1076 sds_mbx_size = sizeof(struct qlcnic_sds_mbx); 1077 context_id = recv_ctx->context_id; 1078 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS; 1079 ahw->hw_ops->alloc_mbx_args(&cmd, adapter, 1080 QLCNIC_CMD_ADD_RCV_RINGS); 1081 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16); 1082 1083 /* set up status rings, mbx 2-81 */ 1084 index = 2; 1085 for (i = 8; i < adapter->drv_sds_rings; i++) { 1086 memset(&sds_mbx, 0, sds_mbx_size); 1087 sds = &recv_ctx->sds_rings[i]; 1088 sds->consumer = 0; 1089 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); 1090 sds_mbx.phy_addr_low = LSD(sds->phys_addr); 1091 sds_mbx.phy_addr_high = MSD(sds->phys_addr); 1092 sds_mbx.sds_ring_size = sds->num_desc; 1093 1094 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1095 intrpt_id = ahw->intr_tbl[i].id; 1096 else 1097 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1098 1099 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1100 sds_mbx.intrpt_id = intrpt_id; 1101 else 1102 sds_mbx.intrpt_id = 0xffff; 1103 sds_mbx.intrpt_val = 0; 1104 buf = &cmd.req.arg[index]; 1105 memcpy(buf, &sds_mbx, sds_mbx_size); 1106 index += sds_mbx_size / sizeof(u32); 1107 } 1108 1109 /* send the mailbox command */ 1110 err = ahw->hw_ops->mbx_cmd(adapter, &cmd); 1111 if (err) { 1112 dev_err(&adapter->pdev->dev, 1113 "Failed to add rings %d\n", err); 1114 goto out; 1115 } 1116 1117 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1]; 1118 index = 0; 1119 /* status descriptor ring */ 1120 for (i = 8; i < adapter->drv_sds_rings; i++) { 1121 sds = &recv_ctx->sds_rings[i]; 1122 sds->crb_sts_consumer = ahw->pci_base0 + 1123 mbx_out->host_csmr[index]; 1124 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1125 intr_mask = ahw->intr_tbl[i].src; 1126 else 1127 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 1128 1129 sds->crb_intr_mask = ahw->pci_base0 + intr_mask; 1130 index++; 1131 } 1132out: 1133 qlcnic_free_mbx_args(&cmd); 1134 return err; 1135} 1136 1137void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter) 1138{ 1139 int err; 1140 u32 temp = 0; 1141 struct qlcnic_cmd_args cmd; 1142 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1143 1144 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX)) 1145 return; 1146 1147 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1148 cmd.req.arg[0] |= (0x3 << 29); 1149 1150 if (qlcnic_sriov_pf_check(adapter)) 1151 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp); 1152 1153 cmd.req.arg[1] = recv_ctx->context_id | temp; 1154 err = qlcnic_issue_cmd(adapter, &cmd); 1155 if (err) 1156 dev_err(&adapter->pdev->dev, 1157 "Failed to destroy rx ctx in firmware\n"); 1158 1159 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED; 1160 qlcnic_free_mbx_args(&cmd); 1161} 1162 1163int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter) 1164{ 1165 int i, err, index, sds_mbx_size, rds_mbx_size; 1166 u8 num_sds, num_rds; 1167 u32 *buf, intrpt_id, intr_mask, cap = 0; 1168 struct qlcnic_host_sds_ring *sds; 1169 struct qlcnic_host_rds_ring *rds; 1170 struct qlcnic_sds_mbx sds_mbx; 1171 struct qlcnic_rds_mbx rds_mbx; 1172 struct qlcnic_cmd_args cmd; 1173 struct qlcnic_rcv_mbx_out *mbx_out; 1174 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; 1175 struct qlcnic_hardware_context *ahw = adapter->ahw; 1176 num_rds = adapter->max_rds_rings; 1177 1178 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS) 1179 num_sds = adapter->drv_sds_rings; 1180 else 1181 num_sds = QLCNIC_MAX_SDS_RINGS; 1182 1183 sds_mbx_size = sizeof(struct qlcnic_sds_mbx); 1184 rds_mbx_size = sizeof(struct qlcnic_rds_mbx); 1185 cap = QLCNIC_CAP0_LEGACY_CONTEXT; 1186 1187 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP) 1188 cap |= QLC_83XX_FW_CAP_LRO_MSS; 1189 1190 /* set mailbox hdr and capabilities */ 1191 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1192 QLCNIC_CMD_CREATE_RX_CTX); 1193 if (err) 1194 return err; 1195 1196 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1197 cmd.req.arg[0] |= (0x3 << 29); 1198 1199 cmd.req.arg[1] = cap; 1200 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) | 1201 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16); 1202 1203 if (qlcnic_sriov_pf_check(adapter)) 1204 qlcnic_pf_set_interface_id_create_rx_ctx(adapter, 1205 &cmd.req.arg[6]); 1206 /* set up status rings, mbx 8-57/87 */ 1207 index = QLC_83XX_HOST_SDS_MBX_IDX; 1208 for (i = 0; i < num_sds; i++) { 1209 memset(&sds_mbx, 0, sds_mbx_size); 1210 sds = &recv_ctx->sds_rings[i]; 1211 sds->consumer = 0; 1212 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); 1213 sds_mbx.phy_addr_low = LSD(sds->phys_addr); 1214 sds_mbx.phy_addr_high = MSD(sds->phys_addr); 1215 sds_mbx.sds_ring_size = sds->num_desc; 1216 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1217 intrpt_id = ahw->intr_tbl[i].id; 1218 else 1219 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1220 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1221 sds_mbx.intrpt_id = intrpt_id; 1222 else 1223 sds_mbx.intrpt_id = 0xffff; 1224 sds_mbx.intrpt_val = 0; 1225 buf = &cmd.req.arg[index]; 1226 memcpy(buf, &sds_mbx, sds_mbx_size); 1227 index += sds_mbx_size / sizeof(u32); 1228 } 1229 /* set up receive rings, mbx 88-111/135 */ 1230 index = QLCNIC_HOST_RDS_MBX_IDX; 1231 rds = &recv_ctx->rds_rings[0]; 1232 rds->producer = 0; 1233 memset(&rds_mbx, 0, rds_mbx_size); 1234 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr); 1235 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr); 1236 rds_mbx.reg_ring_sz = rds->dma_size; 1237 rds_mbx.reg_ring_len = rds->num_desc; 1238 /* Jumbo ring */ 1239 rds = &recv_ctx->rds_rings[1]; 1240 rds->producer = 0; 1241 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr); 1242 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr); 1243 rds_mbx.jmb_ring_sz = rds->dma_size; 1244 rds_mbx.jmb_ring_len = rds->num_desc; 1245 buf = &cmd.req.arg[index]; 1246 memcpy(buf, &rds_mbx, rds_mbx_size); 1247 1248 /* send the mailbox command */ 1249 err = ahw->hw_ops->mbx_cmd(adapter, &cmd); 1250 if (err) { 1251 dev_err(&adapter->pdev->dev, 1252 "Failed to create Rx ctx in firmware%d\n", err); 1253 goto out; 1254 } 1255 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1]; 1256 recv_ctx->context_id = mbx_out->ctx_id; 1257 recv_ctx->state = mbx_out->state; 1258 recv_ctx->virt_port = mbx_out->vport_id; 1259 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n", 1260 recv_ctx->context_id, recv_ctx->state); 1261 /* Receive descriptor ring */ 1262 /* Standard ring */ 1263 rds = &recv_ctx->rds_rings[0]; 1264 rds->crb_rcv_producer = ahw->pci_base0 + 1265 mbx_out->host_prod[0].reg_buf; 1266 /* Jumbo ring */ 1267 rds = &recv_ctx->rds_rings[1]; 1268 rds->crb_rcv_producer = ahw->pci_base0 + 1269 mbx_out->host_prod[0].jmb_buf; 1270 /* status descriptor ring */ 1271 for (i = 0; i < num_sds; i++) { 1272 sds = &recv_ctx->sds_rings[i]; 1273 sds->crb_sts_consumer = ahw->pci_base0 + 1274 mbx_out->host_csmr[i]; 1275 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1276 intr_mask = ahw->intr_tbl[i].src; 1277 else 1278 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 1279 sds->crb_intr_mask = ahw->pci_base0 + intr_mask; 1280 } 1281 1282 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS) 1283 err = qlcnic_83xx_add_rings(adapter); 1284out: 1285 qlcnic_free_mbx_args(&cmd); 1286 return err; 1287} 1288 1289void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter, 1290 struct qlcnic_host_tx_ring *tx_ring) 1291{ 1292 struct qlcnic_cmd_args cmd; 1293 u32 temp = 0; 1294 1295 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX)) 1296 return; 1297 1298 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1299 cmd.req.arg[0] |= (0x3 << 29); 1300 1301 if (qlcnic_sriov_pf_check(adapter)) 1302 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp); 1303 1304 cmd.req.arg[1] = tx_ring->ctx_id | temp; 1305 if (qlcnic_issue_cmd(adapter, &cmd)) 1306 dev_err(&adapter->pdev->dev, 1307 "Failed to destroy tx ctx in firmware\n"); 1308 qlcnic_free_mbx_args(&cmd); 1309} 1310 1311int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter, 1312 struct qlcnic_host_tx_ring *tx, int ring) 1313{ 1314 int err; 1315 u16 msix_id; 1316 u32 *buf, intr_mask, temp = 0; 1317 struct qlcnic_cmd_args cmd; 1318 struct qlcnic_tx_mbx mbx; 1319 struct qlcnic_tx_mbx_out *mbx_out; 1320 struct qlcnic_hardware_context *ahw = adapter->ahw; 1321 u32 msix_vector; 1322 1323 /* Reset host resources */ 1324 tx->producer = 0; 1325 tx->sw_consumer = 0; 1326 *(tx->hw_consumer) = 0; 1327 1328 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx)); 1329 1330 /* setup mailbox inbox registerss */ 1331 mbx.phys_addr_low = LSD(tx->phys_addr); 1332 mbx.phys_addr_high = MSD(tx->phys_addr); 1333 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr); 1334 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr); 1335 mbx.size = tx->num_desc; 1336 if (adapter->flags & QLCNIC_MSIX_ENABLED) { 1337 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) 1338 msix_vector = adapter->drv_sds_rings + ring; 1339 else 1340 msix_vector = adapter->drv_sds_rings - 1; 1341 msix_id = ahw->intr_tbl[msix_vector].id; 1342 } else { 1343 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 1344 } 1345 1346 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) 1347 mbx.intr_id = msix_id; 1348 else 1349 mbx.intr_id = 0xffff; 1350 mbx.src = 0; 1351 1352 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX); 1353 if (err) 1354 return err; 1355 1356 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) 1357 cmd.req.arg[0] |= (0x3 << 29); 1358 1359 if (qlcnic_sriov_pf_check(adapter)) 1360 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp); 1361 1362 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT; 1363 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp; 1364 1365 buf = &cmd.req.arg[6]; 1366 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx)); 1367 /* send the mailbox command*/ 1368 err = qlcnic_issue_cmd(adapter, &cmd); 1369 if (err) { 1370 netdev_err(adapter->netdev, 1371 "Failed to create Tx ctx in firmware 0x%x\n", err); 1372 goto out; 1373 } 1374 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2]; 1375 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod; 1376 tx->ctx_id = mbx_out->ctx_id; 1377 if ((adapter->flags & QLCNIC_MSIX_ENABLED) && 1378 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) { 1379 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src; 1380 tx->crb_intr_mask = ahw->pci_base0 + intr_mask; 1381 } 1382 netdev_info(adapter->netdev, 1383 "Tx Context[0x%x] Created, state:0x%x\n", 1384 tx->ctx_id, mbx_out->state); 1385out: 1386 qlcnic_free_mbx_args(&cmd); 1387 return err; 1388} 1389 1390static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test, 1391 u8 num_sds_ring) 1392{ 1393 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1394 struct qlcnic_host_sds_ring *sds_ring; 1395 struct qlcnic_host_rds_ring *rds_ring; 1396 u16 adapter_state = adapter->is_up; 1397 u8 ring; 1398 int ret; 1399 1400 netif_device_detach(netdev); 1401 1402 if (netif_running(netdev)) 1403 __qlcnic_down(adapter, netdev); 1404 1405 qlcnic_detach(adapter); 1406 1407 adapter->drv_sds_rings = QLCNIC_SINGLE_RING; 1408 adapter->ahw->diag_test = test; 1409 adapter->ahw->linkup = 0; 1410 1411 ret = qlcnic_attach(adapter); 1412 if (ret) { 1413 netif_device_attach(netdev); 1414 return ret; 1415 } 1416 1417 ret = qlcnic_fw_create_ctx(adapter); 1418 if (ret) { 1419 qlcnic_detach(adapter); 1420 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) { 1421 adapter->drv_sds_rings = num_sds_ring; 1422 qlcnic_attach(adapter); 1423 } 1424 netif_device_attach(netdev); 1425 return ret; 1426 } 1427 1428 for (ring = 0; ring < adapter->max_rds_rings; ring++) { 1429 rds_ring = &adapter->recv_ctx->rds_rings[ring]; 1430 qlcnic_post_rx_buffers(adapter, rds_ring, ring); 1431 } 1432 1433 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { 1434 for (ring = 0; ring < adapter->drv_sds_rings; ring++) { 1435 sds_ring = &adapter->recv_ctx->sds_rings[ring]; 1436 qlcnic_enable_sds_intr(adapter, sds_ring); 1437 } 1438 } 1439 1440 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) { 1441 adapter->ahw->loopback_state = 0; 1442 adapter->ahw->hw_ops->setup_link_event(adapter, 1); 1443 } 1444 1445 set_bit(__QLCNIC_DEV_UP, &adapter->state); 1446 return 0; 1447} 1448 1449static void qlcnic_83xx_diag_free_res(struct net_device *netdev, 1450 u8 drv_sds_rings) 1451{ 1452 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1453 struct qlcnic_host_sds_ring *sds_ring; 1454 int ring; 1455 1456 clear_bit(__QLCNIC_DEV_UP, &adapter->state); 1457 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { 1458 for (ring = 0; ring < adapter->drv_sds_rings; ring++) { 1459 sds_ring = &adapter->recv_ctx->sds_rings[ring]; 1460 if (adapter->flags & QLCNIC_MSIX_ENABLED) 1461 qlcnic_disable_sds_intr(adapter, sds_ring); 1462 } 1463 } 1464 1465 qlcnic_fw_destroy_ctx(adapter); 1466 qlcnic_detach(adapter); 1467 1468 adapter->ahw->diag_test = 0; 1469 adapter->drv_sds_rings = drv_sds_rings; 1470 1471 if (qlcnic_attach(adapter)) 1472 goto out; 1473 1474 if (netif_running(netdev)) 1475 __qlcnic_up(adapter, netdev); 1476 1477out: 1478 netif_device_attach(netdev); 1479} 1480 1481static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter) 1482{ 1483 struct qlcnic_hardware_context *ahw = adapter->ahw; 1484 struct qlcnic_cmd_args cmd; 1485 u8 beacon_state; 1486 int err = 0; 1487 1488 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG); 1489 if (!err) { 1490 err = qlcnic_issue_cmd(adapter, &cmd); 1491 if (!err) { 1492 beacon_state = cmd.rsp.arg[4]; 1493 if (beacon_state == QLCNIC_BEACON_DISABLE) 1494 ahw->beacon_state = QLC_83XX_BEACON_OFF; 1495 else if (beacon_state == QLC_83XX_ENABLE_BEACON) 1496 ahw->beacon_state = QLC_83XX_BEACON_ON; 1497 } 1498 } else { 1499 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n", 1500 err); 1501 } 1502 1503 qlcnic_free_mbx_args(&cmd); 1504 1505 return; 1506} 1507 1508int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state, 1509 u32 beacon) 1510{ 1511 struct qlcnic_cmd_args cmd; 1512 u32 mbx_in; 1513 int i, status = 0; 1514 1515 if (state) { 1516 /* Get LED configuration */ 1517 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1518 QLCNIC_CMD_GET_LED_CONFIG); 1519 if (status) 1520 return status; 1521 1522 status = qlcnic_issue_cmd(adapter, &cmd); 1523 if (status) { 1524 dev_err(&adapter->pdev->dev, 1525 "Get led config failed.\n"); 1526 goto mbx_err; 1527 } else { 1528 for (i = 0; i < 4; i++) 1529 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1]; 1530 } 1531 qlcnic_free_mbx_args(&cmd); 1532 /* Set LED Configuration */ 1533 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) | 1534 LSW(QLC_83XX_LED_CONFIG); 1535 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1536 QLCNIC_CMD_SET_LED_CONFIG); 1537 if (status) 1538 return status; 1539 1540 cmd.req.arg[1] = mbx_in; 1541 cmd.req.arg[2] = mbx_in; 1542 cmd.req.arg[3] = mbx_in; 1543 if (beacon) 1544 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON; 1545 status = qlcnic_issue_cmd(adapter, &cmd); 1546 if (status) { 1547 dev_err(&adapter->pdev->dev, 1548 "Set led config failed.\n"); 1549 } 1550mbx_err: 1551 qlcnic_free_mbx_args(&cmd); 1552 return status; 1553 1554 } else { 1555 /* Restoring default LED configuration */ 1556 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1557 QLCNIC_CMD_SET_LED_CONFIG); 1558 if (status) 1559 return status; 1560 1561 cmd.req.arg[1] = adapter->ahw->mbox_reg[0]; 1562 cmd.req.arg[2] = adapter->ahw->mbox_reg[1]; 1563 cmd.req.arg[3] = adapter->ahw->mbox_reg[2]; 1564 if (beacon) 1565 cmd.req.arg[4] = adapter->ahw->mbox_reg[3]; 1566 status = qlcnic_issue_cmd(adapter, &cmd); 1567 if (status) 1568 dev_err(&adapter->pdev->dev, 1569 "Restoring led config failed.\n"); 1570 qlcnic_free_mbx_args(&cmd); 1571 return status; 1572 } 1573} 1574 1575int qlcnic_83xx_set_led(struct net_device *netdev, 1576 enum ethtool_phys_id_state state) 1577{ 1578 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1579 int err = -EIO, active = 1; 1580 1581 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { 1582 netdev_warn(netdev, 1583 "LED test is not supported in non-privileged mode\n"); 1584 return -EOPNOTSUPP; 1585 } 1586 1587 switch (state) { 1588 case ETHTOOL_ID_ACTIVE: 1589 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) 1590 return -EBUSY; 1591 1592 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) 1593 break; 1594 1595 err = qlcnic_83xx_config_led(adapter, active, 0); 1596 if (err) 1597 netdev_err(netdev, "Failed to set LED blink state\n"); 1598 break; 1599 case ETHTOOL_ID_INACTIVE: 1600 active = 0; 1601 1602 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) 1603 break; 1604 1605 err = qlcnic_83xx_config_led(adapter, active, 0); 1606 if (err) 1607 netdev_err(netdev, "Failed to reset LED blink state\n"); 1608 break; 1609 1610 default: 1611 return -EINVAL; 1612 } 1613 1614 if (!active || err) 1615 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); 1616 1617 return err; 1618} 1619 1620void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable) 1621{ 1622 struct qlcnic_cmd_args cmd; 1623 int status; 1624 1625 if (qlcnic_sriov_vf_check(adapter)) 1626 return; 1627 1628 if (enable) 1629 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1630 QLCNIC_CMD_INIT_NIC_FUNC); 1631 else 1632 status = qlcnic_alloc_mbx_args(&cmd, adapter, 1633 QLCNIC_CMD_STOP_NIC_FUNC); 1634 1635 if (status) 1636 return; 1637 1638 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES; 1639 1640 if (adapter->dcb) 1641 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN; 1642 1643 status = qlcnic_issue_cmd(adapter, &cmd); 1644 if (status) 1645 dev_err(&adapter->pdev->dev, 1646 "Failed to %s in NIC IDC function event.\n", 1647 (enable ? "register" : "unregister")); 1648 1649 qlcnic_free_mbx_args(&cmd); 1650} 1651 1652static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter) 1653{ 1654 struct qlcnic_cmd_args cmd; 1655 int err; 1656 1657 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG); 1658 if (err) 1659 return err; 1660 1661 cmd.req.arg[1] = adapter->ahw->port_config; 1662 err = qlcnic_issue_cmd(adapter, &cmd); 1663 if (err) 1664 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n"); 1665 qlcnic_free_mbx_args(&cmd); 1666 return err; 1667} 1668 1669static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter) 1670{ 1671 struct qlcnic_cmd_args cmd; 1672 int err; 1673 1674 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG); 1675 if (err) 1676 return err; 1677 1678 err = qlcnic_issue_cmd(adapter, &cmd); 1679 if (err) 1680 dev_info(&adapter->pdev->dev, "Get Port config failed\n"); 1681 else 1682 adapter->ahw->port_config = cmd.rsp.arg[1]; 1683 qlcnic_free_mbx_args(&cmd); 1684 return err; 1685} 1686 1687int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable) 1688{ 1689 int err; 1690 u32 temp; 1691 struct qlcnic_cmd_args cmd; 1692 1693 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT); 1694 if (err) 1695 return err; 1696 1697 temp = adapter->recv_ctx->context_id << 16; 1698 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp; 1699 err = qlcnic_issue_cmd(adapter, &cmd); 1700 if (err) 1701 dev_info(&adapter->pdev->dev, 1702 "Setup linkevent mailbox failed\n"); 1703 qlcnic_free_mbx_args(&cmd); 1704 return err; 1705} 1706 1707static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter, 1708 u32 *interface_id) 1709{ 1710 if (qlcnic_sriov_pf_check(adapter)) { 1711 qlcnic_alloc_lb_filters_mem(adapter); 1712 qlcnic_pf_set_interface_id_promisc(adapter, interface_id); 1713 adapter->rx_mac_learn = true; 1714 } else { 1715 if (!qlcnic_sriov_vf_check(adapter)) 1716 *interface_id = adapter->recv_ctx->context_id << 16; 1717 } 1718} 1719 1720int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) 1721{ 1722 struct qlcnic_cmd_args *cmd = NULL; 1723 u32 temp = 0; 1724 int err; 1725 1726 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 1727 return -EIO; 1728 1729 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); 1730 if (!cmd) 1731 return -ENOMEM; 1732 1733 err = qlcnic_alloc_mbx_args(cmd, adapter, 1734 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE); 1735 if (err) 1736 goto out; 1737 1738 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; 1739 qlcnic_83xx_set_interface_id_promisc(adapter, &temp); 1740 1741 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter)) 1742 mode = VPORT_MISS_MODE_ACCEPT_ALL; 1743 1744 cmd->req.arg[1] = mode | temp; 1745 err = qlcnic_issue_cmd(adapter, cmd); 1746 if (!err) 1747 return err; 1748 1749 qlcnic_free_mbx_args(cmd); 1750 1751out: 1752 kfree(cmd); 1753 return err; 1754} 1755 1756int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode) 1757{ 1758 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1759 struct qlcnic_hardware_context *ahw = adapter->ahw; 1760 u8 drv_sds_rings = adapter->drv_sds_rings; 1761 u8 drv_tx_rings = adapter->drv_tx_rings; 1762 int ret = 0, loop = 0; 1763 1764 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { 1765 netdev_warn(netdev, 1766 "Loopback test not supported in non privileged mode\n"); 1767 return -ENOTSUPP; 1768 } 1769 1770 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1771 netdev_info(netdev, "Device is resetting\n"); 1772 return -EBUSY; 1773 } 1774 1775 if (qlcnic_get_diag_lock(adapter)) { 1776 netdev_info(netdev, "Device is in diagnostics mode\n"); 1777 return -EBUSY; 1778 } 1779 1780 netdev_info(netdev, "%s loopback test in progress\n", 1781 mode == QLCNIC_ILB_MODE ? "internal" : "external"); 1782 1783 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST, 1784 drv_sds_rings); 1785 if (ret) 1786 goto fail_diag_alloc; 1787 1788 ret = qlcnic_83xx_set_lb_mode(adapter, mode); 1789 if (ret) 1790 goto free_diag_res; 1791 1792 /* Poll for link up event before running traffic */ 1793 do { 1794 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1795 1796 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1797 netdev_info(netdev, 1798 "Device is resetting, free LB test resources\n"); 1799 ret = -EBUSY; 1800 goto free_diag_res; 1801 } 1802 if (loop++ > QLC_83XX_LB_WAIT_COUNT) { 1803 netdev_info(netdev, 1804 "Firmware didn't sent link up event to loopback request\n"); 1805 ret = -ETIMEDOUT; 1806 qlcnic_83xx_clear_lb_mode(adapter, mode); 1807 goto free_diag_res; 1808 } 1809 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1); 1810 1811 ret = qlcnic_do_lb_test(adapter, mode); 1812 1813 qlcnic_83xx_clear_lb_mode(adapter, mode); 1814 1815free_diag_res: 1816 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings); 1817 1818fail_diag_alloc: 1819 adapter->drv_sds_rings = drv_sds_rings; 1820 adapter->drv_tx_rings = drv_tx_rings; 1821 qlcnic_release_diag_lock(adapter); 1822 return ret; 1823} 1824 1825static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter, 1826 u32 *max_wait_count) 1827{ 1828 struct qlcnic_hardware_context *ahw = adapter->ahw; 1829 int temp; 1830 1831 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n", 1832 ahw->extend_lb_time); 1833 temp = ahw->extend_lb_time * 1000; 1834 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT; 1835 ahw->extend_lb_time = 0; 1836} 1837 1838static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1839{ 1840 struct qlcnic_hardware_context *ahw = adapter->ahw; 1841 struct net_device *netdev = adapter->netdev; 1842 u32 config, max_wait_count; 1843 int status = 0, loop = 0; 1844 1845 ahw->extend_lb_time = 0; 1846 max_wait_count = QLC_83XX_LB_WAIT_COUNT; 1847 status = qlcnic_83xx_get_port_config(adapter); 1848 if (status) 1849 return status; 1850 1851 config = ahw->port_config; 1852 1853 /* Check if port is already in loopback mode */ 1854 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) || 1855 (config & QLC_83XX_CFG_LOOPBACK_EXT)) { 1856 netdev_err(netdev, 1857 "Port already in Loopback mode.\n"); 1858 return -EINPROGRESS; 1859 } 1860 1861 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1862 1863 if (mode == QLCNIC_ILB_MODE) 1864 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS; 1865 if (mode == QLCNIC_ELB_MODE) 1866 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT; 1867 1868 status = qlcnic_83xx_set_port_config(adapter); 1869 if (status) { 1870 netdev_err(netdev, 1871 "Failed to Set Loopback Mode = 0x%x.\n", 1872 ahw->port_config); 1873 ahw->port_config = config; 1874 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1875 return status; 1876 } 1877 1878 /* Wait for Link and IDC Completion AEN */ 1879 do { 1880 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1881 1882 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1883 netdev_info(netdev, 1884 "Device is resetting, free LB test resources\n"); 1885 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1886 return -EBUSY; 1887 } 1888 1889 if (ahw->extend_lb_time) 1890 qlcnic_extend_lb_idc_cmpltn_wait(adapter, 1891 &max_wait_count); 1892 1893 if (loop++ > max_wait_count) { 1894 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", 1895 __func__); 1896 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1897 qlcnic_83xx_clear_lb_mode(adapter, mode); 1898 return -ETIMEDOUT; 1899 } 1900 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); 1901 1902 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, 1903 QLCNIC_MAC_ADD); 1904 return status; 1905} 1906 1907static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 1908{ 1909 struct qlcnic_hardware_context *ahw = adapter->ahw; 1910 u32 config = ahw->port_config, max_wait_count; 1911 struct net_device *netdev = adapter->netdev; 1912 int status = 0, loop = 0; 1913 1914 ahw->extend_lb_time = 0; 1915 max_wait_count = QLC_83XX_LB_WAIT_COUNT; 1916 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1917 if (mode == QLCNIC_ILB_MODE) 1918 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS; 1919 if (mode == QLCNIC_ELB_MODE) 1920 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT; 1921 1922 status = qlcnic_83xx_set_port_config(adapter); 1923 if (status) { 1924 netdev_err(netdev, 1925 "Failed to Clear Loopback Mode = 0x%x.\n", 1926 ahw->port_config); 1927 ahw->port_config = config; 1928 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1929 return status; 1930 } 1931 1932 /* Wait for Link and IDC Completion AEN */ 1933 do { 1934 msleep(QLC_83XX_LB_MSLEEP_COUNT); 1935 1936 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 1937 netdev_info(netdev, 1938 "Device is resetting, free LB test resources\n"); 1939 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1940 return -EBUSY; 1941 } 1942 1943 if (ahw->extend_lb_time) 1944 qlcnic_extend_lb_idc_cmpltn_wait(adapter, 1945 &max_wait_count); 1946 1947 if (loop++ > max_wait_count) { 1948 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", 1949 __func__); 1950 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); 1951 return -ETIMEDOUT; 1952 } 1953 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); 1954 1955 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, 1956 QLCNIC_MAC_DEL); 1957 return status; 1958} 1959 1960static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter, 1961 u32 *interface_id) 1962{ 1963 if (qlcnic_sriov_pf_check(adapter)) { 1964 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id); 1965 } else { 1966 if (!qlcnic_sriov_vf_check(adapter)) 1967 *interface_id = adapter->recv_ctx->context_id << 16; 1968 } 1969} 1970 1971void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, 1972 int mode) 1973{ 1974 int err; 1975 u32 temp = 0, temp_ip; 1976 struct qlcnic_cmd_args cmd; 1977 1978 err = qlcnic_alloc_mbx_args(&cmd, adapter, 1979 QLCNIC_CMD_CONFIGURE_IP_ADDR); 1980 if (err) 1981 return; 1982 1983 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp); 1984 1985 if (mode == QLCNIC_IP_UP) 1986 cmd.req.arg[1] = 1 | temp; 1987 else 1988 cmd.req.arg[1] = 2 | temp; 1989 1990 /* 1991 * Adapter needs IP address in network byte order. 1992 * But hardware mailbox registers go through writel(), hence IP address 1993 * gets swapped on big endian architecture. 1994 * To negate swapping of writel() on big endian architecture 1995 * use swab32(value). 1996 */ 1997 1998 temp_ip = swab32(ntohl(ip)); 1999 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32)); 2000 err = qlcnic_issue_cmd(adapter, &cmd); 2001 if (err != QLCNIC_RCODE_SUCCESS) 2002 dev_err(&adapter->netdev->dev, 2003 "could not notify %s IP 0x%x request\n", 2004 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip); 2005 2006 qlcnic_free_mbx_args(&cmd); 2007} 2008 2009int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode) 2010{ 2011 int err; 2012 u32 temp, arg1; 2013 struct qlcnic_cmd_args cmd; 2014 int lro_bit_mask; 2015 2016 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); 2017 2018 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 2019 return 0; 2020 2021 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO); 2022 if (err) 2023 return err; 2024 2025 temp = adapter->recv_ctx->context_id << 16; 2026 arg1 = lro_bit_mask | temp; 2027 cmd.req.arg[1] = arg1; 2028 2029 err = qlcnic_issue_cmd(adapter, &cmd); 2030 if (err) 2031 dev_info(&adapter->pdev->dev, "LRO config failed\n"); 2032 qlcnic_free_mbx_args(&cmd); 2033 2034 return err; 2035} 2036 2037int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable) 2038{ 2039 int err; 2040 u32 word; 2041 struct qlcnic_cmd_args cmd; 2042 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 2043 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 2044 0x255b0ec26d5a56daULL }; 2045 2046 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS); 2047 if (err) 2048 return err; 2049 /* 2050 * RSS request: 2051 * bits 3-0: Rsvd 2052 * 5-4: hash_type_ipv4 2053 * 7-6: hash_type_ipv6 2054 * 8: enable 2055 * 9: use indirection table 2056 * 16-31: indirection table mask 2057 */ 2058 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 2059 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 2060 ((u32)(enable & 0x1) << 8) | 2061 ((0x7ULL) << 16); 2062 cmd.req.arg[1] = (adapter->recv_ctx->context_id); 2063 cmd.req.arg[2] = word; 2064 memcpy(&cmd.req.arg[4], key, sizeof(key)); 2065 2066 err = qlcnic_issue_cmd(adapter, &cmd); 2067 2068 if (err) 2069 dev_info(&adapter->pdev->dev, "RSS config failed\n"); 2070 qlcnic_free_mbx_args(&cmd); 2071 2072 return err; 2073 2074} 2075 2076static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter, 2077 u32 *interface_id) 2078{ 2079 if (qlcnic_sriov_pf_check(adapter)) { 2080 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id); 2081 } else { 2082 if (!qlcnic_sriov_vf_check(adapter)) 2083 *interface_id = adapter->recv_ctx->context_id << 16; 2084 } 2085} 2086 2087int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, 2088 u16 vlan_id, u8 op) 2089{ 2090 struct qlcnic_cmd_args *cmd = NULL; 2091 struct qlcnic_macvlan_mbx mv; 2092 u32 *buf, temp = 0; 2093 int err; 2094 2095 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 2096 return -EIO; 2097 2098 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); 2099 if (!cmd) 2100 return -ENOMEM; 2101 2102 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN); 2103 if (err) 2104 goto out; 2105 2106 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; 2107 2108 if (vlan_id) 2109 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ? 2110 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL; 2111 2112 cmd->req.arg[1] = op | (1 << 8); 2113 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp); 2114 cmd->req.arg[1] |= temp; 2115 mv.vlan = vlan_id; 2116 mv.mac_addr0 = addr[0]; 2117 mv.mac_addr1 = addr[1]; 2118 mv.mac_addr2 = addr[2]; 2119 mv.mac_addr3 = addr[3]; 2120 mv.mac_addr4 = addr[4]; 2121 mv.mac_addr5 = addr[5]; 2122 buf = &cmd->req.arg[2]; 2123 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx)); 2124 err = qlcnic_issue_cmd(adapter, cmd); 2125 if (!err) 2126 return err; 2127 2128 qlcnic_free_mbx_args(cmd); 2129out: 2130 kfree(cmd); 2131 return err; 2132} 2133 2134void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr, 2135 u16 vlan_id) 2136{ 2137 u8 mac[ETH_ALEN]; 2138 memcpy(&mac, addr, ETH_ALEN); 2139 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD); 2140} 2141 2142static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac, 2143 u8 type, struct qlcnic_cmd_args *cmd) 2144{ 2145 switch (type) { 2146 case QLCNIC_SET_STATION_MAC: 2147 case QLCNIC_SET_FAC_DEF_MAC: 2148 memcpy(&cmd->req.arg[2], mac, sizeof(u32)); 2149 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16)); 2150 break; 2151 } 2152 cmd->req.arg[1] = type; 2153} 2154 2155int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac, 2156 u8 function) 2157{ 2158 int err, i; 2159 struct qlcnic_cmd_args cmd; 2160 u32 mac_low, mac_high; 2161 2162 function = 0; 2163 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS); 2164 if (err) 2165 return err; 2166 2167 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd); 2168 err = qlcnic_issue_cmd(adapter, &cmd); 2169 2170 if (err == QLCNIC_RCODE_SUCCESS) { 2171 mac_low = cmd.rsp.arg[1]; 2172 mac_high = cmd.rsp.arg[2]; 2173 2174 for (i = 0; i < 2; i++) 2175 mac[i] = (u8) (mac_high >> ((1 - i) * 8)); 2176 for (i = 2; i < 6; i++) 2177 mac[i] = (u8) (mac_low >> ((5 - i) * 8)); 2178 } else { 2179 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n", 2180 err); 2181 err = -EIO; 2182 } 2183 qlcnic_free_mbx_args(&cmd); 2184 return err; 2185} 2186 2187static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter) 2188{ 2189 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2190 struct qlcnic_cmd_args cmd; 2191 u16 temp; 2192 int err; 2193 2194 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL); 2195 if (err) 2196 return err; 2197 2198 temp = adapter->recv_ctx->context_id; 2199 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16; 2200 temp = coal->rx_time_us; 2201 cmd.req.arg[2] = coal->rx_packets | temp << 16; 2202 cmd.req.arg[3] = coal->flag; 2203 2204 err = qlcnic_issue_cmd(adapter, &cmd); 2205 if (err != QLCNIC_RCODE_SUCCESS) 2206 netdev_err(adapter->netdev, 2207 "failed to set interrupt coalescing parameters\n"); 2208 2209 qlcnic_free_mbx_args(&cmd); 2210 2211 return err; 2212} 2213 2214static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter) 2215{ 2216 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2217 struct qlcnic_cmd_args cmd; 2218 u16 temp; 2219 int err; 2220 2221 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL); 2222 if (err) 2223 return err; 2224 2225 temp = adapter->tx_ring->ctx_id; 2226 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16; 2227 temp = coal->tx_time_us; 2228 cmd.req.arg[2] = coal->tx_packets | temp << 16; 2229 cmd.req.arg[3] = coal->flag; 2230 2231 err = qlcnic_issue_cmd(adapter, &cmd); 2232 if (err != QLCNIC_RCODE_SUCCESS) 2233 netdev_err(adapter->netdev, 2234 "failed to set interrupt coalescing parameters\n"); 2235 2236 qlcnic_free_mbx_args(&cmd); 2237 2238 return err; 2239} 2240 2241int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter) 2242{ 2243 int err = 0; 2244 2245 err = qlcnic_83xx_set_rx_intr_coal(adapter); 2246 if (err) 2247 netdev_err(adapter->netdev, 2248 "failed to set Rx coalescing parameters\n"); 2249 2250 err = qlcnic_83xx_set_tx_intr_coal(adapter); 2251 if (err) 2252 netdev_err(adapter->netdev, 2253 "failed to set Tx coalescing parameters\n"); 2254 2255 return err; 2256} 2257 2258int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter, 2259 struct ethtool_coalesce *ethcoal) 2260{ 2261 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; 2262 u32 rx_coalesce_usecs, rx_max_frames; 2263 u32 tx_coalesce_usecs, tx_max_frames; 2264 int err; 2265 2266 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) 2267 return -EIO; 2268 2269 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs; 2270 tx_max_frames = ethcoal->tx_max_coalesced_frames; 2271 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs; 2272 rx_max_frames = ethcoal->rx_max_coalesced_frames; 2273 coal->flag = QLCNIC_INTR_DEFAULT; 2274 2275 if ((coal->rx_time_us == rx_coalesce_usecs) && 2276 (coal->rx_packets == rx_max_frames)) { 2277 coal->type = QLCNIC_INTR_COAL_TYPE_TX; 2278 coal->tx_time_us = tx_coalesce_usecs; 2279 coal->tx_packets = tx_max_frames; 2280 } else if ((coal->tx_time_us == tx_coalesce_usecs) && 2281 (coal->tx_packets == tx_max_frames)) { 2282 coal->type = QLCNIC_INTR_COAL_TYPE_RX; 2283 coal->rx_time_us = rx_coalesce_usecs; 2284 coal->rx_packets = rx_max_frames; 2285 } else { 2286 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX; 2287 coal->rx_time_us = rx_coalesce_usecs; 2288 coal->rx_packets = rx_max_frames; 2289 coal->tx_time_us = tx_coalesce_usecs; 2290 coal->tx_packets = tx_max_frames; 2291 } 2292 2293 switch (coal->type) { 2294 case QLCNIC_INTR_COAL_TYPE_RX: 2295 err = qlcnic_83xx_set_rx_intr_coal(adapter); 2296 break; 2297 case QLCNIC_INTR_COAL_TYPE_TX: 2298 err = qlcnic_83xx_set_tx_intr_coal(adapter); 2299 break; 2300 case QLCNIC_INTR_COAL_TYPE_RX_TX: 2301 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter); 2302 break; 2303 default: 2304 err = -EINVAL; 2305 netdev_err(adapter->netdev, 2306 "Invalid Interrupt coalescing type\n"); 2307 break; 2308 } 2309 2310 return err; 2311} 2312 2313static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, 2314 u32 data[]) 2315{ 2316 struct qlcnic_hardware_context *ahw = adapter->ahw; 2317 u8 link_status, duplex; 2318 /* link speed */ 2319 link_status = LSB(data[3]) & 1; 2320 if (link_status) { 2321 ahw->link_speed = MSW(data[2]); 2322 duplex = LSB(MSW(data[3])); 2323 if (duplex) 2324 ahw->link_duplex = DUPLEX_FULL; 2325 else 2326 ahw->link_duplex = DUPLEX_HALF; 2327 } else { 2328 ahw->link_speed = SPEED_UNKNOWN; 2329 ahw->link_duplex = DUPLEX_UNKNOWN; 2330 } 2331 2332 ahw->link_autoneg = MSB(MSW(data[3])); 2333 ahw->module_type = MSB(LSW(data[3])); 2334 ahw->has_link_events = 1; 2335 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK; 2336 qlcnic_advert_link_change(adapter, link_status); 2337} 2338 2339static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data) 2340{ 2341 struct qlcnic_adapter *adapter = data; 2342 struct qlcnic_mailbox *mbx; 2343 u32 mask, resp, event; 2344 unsigned long flags; 2345 2346 mbx = adapter->ahw->mailbox; 2347 spin_lock_irqsave(&mbx->aen_lock, flags); 2348 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); 2349 if (!(resp & QLCNIC_SET_OWNER)) 2350 goto out; 2351 2352 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); 2353 if (event & QLCNIC_MBX_ASYNC_EVENT) 2354 __qlcnic_83xx_process_aen(adapter); 2355 else 2356 qlcnic_83xx_notify_mbx_response(mbx); 2357 2358out: 2359 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); 2360 writel(0, adapter->ahw->pci_base0 + mask); 2361 spin_unlock_irqrestore(&mbx->aen_lock, flags); 2362 return IRQ_HANDLED; 2363} 2364 2365int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter, 2366 struct qlcnic_info *nic) 2367{ 2368 int i, err = -EIO; 2369 struct qlcnic_cmd_args cmd; 2370 2371 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) { 2372 dev_err(&adapter->pdev->dev, 2373 "%s: Error, invoked by non management func\n", 2374 __func__); 2375 return err; 2376 } 2377 2378 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO); 2379 if (err) 2380 return err; 2381 2382 cmd.req.arg[1] = (nic->pci_func << 16); 2383 cmd.req.arg[2] = 0x1 << 16; 2384 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16); 2385 cmd.req.arg[4] = nic->capabilities; 2386 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16); 2387 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16); 2388 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16); 2389 for (i = 8; i < 32; i++) 2390 cmd.req.arg[i] = 0; 2391 2392 err = qlcnic_issue_cmd(adapter, &cmd); 2393 2394 if (err != QLCNIC_RCODE_SUCCESS) { 2395 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n", 2396 err); 2397 err = -EIO; 2398 } 2399 2400 qlcnic_free_mbx_args(&cmd); 2401 2402 return err; 2403} 2404 2405int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter, 2406 struct qlcnic_info *npar_info, u8 func_id) 2407{ 2408 int err; 2409 u32 temp; 2410 u8 op = 0; 2411 struct qlcnic_cmd_args cmd; 2412 struct qlcnic_hardware_context *ahw = adapter->ahw; 2413 2414 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO); 2415 if (err) 2416 return err; 2417 2418 if (func_id != ahw->pci_func) { 2419 temp = func_id << 16; 2420 cmd.req.arg[1] = op | BIT_31 | temp; 2421 } else { 2422 cmd.req.arg[1] = ahw->pci_func << 16; 2423 } 2424 err = qlcnic_issue_cmd(adapter, &cmd); 2425 if (err) { 2426 dev_info(&adapter->pdev->dev, 2427 "Failed to get nic info %d\n", err); 2428 goto out; 2429 } 2430 2431 npar_info->op_type = cmd.rsp.arg[1]; 2432 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF; 2433 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16; 2434 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF; 2435 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16; 2436 npar_info->capabilities = cmd.rsp.arg[4]; 2437 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF; 2438 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16; 2439 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF; 2440 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16; 2441 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF; 2442 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16; 2443 if (cmd.rsp.arg[8] & 0x1) 2444 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1; 2445 if (cmd.rsp.arg[8] & 0x10000) { 2446 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17; 2447 npar_info->max_linkspeed_reg_offset = temp; 2448 } 2449 2450 memcpy(ahw->extra_capability, &cmd.rsp.arg[16], 2451 sizeof(ahw->extra_capability)); 2452 2453out: 2454 qlcnic_free_mbx_args(&cmd); 2455 return err; 2456} 2457 2458int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type, 2459 u16 *nic, u16 *fcoe, u16 *iscsi) 2460{ 2461 struct device *dev = &adapter->pdev->dev; 2462 int err = 0; 2463 2464 switch (type) { 2465 case QLCNIC_TYPE_NIC: 2466 (*nic)++; 2467 break; 2468 case QLCNIC_TYPE_FCOE: 2469 (*fcoe)++; 2470 break; 2471 case QLCNIC_TYPE_ISCSI: 2472 (*iscsi)++; 2473 break; 2474 default: 2475 dev_err(dev, "%s: Unknown PCI type[%x]\n", 2476 __func__, type); 2477 err = -EIO; 2478 } 2479 2480 return err; 2481} 2482 2483int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter, 2484 struct qlcnic_pci_info *pci_info) 2485{ 2486 struct qlcnic_hardware_context *ahw = adapter->ahw; 2487 struct device *dev = &adapter->pdev->dev; 2488 u16 nic = 0, fcoe = 0, iscsi = 0; 2489 struct qlcnic_cmd_args cmd; 2490 int i, err = 0, j = 0; 2491 u32 temp; 2492 2493 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO); 2494 if (err) 2495 return err; 2496 2497 err = qlcnic_issue_cmd(adapter, &cmd); 2498 2499 ahw->total_nic_func = 0; 2500 if (err == QLCNIC_RCODE_SUCCESS) { 2501 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF; 2502 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) { 2503 pci_info->id = cmd.rsp.arg[i] & 0xFFFF; 2504 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2505 i++; 2506 if (!pci_info->active) { 2507 i += QLC_SKIP_INACTIVE_PCI_REGS; 2508 continue; 2509 } 2510 pci_info->type = cmd.rsp.arg[i] & 0xFFFF; 2511 err = qlcnic_get_pci_func_type(adapter, pci_info->type, 2512 &nic, &fcoe, &iscsi); 2513 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2514 pci_info->default_port = temp; 2515 i++; 2516 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF; 2517 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; 2518 pci_info->tx_max_bw = temp; 2519 i = i + 2; 2520 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2); 2521 i++; 2522 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2); 2523 i = i + 3; 2524 } 2525 } else { 2526 dev_err(dev, "Failed to get PCI Info, error = %d\n", err); 2527 err = -EIO; 2528 } 2529 2530 ahw->total_nic_func = nic; 2531 ahw->total_pci_func = nic + fcoe + iscsi; 2532 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) { 2533 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n", 2534 __func__, ahw->total_nic_func, ahw->total_pci_func); 2535 err = -EIO; 2536 } 2537 qlcnic_free_mbx_args(&cmd); 2538 2539 return err; 2540} 2541 2542int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type) 2543{ 2544 int i, index, err; 2545 u8 max_ints; 2546 u32 val, temp, type; 2547 struct qlcnic_cmd_args cmd; 2548 2549 max_ints = adapter->ahw->num_msix - 1; 2550 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT); 2551 if (err) 2552 return err; 2553 2554 cmd.req.arg[1] = max_ints; 2555 2556 if (qlcnic_sriov_vf_check(adapter)) 2557 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16; 2558 2559 for (i = 0, index = 2; i < max_ints; i++) { 2560 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL; 2561 val = type | (adapter->ahw->intr_tbl[i].type << 4); 2562 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX) 2563 val |= (adapter->ahw->intr_tbl[i].id << 16); 2564 cmd.req.arg[index++] = val; 2565 } 2566 err = qlcnic_issue_cmd(adapter, &cmd); 2567 if (err) { 2568 dev_err(&adapter->pdev->dev, 2569 "Failed to configure interrupts 0x%x\n", err); 2570 goto out; 2571 } 2572 2573 max_ints = cmd.rsp.arg[1]; 2574 for (i = 0, index = 2; i < max_ints; i++, index += 2) { 2575 val = cmd.rsp.arg[index]; 2576 if (LSB(val)) { 2577 dev_info(&adapter->pdev->dev, 2578 "Can't configure interrupt %d\n", 2579 adapter->ahw->intr_tbl[i].id); 2580 continue; 2581 } 2582 if (op_type) { 2583 adapter->ahw->intr_tbl[i].id = MSW(val); 2584 adapter->ahw->intr_tbl[i].enabled = 1; 2585 temp = cmd.rsp.arg[index + 1]; 2586 adapter->ahw->intr_tbl[i].src = temp; 2587 } else { 2588 adapter->ahw->intr_tbl[i].id = i; 2589 adapter->ahw->intr_tbl[i].enabled = 0; 2590 adapter->ahw->intr_tbl[i].src = 0; 2591 } 2592 } 2593out: 2594 qlcnic_free_mbx_args(&cmd); 2595 return err; 2596} 2597 2598int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter) 2599{ 2600 int id, timeout = 0; 2601 u32 status = 0; 2602 2603 while (status == 0) { 2604 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK); 2605 if (status) 2606 break; 2607 2608 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) { 2609 id = QLC_SHARED_REG_RD32(adapter, 2610 QLCNIC_FLASH_LOCK_OWNER); 2611 dev_err(&adapter->pdev->dev, 2612 "%s: failed, lock held by %d\n", __func__, id); 2613 return -EIO; 2614 } 2615 usleep_range(1000, 2000); 2616 } 2617 2618 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum); 2619 return 0; 2620} 2621 2622void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter) 2623{ 2624 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK); 2625 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF); 2626} 2627 2628int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, 2629 u32 flash_addr, u8 *p_data, 2630 int count) 2631{ 2632 u32 word, range, flash_offset, addr = flash_addr, ret; 2633 ulong indirect_add, direct_window; 2634 int i, err = 0; 2635 2636 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1); 2637 if (addr & 0x3) { 2638 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); 2639 return -EIO; 2640 } 2641 2642 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW, 2643 (addr & 0xFFFF0000)); 2644 2645 range = flash_offset + (count * sizeof(u32)); 2646 /* Check if data is spread across multiple sectors */ 2647 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { 2648 2649 /* Multi sector read */ 2650 for (i = 0; i < count; i++) { 2651 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); 2652 ret = QLCRD32(adapter, indirect_add, &err); 2653 if (err == -EIO) 2654 return err; 2655 2656 word = ret; 2657 *(u32 *)p_data = word; 2658 p_data = p_data + 4; 2659 addr = addr + 4; 2660 flash_offset = flash_offset + 4; 2661 2662 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { 2663 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW; 2664 /* This write is needed once for each sector */ 2665 qlcnic_83xx_wrt_reg_indirect(adapter, 2666 direct_window, 2667 (addr)); 2668 flash_offset = 0; 2669 } 2670 } 2671 } else { 2672 /* Single sector read */ 2673 for (i = 0; i < count; i++) { 2674 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); 2675 ret = QLCRD32(adapter, indirect_add, &err); 2676 if (err == -EIO) 2677 return err; 2678 2679 word = ret; 2680 *(u32 *)p_data = word; 2681 p_data = p_data + 4; 2682 addr = addr + 4; 2683 } 2684 } 2685 2686 return 0; 2687} 2688 2689static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter) 2690{ 2691 u32 status; 2692 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT; 2693 int err = 0; 2694 2695 do { 2696 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err); 2697 if (err == -EIO) 2698 return err; 2699 2700 if ((status & QLC_83XX_FLASH_STATUS_READY) == 2701 QLC_83XX_FLASH_STATUS_READY) 2702 break; 2703 2704 usleep_range(1000, 1100); 2705 } while (--retries); 2706 2707 if (!retries) 2708 return -EIO; 2709 2710 return 0; 2711} 2712 2713int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter) 2714{ 2715 int ret; 2716 u32 cmd; 2717 cmd = adapter->ahw->fdt.write_statusreg_cmd; 2718 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2719 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd)); 2720 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2721 adapter->ahw->fdt.write_enable_bits); 2722 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2723 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); 2724 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2725 if (ret) 2726 return -EIO; 2727 2728 return 0; 2729} 2730 2731int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter) 2732{ 2733 int ret; 2734 2735 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2736 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | 2737 adapter->ahw->fdt.write_statusreg_cmd)); 2738 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2739 adapter->ahw->fdt.write_disable_bits); 2740 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2741 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); 2742 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2743 if (ret) 2744 return -EIO; 2745 2746 return 0; 2747} 2748 2749int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter) 2750{ 2751 int ret, err = 0; 2752 u32 mfg_id; 2753 2754 if (qlcnic_83xx_lock_flash(adapter)) 2755 return -EIO; 2756 2757 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2758 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL); 2759 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2760 QLC_83XX_FLASH_READ_CTRL); 2761 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2762 if (ret) { 2763 qlcnic_83xx_unlock_flash(adapter); 2764 return -EIO; 2765 } 2766 2767 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); 2768 if (err == -EIO) { 2769 qlcnic_83xx_unlock_flash(adapter); 2770 return err; 2771 } 2772 2773 adapter->flash_mfg_id = (mfg_id & 0xFF); 2774 qlcnic_83xx_unlock_flash(adapter); 2775 2776 return 0; 2777} 2778 2779int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter) 2780{ 2781 int count, fdt_size, ret = 0; 2782 2783 fdt_size = sizeof(struct qlcnic_fdt); 2784 count = fdt_size / sizeof(u32); 2785 2786 if (qlcnic_83xx_lock_flash(adapter)) 2787 return -EIO; 2788 2789 memset(&adapter->ahw->fdt, 0, fdt_size); 2790 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION, 2791 (u8 *)&adapter->ahw->fdt, 2792 count); 2793 qlcnic_swap32_buffer((u32 *)&adapter->ahw->fdt, count); 2794 qlcnic_83xx_unlock_flash(adapter); 2795 return ret; 2796} 2797 2798int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter, 2799 u32 sector_start_addr) 2800{ 2801 u32 reversed_addr, addr1, addr2, cmd; 2802 int ret = -EIO; 2803 2804 if (qlcnic_83xx_lock_flash(adapter) != 0) 2805 return -EIO; 2806 2807 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { 2808 ret = qlcnic_83xx_enable_flash_write(adapter); 2809 if (ret) { 2810 qlcnic_83xx_unlock_flash(adapter); 2811 dev_err(&adapter->pdev->dev, 2812 "%s failed at %d\n", 2813 __func__, __LINE__); 2814 return ret; 2815 } 2816 } 2817 2818 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2819 if (ret) { 2820 qlcnic_83xx_unlock_flash(adapter); 2821 dev_err(&adapter->pdev->dev, 2822 "%s: failed at %d\n", __func__, __LINE__); 2823 return -EIO; 2824 } 2825 2826 addr1 = (sector_start_addr & 0xFF) << 16; 2827 addr2 = (sector_start_addr & 0xFF0000) >> 16; 2828 reversed_addr = addr1 | addr2 | (sector_start_addr & 0xFF00); 2829 2830 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2831 reversed_addr); 2832 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd; 2833 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) 2834 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd); 2835 else 2836 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2837 QLC_83XX_FLASH_OEM_ERASE_SIG); 2838 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2839 QLC_83XX_FLASH_LAST_ERASE_MS_VAL); 2840 2841 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2842 if (ret) { 2843 qlcnic_83xx_unlock_flash(adapter); 2844 dev_err(&adapter->pdev->dev, 2845 "%s: failed at %d\n", __func__, __LINE__); 2846 return -EIO; 2847 } 2848 2849 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { 2850 ret = qlcnic_83xx_disable_flash_write(adapter); 2851 if (ret) { 2852 qlcnic_83xx_unlock_flash(adapter); 2853 dev_err(&adapter->pdev->dev, 2854 "%s: failed at %d\n", __func__, __LINE__); 2855 return ret; 2856 } 2857 } 2858 2859 qlcnic_83xx_unlock_flash(adapter); 2860 2861 return 0; 2862} 2863 2864int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr, 2865 u32 *p_data) 2866{ 2867 int ret = -EIO; 2868 u32 addr1 = 0x00800000 | (addr >> 2); 2869 2870 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1); 2871 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data); 2872 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2873 QLC_83XX_FLASH_LAST_ERASE_MS_VAL); 2874 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2875 if (ret) { 2876 dev_err(&adapter->pdev->dev, 2877 "%s: failed at %d\n", __func__, __LINE__); 2878 return -EIO; 2879 } 2880 2881 return 0; 2882} 2883 2884int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, 2885 u32 *p_data, int count) 2886{ 2887 u32 temp; 2888 int ret = -EIO, err = 0; 2889 2890 if ((count < QLC_83XX_FLASH_WRITE_MIN) || 2891 (count > QLC_83XX_FLASH_WRITE_MAX)) { 2892 dev_err(&adapter->pdev->dev, 2893 "%s: Invalid word count\n", __func__); 2894 return -EIO; 2895 } 2896 2897 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); 2898 if (err == -EIO) 2899 return err; 2900 2901 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL, 2902 (temp | QLC_83XX_FLASH_SPI_CTRL)); 2903 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2904 QLC_83XX_FLASH_ADDR_TEMP_VAL); 2905 2906 /* First DWORD write */ 2907 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); 2908 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2909 QLC_83XX_FLASH_FIRST_MS_PATTERN); 2910 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2911 if (ret) { 2912 dev_err(&adapter->pdev->dev, 2913 "%s: failed at %d\n", __func__, __LINE__); 2914 return -EIO; 2915 } 2916 2917 count--; 2918 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2919 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL); 2920 /* Second to N-1 DWORD writes */ 2921 while (count != 1) { 2922 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, 2923 *p_data++); 2924 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2925 QLC_83XX_FLASH_SECOND_MS_PATTERN); 2926 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2927 if (ret) { 2928 dev_err(&adapter->pdev->dev, 2929 "%s: failed at %d\n", __func__, __LINE__); 2930 return -EIO; 2931 } 2932 count--; 2933 } 2934 2935 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 2936 QLC_83XX_FLASH_ADDR_TEMP_VAL | 2937 (addr >> 2)); 2938 /* Last DWORD write */ 2939 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); 2940 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 2941 QLC_83XX_FLASH_LAST_MS_PATTERN); 2942 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 2943 if (ret) { 2944 dev_err(&adapter->pdev->dev, 2945 "%s: failed at %d\n", __func__, __LINE__); 2946 return -EIO; 2947 } 2948 2949 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err); 2950 if (err == -EIO) 2951 return err; 2952 2953 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) { 2954 dev_err(&adapter->pdev->dev, "%s: failed at %d\n", 2955 __func__, __LINE__); 2956 /* Operation failed, clear error bit */ 2957 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); 2958 if (err == -EIO) 2959 return err; 2960 2961 qlcnic_83xx_wrt_reg_indirect(adapter, 2962 QLC_83XX_FLASH_SPI_CONTROL, 2963 (temp | QLC_83XX_FLASH_SPI_CTRL)); 2964 } 2965 2966 return 0; 2967} 2968 2969static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter) 2970{ 2971 u32 val, id; 2972 2973 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); 2974 2975 /* Check if recovery need to be performed by the calling function */ 2976 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) { 2977 val = val & ~0x3F; 2978 val = val | ((adapter->portnum << 2) | 2979 QLC_83XX_NEED_DRV_LOCK_RECOVERY); 2980 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2981 dev_info(&adapter->pdev->dev, 2982 "%s: lock recovery initiated\n", __func__); 2983 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY); 2984 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); 2985 id = ((val >> 2) & 0xF); 2986 if (id == adapter->portnum) { 2987 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK; 2988 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS; 2989 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2990 /* Force release the lock */ 2991 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); 2992 /* Clear recovery bits */ 2993 val = val & ~0x3F; 2994 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); 2995 dev_info(&adapter->pdev->dev, 2996 "%s: lock recovery completed\n", __func__); 2997 } else { 2998 dev_info(&adapter->pdev->dev, 2999 "%s: func %d to resume lock recovery process\n", 3000 __func__, id); 3001 } 3002 } else { 3003 dev_info(&adapter->pdev->dev, 3004 "%s: lock recovery initiated by other functions\n", 3005 __func__); 3006 } 3007} 3008 3009int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter) 3010{ 3011 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0; 3012 int max_attempt = 0; 3013 3014 while (status == 0) { 3015 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK); 3016 if (status) 3017 break; 3018 3019 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY); 3020 i++; 3021 3022 if (i == 1) 3023 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 3024 3025 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) { 3026 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 3027 if (val == temp) { 3028 id = val & 0xFF; 3029 dev_info(&adapter->pdev->dev, 3030 "%s: lock to be recovered from %d\n", 3031 __func__, id); 3032 qlcnic_83xx_recover_driver_lock(adapter); 3033 i = 0; 3034 max_attempt++; 3035 } else { 3036 dev_err(&adapter->pdev->dev, 3037 "%s: failed to get lock\n", __func__); 3038 return -EIO; 3039 } 3040 } 3041 3042 /* Force exit from while loop after few attempts */ 3043 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) { 3044 dev_err(&adapter->pdev->dev, 3045 "%s: failed to get lock\n", __func__); 3046 return -EIO; 3047 } 3048 } 3049 3050 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 3051 lock_alive_counter = val >> 8; 3052 lock_alive_counter++; 3053 val = lock_alive_counter << 8 | adapter->portnum; 3054 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); 3055 3056 return 0; 3057} 3058 3059void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter) 3060{ 3061 u32 val, lock_alive_counter, id; 3062 3063 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); 3064 id = val & 0xFF; 3065 lock_alive_counter = val >> 8; 3066 3067 if (id != adapter->portnum) 3068 dev_err(&adapter->pdev->dev, 3069 "%s:Warning func %d is unlocking lock owned by %d\n", 3070 __func__, adapter->portnum, id); 3071 3072 val = (lock_alive_counter << 8) | 0xFF; 3073 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); 3074 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); 3075} 3076 3077int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, 3078 u32 *data, u32 count) 3079{ 3080 int i, j, ret = 0; 3081 u32 temp; 3082 3083 /* Check alignment */ 3084 if (addr & 0xF) 3085 return -EIO; 3086 3087 mutex_lock(&adapter->ahw->mem_lock); 3088 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0); 3089 3090 for (i = 0; i < count; i++, addr += 16) { 3091 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET, 3092 QLCNIC_ADDR_QDR_NET_MAX)) || 3093 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET, 3094 QLCNIC_ADDR_DDR_NET_MAX)))) { 3095 mutex_unlock(&adapter->ahw->mem_lock); 3096 return -EIO; 3097 } 3098 3099 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr); 3100 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++); 3101 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++); 3102 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++); 3103 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++); 3104 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE); 3105 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START); 3106 3107 for (j = 0; j < MAX_CTL_CHECK; j++) { 3108 temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL); 3109 3110 if ((temp & TA_CTL_BUSY) == 0) 3111 break; 3112 } 3113 3114 /* Status check failure */ 3115 if (j >= MAX_CTL_CHECK) { 3116 printk_ratelimited(KERN_WARNING 3117 "MS memory write failed\n"); 3118 mutex_unlock(&adapter->ahw->mem_lock); 3119 return -EIO; 3120 } 3121 } 3122 3123 mutex_unlock(&adapter->ahw->mem_lock); 3124 3125 return ret; 3126} 3127 3128int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr, 3129 u8 *p_data, int count) 3130{ 3131 u32 word, addr = flash_addr, ret; 3132 ulong indirect_addr; 3133 int i, err = 0; 3134 3135 if (qlcnic_83xx_lock_flash(adapter) != 0) 3136 return -EIO; 3137 3138 if (addr & 0x3) { 3139 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); 3140 qlcnic_83xx_unlock_flash(adapter); 3141 return -EIO; 3142 } 3143 3144 for (i = 0; i < count; i++) { 3145 if (qlcnic_83xx_wrt_reg_indirect(adapter, 3146 QLC_83XX_FLASH_DIRECT_WINDOW, 3147 (addr))) { 3148 qlcnic_83xx_unlock_flash(adapter); 3149 return -EIO; 3150 } 3151 3152 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr); 3153 ret = QLCRD32(adapter, indirect_addr, &err); 3154 if (err == -EIO) 3155 return err; 3156 3157 word = ret; 3158 *(u32 *)p_data = word; 3159 p_data = p_data + 4; 3160 addr = addr + 4; 3161 } 3162 3163 qlcnic_83xx_unlock_flash(adapter); 3164 3165 return 0; 3166} 3167 3168int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter) 3169{ 3170 u8 pci_func; 3171 int err; 3172 u32 config = 0, state; 3173 struct qlcnic_cmd_args cmd; 3174 struct qlcnic_hardware_context *ahw = adapter->ahw; 3175 3176 if (qlcnic_sriov_vf_check(adapter)) 3177 pci_func = adapter->portnum; 3178 else 3179 pci_func = ahw->pci_func; 3180 3181 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func)); 3182 if (!QLC_83xx_FUNC_VAL(state, pci_func)) { 3183 dev_info(&adapter->pdev->dev, "link state down\n"); 3184 return config; 3185 } 3186 3187 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS); 3188 if (err) 3189 return err; 3190 3191 err = qlcnic_issue_cmd(adapter, &cmd); 3192 if (err) { 3193 dev_info(&adapter->pdev->dev, 3194 "Get Link Status Command failed: 0x%x\n", err); 3195 goto out; 3196 } else { 3197 config = cmd.rsp.arg[1]; 3198 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) { 3199 case QLC_83XX_10M_LINK: 3200 ahw->link_speed = SPEED_10; 3201 break; 3202 case QLC_83XX_100M_LINK: 3203 ahw->link_speed = SPEED_100; 3204 break; 3205 case QLC_83XX_1G_LINK: 3206 ahw->link_speed = SPEED_1000; 3207 break; 3208 case QLC_83XX_10G_LINK: 3209 ahw->link_speed = SPEED_10000; 3210 break; 3211 default: 3212 ahw->link_speed = 0; 3213 break; 3214 } 3215 config = cmd.rsp.arg[3]; 3216 switch (QLC_83XX_SFP_MODULE_TYPE(config)) { 3217 case QLC_83XX_MODULE_FIBRE_10GBASE_LRM: 3218 case QLC_83XX_MODULE_FIBRE_10GBASE_LR: 3219 case QLC_83XX_MODULE_FIBRE_10GBASE_SR: 3220 ahw->supported_type = PORT_FIBRE; 3221 ahw->port_type = QLCNIC_XGBE; 3222 break; 3223 case QLC_83XX_MODULE_FIBRE_1000BASE_SX: 3224 case QLC_83XX_MODULE_FIBRE_1000BASE_LX: 3225 case QLC_83XX_MODULE_FIBRE_1000BASE_CX: 3226 ahw->supported_type = PORT_FIBRE; 3227 ahw->port_type = QLCNIC_GBE; 3228 break; 3229 case QLC_83XX_MODULE_TP_1000BASE_T: 3230 ahw->supported_type = PORT_TP; 3231 ahw->port_type = QLCNIC_GBE; 3232 break; 3233 case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP: 3234 case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP: 3235 case QLC_83XX_MODULE_DA_10GE_LEGACY_CP: 3236 case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP: 3237 ahw->supported_type = PORT_DA; 3238 ahw->port_type = QLCNIC_XGBE; 3239 break; 3240 default: 3241 ahw->supported_type = PORT_OTHER; 3242 ahw->port_type = QLCNIC_XGBE; 3243 } 3244 if (config & 1) 3245 err = 1; 3246 } 3247out: 3248 qlcnic_free_mbx_args(&cmd); 3249 return config; 3250} 3251 3252int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter, 3253 struct ethtool_cmd *ecmd) 3254{ 3255 struct qlcnic_hardware_context *ahw = adapter->ahw; 3256 u32 config = 0; 3257 int status = 0; 3258 3259 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) { 3260 /* Get port configuration info */ 3261 status = qlcnic_83xx_get_port_info(adapter); 3262 /* Get Link Status related info */ 3263 config = qlcnic_83xx_test_link(adapter); 3264 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config); 3265 } 3266 3267 /* hard code until there is a way to get it from flash */ 3268 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G; 3269 3270 if (netif_running(adapter->netdev) && ahw->has_link_events) { 3271 ethtool_cmd_speed_set(ecmd, ahw->link_speed); 3272 ecmd->duplex = ahw->link_duplex; 3273 ecmd->autoneg = ahw->link_autoneg; 3274 } else { 3275 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); 3276 ecmd->duplex = DUPLEX_UNKNOWN; 3277 ecmd->autoneg = AUTONEG_DISABLE; 3278 } 3279 3280 ecmd->supported = (SUPPORTED_10baseT_Full | 3281 SUPPORTED_100baseT_Full | 3282 SUPPORTED_1000baseT_Full | 3283 SUPPORTED_10000baseT_Full | 3284 SUPPORTED_Autoneg); 3285 3286 if (ecmd->autoneg == AUTONEG_ENABLE) { 3287 if (ahw->port_config & QLC_83XX_10_CAPABLE) 3288 ecmd->advertising |= SUPPORTED_10baseT_Full; 3289 if (ahw->port_config & QLC_83XX_100_CAPABLE) 3290 ecmd->advertising |= SUPPORTED_100baseT_Full; 3291 if (ahw->port_config & QLC_83XX_1G_CAPABLE) 3292 ecmd->advertising |= SUPPORTED_1000baseT_Full; 3293 if (ahw->port_config & QLC_83XX_10G_CAPABLE) 3294 ecmd->advertising |= SUPPORTED_10000baseT_Full; 3295 if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE) 3296 ecmd->advertising |= ADVERTISED_Autoneg; 3297 } else { 3298 switch (ahw->link_speed) { 3299 case SPEED_10: 3300 ecmd->advertising = SUPPORTED_10baseT_Full; 3301 break; 3302 case SPEED_100: 3303 ecmd->advertising = SUPPORTED_100baseT_Full; 3304 break; 3305 case SPEED_1000: 3306 ecmd->advertising = SUPPORTED_1000baseT_Full; 3307 break; 3308 case SPEED_10000: 3309 ecmd->advertising = SUPPORTED_10000baseT_Full; 3310 break; 3311 default: 3312 break; 3313 } 3314 3315 } 3316 3317 switch (ahw->supported_type) { 3318 case PORT_FIBRE: 3319 ecmd->supported |= SUPPORTED_FIBRE; 3320 ecmd->advertising |= ADVERTISED_FIBRE; 3321 ecmd->port = PORT_FIBRE; 3322 ecmd->transceiver = XCVR_EXTERNAL; 3323 break; 3324 case PORT_TP: 3325 ecmd->supported |= SUPPORTED_TP; 3326 ecmd->advertising |= ADVERTISED_TP; 3327 ecmd->port = PORT_TP; 3328 ecmd->transceiver = XCVR_INTERNAL; 3329 break; 3330 case PORT_DA: 3331 ecmd->supported |= SUPPORTED_FIBRE; 3332 ecmd->advertising |= ADVERTISED_FIBRE; 3333 ecmd->port = PORT_DA; 3334 ecmd->transceiver = XCVR_EXTERNAL; 3335 break; 3336 default: 3337 ecmd->supported |= SUPPORTED_FIBRE; 3338 ecmd->advertising |= ADVERTISED_FIBRE; 3339 ecmd->port = PORT_OTHER; 3340 ecmd->transceiver = XCVR_EXTERNAL; 3341 break; 3342 } 3343 ecmd->phy_address = ahw->physical_port; 3344 return status; 3345} 3346 3347int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter, 3348 struct ethtool_cmd *ecmd) 3349{ 3350 struct qlcnic_hardware_context *ahw = adapter->ahw; 3351 u32 config = adapter->ahw->port_config; 3352 int status = 0; 3353 3354 /* 83xx devices do not support Half duplex */ 3355 if (ecmd->duplex == DUPLEX_HALF) { 3356 netdev_info(adapter->netdev, 3357 "Half duplex mode not supported\n"); 3358 return -EINVAL; 3359 } 3360 3361 if (ecmd->autoneg) { 3362 ahw->port_config |= QLC_83XX_AUTONEG_ENABLE; 3363 ahw->port_config |= (QLC_83XX_100_CAPABLE | 3364 QLC_83XX_1G_CAPABLE | 3365 QLC_83XX_10G_CAPABLE); 3366 } else { /* force speed */ 3367 ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE; 3368 switch (ethtool_cmd_speed(ecmd)) { 3369 case SPEED_10: 3370 ahw->port_config &= ~(QLC_83XX_100_CAPABLE | 3371 QLC_83XX_1G_CAPABLE | 3372 QLC_83XX_10G_CAPABLE); 3373 ahw->port_config |= QLC_83XX_10_CAPABLE; 3374 break; 3375 case SPEED_100: 3376 ahw->port_config &= ~(QLC_83XX_10_CAPABLE | 3377 QLC_83XX_1G_CAPABLE | 3378 QLC_83XX_10G_CAPABLE); 3379 ahw->port_config |= QLC_83XX_100_CAPABLE; 3380 break; 3381 case SPEED_1000: 3382 ahw->port_config &= ~(QLC_83XX_10_CAPABLE | 3383 QLC_83XX_100_CAPABLE | 3384 QLC_83XX_10G_CAPABLE); 3385 ahw->port_config |= QLC_83XX_1G_CAPABLE; 3386 break; 3387 case SPEED_10000: 3388 ahw->port_config &= ~(QLC_83XX_10_CAPABLE | 3389 QLC_83XX_100_CAPABLE | 3390 QLC_83XX_1G_CAPABLE); 3391 ahw->port_config |= QLC_83XX_10G_CAPABLE; 3392 break; 3393 default: 3394 return -EINVAL; 3395 } 3396 } 3397 status = qlcnic_83xx_set_port_config(adapter); 3398 if (status) { 3399 netdev_info(adapter->netdev, 3400 "Failed to Set Link Speed and autoneg.\n"); 3401 ahw->port_config = config; 3402 } 3403 3404 return status; 3405} 3406 3407static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd, 3408 u64 *data, int index) 3409{ 3410 u32 low, hi; 3411 u64 val; 3412 3413 low = cmd->rsp.arg[index]; 3414 hi = cmd->rsp.arg[index + 1]; 3415 val = (((u64) low) | (((u64) hi) << 32)); 3416 *data++ = val; 3417 return data; 3418} 3419 3420static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter, 3421 struct qlcnic_cmd_args *cmd, u64 *data, 3422 int type, int *ret) 3423{ 3424 int err, k, total_regs; 3425 3426 *ret = 0; 3427 err = qlcnic_issue_cmd(adapter, cmd); 3428 if (err != QLCNIC_RCODE_SUCCESS) { 3429 dev_info(&adapter->pdev->dev, 3430 "Error in get statistics mailbox command\n"); 3431 *ret = -EIO; 3432 return data; 3433 } 3434 total_regs = cmd->rsp.num; 3435 switch (type) { 3436 case QLC_83XX_STAT_MAC: 3437 /* fill in MAC tx counters */ 3438 for (k = 2; k < 28; k += 2) 3439 data = qlcnic_83xx_copy_stats(cmd, data, k); 3440 /* skip 24 bytes of reserved area */ 3441 /* fill in MAC rx counters */ 3442 for (k += 6; k < 60; k += 2) 3443 data = qlcnic_83xx_copy_stats(cmd, data, k); 3444 /* skip 24 bytes of reserved area */ 3445 /* fill in MAC rx frame stats */ 3446 for (k += 6; k < 80; k += 2) 3447 data = qlcnic_83xx_copy_stats(cmd, data, k); 3448 /* fill in eSwitch stats */ 3449 for (; k < total_regs; k += 2) 3450 data = qlcnic_83xx_copy_stats(cmd, data, k); 3451 break; 3452 case QLC_83XX_STAT_RX: 3453 for (k = 2; k < 8; k += 2) 3454 data = qlcnic_83xx_copy_stats(cmd, data, k); 3455 /* skip 8 bytes of reserved data */ 3456 for (k += 2; k < 24; k += 2) 3457 data = qlcnic_83xx_copy_stats(cmd, data, k); 3458 /* skip 8 bytes containing RE1FBQ error data */ 3459 for (k += 2; k < total_regs; k += 2) 3460 data = qlcnic_83xx_copy_stats(cmd, data, k); 3461 break; 3462 case QLC_83XX_STAT_TX: 3463 for (k = 2; k < 10; k += 2) 3464 data = qlcnic_83xx_copy_stats(cmd, data, k); 3465 /* skip 8 bytes of reserved data */ 3466 for (k += 2; k < total_regs; k += 2) 3467 data = qlcnic_83xx_copy_stats(cmd, data, k); 3468 break; 3469 default: 3470 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n"); 3471 *ret = -EIO; 3472 } 3473 return data; 3474} 3475 3476void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data) 3477{ 3478 struct qlcnic_cmd_args cmd; 3479 struct net_device *netdev = adapter->netdev; 3480 int ret = 0; 3481 3482 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS); 3483 if (ret) 3484 return; 3485 /* Get Tx stats */ 3486 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); 3487 cmd.rsp.num = QLC_83XX_TX_STAT_REGS; 3488 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3489 QLC_83XX_STAT_TX, &ret); 3490 if (ret) { 3491 netdev_err(netdev, "Error getting Tx stats\n"); 3492 goto out; 3493 } 3494 /* Get MAC stats */ 3495 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16); 3496 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS; 3497 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); 3498 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3499 QLC_83XX_STAT_MAC, &ret); 3500 if (ret) { 3501 netdev_err(netdev, "Error getting MAC stats\n"); 3502 goto out; 3503 } 3504 /* Get Rx stats */ 3505 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16; 3506 cmd.rsp.num = QLC_83XX_RX_STAT_REGS; 3507 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); 3508 data = qlcnic_83xx_fill_stats(adapter, &cmd, data, 3509 QLC_83XX_STAT_RX, &ret); 3510 if (ret) 3511 netdev_err(netdev, "Error getting Rx stats\n"); 3512out: 3513 qlcnic_free_mbx_args(&cmd); 3514} 3515 3516int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter) 3517{ 3518 u32 major, minor, sub; 3519 3520 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); 3521 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); 3522 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); 3523 3524 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) { 3525 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n", 3526 __func__); 3527 return 1; 3528 } 3529 return 0; 3530} 3531 3532inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter) 3533{ 3534 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) * 3535 sizeof(*adapter->ahw->ext_reg_tbl)) + 3536 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) * 3537 sizeof(*adapter->ahw->reg_tbl)); 3538} 3539 3540int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff) 3541{ 3542 int i, j = 0; 3543 3544 for (i = QLCNIC_DEV_INFO_SIZE + 1; 3545 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++) 3546 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j); 3547 3548 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++) 3549 regs_buff[i++] = QLCRDX(adapter->ahw, j); 3550 return i; 3551} 3552 3553int qlcnic_83xx_interrupt_test(struct net_device *netdev) 3554{ 3555 struct qlcnic_adapter *adapter = netdev_priv(netdev); 3556 struct qlcnic_hardware_context *ahw = adapter->ahw; 3557 struct qlcnic_cmd_args cmd; 3558 u8 val, drv_sds_rings = adapter->drv_sds_rings; 3559 u8 drv_tx_rings = adapter->drv_tx_rings; 3560 u32 data; 3561 u16 intrpt_id, id; 3562 int ret; 3563 3564 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { 3565 netdev_info(netdev, "Device is resetting\n"); 3566 return -EBUSY; 3567 } 3568 3569 if (qlcnic_get_diag_lock(adapter)) { 3570 netdev_info(netdev, "Device in diagnostics mode\n"); 3571 return -EBUSY; 3572 } 3573 3574 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST, 3575 drv_sds_rings); 3576 if (ret) 3577 goto fail_diag_irq; 3578 3579 ahw->diag_cnt = 0; 3580 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST); 3581 if (ret) 3582 goto fail_diag_irq; 3583 3584 if (adapter->flags & QLCNIC_MSIX_ENABLED) 3585 intrpt_id = ahw->intr_tbl[0].id; 3586 else 3587 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); 3588 3589 cmd.req.arg[1] = 1; 3590 cmd.req.arg[2] = intrpt_id; 3591 cmd.req.arg[3] = BIT_0; 3592 3593 ret = qlcnic_issue_cmd(adapter, &cmd); 3594 data = cmd.rsp.arg[2]; 3595 id = LSW(data); 3596 val = LSB(MSW(data)); 3597 if (id != intrpt_id) 3598 dev_info(&adapter->pdev->dev, 3599 "Interrupt generated: 0x%x, requested:0x%x\n", 3600 id, intrpt_id); 3601 if (val) 3602 dev_err(&adapter->pdev->dev, 3603 "Interrupt test error: 0x%x\n", val); 3604 if (ret) 3605 goto done; 3606 3607 msleep(20); 3608 ret = !ahw->diag_cnt; 3609 3610done: 3611 qlcnic_free_mbx_args(&cmd); 3612 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings); 3613 3614fail_diag_irq: 3615 adapter->drv_sds_rings = drv_sds_rings; 3616 adapter->drv_tx_rings = drv_tx_rings; 3617 qlcnic_release_diag_lock(adapter); 3618 return ret; 3619} 3620 3621void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter, 3622 struct ethtool_pauseparam *pause) 3623{ 3624 struct qlcnic_hardware_context *ahw = adapter->ahw; 3625 int status = 0; 3626 u32 config; 3627 3628 status = qlcnic_83xx_get_port_config(adapter); 3629 if (status) { 3630 dev_err(&adapter->pdev->dev, 3631 "%s: Get Pause Config failed\n", __func__); 3632 return; 3633 } 3634 config = ahw->port_config; 3635 if (config & QLC_83XX_CFG_STD_PAUSE) { 3636 switch (MSW(config)) { 3637 case QLC_83XX_TX_PAUSE: 3638 pause->tx_pause = 1; 3639 break; 3640 case QLC_83XX_RX_PAUSE: 3641 pause->rx_pause = 1; 3642 break; 3643 case QLC_83XX_TX_RX_PAUSE: 3644 default: 3645 /* Backward compatibility for existing 3646 * flash definitions 3647 */ 3648 pause->tx_pause = 1; 3649 pause->rx_pause = 1; 3650 } 3651 } 3652 3653 if (QLC_83XX_AUTONEG(config)) 3654 pause->autoneg = 1; 3655} 3656 3657int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter, 3658 struct ethtool_pauseparam *pause) 3659{ 3660 struct qlcnic_hardware_context *ahw = adapter->ahw; 3661 int status = 0; 3662 u32 config; 3663 3664 status = qlcnic_83xx_get_port_config(adapter); 3665 if (status) { 3666 dev_err(&adapter->pdev->dev, 3667 "%s: Get Pause Config failed.\n", __func__); 3668 return status; 3669 } 3670 config = ahw->port_config; 3671 3672 if (ahw->port_type == QLCNIC_GBE) { 3673 if (pause->autoneg) 3674 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG; 3675 if (!pause->autoneg) 3676 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG; 3677 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) { 3678 return -EOPNOTSUPP; 3679 } 3680 3681 if (!(config & QLC_83XX_CFG_STD_PAUSE)) 3682 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE; 3683 3684 if (pause->rx_pause && pause->tx_pause) { 3685 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE; 3686 } else if (pause->rx_pause && !pause->tx_pause) { 3687 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE; 3688 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE; 3689 } else if (pause->tx_pause && !pause->rx_pause) { 3690 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE; 3691 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE; 3692 } else if (!pause->rx_pause && !pause->tx_pause) { 3693 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE | 3694 QLC_83XX_CFG_STD_PAUSE); 3695 } 3696 status = qlcnic_83xx_set_port_config(adapter); 3697 if (status) { 3698 dev_err(&adapter->pdev->dev, 3699 "%s: Set Pause Config failed.\n", __func__); 3700 ahw->port_config = config; 3701 } 3702 return status; 3703} 3704 3705static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter) 3706{ 3707 int ret, err = 0; 3708 u32 temp; 3709 3710 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, 3711 QLC_83XX_FLASH_OEM_READ_SIG); 3712 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, 3713 QLC_83XX_FLASH_READ_CTRL); 3714 ret = qlcnic_83xx_poll_flash_status_reg(adapter); 3715 if (ret) 3716 return -EIO; 3717 3718 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); 3719 if (err == -EIO) 3720 return err; 3721 3722 return temp & 0xFF; 3723} 3724 3725int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter) 3726{ 3727 int status; 3728 3729 status = qlcnic_83xx_read_flash_status_reg(adapter); 3730 if (status == -EIO) { 3731 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n", 3732 __func__); 3733 return 1; 3734 } 3735 return 0; 3736} 3737 3738static int qlcnic_83xx_shutdown(struct pci_dev *pdev) 3739{ 3740 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 3741 struct net_device *netdev = adapter->netdev; 3742 int retval; 3743 3744 netif_device_detach(netdev); 3745 qlcnic_cancel_idc_work(adapter); 3746 3747 if (netif_running(netdev)) 3748 qlcnic_down(adapter, netdev); 3749 3750 qlcnic_83xx_disable_mbx_intr(adapter); 3751 cancel_delayed_work_sync(&adapter->idc_aen_work); 3752 3753 retval = pci_save_state(pdev); 3754 if (retval) 3755 return retval; 3756 3757 return 0; 3758} 3759 3760static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter) 3761{ 3762 struct qlcnic_hardware_context *ahw = adapter->ahw; 3763 struct qlc_83xx_idc *idc = &ahw->idc; 3764 int err = 0; 3765 3766 err = qlcnic_83xx_idc_init(adapter); 3767 if (err) 3768 return err; 3769 3770 if (ahw->nic_mode == QLCNIC_VNIC_MODE) { 3771 if (ahw->op_mode == QLCNIC_MGMT_FUNC) { 3772 qlcnic_83xx_set_vnic_opmode(adapter); 3773 } else { 3774 err = qlcnic_83xx_check_vnic_state(adapter); 3775 if (err) 3776 return err; 3777 } 3778 } 3779 3780 err = qlcnic_83xx_idc_reattach_driver(adapter); 3781 if (err) 3782 return err; 3783 3784 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 3785 idc->delay); 3786 return err; 3787} 3788 3789void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx) 3790{ 3791 reinit_completion(&mbx->completion); 3792 set_bit(QLC_83XX_MBX_READY, &mbx->status); 3793} 3794 3795void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx) 3796{ 3797 if (!mbx) 3798 return; 3799 3800 destroy_workqueue(mbx->work_q); 3801 kfree(mbx); 3802} 3803 3804static inline void 3805qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter, 3806 struct qlcnic_cmd_args *cmd) 3807{ 3808 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); 3809 3810 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) { 3811 qlcnic_free_mbx_args(cmd); 3812 kfree(cmd); 3813 return; 3814 } 3815 complete(&cmd->completion); 3816} 3817 3818static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter) 3819{ 3820 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3821 struct list_head *head = &mbx->cmd_q; 3822 struct qlcnic_cmd_args *cmd = NULL; 3823 3824 spin_lock(&mbx->queue_lock); 3825 3826 while (!list_empty(head)) { 3827 cmd = list_entry(head->next, struct qlcnic_cmd_args, list); 3828 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n", 3829 __func__, cmd->cmd_op); 3830 list_del(&cmd->list); 3831 mbx->num_cmds--; 3832 qlcnic_83xx_notify_cmd_completion(adapter, cmd); 3833 } 3834 3835 spin_unlock(&mbx->queue_lock); 3836} 3837 3838static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter) 3839{ 3840 struct qlcnic_hardware_context *ahw = adapter->ahw; 3841 struct qlcnic_mailbox *mbx = ahw->mailbox; 3842 u32 host_mbx_ctrl; 3843 3844 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) 3845 return -EBUSY; 3846 3847 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL); 3848 if (host_mbx_ctrl) { 3849 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3850 ahw->idc.collect_dump = 1; 3851 return -EIO; 3852 } 3853 3854 return 0; 3855} 3856 3857static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter, 3858 u8 issue_cmd) 3859{ 3860 if (issue_cmd) 3861 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER); 3862 else 3863 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); 3864} 3865 3866static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter, 3867 struct qlcnic_cmd_args *cmd) 3868{ 3869 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3870 3871 spin_lock(&mbx->queue_lock); 3872 3873 list_del(&cmd->list); 3874 mbx->num_cmds--; 3875 3876 spin_unlock(&mbx->queue_lock); 3877 3878 qlcnic_83xx_notify_cmd_completion(adapter, cmd); 3879} 3880 3881static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter, 3882 struct qlcnic_cmd_args *cmd) 3883{ 3884 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp; 3885 struct qlcnic_hardware_context *ahw = adapter->ahw; 3886 int i, j; 3887 3888 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) { 3889 mbx_cmd = cmd->req.arg[0]; 3890 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); 3891 for (i = 1; i < cmd->req.num; i++) 3892 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i)); 3893 } else { 3894 fw_hal_version = ahw->fw_hal_version; 3895 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32); 3896 total_size = cmd->pay_size + hdr_size; 3897 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16; 3898 mbx_cmd = tmp | fw_hal_version << 29; 3899 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); 3900 3901 /* Back channel specific operations bits */ 3902 mbx_cmd = 0x1 | 1 << 4; 3903 3904 if (qlcnic_sriov_pf_check(adapter)) 3905 mbx_cmd |= cmd->func_num << 5; 3906 3907 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1)); 3908 3909 for (i = 2, j = 0; j < hdr_size; i++, j++) 3910 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i)); 3911 for (j = 0; j < cmd->pay_size; j++, i++) 3912 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i)); 3913 } 3914} 3915 3916void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter) 3917{ 3918 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3919 3920 if (!mbx) 3921 return; 3922 3923 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 3924 complete(&mbx->completion); 3925 cancel_work_sync(&mbx->work); 3926 flush_workqueue(mbx->work_q); 3927 qlcnic_83xx_flush_mbx_queue(adapter); 3928} 3929 3930static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter, 3931 struct qlcnic_cmd_args *cmd, 3932 unsigned long *timeout) 3933{ 3934 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 3935 3936 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) { 3937 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); 3938 init_completion(&cmd->completion); 3939 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN; 3940 3941 spin_lock(&mbx->queue_lock); 3942 3943 list_add_tail(&cmd->list, &mbx->cmd_q); 3944 mbx->num_cmds++; 3945 cmd->total_cmds = mbx->num_cmds; 3946 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT; 3947 queue_work(mbx->work_q, &mbx->work); 3948 3949 spin_unlock(&mbx->queue_lock); 3950 3951 return 0; 3952 } 3953 3954 return -EBUSY; 3955} 3956 3957static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter, 3958 struct qlcnic_cmd_args *cmd) 3959{ 3960 u8 mac_cmd_rcode; 3961 u32 fw_data; 3962 3963 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) { 3964 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2)); 3965 mac_cmd_rcode = (u8)fw_data; 3966 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE || 3967 mac_cmd_rcode == QLC_83XX_MAC_PRESENT || 3968 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) { 3969 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; 3970 return QLCNIC_RCODE_SUCCESS; 3971 } 3972 } 3973 3974 return -EINVAL; 3975} 3976 3977static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter, 3978 struct qlcnic_cmd_args *cmd) 3979{ 3980 struct qlcnic_hardware_context *ahw = adapter->ahw; 3981 struct device *dev = &adapter->pdev->dev; 3982 u8 mbx_err_code; 3983 u32 fw_data; 3984 3985 fw_data = readl(QLCNIC_MBX_FW(ahw, 0)); 3986 mbx_err_code = QLCNIC_MBX_STATUS(fw_data); 3987 qlcnic_83xx_get_mbx_data(adapter, cmd); 3988 3989 switch (mbx_err_code) { 3990 case QLCNIC_MBX_RSP_OK: 3991 case QLCNIC_MBX_PORT_RSP_OK: 3992 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; 3993 break; 3994 default: 3995 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd)) 3996 break; 3997 3998 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n", 3999 __func__, cmd->cmd_op, cmd->type, ahw->pci_func, 4000 ahw->op_mode, mbx_err_code); 4001 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED; 4002 qlcnic_dump_mbx(adapter, cmd); 4003 } 4004 4005 return; 4006} 4007 4008static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter) 4009{ 4010 struct qlcnic_hardware_context *ahw = adapter->ahw; 4011 u32 offset; 4012 4013 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); 4014 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x", 4015 readl(ahw->pci_base0 + offset), 4016 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL), 4017 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL), 4018 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL)); 4019} 4020 4021static void qlcnic_83xx_mailbox_worker(struct work_struct *work) 4022{ 4023 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox, 4024 work); 4025 struct qlcnic_adapter *adapter = mbx->adapter; 4026 struct qlcnic_mbx_ops *mbx_ops = mbx->ops; 4027 struct device *dev = &adapter->pdev->dev; 4028 atomic_t *rsp_status = &mbx->rsp_status; 4029 struct list_head *head = &mbx->cmd_q; 4030 struct qlcnic_hardware_context *ahw; 4031 struct qlcnic_cmd_args *cmd = NULL; 4032 4033 ahw = adapter->ahw; 4034 4035 while (true) { 4036 if (qlcnic_83xx_check_mbx_status(adapter)) { 4037 qlcnic_83xx_flush_mbx_queue(adapter); 4038 return; 4039 } 4040 4041 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); 4042 4043 spin_lock(&mbx->queue_lock); 4044 4045 if (list_empty(head)) { 4046 spin_unlock(&mbx->queue_lock); 4047 return; 4048 } 4049 cmd = list_entry(head->next, struct qlcnic_cmd_args, list); 4050 4051 spin_unlock(&mbx->queue_lock); 4052 4053 mbx_ops->encode_cmd(adapter, cmd); 4054 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST); 4055 4056 if (wait_for_completion_timeout(&mbx->completion, 4057 QLC_83XX_MBX_TIMEOUT)) { 4058 mbx_ops->decode_resp(adapter, cmd); 4059 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION); 4060 } else { 4061 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n", 4062 __func__, cmd->cmd_op, cmd->type, ahw->pci_func, 4063 ahw->op_mode); 4064 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 4065 qlcnic_dump_mailbox_registers(adapter); 4066 qlcnic_83xx_get_mbx_data(adapter, cmd); 4067 qlcnic_dump_mbx(adapter, cmd); 4068 qlcnic_83xx_idc_request_reset(adapter, 4069 QLCNIC_FORCE_FW_DUMP_KEY); 4070 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT; 4071 } 4072 mbx_ops->dequeue_cmd(adapter, cmd); 4073 } 4074} 4075 4076static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = { 4077 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd, 4078 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd, 4079 .decode_resp = qlcnic_83xx_decode_mbx_rsp, 4080 .encode_cmd = qlcnic_83xx_encode_mbx_cmd, 4081 .nofity_fw = qlcnic_83xx_signal_mbx_cmd, 4082}; 4083 4084int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter) 4085{ 4086 struct qlcnic_hardware_context *ahw = adapter->ahw; 4087 struct qlcnic_mailbox *mbx; 4088 4089 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL); 4090 if (!ahw->mailbox) 4091 return -ENOMEM; 4092 4093 mbx = ahw->mailbox; 4094 mbx->ops = &qlcnic_83xx_mbx_ops; 4095 mbx->adapter = adapter; 4096 4097 spin_lock_init(&mbx->queue_lock); 4098 spin_lock_init(&mbx->aen_lock); 4099 INIT_LIST_HEAD(&mbx->cmd_q); 4100 init_completion(&mbx->completion); 4101 4102 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox"); 4103 if (mbx->work_q == NULL) { 4104 kfree(mbx); 4105 return -ENOMEM; 4106 } 4107 4108 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker); 4109 set_bit(QLC_83XX_MBX_READY, &mbx->status); 4110 return 0; 4111} 4112 4113static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev, 4114 pci_channel_state_t state) 4115{ 4116 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 4117 4118 if (state == pci_channel_io_perm_failure) 4119 return PCI_ERS_RESULT_DISCONNECT; 4120 4121 if (state == pci_channel_io_normal) 4122 return PCI_ERS_RESULT_RECOVERED; 4123 4124 set_bit(__QLCNIC_AER, &adapter->state); 4125 set_bit(__QLCNIC_RESETTING, &adapter->state); 4126 4127 qlcnic_83xx_aer_stop_poll_work(adapter); 4128 4129 pci_save_state(pdev); 4130 pci_disable_device(pdev); 4131 4132 return PCI_ERS_RESULT_NEED_RESET; 4133} 4134 4135static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev) 4136{ 4137 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 4138 int err = 0; 4139 4140 pdev->error_state = pci_channel_io_normal; 4141 err = pci_enable_device(pdev); 4142 if (err) 4143 goto disconnect; 4144 4145 pci_set_power_state(pdev, PCI_D0); 4146 pci_set_master(pdev); 4147 pci_restore_state(pdev); 4148 4149 err = qlcnic_83xx_aer_reset(adapter); 4150 if (err == 0) 4151 return PCI_ERS_RESULT_RECOVERED; 4152disconnect: 4153 clear_bit(__QLCNIC_AER, &adapter->state); 4154 clear_bit(__QLCNIC_RESETTING, &adapter->state); 4155 return PCI_ERS_RESULT_DISCONNECT; 4156} 4157 4158static void qlcnic_83xx_io_resume(struct pci_dev *pdev) 4159{ 4160 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 4161 4162 pci_cleanup_aer_uncorrect_error_status(pdev); 4163 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state)) 4164 qlcnic_83xx_aer_start_poll_work(adapter); 4165} 4166