1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11#include <linux/bitops.h> 12#include <linux/delay.h> 13#include <linux/pci.h> 14#include <linux/module.h> 15#include <linux/seq_file.h> 16#include <linux/i2c.h> 17#include <linux/mii.h> 18#include <linux/slab.h> 19#include "net_driver.h" 20#include "bitfield.h" 21#include "efx.h" 22#include "nic.h" 23#include "farch_regs.h" 24#include "io.h" 25#include "phy.h" 26#include "workarounds.h" 27#include "selftest.h" 28#include "mdio_10g.h" 29 30/* Hardware control for SFC4000 (aka Falcon). */ 31 32/************************************************************************** 33 * 34 * NIC stats 35 * 36 ************************************************************************** 37 */ 38 39#define FALCON_MAC_STATS_SIZE 0x100 40 41#define XgRxOctets_offset 0x0 42#define XgRxOctets_WIDTH 48 43#define XgRxOctetsOK_offset 0x8 44#define XgRxOctetsOK_WIDTH 48 45#define XgRxPkts_offset 0x10 46#define XgRxPkts_WIDTH 32 47#define XgRxPktsOK_offset 0x14 48#define XgRxPktsOK_WIDTH 32 49#define XgRxBroadcastPkts_offset 0x18 50#define XgRxBroadcastPkts_WIDTH 32 51#define XgRxMulticastPkts_offset 0x1C 52#define XgRxMulticastPkts_WIDTH 32 53#define XgRxUnicastPkts_offset 0x20 54#define XgRxUnicastPkts_WIDTH 32 55#define XgRxUndersizePkts_offset 0x24 56#define XgRxUndersizePkts_WIDTH 32 57#define XgRxOversizePkts_offset 0x28 58#define XgRxOversizePkts_WIDTH 32 59#define XgRxJabberPkts_offset 0x2C 60#define XgRxJabberPkts_WIDTH 32 61#define XgRxUndersizeFCSerrorPkts_offset 0x30 62#define XgRxUndersizeFCSerrorPkts_WIDTH 32 63#define XgRxDropEvents_offset 0x34 64#define XgRxDropEvents_WIDTH 32 65#define XgRxFCSerrorPkts_offset 0x38 66#define XgRxFCSerrorPkts_WIDTH 32 67#define XgRxAlignError_offset 0x3C 68#define XgRxAlignError_WIDTH 32 69#define XgRxSymbolError_offset 0x40 70#define XgRxSymbolError_WIDTH 32 71#define XgRxInternalMACError_offset 0x44 72#define XgRxInternalMACError_WIDTH 32 73#define XgRxControlPkts_offset 0x48 74#define XgRxControlPkts_WIDTH 32 75#define XgRxPausePkts_offset 0x4C 76#define XgRxPausePkts_WIDTH 32 77#define XgRxPkts64Octets_offset 0x50 78#define XgRxPkts64Octets_WIDTH 32 79#define XgRxPkts65to127Octets_offset 0x54 80#define XgRxPkts65to127Octets_WIDTH 32 81#define XgRxPkts128to255Octets_offset 0x58 82#define XgRxPkts128to255Octets_WIDTH 32 83#define XgRxPkts256to511Octets_offset 0x5C 84#define XgRxPkts256to511Octets_WIDTH 32 85#define XgRxPkts512to1023Octets_offset 0x60 86#define XgRxPkts512to1023Octets_WIDTH 32 87#define XgRxPkts1024to15xxOctets_offset 0x64 88#define XgRxPkts1024to15xxOctets_WIDTH 32 89#define XgRxPkts15xxtoMaxOctets_offset 0x68 90#define XgRxPkts15xxtoMaxOctets_WIDTH 32 91#define XgRxLengthError_offset 0x6C 92#define XgRxLengthError_WIDTH 32 93#define XgTxPkts_offset 0x80 94#define XgTxPkts_WIDTH 32 95#define XgTxOctets_offset 0x88 96#define XgTxOctets_WIDTH 48 97#define XgTxMulticastPkts_offset 0x90 98#define XgTxMulticastPkts_WIDTH 32 99#define XgTxBroadcastPkts_offset 0x94 100#define XgTxBroadcastPkts_WIDTH 32 101#define XgTxUnicastPkts_offset 0x98 102#define XgTxUnicastPkts_WIDTH 32 103#define XgTxControlPkts_offset 0x9C 104#define XgTxControlPkts_WIDTH 32 105#define XgTxPausePkts_offset 0xA0 106#define XgTxPausePkts_WIDTH 32 107#define XgTxPkts64Octets_offset 0xA4 108#define XgTxPkts64Octets_WIDTH 32 109#define XgTxPkts65to127Octets_offset 0xA8 110#define XgTxPkts65to127Octets_WIDTH 32 111#define XgTxPkts128to255Octets_offset 0xAC 112#define XgTxPkts128to255Octets_WIDTH 32 113#define XgTxPkts256to511Octets_offset 0xB0 114#define XgTxPkts256to511Octets_WIDTH 32 115#define XgTxPkts512to1023Octets_offset 0xB4 116#define XgTxPkts512to1023Octets_WIDTH 32 117#define XgTxPkts1024to15xxOctets_offset 0xB8 118#define XgTxPkts1024to15xxOctets_WIDTH 32 119#define XgTxPkts1519toMaxOctets_offset 0xBC 120#define XgTxPkts1519toMaxOctets_WIDTH 32 121#define XgTxUndersizePkts_offset 0xC0 122#define XgTxUndersizePkts_WIDTH 32 123#define XgTxOversizePkts_offset 0xC4 124#define XgTxOversizePkts_WIDTH 32 125#define XgTxNonTcpUdpPkt_offset 0xC8 126#define XgTxNonTcpUdpPkt_WIDTH 16 127#define XgTxMacSrcErrPkt_offset 0xCC 128#define XgTxMacSrcErrPkt_WIDTH 16 129#define XgTxIpSrcErrPkt_offset 0xD0 130#define XgTxIpSrcErrPkt_WIDTH 16 131#define XgDmaDone_offset 0xD4 132#define XgDmaDone_WIDTH 32 133 134#define FALCON_XMAC_STATS_DMA_FLAG(efx) \ 135 (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset)) 136 137#define FALCON_DMA_STAT(ext_name, hw_name) \ 138 [FALCON_STAT_ ## ext_name] = \ 139 { #ext_name, \ 140 /* 48-bit stats are zero-padded to 64 on DMA */ \ 141 hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH, \ 142 hw_name ## _ ## offset } 143#define FALCON_OTHER_STAT(ext_name) \ 144 [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 } 145#define GENERIC_SW_STAT(ext_name) \ 146 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 147 148static const struct efx_hw_stat_desc falcon_stat_desc[FALCON_STAT_COUNT] = { 149 FALCON_DMA_STAT(tx_bytes, XgTxOctets), 150 FALCON_DMA_STAT(tx_packets, XgTxPkts), 151 FALCON_DMA_STAT(tx_pause, XgTxPausePkts), 152 FALCON_DMA_STAT(tx_control, XgTxControlPkts), 153 FALCON_DMA_STAT(tx_unicast, XgTxUnicastPkts), 154 FALCON_DMA_STAT(tx_multicast, XgTxMulticastPkts), 155 FALCON_DMA_STAT(tx_broadcast, XgTxBroadcastPkts), 156 FALCON_DMA_STAT(tx_lt64, XgTxUndersizePkts), 157 FALCON_DMA_STAT(tx_64, XgTxPkts64Octets), 158 FALCON_DMA_STAT(tx_65_to_127, XgTxPkts65to127Octets), 159 FALCON_DMA_STAT(tx_128_to_255, XgTxPkts128to255Octets), 160 FALCON_DMA_STAT(tx_256_to_511, XgTxPkts256to511Octets), 161 FALCON_DMA_STAT(tx_512_to_1023, XgTxPkts512to1023Octets), 162 FALCON_DMA_STAT(tx_1024_to_15xx, XgTxPkts1024to15xxOctets), 163 FALCON_DMA_STAT(tx_15xx_to_jumbo, XgTxPkts1519toMaxOctets), 164 FALCON_DMA_STAT(tx_gtjumbo, XgTxOversizePkts), 165 FALCON_DMA_STAT(tx_non_tcpudp, XgTxNonTcpUdpPkt), 166 FALCON_DMA_STAT(tx_mac_src_error, XgTxMacSrcErrPkt), 167 FALCON_DMA_STAT(tx_ip_src_error, XgTxIpSrcErrPkt), 168 FALCON_DMA_STAT(rx_bytes, XgRxOctets), 169 FALCON_DMA_STAT(rx_good_bytes, XgRxOctetsOK), 170 FALCON_OTHER_STAT(rx_bad_bytes), 171 FALCON_DMA_STAT(rx_packets, XgRxPkts), 172 FALCON_DMA_STAT(rx_good, XgRxPktsOK), 173 FALCON_DMA_STAT(rx_bad, XgRxFCSerrorPkts), 174 FALCON_DMA_STAT(rx_pause, XgRxPausePkts), 175 FALCON_DMA_STAT(rx_control, XgRxControlPkts), 176 FALCON_DMA_STAT(rx_unicast, XgRxUnicastPkts), 177 FALCON_DMA_STAT(rx_multicast, XgRxMulticastPkts), 178 FALCON_DMA_STAT(rx_broadcast, XgRxBroadcastPkts), 179 FALCON_DMA_STAT(rx_lt64, XgRxUndersizePkts), 180 FALCON_DMA_STAT(rx_64, XgRxPkts64Octets), 181 FALCON_DMA_STAT(rx_65_to_127, XgRxPkts65to127Octets), 182 FALCON_DMA_STAT(rx_128_to_255, XgRxPkts128to255Octets), 183 FALCON_DMA_STAT(rx_256_to_511, XgRxPkts256to511Octets), 184 FALCON_DMA_STAT(rx_512_to_1023, XgRxPkts512to1023Octets), 185 FALCON_DMA_STAT(rx_1024_to_15xx, XgRxPkts1024to15xxOctets), 186 FALCON_DMA_STAT(rx_15xx_to_jumbo, XgRxPkts15xxtoMaxOctets), 187 FALCON_DMA_STAT(rx_gtjumbo, XgRxOversizePkts), 188 FALCON_DMA_STAT(rx_bad_lt64, XgRxUndersizeFCSerrorPkts), 189 FALCON_DMA_STAT(rx_bad_gtjumbo, XgRxJabberPkts), 190 FALCON_DMA_STAT(rx_overflow, XgRxDropEvents), 191 FALCON_DMA_STAT(rx_symbol_error, XgRxSymbolError), 192 FALCON_DMA_STAT(rx_align_error, XgRxAlignError), 193 FALCON_DMA_STAT(rx_length_error, XgRxLengthError), 194 FALCON_DMA_STAT(rx_internal_error, XgRxInternalMACError), 195 FALCON_OTHER_STAT(rx_nodesc_drop_cnt), 196 GENERIC_SW_STAT(rx_nodesc_trunc), 197 GENERIC_SW_STAT(rx_noskb_drops), 198}; 199static const unsigned long falcon_stat_mask[] = { 200 [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL, 201}; 202 203/************************************************************************** 204 * 205 * Basic SPI command set and bit definitions 206 * 207 *************************************************************************/ 208 209#define SPI_WRSR 0x01 /* Write status register */ 210#define SPI_WRITE 0x02 /* Write data to memory array */ 211#define SPI_READ 0x03 /* Read data from memory array */ 212#define SPI_WRDI 0x04 /* Reset write enable latch */ 213#define SPI_RDSR 0x05 /* Read status register */ 214#define SPI_WREN 0x06 /* Set write enable latch */ 215#define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */ 216 217#define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */ 218#define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */ 219#define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */ 220#define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */ 221#define SPI_STATUS_WEN 0x02 /* State of the write enable latch */ 222#define SPI_STATUS_NRDY 0x01 /* Device busy flag */ 223 224/************************************************************************** 225 * 226 * Non-volatile memory layout 227 * 228 ************************************************************************** 229 */ 230 231/* SFC4000 flash is partitioned into: 232 * 0-0x400 chip and board config (see struct falcon_nvconfig) 233 * 0x400-0x8000 unused (or may contain VPD if EEPROM not present) 234 * 0x8000-end boot code (mapped to PCI expansion ROM) 235 * SFC4000 small EEPROM (size < 0x400) is used for VPD only. 236 * SFC4000 large EEPROM (size >= 0x400) is partitioned into: 237 * 0-0x400 chip and board config 238 * configurable VPD 239 * 0x800-0x1800 boot config 240 * Aside from the chip and board config, all of these are optional and may 241 * be absent or truncated depending on the devices used. 242 */ 243#define FALCON_NVCONFIG_END 0x400U 244#define FALCON_FLASH_BOOTCODE_START 0x8000U 245#define FALCON_EEPROM_BOOTCONFIG_START 0x800U 246#define FALCON_EEPROM_BOOTCONFIG_END 0x1800U 247 248/* Board configuration v2 (v1 is obsolete; later versions are compatible) */ 249struct falcon_nvconfig_board_v2 { 250 __le16 nports; 251 u8 port0_phy_addr; 252 u8 port0_phy_type; 253 u8 port1_phy_addr; 254 u8 port1_phy_type; 255 __le16 asic_sub_revision; 256 __le16 board_revision; 257} __packed; 258 259/* Board configuration v3 extra information */ 260struct falcon_nvconfig_board_v3 { 261 __le32 spi_device_type[2]; 262} __packed; 263 264/* Bit numbers for spi_device_type */ 265#define SPI_DEV_TYPE_SIZE_LBN 0 266#define SPI_DEV_TYPE_SIZE_WIDTH 5 267#define SPI_DEV_TYPE_ADDR_LEN_LBN 6 268#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2 269#define SPI_DEV_TYPE_ERASE_CMD_LBN 8 270#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8 271#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16 272#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5 273#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24 274#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5 275#define SPI_DEV_TYPE_FIELD(type, field) \ 276 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field))) 277 278#define FALCON_NVCONFIG_OFFSET 0x300 279 280#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C 281struct falcon_nvconfig { 282 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */ 283 u8 mac_address[2][8]; /* 0x310 */ 284 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */ 285 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */ 286 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */ 287 efx_oword_t hw_init_reg; /* 0x350 */ 288 efx_oword_t nic_stat_reg; /* 0x360 */ 289 efx_oword_t glb_ctl_reg; /* 0x370 */ 290 efx_oword_t srm_cfg_reg; /* 0x380 */ 291 efx_oword_t spare_reg; /* 0x390 */ 292 __le16 board_magic_num; /* 0x3A0 */ 293 __le16 board_struct_ver; 294 __le16 board_checksum; 295 struct falcon_nvconfig_board_v2 board_v2; 296 efx_oword_t ee_base_page_reg; /* 0x3B0 */ 297 struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */ 298} __packed; 299 300/*************************************************************************/ 301 302static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method); 303static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx); 304 305static const unsigned int 306/* "Large" EEPROM device: Atmel AT25640 or similar 307 * 8 KB, 16-bit address, 32 B write block */ 308large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) 309 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) 310 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), 311/* Default flash device: Atmel AT25F1024 312 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ 313default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) 314 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) 315 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) 316 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) 317 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); 318 319/************************************************************************** 320 * 321 * I2C bus - this is a bit-bashing interface using GPIO pins 322 * Note that it uses the output enables to tristate the outputs 323 * SDA is the data pin and SCL is the clock 324 * 325 ************************************************************************** 326 */ 327static void falcon_setsda(void *data, int state) 328{ 329 struct efx_nic *efx = (struct efx_nic *)data; 330 efx_oword_t reg; 331 332 efx_reado(efx, ®, FR_AB_GPIO_CTL); 333 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); 334 efx_writeo(efx, ®, FR_AB_GPIO_CTL); 335} 336 337static void falcon_setscl(void *data, int state) 338{ 339 struct efx_nic *efx = (struct efx_nic *)data; 340 efx_oword_t reg; 341 342 efx_reado(efx, ®, FR_AB_GPIO_CTL); 343 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); 344 efx_writeo(efx, ®, FR_AB_GPIO_CTL); 345} 346 347static int falcon_getsda(void *data) 348{ 349 struct efx_nic *efx = (struct efx_nic *)data; 350 efx_oword_t reg; 351 352 efx_reado(efx, ®, FR_AB_GPIO_CTL); 353 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); 354} 355 356static int falcon_getscl(void *data) 357{ 358 struct efx_nic *efx = (struct efx_nic *)data; 359 efx_oword_t reg; 360 361 efx_reado(efx, ®, FR_AB_GPIO_CTL); 362 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); 363} 364 365static const struct i2c_algo_bit_data falcon_i2c_bit_operations = { 366 .setsda = falcon_setsda, 367 .setscl = falcon_setscl, 368 .getsda = falcon_getsda, 369 .getscl = falcon_getscl, 370 .udelay = 5, 371 /* Wait up to 50 ms for slave to let us pull SCL high */ 372 .timeout = DIV_ROUND_UP(HZ, 20), 373}; 374 375static void falcon_push_irq_moderation(struct efx_channel *channel) 376{ 377 efx_dword_t timer_cmd; 378 struct efx_nic *efx = channel->efx; 379 380 /* Set timer register */ 381 if (channel->irq_moderation) { 382 EFX_POPULATE_DWORD_2(timer_cmd, 383 FRF_AB_TC_TIMER_MODE, 384 FFE_BB_TIMER_MODE_INT_HLDOFF, 385 FRF_AB_TC_TIMER_VAL, 386 channel->irq_moderation - 1); 387 } else { 388 EFX_POPULATE_DWORD_2(timer_cmd, 389 FRF_AB_TC_TIMER_MODE, 390 FFE_BB_TIMER_MODE_DIS, 391 FRF_AB_TC_TIMER_VAL, 0); 392 } 393 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); 394 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, 395 channel->channel); 396} 397 398static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); 399 400static void falcon_prepare_flush(struct efx_nic *efx) 401{ 402 falcon_deconfigure_mac_wrapper(efx); 403 404 /* Wait for the tx and rx fifo's to get to the next packet boundary 405 * (~1ms without back-pressure), then to drain the remainder of the 406 * fifo's at data path speeds (negligible), with a healthy margin. */ 407 msleep(10); 408} 409 410/* Acknowledge a legacy interrupt from Falcon 411 * 412 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. 413 * 414 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the 415 * BIU. Interrupt acknowledge is read sensitive so must write instead 416 * (then read to ensure the BIU collector is flushed) 417 * 418 * NB most hardware supports MSI interrupts 419 */ 420static inline void falcon_irq_ack_a1(struct efx_nic *efx) 421{ 422 efx_dword_t reg; 423 424 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); 425 efx_writed(efx, ®, FR_AA_INT_ACK_KER); 426 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); 427} 428 429static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) 430{ 431 struct efx_nic *efx = dev_id; 432 efx_oword_t *int_ker = efx->irq_status.addr; 433 int syserr; 434 int queues; 435 436 /* Check to see if this is our interrupt. If it isn't, we 437 * exit without having touched the hardware. 438 */ 439 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { 440 netif_vdbg(efx, intr, efx->net_dev, 441 "IRQ %d on CPU %d not for me\n", irq, 442 raw_smp_processor_id()); 443 return IRQ_NONE; 444 } 445 efx->last_irq_cpu = raw_smp_processor_id(); 446 netif_vdbg(efx, intr, efx->net_dev, 447 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", 448 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); 449 450 if (!likely(ACCESS_ONCE(efx->irq_soft_enabled))) 451 return IRQ_HANDLED; 452 453 /* Check to see if we have a serious error condition */ 454 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); 455 if (unlikely(syserr)) 456 return efx_farch_fatal_interrupt(efx); 457 458 /* Determine interrupting queues, clear interrupt status 459 * register and acknowledge the device interrupt. 460 */ 461 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); 462 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); 463 EFX_ZERO_OWORD(*int_ker); 464 wmb(); /* Ensure the vector is cleared before interrupt ack */ 465 falcon_irq_ack_a1(efx); 466 467 if (queues & 1) 468 efx_schedule_channel_irq(efx_get_channel(efx, 0)); 469 if (queues & 2) 470 efx_schedule_channel_irq(efx_get_channel(efx, 1)); 471 return IRQ_HANDLED; 472} 473 474/************************************************************************** 475 * 476 * RSS 477 * 478 ************************************************************************** 479 */ 480 481static void falcon_b0_rx_push_rss_config(struct efx_nic *efx) 482{ 483 efx_oword_t temp; 484 485 /* Set hash key for IPv4 */ 486 memcpy(&temp, efx->rx_hash_key, sizeof(temp)); 487 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); 488 489 efx_farch_rx_push_indir_table(efx); 490} 491 492/************************************************************************** 493 * 494 * EEPROM/flash 495 * 496 ************************************************************************** 497 */ 498 499#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) 500 501static int falcon_spi_poll(struct efx_nic *efx) 502{ 503 efx_oword_t reg; 504 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); 505 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; 506} 507 508/* Wait for SPI command completion */ 509static int falcon_spi_wait(struct efx_nic *efx) 510{ 511 /* Most commands will finish quickly, so we start polling at 512 * very short intervals. Sometimes the command may have to 513 * wait for VPD or expansion ROM access outside of our 514 * control, so we allow up to 100 ms. */ 515 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); 516 int i; 517 518 for (i = 0; i < 10; i++) { 519 if (!falcon_spi_poll(efx)) 520 return 0; 521 udelay(10); 522 } 523 524 for (;;) { 525 if (!falcon_spi_poll(efx)) 526 return 0; 527 if (time_after_eq(jiffies, timeout)) { 528 netif_err(efx, hw, efx->net_dev, 529 "timed out waiting for SPI\n"); 530 return -ETIMEDOUT; 531 } 532 schedule_timeout_uninterruptible(1); 533 } 534} 535 536static int 537falcon_spi_cmd(struct efx_nic *efx, const struct falcon_spi_device *spi, 538 unsigned int command, int address, 539 const void *in, void *out, size_t len) 540{ 541 bool addressed = (address >= 0); 542 bool reading = (out != NULL); 543 efx_oword_t reg; 544 int rc; 545 546 /* Input validation */ 547 if (len > FALCON_SPI_MAX_LEN) 548 return -EINVAL; 549 550 /* Check that previous command is not still running */ 551 rc = falcon_spi_poll(efx); 552 if (rc) 553 return rc; 554 555 /* Program address register, if we have an address */ 556 if (addressed) { 557 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); 558 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); 559 } 560 561 /* Program data register, if we have data */ 562 if (in != NULL) { 563 memcpy(®, in, len); 564 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); 565 } 566 567 /* Issue read/write command */ 568 EFX_POPULATE_OWORD_7(reg, 569 FRF_AB_EE_SPI_HCMD_CMD_EN, 1, 570 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, 571 FRF_AB_EE_SPI_HCMD_DABCNT, len, 572 FRF_AB_EE_SPI_HCMD_READ, reading, 573 FRF_AB_EE_SPI_HCMD_DUBCNT, 0, 574 FRF_AB_EE_SPI_HCMD_ADBCNT, 575 (addressed ? spi->addr_len : 0), 576 FRF_AB_EE_SPI_HCMD_ENC, command); 577 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); 578 579 /* Wait for read/write to complete */ 580 rc = falcon_spi_wait(efx); 581 if (rc) 582 return rc; 583 584 /* Read data */ 585 if (out != NULL) { 586 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); 587 memcpy(out, ®, len); 588 } 589 590 return 0; 591} 592 593static inline u8 594falcon_spi_munge_command(const struct falcon_spi_device *spi, 595 const u8 command, const unsigned int address) 596{ 597 return command | (((address >> 8) & spi->munge_address) << 3); 598} 599 600static int 601falcon_spi_read(struct efx_nic *efx, const struct falcon_spi_device *spi, 602 loff_t start, size_t len, size_t *retlen, u8 *buffer) 603{ 604 size_t block_len, pos = 0; 605 unsigned int command; 606 int rc = 0; 607 608 while (pos < len) { 609 block_len = min(len - pos, FALCON_SPI_MAX_LEN); 610 611 command = falcon_spi_munge_command(spi, SPI_READ, start + pos); 612 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, 613 buffer + pos, block_len); 614 if (rc) 615 break; 616 pos += block_len; 617 618 /* Avoid locking up the system */ 619 cond_resched(); 620 if (signal_pending(current)) { 621 rc = -EINTR; 622 break; 623 } 624 } 625 626 if (retlen) 627 *retlen = pos; 628 return rc; 629} 630 631#ifdef CONFIG_SFC_MTD 632 633struct falcon_mtd_partition { 634 struct efx_mtd_partition common; 635 const struct falcon_spi_device *spi; 636 size_t offset; 637}; 638 639#define to_falcon_mtd_partition(mtd) \ 640 container_of(mtd, struct falcon_mtd_partition, common.mtd) 641 642static size_t 643falcon_spi_write_limit(const struct falcon_spi_device *spi, size_t start) 644{ 645 return min(FALCON_SPI_MAX_LEN, 646 (spi->block_size - (start & (spi->block_size - 1)))); 647} 648 649/* Wait up to 10 ms for buffered write completion */ 650static int 651falcon_spi_wait_write(struct efx_nic *efx, const struct falcon_spi_device *spi) 652{ 653 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); 654 u8 status; 655 int rc; 656 657 for (;;) { 658 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, 659 &status, sizeof(status)); 660 if (rc) 661 return rc; 662 if (!(status & SPI_STATUS_NRDY)) 663 return 0; 664 if (time_after_eq(jiffies, timeout)) { 665 netif_err(efx, hw, efx->net_dev, 666 "SPI write timeout on device %d" 667 " last status=0x%02x\n", 668 spi->device_id, status); 669 return -ETIMEDOUT; 670 } 671 schedule_timeout_uninterruptible(1); 672 } 673} 674 675static int 676falcon_spi_write(struct efx_nic *efx, const struct falcon_spi_device *spi, 677 loff_t start, size_t len, size_t *retlen, const u8 *buffer) 678{ 679 u8 verify_buffer[FALCON_SPI_MAX_LEN]; 680 size_t block_len, pos = 0; 681 unsigned int command; 682 int rc = 0; 683 684 while (pos < len) { 685 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); 686 if (rc) 687 break; 688 689 block_len = min(len - pos, 690 falcon_spi_write_limit(spi, start + pos)); 691 command = falcon_spi_munge_command(spi, SPI_WRITE, start + pos); 692 rc = falcon_spi_cmd(efx, spi, command, start + pos, 693 buffer + pos, NULL, block_len); 694 if (rc) 695 break; 696 697 rc = falcon_spi_wait_write(efx, spi); 698 if (rc) 699 break; 700 701 command = falcon_spi_munge_command(spi, SPI_READ, start + pos); 702 rc = falcon_spi_cmd(efx, spi, command, start + pos, 703 NULL, verify_buffer, block_len); 704 if (memcmp(verify_buffer, buffer + pos, block_len)) { 705 rc = -EIO; 706 break; 707 } 708 709 pos += block_len; 710 711 /* Avoid locking up the system */ 712 cond_resched(); 713 if (signal_pending(current)) { 714 rc = -EINTR; 715 break; 716 } 717 } 718 719 if (retlen) 720 *retlen = pos; 721 return rc; 722} 723 724static int 725falcon_spi_slow_wait(struct falcon_mtd_partition *part, bool uninterruptible) 726{ 727 const struct falcon_spi_device *spi = part->spi; 728 struct efx_nic *efx = part->common.mtd.priv; 729 u8 status; 730 int rc, i; 731 732 /* Wait up to 4s for flash/EEPROM to finish a slow operation. */ 733 for (i = 0; i < 40; i++) { 734 __set_current_state(uninterruptible ? 735 TASK_UNINTERRUPTIBLE : TASK_INTERRUPTIBLE); 736 schedule_timeout(HZ / 10); 737 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, 738 &status, sizeof(status)); 739 if (rc) 740 return rc; 741 if (!(status & SPI_STATUS_NRDY)) 742 return 0; 743 if (signal_pending(current)) 744 return -EINTR; 745 } 746 pr_err("%s: timed out waiting for %s\n", 747 part->common.name, part->common.dev_type_name); 748 return -ETIMEDOUT; 749} 750 751static int 752falcon_spi_unlock(struct efx_nic *efx, const struct falcon_spi_device *spi) 753{ 754 const u8 unlock_mask = (SPI_STATUS_BP2 | SPI_STATUS_BP1 | 755 SPI_STATUS_BP0); 756 u8 status; 757 int rc; 758 759 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, 760 &status, sizeof(status)); 761 if (rc) 762 return rc; 763 764 if (!(status & unlock_mask)) 765 return 0; /* already unlocked */ 766 767 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); 768 if (rc) 769 return rc; 770 rc = falcon_spi_cmd(efx, spi, SPI_SST_EWSR, -1, NULL, NULL, 0); 771 if (rc) 772 return rc; 773 774 status &= ~unlock_mask; 775 rc = falcon_spi_cmd(efx, spi, SPI_WRSR, -1, &status, 776 NULL, sizeof(status)); 777 if (rc) 778 return rc; 779 rc = falcon_spi_wait_write(efx, spi); 780 if (rc) 781 return rc; 782 783 return 0; 784} 785 786#define FALCON_SPI_VERIFY_BUF_LEN 16 787 788static int 789falcon_spi_erase(struct falcon_mtd_partition *part, loff_t start, size_t len) 790{ 791 const struct falcon_spi_device *spi = part->spi; 792 struct efx_nic *efx = part->common.mtd.priv; 793 unsigned pos, block_len; 794 u8 empty[FALCON_SPI_VERIFY_BUF_LEN]; 795 u8 buffer[FALCON_SPI_VERIFY_BUF_LEN]; 796 int rc; 797 798 if (len != spi->erase_size) 799 return -EINVAL; 800 801 if (spi->erase_command == 0) 802 return -EOPNOTSUPP; 803 804 rc = falcon_spi_unlock(efx, spi); 805 if (rc) 806 return rc; 807 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); 808 if (rc) 809 return rc; 810 rc = falcon_spi_cmd(efx, spi, spi->erase_command, start, NULL, 811 NULL, 0); 812 if (rc) 813 return rc; 814 rc = falcon_spi_slow_wait(part, false); 815 816 /* Verify the entire region has been wiped */ 817 memset(empty, 0xff, sizeof(empty)); 818 for (pos = 0; pos < len; pos += block_len) { 819 block_len = min(len - pos, sizeof(buffer)); 820 rc = falcon_spi_read(efx, spi, start + pos, block_len, 821 NULL, buffer); 822 if (rc) 823 return rc; 824 if (memcmp(empty, buffer, block_len)) 825 return -EIO; 826 827 /* Avoid locking up the system */ 828 cond_resched(); 829 if (signal_pending(current)) 830 return -EINTR; 831 } 832 833 return rc; 834} 835 836static void falcon_mtd_rename(struct efx_mtd_partition *part) 837{ 838 struct efx_nic *efx = part->mtd.priv; 839 840 snprintf(part->name, sizeof(part->name), "%s %s", 841 efx->name, part->type_name); 842} 843 844static int falcon_mtd_read(struct mtd_info *mtd, loff_t start, 845 size_t len, size_t *retlen, u8 *buffer) 846{ 847 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); 848 struct efx_nic *efx = mtd->priv; 849 struct falcon_nic_data *nic_data = efx->nic_data; 850 int rc; 851 852 rc = mutex_lock_interruptible(&nic_data->spi_lock); 853 if (rc) 854 return rc; 855 rc = falcon_spi_read(efx, part->spi, part->offset + start, 856 len, retlen, buffer); 857 mutex_unlock(&nic_data->spi_lock); 858 return rc; 859} 860 861static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len) 862{ 863 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); 864 struct efx_nic *efx = mtd->priv; 865 struct falcon_nic_data *nic_data = efx->nic_data; 866 int rc; 867 868 rc = mutex_lock_interruptible(&nic_data->spi_lock); 869 if (rc) 870 return rc; 871 rc = falcon_spi_erase(part, part->offset + start, len); 872 mutex_unlock(&nic_data->spi_lock); 873 return rc; 874} 875 876static int falcon_mtd_write(struct mtd_info *mtd, loff_t start, 877 size_t len, size_t *retlen, const u8 *buffer) 878{ 879 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); 880 struct efx_nic *efx = mtd->priv; 881 struct falcon_nic_data *nic_data = efx->nic_data; 882 int rc; 883 884 rc = mutex_lock_interruptible(&nic_data->spi_lock); 885 if (rc) 886 return rc; 887 rc = falcon_spi_write(efx, part->spi, part->offset + start, 888 len, retlen, buffer); 889 mutex_unlock(&nic_data->spi_lock); 890 return rc; 891} 892 893static int falcon_mtd_sync(struct mtd_info *mtd) 894{ 895 struct falcon_mtd_partition *part = to_falcon_mtd_partition(mtd); 896 struct efx_nic *efx = mtd->priv; 897 struct falcon_nic_data *nic_data = efx->nic_data; 898 int rc; 899 900 mutex_lock(&nic_data->spi_lock); 901 rc = falcon_spi_slow_wait(part, true); 902 mutex_unlock(&nic_data->spi_lock); 903 return rc; 904} 905 906static int falcon_mtd_probe(struct efx_nic *efx) 907{ 908 struct falcon_nic_data *nic_data = efx->nic_data; 909 struct falcon_mtd_partition *parts; 910 struct falcon_spi_device *spi; 911 size_t n_parts; 912 int rc = -ENODEV; 913 914 ASSERT_RTNL(); 915 916 /* Allocate space for maximum number of partitions */ 917 parts = kcalloc(2, sizeof(*parts), GFP_KERNEL); 918 if (!parts) 919 return -ENOMEM; 920 n_parts = 0; 921 922 spi = &nic_data->spi_flash; 923 if (falcon_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) { 924 parts[n_parts].spi = spi; 925 parts[n_parts].offset = FALCON_FLASH_BOOTCODE_START; 926 parts[n_parts].common.dev_type_name = "flash"; 927 parts[n_parts].common.type_name = "sfc_flash_bootrom"; 928 parts[n_parts].common.mtd.type = MTD_NORFLASH; 929 parts[n_parts].common.mtd.flags = MTD_CAP_NORFLASH; 930 parts[n_parts].common.mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START; 931 parts[n_parts].common.mtd.erasesize = spi->erase_size; 932 n_parts++; 933 } 934 935 spi = &nic_data->spi_eeprom; 936 if (falcon_spi_present(spi) && spi->size > FALCON_EEPROM_BOOTCONFIG_START) { 937 parts[n_parts].spi = spi; 938 parts[n_parts].offset = FALCON_EEPROM_BOOTCONFIG_START; 939 parts[n_parts].common.dev_type_name = "EEPROM"; 940 parts[n_parts].common.type_name = "sfc_bootconfig"; 941 parts[n_parts].common.mtd.type = MTD_RAM; 942 parts[n_parts].common.mtd.flags = MTD_CAP_RAM; 943 parts[n_parts].common.mtd.size = 944 min(spi->size, FALCON_EEPROM_BOOTCONFIG_END) - 945 FALCON_EEPROM_BOOTCONFIG_START; 946 parts[n_parts].common.mtd.erasesize = spi->erase_size; 947 n_parts++; 948 } 949 950 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 951 if (rc) 952 kfree(parts); 953 return rc; 954} 955 956#endif /* CONFIG_SFC_MTD */ 957 958/************************************************************************** 959 * 960 * XMAC operations 961 * 962 ************************************************************************** 963 */ 964 965/* Configure the XAUI driver that is an output from Falcon */ 966static void falcon_setup_xaui(struct efx_nic *efx) 967{ 968 efx_oword_t sdctl, txdrv; 969 970 /* Move the XAUI into low power, unless there is no PHY, in 971 * which case the XAUI will have to drive a cable. */ 972 if (efx->phy_type == PHY_TYPE_NONE) 973 return; 974 975 efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL); 976 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF); 977 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF); 978 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF); 979 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF); 980 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF); 981 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF); 982 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF); 983 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF); 984 efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL); 985 986 EFX_POPULATE_OWORD_8(txdrv, 987 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF, 988 FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF, 989 FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF, 990 FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF, 991 FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF, 992 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF, 993 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF, 994 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF); 995 efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL); 996} 997 998int falcon_reset_xaui(struct efx_nic *efx) 999{ 1000 struct falcon_nic_data *nic_data = efx->nic_data; 1001 efx_oword_t reg; 1002 int count; 1003 1004 /* Don't fetch MAC statistics over an XMAC reset */ 1005 WARN_ON(nic_data->stats_disable_count == 0); 1006 1007 /* Start reset sequence */ 1008 EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); 1009 efx_writeo(efx, ®, FR_AB_XX_PWR_RST); 1010 1011 /* Wait up to 10 ms for completion, then reinitialise */ 1012 for (count = 0; count < 1000; count++) { 1013 efx_reado(efx, ®, FR_AB_XX_PWR_RST); 1014 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 && 1015 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) { 1016 falcon_setup_xaui(efx); 1017 return 0; 1018 } 1019 udelay(10); 1020 } 1021 netif_err(efx, hw, efx->net_dev, 1022 "timed out waiting for XAUI/XGXS reset\n"); 1023 return -ETIMEDOUT; 1024} 1025 1026static void falcon_ack_status_intr(struct efx_nic *efx) 1027{ 1028 struct falcon_nic_data *nic_data = efx->nic_data; 1029 efx_oword_t reg; 1030 1031 if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx)) 1032 return; 1033 1034 /* We expect xgmii faults if the wireside link is down */ 1035 if (!efx->link_state.up) 1036 return; 1037 1038 /* We can only use this interrupt to signal the negative edge of 1039 * xaui_align [we have to poll the positive edge]. */ 1040 if (nic_data->xmac_poll_required) 1041 return; 1042 1043 efx_reado(efx, ®, FR_AB_XM_MGT_INT_MSK); 1044} 1045 1046static bool falcon_xgxs_link_ok(struct efx_nic *efx) 1047{ 1048 efx_oword_t reg; 1049 bool align_done, link_ok = false; 1050 int sync_status; 1051 1052 /* Read link status */ 1053 efx_reado(efx, ®, FR_AB_XX_CORE_STAT); 1054 1055 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE); 1056 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT); 1057 if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES)) 1058 link_ok = true; 1059 1060 /* Clear link status ready for next read */ 1061 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES); 1062 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES); 1063 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES); 1064 efx_writeo(efx, ®, FR_AB_XX_CORE_STAT); 1065 1066 return link_ok; 1067} 1068 1069static bool falcon_xmac_link_ok(struct efx_nic *efx) 1070{ 1071 /* 1072 * Check MAC's XGXS link status except when using XGMII loopback 1073 * which bypasses the XGXS block. 1074 * If possible, check PHY's XGXS link status except when using 1075 * MAC loopback. 1076 */ 1077 return (efx->loopback_mode == LOOPBACK_XGMII || 1078 falcon_xgxs_link_ok(efx)) && 1079 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) || 1080 LOOPBACK_INTERNAL(efx) || 1081 efx_mdio_phyxgxs_lane_sync(efx)); 1082} 1083 1084static void falcon_reconfigure_xmac_core(struct efx_nic *efx) 1085{ 1086 unsigned int max_frame_len; 1087 efx_oword_t reg; 1088 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX); 1089 bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX); 1090 1091 /* Configure MAC - cut-thru mode is hard wired on */ 1092 EFX_POPULATE_OWORD_3(reg, 1093 FRF_AB_XM_RX_JUMBO_MODE, 1, 1094 FRF_AB_XM_TX_STAT_EN, 1, 1095 FRF_AB_XM_RX_STAT_EN, 1); 1096 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); 1097 1098 /* Configure TX */ 1099 EFX_POPULATE_OWORD_6(reg, 1100 FRF_AB_XM_TXEN, 1, 1101 FRF_AB_XM_TX_PRMBL, 1, 1102 FRF_AB_XM_AUTO_PAD, 1, 1103 FRF_AB_XM_TXCRC, 1, 1104 FRF_AB_XM_FCNTL, tx_fc, 1105 FRF_AB_XM_IPG, 0x3); 1106 efx_writeo(efx, ®, FR_AB_XM_TX_CFG); 1107 1108 /* Configure RX */ 1109 EFX_POPULATE_OWORD_5(reg, 1110 FRF_AB_XM_RXEN, 1, 1111 FRF_AB_XM_AUTO_DEPAD, 0, 1112 FRF_AB_XM_ACPT_ALL_MCAST, 1, 1113 FRF_AB_XM_ACPT_ALL_UCAST, !efx->unicast_filter, 1114 FRF_AB_XM_PASS_CRC_ERR, 1); 1115 efx_writeo(efx, ®, FR_AB_XM_RX_CFG); 1116 1117 /* Set frame length */ 1118 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 1119 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); 1120 efx_writeo(efx, ®, FR_AB_XM_RX_PARAM); 1121 EFX_POPULATE_OWORD_2(reg, 1122 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len, 1123 FRF_AB_XM_TX_JUMBO_MODE, 1); 1124 efx_writeo(efx, ®, FR_AB_XM_TX_PARAM); 1125 1126 EFX_POPULATE_OWORD_2(reg, 1127 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ 1128 FRF_AB_XM_DIS_FCNTL, !rx_fc); 1129 efx_writeo(efx, ®, FR_AB_XM_FC); 1130 1131 /* Set MAC address */ 1132 memcpy(®, &efx->net_dev->dev_addr[0], 4); 1133 efx_writeo(efx, ®, FR_AB_XM_ADR_LO); 1134 memcpy(®, &efx->net_dev->dev_addr[4], 2); 1135 efx_writeo(efx, ®, FR_AB_XM_ADR_HI); 1136} 1137 1138static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) 1139{ 1140 efx_oword_t reg; 1141 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS); 1142 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI); 1143 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII); 1144 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; 1145 1146 /* XGXS block is flaky and will need to be reset if moving 1147 * into our out of XGMII, XGXS or XAUI loopbacks. */ 1148 efx_reado(efx, ®, FR_AB_XX_CORE_STAT); 1149 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN); 1150 old_xgmii_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN); 1151 1152 efx_reado(efx, ®, FR_AB_XX_SD_CTL); 1153 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA); 1154 1155 /* The PHY driver may have turned XAUI off */ 1156 if ((xgxs_loopback != old_xgxs_loopback) || 1157 (xaui_loopback != old_xaui_loopback) || 1158 (xgmii_loopback != old_xgmii_loopback)) 1159 falcon_reset_xaui(efx); 1160 1161 efx_reado(efx, ®, FR_AB_XX_CORE_STAT); 1162 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG, 1163 (xgxs_loopback || xaui_loopback) ? 1164 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0); 1165 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback); 1166 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback); 1167 efx_writeo(efx, ®, FR_AB_XX_CORE_STAT); 1168 1169 efx_reado(efx, ®, FR_AB_XX_SD_CTL); 1170 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback); 1171 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback); 1172 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback); 1173 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback); 1174 efx_writeo(efx, ®, FR_AB_XX_SD_CTL); 1175} 1176 1177 1178/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */ 1179static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries) 1180{ 1181 bool mac_up = falcon_xmac_link_ok(efx); 1182 1183 if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS || 1184 efx_phy_mode_disabled(efx->phy_mode)) 1185 /* XAUI link is expected to be down */ 1186 return mac_up; 1187 1188 falcon_stop_nic_stats(efx); 1189 1190 while (!mac_up && tries) { 1191 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n"); 1192 falcon_reset_xaui(efx); 1193 udelay(200); 1194 1195 mac_up = falcon_xmac_link_ok(efx); 1196 --tries; 1197 } 1198 1199 falcon_start_nic_stats(efx); 1200 1201 return mac_up; 1202} 1203 1204static bool falcon_xmac_check_fault(struct efx_nic *efx) 1205{ 1206 return !falcon_xmac_link_ok_retry(efx, 5); 1207} 1208 1209static int falcon_reconfigure_xmac(struct efx_nic *efx) 1210{ 1211 struct falcon_nic_data *nic_data = efx->nic_data; 1212 1213 efx_farch_filter_sync_rx_mode(efx); 1214 1215 falcon_reconfigure_xgxs_core(efx); 1216 falcon_reconfigure_xmac_core(efx); 1217 1218 falcon_reconfigure_mac_wrapper(efx); 1219 1220 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5); 1221 falcon_ack_status_intr(efx); 1222 1223 return 0; 1224} 1225 1226static void falcon_poll_xmac(struct efx_nic *efx) 1227{ 1228 struct falcon_nic_data *nic_data = efx->nic_data; 1229 1230 /* We expect xgmii faults if the wireside link is down */ 1231 if (!efx->link_state.up || !nic_data->xmac_poll_required) 1232 return; 1233 1234 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1); 1235 falcon_ack_status_intr(efx); 1236} 1237 1238/************************************************************************** 1239 * 1240 * MAC wrapper 1241 * 1242 ************************************************************************** 1243 */ 1244 1245static void falcon_push_multicast_hash(struct efx_nic *efx) 1246{ 1247 union efx_multicast_hash *mc_hash = &efx->multicast_hash; 1248 1249 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 1250 1251 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); 1252 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); 1253} 1254 1255static void falcon_reset_macs(struct efx_nic *efx) 1256{ 1257 struct falcon_nic_data *nic_data = efx->nic_data; 1258 efx_oword_t reg, mac_ctrl; 1259 int count; 1260 1261 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { 1262 /* It's not safe to use GLB_CTL_REG to reset the 1263 * macs, so instead use the internal MAC resets 1264 */ 1265 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); 1266 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); 1267 1268 for (count = 0; count < 10000; count++) { 1269 efx_reado(efx, ®, FR_AB_XM_GLB_CFG); 1270 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == 1271 0) 1272 return; 1273 udelay(10); 1274 } 1275 1276 netif_err(efx, hw, efx->net_dev, 1277 "timed out waiting for XMAC core reset\n"); 1278 } 1279 1280 /* Mac stats will fail whist the TX fifo is draining */ 1281 WARN_ON(nic_data->stats_disable_count == 0); 1282 1283 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); 1284 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); 1285 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); 1286 1287 efx_reado(efx, ®, FR_AB_GLB_CTL); 1288 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); 1289 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); 1290 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); 1291 efx_writeo(efx, ®, FR_AB_GLB_CTL); 1292 1293 count = 0; 1294 while (1) { 1295 efx_reado(efx, ®, FR_AB_GLB_CTL); 1296 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && 1297 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && 1298 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { 1299 netif_dbg(efx, hw, efx->net_dev, 1300 "Completed MAC reset after %d loops\n", 1301 count); 1302 break; 1303 } 1304 if (count > 20) { 1305 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); 1306 break; 1307 } 1308 count++; 1309 udelay(10); 1310 } 1311 1312 /* Ensure the correct MAC is selected before statistics 1313 * are re-enabled by the caller */ 1314 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); 1315 1316 falcon_setup_xaui(efx); 1317} 1318 1319static void falcon_drain_tx_fifo(struct efx_nic *efx) 1320{ 1321 efx_oword_t reg; 1322 1323 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || 1324 (efx->loopback_mode != LOOPBACK_NONE)) 1325 return; 1326 1327 efx_reado(efx, ®, FR_AB_MAC_CTRL); 1328 /* There is no point in draining more than once */ 1329 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) 1330 return; 1331 1332 falcon_reset_macs(efx); 1333} 1334 1335static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) 1336{ 1337 efx_oword_t reg; 1338 1339 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) 1340 return; 1341 1342 /* Isolate the MAC -> RX */ 1343 efx_reado(efx, ®, FR_AZ_RX_CFG); 1344 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); 1345 efx_writeo(efx, ®, FR_AZ_RX_CFG); 1346 1347 /* Isolate TX -> MAC */ 1348 falcon_drain_tx_fifo(efx); 1349} 1350 1351static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) 1352{ 1353 struct efx_link_state *link_state = &efx->link_state; 1354 efx_oword_t reg; 1355 int link_speed, isolate; 1356 1357 isolate = !!ACCESS_ONCE(efx->reset_pending); 1358 1359 switch (link_state->speed) { 1360 case 10000: link_speed = 3; break; 1361 case 1000: link_speed = 2; break; 1362 case 100: link_speed = 1; break; 1363 default: link_speed = 0; break; 1364 } 1365 1366 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work 1367 * as advertised. Disable to ensure packets are not 1368 * indefinitely held and TX queue can be flushed at any point 1369 * while the link is down. */ 1370 EFX_POPULATE_OWORD_5(reg, 1371 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, 1372 FRF_AB_MAC_BCAD_ACPT, 1, 1373 FRF_AB_MAC_UC_PROM, !efx->unicast_filter, 1374 FRF_AB_MAC_LINK_STATUS, 1, /* always set */ 1375 FRF_AB_MAC_SPEED, link_speed); 1376 /* On B0, MAC backpressure can be disabled and packets get 1377 * discarded. */ 1378 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 1379 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1380 !link_state->up || isolate); 1381 } 1382 1383 efx_writeo(efx, ®, FR_AB_MAC_CTRL); 1384 1385 /* Restore the multicast hash registers. */ 1386 falcon_push_multicast_hash(efx); 1387 1388 efx_reado(efx, ®, FR_AZ_RX_CFG); 1389 /* Enable XOFF signal from RX FIFO (we enabled it during NIC 1390 * initialisation but it may read back as 0) */ 1391 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); 1392 /* Unisolate the MAC -> RX */ 1393 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1394 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); 1395 efx_writeo(efx, ®, FR_AZ_RX_CFG); 1396} 1397 1398static void falcon_stats_request(struct efx_nic *efx) 1399{ 1400 struct falcon_nic_data *nic_data = efx->nic_data; 1401 efx_oword_t reg; 1402 1403 WARN_ON(nic_data->stats_pending); 1404 WARN_ON(nic_data->stats_disable_count); 1405 1406 FALCON_XMAC_STATS_DMA_FLAG(efx) = 0; 1407 nic_data->stats_pending = true; 1408 wmb(); /* ensure done flag is clear */ 1409 1410 /* Initiate DMA transfer of stats */ 1411 EFX_POPULATE_OWORD_2(reg, 1412 FRF_AB_MAC_STAT_DMA_CMD, 1, 1413 FRF_AB_MAC_STAT_DMA_ADR, 1414 efx->stats_buffer.dma_addr); 1415 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); 1416 1417 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); 1418} 1419 1420static void falcon_stats_complete(struct efx_nic *efx) 1421{ 1422 struct falcon_nic_data *nic_data = efx->nic_data; 1423 1424 if (!nic_data->stats_pending) 1425 return; 1426 1427 nic_data->stats_pending = false; 1428 if (FALCON_XMAC_STATS_DMA_FLAG(efx)) { 1429 rmb(); /* read the done flag before the stats */ 1430 efx_nic_update_stats(falcon_stat_desc, FALCON_STAT_COUNT, 1431 falcon_stat_mask, nic_data->stats, 1432 efx->stats_buffer.addr, true); 1433 } else { 1434 netif_err(efx, hw, efx->net_dev, 1435 "timed out waiting for statistics\n"); 1436 } 1437} 1438 1439static void falcon_stats_timer_func(unsigned long context) 1440{ 1441 struct efx_nic *efx = (struct efx_nic *)context; 1442 struct falcon_nic_data *nic_data = efx->nic_data; 1443 1444 spin_lock(&efx->stats_lock); 1445 1446 falcon_stats_complete(efx); 1447 if (nic_data->stats_disable_count == 0) 1448 falcon_stats_request(efx); 1449 1450 spin_unlock(&efx->stats_lock); 1451} 1452 1453static bool falcon_loopback_link_poll(struct efx_nic *efx) 1454{ 1455 struct efx_link_state old_state = efx->link_state; 1456 1457 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 1458 WARN_ON(!LOOPBACK_INTERNAL(efx)); 1459 1460 efx->link_state.fd = true; 1461 efx->link_state.fc = efx->wanted_fc; 1462 efx->link_state.up = true; 1463 efx->link_state.speed = 10000; 1464 1465 return !efx_link_state_equal(&efx->link_state, &old_state); 1466} 1467 1468static int falcon_reconfigure_port(struct efx_nic *efx) 1469{ 1470 int rc; 1471 1472 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); 1473 1474 /* Poll the PHY link state *before* reconfiguring it. This means we 1475 * will pick up the correct speed (in loopback) to select the correct 1476 * MAC. 1477 */ 1478 if (LOOPBACK_INTERNAL(efx)) 1479 falcon_loopback_link_poll(efx); 1480 else 1481 efx->phy_op->poll(efx); 1482 1483 falcon_stop_nic_stats(efx); 1484 falcon_deconfigure_mac_wrapper(efx); 1485 1486 falcon_reset_macs(efx); 1487 1488 efx->phy_op->reconfigure(efx); 1489 rc = falcon_reconfigure_xmac(efx); 1490 BUG_ON(rc); 1491 1492 falcon_start_nic_stats(efx); 1493 1494 /* Synchronise efx->link_state with the kernel */ 1495 efx_link_status_changed(efx); 1496 1497 return 0; 1498} 1499 1500/* TX flow control may automatically turn itself off if the link 1501 * partner (intermittently) stops responding to pause frames. There 1502 * isn't any indication that this has happened, so the best we do is 1503 * leave it up to the user to spot this and fix it by cycling transmit 1504 * flow control on this end. 1505 */ 1506 1507static void falcon_a1_prepare_enable_fc_tx(struct efx_nic *efx) 1508{ 1509 /* Schedule a reset to recover */ 1510 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE); 1511} 1512 1513static void falcon_b0_prepare_enable_fc_tx(struct efx_nic *efx) 1514{ 1515 /* Recover by resetting the EM block */ 1516 falcon_stop_nic_stats(efx); 1517 falcon_drain_tx_fifo(efx); 1518 falcon_reconfigure_xmac(efx); 1519 falcon_start_nic_stats(efx); 1520} 1521 1522/************************************************************************** 1523 * 1524 * PHY access via GMII 1525 * 1526 ************************************************************************** 1527 */ 1528 1529/* Wait for GMII access to complete */ 1530static int falcon_gmii_wait(struct efx_nic *efx) 1531{ 1532 efx_oword_t md_stat; 1533 int count; 1534 1535 /* wait up to 50ms - taken max from datasheet */ 1536 for (count = 0; count < 5000; count++) { 1537 efx_reado(efx, &md_stat, FR_AB_MD_STAT); 1538 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { 1539 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || 1540 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { 1541 netif_err(efx, hw, efx->net_dev, 1542 "error from GMII access " 1543 EFX_OWORD_FMT"\n", 1544 EFX_OWORD_VAL(md_stat)); 1545 return -EIO; 1546 } 1547 return 0; 1548 } 1549 udelay(10); 1550 } 1551 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); 1552 return -ETIMEDOUT; 1553} 1554 1555/* Write an MDIO register of a PHY connected to Falcon. */ 1556static int falcon_mdio_write(struct net_device *net_dev, 1557 int prtad, int devad, u16 addr, u16 value) 1558{ 1559 struct efx_nic *efx = netdev_priv(net_dev); 1560 struct falcon_nic_data *nic_data = efx->nic_data; 1561 efx_oword_t reg; 1562 int rc; 1563 1564 netif_vdbg(efx, hw, efx->net_dev, 1565 "writing MDIO %d register %d.%d with 0x%04x\n", 1566 prtad, devad, addr, value); 1567 1568 mutex_lock(&nic_data->mdio_lock); 1569 1570 /* Check MDIO not currently being accessed */ 1571 rc = falcon_gmii_wait(efx); 1572 if (rc) 1573 goto out; 1574 1575 /* Write the address/ID register */ 1576 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); 1577 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); 1578 1579 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, 1580 FRF_AB_MD_DEV_ADR, devad); 1581 efx_writeo(efx, ®, FR_AB_MD_ID); 1582 1583 /* Write data */ 1584 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); 1585 efx_writeo(efx, ®, FR_AB_MD_TXD); 1586 1587 EFX_POPULATE_OWORD_2(reg, 1588 FRF_AB_MD_WRC, 1, 1589 FRF_AB_MD_GC, 0); 1590 efx_writeo(efx, ®, FR_AB_MD_CS); 1591 1592 /* Wait for data to be written */ 1593 rc = falcon_gmii_wait(efx); 1594 if (rc) { 1595 /* Abort the write operation */ 1596 EFX_POPULATE_OWORD_2(reg, 1597 FRF_AB_MD_WRC, 0, 1598 FRF_AB_MD_GC, 1); 1599 efx_writeo(efx, ®, FR_AB_MD_CS); 1600 udelay(10); 1601 } 1602 1603out: 1604 mutex_unlock(&nic_data->mdio_lock); 1605 return rc; 1606} 1607 1608/* Read an MDIO register of a PHY connected to Falcon. */ 1609static int falcon_mdio_read(struct net_device *net_dev, 1610 int prtad, int devad, u16 addr) 1611{ 1612 struct efx_nic *efx = netdev_priv(net_dev); 1613 struct falcon_nic_data *nic_data = efx->nic_data; 1614 efx_oword_t reg; 1615 int rc; 1616 1617 mutex_lock(&nic_data->mdio_lock); 1618 1619 /* Check MDIO not currently being accessed */ 1620 rc = falcon_gmii_wait(efx); 1621 if (rc) 1622 goto out; 1623 1624 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); 1625 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); 1626 1627 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, 1628 FRF_AB_MD_DEV_ADR, devad); 1629 efx_writeo(efx, ®, FR_AB_MD_ID); 1630 1631 /* Request data to be read */ 1632 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); 1633 efx_writeo(efx, ®, FR_AB_MD_CS); 1634 1635 /* Wait for data to become available */ 1636 rc = falcon_gmii_wait(efx); 1637 if (rc == 0) { 1638 efx_reado(efx, ®, FR_AB_MD_RXD); 1639 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); 1640 netif_vdbg(efx, hw, efx->net_dev, 1641 "read from MDIO %d register %d.%d, got %04x\n", 1642 prtad, devad, addr, rc); 1643 } else { 1644 /* Abort the read operation */ 1645 EFX_POPULATE_OWORD_2(reg, 1646 FRF_AB_MD_RIC, 0, 1647 FRF_AB_MD_GC, 1); 1648 efx_writeo(efx, ®, FR_AB_MD_CS); 1649 1650 netif_dbg(efx, hw, efx->net_dev, 1651 "read from MDIO %d register %d.%d, got error %d\n", 1652 prtad, devad, addr, rc); 1653 } 1654 1655out: 1656 mutex_unlock(&nic_data->mdio_lock); 1657 return rc; 1658} 1659 1660/* This call is responsible for hooking in the MAC and PHY operations */ 1661static int falcon_probe_port(struct efx_nic *efx) 1662{ 1663 struct falcon_nic_data *nic_data = efx->nic_data; 1664 int rc; 1665 1666 switch (efx->phy_type) { 1667 case PHY_TYPE_SFX7101: 1668 efx->phy_op = &falcon_sfx7101_phy_ops; 1669 break; 1670 case PHY_TYPE_QT2022C2: 1671 case PHY_TYPE_QT2025C: 1672 efx->phy_op = &falcon_qt202x_phy_ops; 1673 break; 1674 case PHY_TYPE_TXC43128: 1675 efx->phy_op = &falcon_txc_phy_ops; 1676 break; 1677 default: 1678 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", 1679 efx->phy_type); 1680 return -ENODEV; 1681 } 1682 1683 /* Fill out MDIO structure and loopback modes */ 1684 mutex_init(&nic_data->mdio_lock); 1685 efx->mdio.mdio_read = falcon_mdio_read; 1686 efx->mdio.mdio_write = falcon_mdio_write; 1687 rc = efx->phy_op->probe(efx); 1688 if (rc != 0) 1689 return rc; 1690 1691 /* Initial assumption */ 1692 efx->link_state.speed = 10000; 1693 efx->link_state.fd = true; 1694 1695 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ 1696 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) 1697 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; 1698 else 1699 efx->wanted_fc = EFX_FC_RX; 1700 if (efx->mdio.mmds & MDIO_DEVS_AN) 1701 efx->wanted_fc |= EFX_FC_AUTO; 1702 1703 /* Allocate buffer for stats */ 1704 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, 1705 FALCON_MAC_STATS_SIZE, GFP_KERNEL); 1706 if (rc) 1707 return rc; 1708 netif_dbg(efx, probe, efx->net_dev, 1709 "stats buffer at %llx (virt %p phys %llx)\n", 1710 (u64)efx->stats_buffer.dma_addr, 1711 efx->stats_buffer.addr, 1712 (u64)virt_to_phys(efx->stats_buffer.addr)); 1713 1714 return 0; 1715} 1716 1717static void falcon_remove_port(struct efx_nic *efx) 1718{ 1719 efx->phy_op->remove(efx); 1720 efx_nic_free_buffer(efx, &efx->stats_buffer); 1721} 1722 1723/* Global events are basically PHY events */ 1724static bool 1725falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event) 1726{ 1727 struct efx_nic *efx = channel->efx; 1728 struct falcon_nic_data *nic_data = efx->nic_data; 1729 1730 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || 1731 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || 1732 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) 1733 /* Ignored */ 1734 return true; 1735 1736 if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) && 1737 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { 1738 nic_data->xmac_poll_required = true; 1739 return true; 1740 } 1741 1742 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 1743 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : 1744 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { 1745 netif_err(efx, rx_err, efx->net_dev, 1746 "channel %d seen global RX_RESET event. Resetting.\n", 1747 channel->channel); 1748 1749 atomic_inc(&efx->rx_reset); 1750 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? 1751 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); 1752 return true; 1753 } 1754 1755 return false; 1756} 1757 1758/************************************************************************** 1759 * 1760 * Falcon test code 1761 * 1762 **************************************************************************/ 1763 1764static int 1765falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) 1766{ 1767 struct falcon_nic_data *nic_data = efx->nic_data; 1768 struct falcon_nvconfig *nvconfig; 1769 struct falcon_spi_device *spi; 1770 void *region; 1771 int rc, magic_num, struct_ver; 1772 __le16 *word, *limit; 1773 u32 csum; 1774 1775 if (falcon_spi_present(&nic_data->spi_flash)) 1776 spi = &nic_data->spi_flash; 1777 else if (falcon_spi_present(&nic_data->spi_eeprom)) 1778 spi = &nic_data->spi_eeprom; 1779 else 1780 return -EINVAL; 1781 1782 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); 1783 if (!region) 1784 return -ENOMEM; 1785 nvconfig = region + FALCON_NVCONFIG_OFFSET; 1786 1787 mutex_lock(&nic_data->spi_lock); 1788 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); 1789 mutex_unlock(&nic_data->spi_lock); 1790 if (rc) { 1791 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", 1792 falcon_spi_present(&nic_data->spi_flash) ? 1793 "flash" : "EEPROM"); 1794 rc = -EIO; 1795 goto out; 1796 } 1797 1798 magic_num = le16_to_cpu(nvconfig->board_magic_num); 1799 struct_ver = le16_to_cpu(nvconfig->board_struct_ver); 1800 1801 rc = -EINVAL; 1802 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { 1803 netif_err(efx, hw, efx->net_dev, 1804 "NVRAM bad magic 0x%x\n", magic_num); 1805 goto out; 1806 } 1807 if (struct_ver < 2) { 1808 netif_err(efx, hw, efx->net_dev, 1809 "NVRAM has ancient version 0x%x\n", struct_ver); 1810 goto out; 1811 } else if (struct_ver < 4) { 1812 word = &nvconfig->board_magic_num; 1813 limit = (__le16 *) (nvconfig + 1); 1814 } else { 1815 word = region; 1816 limit = region + FALCON_NVCONFIG_END; 1817 } 1818 for (csum = 0; word < limit; ++word) 1819 csum += le16_to_cpu(*word); 1820 1821 if (~csum & 0xffff) { 1822 netif_err(efx, hw, efx->net_dev, 1823 "NVRAM has incorrect checksum\n"); 1824 goto out; 1825 } 1826 1827 rc = 0; 1828 if (nvconfig_out) 1829 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); 1830 1831 out: 1832 kfree(region); 1833 return rc; 1834} 1835 1836static int falcon_test_nvram(struct efx_nic *efx) 1837{ 1838 return falcon_read_nvram(efx, NULL); 1839} 1840 1841static const struct efx_farch_register_test falcon_b0_register_tests[] = { 1842 { FR_AZ_ADR_REGION, 1843 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, 1844 { FR_AZ_RX_CFG, 1845 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, 1846 { FR_AZ_TX_CFG, 1847 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, 1848 { FR_AZ_TX_RESERVED, 1849 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, 1850 { FR_AB_MAC_CTRL, 1851 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, 1852 { FR_AZ_SRM_TX_DC_CFG, 1853 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, 1854 { FR_AZ_RX_DC_CFG, 1855 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, 1856 { FR_AZ_RX_DC_PF_WM, 1857 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, 1858 { FR_BZ_DP_CTRL, 1859 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, 1860 { FR_AB_GM_CFG2, 1861 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, 1862 { FR_AB_GMF_CFG0, 1863 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, 1864 { FR_AB_XM_GLB_CFG, 1865 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, 1866 { FR_AB_XM_TX_CFG, 1867 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, 1868 { FR_AB_XM_RX_CFG, 1869 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, 1870 { FR_AB_XM_RX_PARAM, 1871 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, 1872 { FR_AB_XM_FC, 1873 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, 1874 { FR_AB_XM_ADR_LO, 1875 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, 1876 { FR_AB_XX_SD_CTL, 1877 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, 1878}; 1879 1880static int 1881falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 1882{ 1883 enum reset_type reset_method = RESET_TYPE_INVISIBLE; 1884 int rc, rc2; 1885 1886 mutex_lock(&efx->mac_lock); 1887 if (efx->loopback_modes) { 1888 /* We need the 312 clock from the PHY to test the XMAC 1889 * registers, so move into XGMII loopback if available */ 1890 if (efx->loopback_modes & (1 << LOOPBACK_XGMII)) 1891 efx->loopback_mode = LOOPBACK_XGMII; 1892 else 1893 efx->loopback_mode = __ffs(efx->loopback_modes); 1894 } 1895 __efx_reconfigure_port(efx); 1896 mutex_unlock(&efx->mac_lock); 1897 1898 efx_reset_down(efx, reset_method); 1899 1900 tests->registers = 1901 efx_farch_test_registers(efx, falcon_b0_register_tests, 1902 ARRAY_SIZE(falcon_b0_register_tests)) 1903 ? -1 : 1; 1904 1905 rc = falcon_reset_hw(efx, reset_method); 1906 rc2 = efx_reset_up(efx, reset_method, rc == 0); 1907 return rc ? rc : rc2; 1908} 1909 1910/************************************************************************** 1911 * 1912 * Device reset 1913 * 1914 ************************************************************************** 1915 */ 1916 1917static enum reset_type falcon_map_reset_reason(enum reset_type reason) 1918{ 1919 switch (reason) { 1920 case RESET_TYPE_RX_RECOVERY: 1921 case RESET_TYPE_DMA_ERROR: 1922 case RESET_TYPE_TX_SKIP: 1923 /* These can occasionally occur due to hardware bugs. 1924 * We try to reset without disrupting the link. 1925 */ 1926 return RESET_TYPE_INVISIBLE; 1927 default: 1928 return RESET_TYPE_ALL; 1929 } 1930} 1931 1932static int falcon_map_reset_flags(u32 *flags) 1933{ 1934 enum { 1935 FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER | 1936 ETH_RESET_OFFLOAD | ETH_RESET_MAC), 1937 FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY, 1938 FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ, 1939 }; 1940 1941 if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) { 1942 *flags &= ~FALCON_RESET_WORLD; 1943 return RESET_TYPE_WORLD; 1944 } 1945 1946 if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) { 1947 *flags &= ~FALCON_RESET_ALL; 1948 return RESET_TYPE_ALL; 1949 } 1950 1951 if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) { 1952 *flags &= ~FALCON_RESET_INVISIBLE; 1953 return RESET_TYPE_INVISIBLE; 1954 } 1955 1956 return -EINVAL; 1957} 1958 1959/* Resets NIC to known state. This routine must be called in process 1960 * context and is allowed to sleep. */ 1961static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method) 1962{ 1963 struct falcon_nic_data *nic_data = efx->nic_data; 1964 efx_oword_t glb_ctl_reg_ker; 1965 int rc; 1966 1967 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", 1968 RESET_TYPE(method)); 1969 1970 /* Initiate device reset */ 1971 if (method == RESET_TYPE_WORLD) { 1972 rc = pci_save_state(efx->pci_dev); 1973 if (rc) { 1974 netif_err(efx, drv, efx->net_dev, 1975 "failed to backup PCI state of primary " 1976 "function prior to hardware reset\n"); 1977 goto fail1; 1978 } 1979 if (efx_nic_is_dual_func(efx)) { 1980 rc = pci_save_state(nic_data->pci_dev2); 1981 if (rc) { 1982 netif_err(efx, drv, efx->net_dev, 1983 "failed to backup PCI state of " 1984 "secondary function prior to " 1985 "hardware reset\n"); 1986 goto fail2; 1987 } 1988 } 1989 1990 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, 1991 FRF_AB_EXT_PHY_RST_DUR, 1992 FFE_AB_EXT_PHY_RST_DUR_10240US, 1993 FRF_AB_SWRST, 1); 1994 } else { 1995 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, 1996 /* exclude PHY from "invisible" reset */ 1997 FRF_AB_EXT_PHY_RST_CTL, 1998 method == RESET_TYPE_INVISIBLE, 1999 /* exclude EEPROM/flash and PCIe */ 2000 FRF_AB_PCIE_CORE_RST_CTL, 1, 2001 FRF_AB_PCIE_NSTKY_RST_CTL, 1, 2002 FRF_AB_PCIE_SD_RST_CTL, 1, 2003 FRF_AB_EE_RST_CTL, 1, 2004 FRF_AB_EXT_PHY_RST_DUR, 2005 FFE_AB_EXT_PHY_RST_DUR_10240US, 2006 FRF_AB_SWRST, 1); 2007 } 2008 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); 2009 2010 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); 2011 schedule_timeout_uninterruptible(HZ / 20); 2012 2013 /* Restore PCI configuration if needed */ 2014 if (method == RESET_TYPE_WORLD) { 2015 if (efx_nic_is_dual_func(efx)) 2016 pci_restore_state(nic_data->pci_dev2); 2017 pci_restore_state(efx->pci_dev); 2018 netif_dbg(efx, drv, efx->net_dev, 2019 "successfully restored PCI config\n"); 2020 } 2021 2022 /* Assert that reset complete */ 2023 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); 2024 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { 2025 rc = -ETIMEDOUT; 2026 netif_err(efx, hw, efx->net_dev, 2027 "timed out waiting for hardware reset\n"); 2028 goto fail3; 2029 } 2030 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); 2031 2032 return 0; 2033 2034 /* pci_save_state() and pci_restore_state() MUST be called in pairs */ 2035fail2: 2036 pci_restore_state(efx->pci_dev); 2037fail1: 2038fail3: 2039 return rc; 2040} 2041 2042static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) 2043{ 2044 struct falcon_nic_data *nic_data = efx->nic_data; 2045 int rc; 2046 2047 mutex_lock(&nic_data->spi_lock); 2048 rc = __falcon_reset_hw(efx, method); 2049 mutex_unlock(&nic_data->spi_lock); 2050 2051 return rc; 2052} 2053 2054static void falcon_monitor(struct efx_nic *efx) 2055{ 2056 bool link_changed; 2057 int rc; 2058 2059 BUG_ON(!mutex_is_locked(&efx->mac_lock)); 2060 2061 rc = falcon_board(efx)->type->monitor(efx); 2062 if (rc) { 2063 netif_err(efx, hw, efx->net_dev, 2064 "Board sensor %s; shutting down PHY\n", 2065 (rc == -ERANGE) ? "reported fault" : "failed"); 2066 efx->phy_mode |= PHY_MODE_LOW_POWER; 2067 rc = __efx_reconfigure_port(efx); 2068 WARN_ON(rc); 2069 } 2070 2071 if (LOOPBACK_INTERNAL(efx)) 2072 link_changed = falcon_loopback_link_poll(efx); 2073 else 2074 link_changed = efx->phy_op->poll(efx); 2075 2076 if (link_changed) { 2077 falcon_stop_nic_stats(efx); 2078 falcon_deconfigure_mac_wrapper(efx); 2079 2080 falcon_reset_macs(efx); 2081 rc = falcon_reconfigure_xmac(efx); 2082 BUG_ON(rc); 2083 2084 falcon_start_nic_stats(efx); 2085 2086 efx_link_status_changed(efx); 2087 } 2088 2089 falcon_poll_xmac(efx); 2090} 2091 2092/* Zeroes out the SRAM contents. This routine must be called in 2093 * process context and is allowed to sleep. 2094 */ 2095static int falcon_reset_sram(struct efx_nic *efx) 2096{ 2097 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; 2098 int count; 2099 2100 /* Set the SRAM wake/sleep GPIO appropriately. */ 2101 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); 2102 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); 2103 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); 2104 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); 2105 2106 /* Initiate SRAM reset */ 2107 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, 2108 FRF_AZ_SRM_INIT_EN, 1, 2109 FRF_AZ_SRM_NB_SZ, 0); 2110 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); 2111 2112 /* Wait for SRAM reset to complete */ 2113 count = 0; 2114 do { 2115 netif_dbg(efx, hw, efx->net_dev, 2116 "waiting for SRAM reset (attempt %d)...\n", count); 2117 2118 /* SRAM reset is slow; expect around 16ms */ 2119 schedule_timeout_uninterruptible(HZ / 50); 2120 2121 /* Check for reset complete */ 2122 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); 2123 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { 2124 netif_dbg(efx, hw, efx->net_dev, 2125 "SRAM reset complete\n"); 2126 2127 return 0; 2128 } 2129 } while (++count < 20); /* wait up to 0.4 sec */ 2130 2131 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); 2132 return -ETIMEDOUT; 2133} 2134 2135static void falcon_spi_device_init(struct efx_nic *efx, 2136 struct falcon_spi_device *spi_device, 2137 unsigned int device_id, u32 device_type) 2138{ 2139 if (device_type != 0) { 2140 spi_device->device_id = device_id; 2141 spi_device->size = 2142 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); 2143 spi_device->addr_len = 2144 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); 2145 spi_device->munge_address = (spi_device->size == 1 << 9 && 2146 spi_device->addr_len == 1); 2147 spi_device->erase_command = 2148 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); 2149 spi_device->erase_size = 2150 1 << SPI_DEV_TYPE_FIELD(device_type, 2151 SPI_DEV_TYPE_ERASE_SIZE); 2152 spi_device->block_size = 2153 1 << SPI_DEV_TYPE_FIELD(device_type, 2154 SPI_DEV_TYPE_BLOCK_SIZE); 2155 } else { 2156 spi_device->size = 0; 2157 } 2158} 2159 2160/* Extract non-volatile configuration */ 2161static int falcon_probe_nvconfig(struct efx_nic *efx) 2162{ 2163 struct falcon_nic_data *nic_data = efx->nic_data; 2164 struct falcon_nvconfig *nvconfig; 2165 int rc; 2166 2167 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); 2168 if (!nvconfig) 2169 return -ENOMEM; 2170 2171 rc = falcon_read_nvram(efx, nvconfig); 2172 if (rc) 2173 goto out; 2174 2175 efx->phy_type = nvconfig->board_v2.port0_phy_type; 2176 efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr; 2177 2178 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { 2179 falcon_spi_device_init( 2180 efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH, 2181 le32_to_cpu(nvconfig->board_v3 2182 .spi_device_type[FFE_AB_SPI_DEVICE_FLASH])); 2183 falcon_spi_device_init( 2184 efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, 2185 le32_to_cpu(nvconfig->board_v3 2186 .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM])); 2187 } 2188 2189 /* Read the MAC addresses */ 2190 ether_addr_copy(efx->net_dev->perm_addr, nvconfig->mac_address[0]); 2191 2192 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", 2193 efx->phy_type, efx->mdio.prtad); 2194 2195 rc = falcon_probe_board(efx, 2196 le16_to_cpu(nvconfig->board_v2.board_revision)); 2197out: 2198 kfree(nvconfig); 2199 return rc; 2200} 2201 2202static int falcon_dimension_resources(struct efx_nic *efx) 2203{ 2204 efx->rx_dc_base = 0x20000; 2205 efx->tx_dc_base = 0x26000; 2206 return 0; 2207} 2208 2209/* Probe all SPI devices on the NIC */ 2210static void falcon_probe_spi_devices(struct efx_nic *efx) 2211{ 2212 struct falcon_nic_data *nic_data = efx->nic_data; 2213 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; 2214 int boot_dev; 2215 2216 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); 2217 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); 2218 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); 2219 2220 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { 2221 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? 2222 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); 2223 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", 2224 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? 2225 "flash" : "EEPROM"); 2226 } else { 2227 /* Disable VPD and set clock dividers to safe 2228 * values for initial programming. */ 2229 boot_dev = -1; 2230 netif_dbg(efx, probe, efx->net_dev, 2231 "Booted from internal ASIC settings;" 2232 " setting SPI config\n"); 2233 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, 2234 /* 125 MHz / 7 ~= 20 MHz */ 2235 FRF_AB_EE_SF_CLOCK_DIV, 7, 2236 /* 125 MHz / 63 ~= 2 MHz */ 2237 FRF_AB_EE_EE_CLOCK_DIV, 63); 2238 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); 2239 } 2240 2241 mutex_init(&nic_data->spi_lock); 2242 2243 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) 2244 falcon_spi_device_init(efx, &nic_data->spi_flash, 2245 FFE_AB_SPI_DEVICE_FLASH, 2246 default_flash_type); 2247 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) 2248 falcon_spi_device_init(efx, &nic_data->spi_eeprom, 2249 FFE_AB_SPI_DEVICE_EEPROM, 2250 large_eeprom_type); 2251} 2252 2253static unsigned int falcon_a1_mem_map_size(struct efx_nic *efx) 2254{ 2255 return 0x20000; 2256} 2257 2258static unsigned int falcon_b0_mem_map_size(struct efx_nic *efx) 2259{ 2260 /* Map everything up to and including the RSS indirection table. 2261 * The PCI core takes care of mapping the MSI-X tables. 2262 */ 2263 return FR_BZ_RX_INDIRECTION_TBL + 2264 FR_BZ_RX_INDIRECTION_TBL_STEP * FR_BZ_RX_INDIRECTION_TBL_ROWS; 2265} 2266 2267static int falcon_probe_nic(struct efx_nic *efx) 2268{ 2269 struct falcon_nic_data *nic_data; 2270 struct falcon_board *board; 2271 int rc; 2272 2273 efx->primary = efx; /* only one usable function per controller */ 2274 2275 /* Allocate storage for hardware specific data */ 2276 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 2277 if (!nic_data) 2278 return -ENOMEM; 2279 efx->nic_data = nic_data; 2280 2281 rc = -ENODEV; 2282 2283 if (efx_farch_fpga_ver(efx) != 0) { 2284 netif_err(efx, probe, efx->net_dev, 2285 "Falcon FPGA not supported\n"); 2286 goto fail1; 2287 } 2288 2289 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { 2290 efx_oword_t nic_stat; 2291 struct pci_dev *dev; 2292 u8 pci_rev = efx->pci_dev->revision; 2293 2294 if ((pci_rev == 0xff) || (pci_rev == 0)) { 2295 netif_err(efx, probe, efx->net_dev, 2296 "Falcon rev A0 not supported\n"); 2297 goto fail1; 2298 } 2299 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); 2300 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { 2301 netif_err(efx, probe, efx->net_dev, 2302 "Falcon rev A1 1G not supported\n"); 2303 goto fail1; 2304 } 2305 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { 2306 netif_err(efx, probe, efx->net_dev, 2307 "Falcon rev A1 PCI-X not supported\n"); 2308 goto fail1; 2309 } 2310 2311 dev = pci_dev_get(efx->pci_dev); 2312 while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE, 2313 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, 2314 dev))) { 2315 if (dev->bus == efx->pci_dev->bus && 2316 dev->devfn == efx->pci_dev->devfn + 1) { 2317 nic_data->pci_dev2 = dev; 2318 break; 2319 } 2320 } 2321 if (!nic_data->pci_dev2) { 2322 netif_err(efx, probe, efx->net_dev, 2323 "failed to find secondary function\n"); 2324 rc = -ENODEV; 2325 goto fail2; 2326 } 2327 } 2328 2329 /* Now we can reset the NIC */ 2330 rc = __falcon_reset_hw(efx, RESET_TYPE_ALL); 2331 if (rc) { 2332 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); 2333 goto fail3; 2334 } 2335 2336 /* Allocate memory for INT_KER */ 2337 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t), 2338 GFP_KERNEL); 2339 if (rc) 2340 goto fail4; 2341 BUG_ON(efx->irq_status.dma_addr & 0x0f); 2342 2343 netif_dbg(efx, probe, efx->net_dev, 2344 "INT_KER at %llx (virt %p phys %llx)\n", 2345 (u64)efx->irq_status.dma_addr, 2346 efx->irq_status.addr, 2347 (u64)virt_to_phys(efx->irq_status.addr)); 2348 2349 falcon_probe_spi_devices(efx); 2350 2351 /* Read in the non-volatile configuration */ 2352 rc = falcon_probe_nvconfig(efx); 2353 if (rc) { 2354 if (rc == -EINVAL) 2355 netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n"); 2356 goto fail5; 2357 } 2358 2359 efx->max_channels = (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? 4 : 2360 EFX_MAX_CHANNELS); 2361 efx->timer_quantum_ns = 4968; /* 621 cycles */ 2362 2363 /* Initialise I2C adapter */ 2364 board = falcon_board(efx); 2365 board->i2c_adap.owner = THIS_MODULE; 2366 board->i2c_data = falcon_i2c_bit_operations; 2367 board->i2c_data.data = efx; 2368 board->i2c_adap.algo_data = &board->i2c_data; 2369 board->i2c_adap.dev.parent = &efx->pci_dev->dev; 2370 strlcpy(board->i2c_adap.name, "SFC4000 GPIO", 2371 sizeof(board->i2c_adap.name)); 2372 rc = i2c_bit_add_bus(&board->i2c_adap); 2373 if (rc) 2374 goto fail5; 2375 2376 rc = falcon_board(efx)->type->init(efx); 2377 if (rc) { 2378 netif_err(efx, probe, efx->net_dev, 2379 "failed to initialise board\n"); 2380 goto fail6; 2381 } 2382 2383 nic_data->stats_disable_count = 1; 2384 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, 2385 (unsigned long)efx); 2386 2387 return 0; 2388 2389 fail6: 2390 i2c_del_adapter(&board->i2c_adap); 2391 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); 2392 fail5: 2393 efx_nic_free_buffer(efx, &efx->irq_status); 2394 fail4: 2395 fail3: 2396 if (nic_data->pci_dev2) { 2397 pci_dev_put(nic_data->pci_dev2); 2398 nic_data->pci_dev2 = NULL; 2399 } 2400 fail2: 2401 fail1: 2402 kfree(efx->nic_data); 2403 return rc; 2404} 2405 2406static void falcon_init_rx_cfg(struct efx_nic *efx) 2407{ 2408 /* RX control FIFO thresholds (32 entries) */ 2409 const unsigned ctrl_xon_thr = 20; 2410 const unsigned ctrl_xoff_thr = 25; 2411 efx_oword_t reg; 2412 2413 efx_reado(efx, ®, FR_AZ_RX_CFG); 2414 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { 2415 /* Data FIFO size is 5.5K. The RX DMA engine only 2416 * supports scattering for user-mode queues, but will 2417 * split DMA writes at intervals of RX_USR_BUF_SIZE 2418 * (32-byte units) even for kernel-mode queues. We 2419 * set it to be so large that that never happens. 2420 */ 2421 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); 2422 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, 2423 (3 * 4096) >> 5); 2424 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8); 2425 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8); 2426 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); 2427 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); 2428 } else { 2429 /* Data FIFO size is 80K; register fields moved */ 2430 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); 2431 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, 2432 EFX_RX_USR_BUF_SIZE >> 5); 2433 /* Send XON and XOFF at ~3 * max MTU away from empty/full */ 2434 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8); 2435 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8); 2436 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); 2437 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); 2438 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 2439 2440 /* Enable hash insertion. This is broken for the 2441 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and 2442 * IPv4 hashes. */ 2443 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); 2444 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); 2445 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); 2446 } 2447 /* Always enable XOFF signal from RX FIFO. We enable 2448 * or disable transmission of pause frames at the MAC. */ 2449 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); 2450 efx_writeo(efx, ®, FR_AZ_RX_CFG); 2451} 2452 2453/* This call performs hardware-specific global initialisation, such as 2454 * defining the descriptor cache sizes and number of RSS channels. 2455 * It does not set up any buffers, descriptor rings or event queues. 2456 */ 2457static int falcon_init_nic(struct efx_nic *efx) 2458{ 2459 efx_oword_t temp; 2460 int rc; 2461 2462 /* Use on-chip SRAM */ 2463 efx_reado(efx, &temp, FR_AB_NIC_STAT); 2464 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); 2465 efx_writeo(efx, &temp, FR_AB_NIC_STAT); 2466 2467 rc = falcon_reset_sram(efx); 2468 if (rc) 2469 return rc; 2470 2471 /* Clear the parity enables on the TX data fifos as 2472 * they produce false parity errors because of timing issues 2473 */ 2474 if (EFX_WORKAROUND_5129(efx)) { 2475 efx_reado(efx, &temp, FR_AZ_CSR_SPARE); 2476 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); 2477 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); 2478 } 2479 2480 if (EFX_WORKAROUND_7244(efx)) { 2481 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); 2482 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); 2483 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); 2484 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); 2485 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); 2486 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); 2487 } 2488 2489 /* XXX This is documented only for Falcon A0/A1 */ 2490 /* Setup RX. Wait for descriptor is broken and must 2491 * be disabled. RXDP recovery shouldn't be needed, but is. 2492 */ 2493 efx_reado(efx, &temp, FR_AA_RX_SELF_RST); 2494 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); 2495 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); 2496 if (EFX_WORKAROUND_5583(efx)) 2497 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); 2498 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); 2499 2500 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 2501 * descriptors (which is bad). 2502 */ 2503 efx_reado(efx, &temp, FR_AZ_TX_CFG); 2504 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); 2505 efx_writeo(efx, &temp, FR_AZ_TX_CFG); 2506 2507 falcon_init_rx_cfg(efx); 2508 2509 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { 2510 falcon_b0_rx_push_rss_config(efx); 2511 2512 /* Set destination of both TX and RX Flush events */ 2513 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); 2514 efx_writeo(efx, &temp, FR_BZ_DP_CTRL); 2515 } 2516 2517 efx_farch_init_common(efx); 2518 2519 return 0; 2520} 2521 2522static void falcon_remove_nic(struct efx_nic *efx) 2523{ 2524 struct falcon_nic_data *nic_data = efx->nic_data; 2525 struct falcon_board *board = falcon_board(efx); 2526 2527 board->type->fini(efx); 2528 2529 /* Remove I2C adapter and clear it in preparation for a retry */ 2530 i2c_del_adapter(&board->i2c_adap); 2531 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); 2532 2533 efx_nic_free_buffer(efx, &efx->irq_status); 2534 2535 __falcon_reset_hw(efx, RESET_TYPE_ALL); 2536 2537 /* Release the second function after the reset */ 2538 if (nic_data->pci_dev2) { 2539 pci_dev_put(nic_data->pci_dev2); 2540 nic_data->pci_dev2 = NULL; 2541 } 2542 2543 /* Tear down the private nic state */ 2544 kfree(efx->nic_data); 2545 efx->nic_data = NULL; 2546} 2547 2548static size_t falcon_describe_nic_stats(struct efx_nic *efx, u8 *names) 2549{ 2550 return efx_nic_describe_stats(falcon_stat_desc, FALCON_STAT_COUNT, 2551 falcon_stat_mask, names); 2552} 2553 2554static size_t falcon_update_nic_stats(struct efx_nic *efx, u64 *full_stats, 2555 struct rtnl_link_stats64 *core_stats) 2556{ 2557 struct falcon_nic_data *nic_data = efx->nic_data; 2558 u64 *stats = nic_data->stats; 2559 efx_oword_t cnt; 2560 2561 if (!nic_data->stats_disable_count) { 2562 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); 2563 stats[FALCON_STAT_rx_nodesc_drop_cnt] += 2564 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); 2565 2566 if (nic_data->stats_pending && 2567 FALCON_XMAC_STATS_DMA_FLAG(efx)) { 2568 nic_data->stats_pending = false; 2569 rmb(); /* read the done flag before the stats */ 2570 efx_nic_update_stats( 2571 falcon_stat_desc, FALCON_STAT_COUNT, 2572 falcon_stat_mask, 2573 stats, efx->stats_buffer.addr, true); 2574 } 2575 2576 /* Update derived statistic */ 2577 efx_update_diff_stat(&stats[FALCON_STAT_rx_bad_bytes], 2578 stats[FALCON_STAT_rx_bytes] - 2579 stats[FALCON_STAT_rx_good_bytes] - 2580 stats[FALCON_STAT_rx_control] * 64); 2581 efx_update_sw_stats(efx, stats); 2582 } 2583 2584 if (full_stats) 2585 memcpy(full_stats, stats, sizeof(u64) * FALCON_STAT_COUNT); 2586 2587 if (core_stats) { 2588 core_stats->rx_packets = stats[FALCON_STAT_rx_packets]; 2589 core_stats->tx_packets = stats[FALCON_STAT_tx_packets]; 2590 core_stats->rx_bytes = stats[FALCON_STAT_rx_bytes]; 2591 core_stats->tx_bytes = stats[FALCON_STAT_tx_bytes]; 2592 core_stats->rx_dropped = stats[FALCON_STAT_rx_nodesc_drop_cnt] + 2593 stats[GENERIC_STAT_rx_nodesc_trunc] + 2594 stats[GENERIC_STAT_rx_noskb_drops]; 2595 core_stats->multicast = stats[FALCON_STAT_rx_multicast]; 2596 core_stats->rx_length_errors = 2597 stats[FALCON_STAT_rx_gtjumbo] + 2598 stats[FALCON_STAT_rx_length_error]; 2599 core_stats->rx_crc_errors = stats[FALCON_STAT_rx_bad]; 2600 core_stats->rx_frame_errors = stats[FALCON_STAT_rx_align_error]; 2601 core_stats->rx_fifo_errors = stats[FALCON_STAT_rx_overflow]; 2602 2603 core_stats->rx_errors = (core_stats->rx_length_errors + 2604 core_stats->rx_crc_errors + 2605 core_stats->rx_frame_errors + 2606 stats[FALCON_STAT_rx_symbol_error]); 2607 } 2608 2609 return FALCON_STAT_COUNT; 2610} 2611 2612void falcon_start_nic_stats(struct efx_nic *efx) 2613{ 2614 struct falcon_nic_data *nic_data = efx->nic_data; 2615 2616 spin_lock_bh(&efx->stats_lock); 2617 if (--nic_data->stats_disable_count == 0) 2618 falcon_stats_request(efx); 2619 spin_unlock_bh(&efx->stats_lock); 2620} 2621 2622/* We don't acutally pull stats on falcon. Wait 10ms so that 2623 * they arrive when we call this just after start_stats 2624 */ 2625static void falcon_pull_nic_stats(struct efx_nic *efx) 2626{ 2627 msleep(10); 2628} 2629 2630void falcon_stop_nic_stats(struct efx_nic *efx) 2631{ 2632 struct falcon_nic_data *nic_data = efx->nic_data; 2633 int i; 2634 2635 might_sleep(); 2636 2637 spin_lock_bh(&efx->stats_lock); 2638 ++nic_data->stats_disable_count; 2639 spin_unlock_bh(&efx->stats_lock); 2640 2641 del_timer_sync(&nic_data->stats_timer); 2642 2643 /* Wait enough time for the most recent transfer to 2644 * complete. */ 2645 for (i = 0; i < 4 && nic_data->stats_pending; i++) { 2646 if (FALCON_XMAC_STATS_DMA_FLAG(efx)) 2647 break; 2648 msleep(1); 2649 } 2650 2651 spin_lock_bh(&efx->stats_lock); 2652 falcon_stats_complete(efx); 2653 spin_unlock_bh(&efx->stats_lock); 2654} 2655 2656static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) 2657{ 2658 falcon_board(efx)->type->set_id_led(efx, mode); 2659} 2660 2661/************************************************************************** 2662 * 2663 * Wake on LAN 2664 * 2665 ************************************************************************** 2666 */ 2667 2668static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 2669{ 2670 wol->supported = 0; 2671 wol->wolopts = 0; 2672 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2673} 2674 2675static int falcon_set_wol(struct efx_nic *efx, u32 type) 2676{ 2677 if (type != 0) 2678 return -EINVAL; 2679 return 0; 2680} 2681 2682/************************************************************************** 2683 * 2684 * Revision-dependent attributes used by efx.c and nic.c 2685 * 2686 ************************************************************************** 2687 */ 2688 2689const struct efx_nic_type falcon_a1_nic_type = { 2690 .mem_map_size = falcon_a1_mem_map_size, 2691 .probe = falcon_probe_nic, 2692 .remove = falcon_remove_nic, 2693 .init = falcon_init_nic, 2694 .dimension_resources = falcon_dimension_resources, 2695 .fini = falcon_irq_ack_a1, 2696 .monitor = falcon_monitor, 2697 .map_reset_reason = falcon_map_reset_reason, 2698 .map_reset_flags = falcon_map_reset_flags, 2699 .reset = falcon_reset_hw, 2700 .probe_port = falcon_probe_port, 2701 .remove_port = falcon_remove_port, 2702 .handle_global_event = falcon_handle_global_event, 2703 .fini_dmaq = efx_farch_fini_dmaq, 2704 .prepare_flush = falcon_prepare_flush, 2705 .finish_flush = efx_port_dummy_op_void, 2706 .prepare_flr = efx_port_dummy_op_void, 2707 .finish_flr = efx_farch_finish_flr, 2708 .describe_stats = falcon_describe_nic_stats, 2709 .update_stats = falcon_update_nic_stats, 2710 .start_stats = falcon_start_nic_stats, 2711 .pull_stats = falcon_pull_nic_stats, 2712 .stop_stats = falcon_stop_nic_stats, 2713 .set_id_led = falcon_set_id_led, 2714 .push_irq_moderation = falcon_push_irq_moderation, 2715 .reconfigure_port = falcon_reconfigure_port, 2716 .prepare_enable_fc_tx = falcon_a1_prepare_enable_fc_tx, 2717 .reconfigure_mac = falcon_reconfigure_xmac, 2718 .check_mac_fault = falcon_xmac_check_fault, 2719 .get_wol = falcon_get_wol, 2720 .set_wol = falcon_set_wol, 2721 .resume_wol = efx_port_dummy_op_void, 2722 .test_nvram = falcon_test_nvram, 2723 .irq_enable_master = efx_farch_irq_enable_master, 2724 .irq_test_generate = efx_farch_irq_test_generate, 2725 .irq_disable_non_ev = efx_farch_irq_disable_master, 2726 .irq_handle_msi = efx_farch_msi_interrupt, 2727 .irq_handle_legacy = falcon_legacy_interrupt_a1, 2728 .tx_probe = efx_farch_tx_probe, 2729 .tx_init = efx_farch_tx_init, 2730 .tx_remove = efx_farch_tx_remove, 2731 .tx_write = efx_farch_tx_write, 2732 .rx_push_rss_config = efx_port_dummy_op_void, 2733 .rx_probe = efx_farch_rx_probe, 2734 .rx_init = efx_farch_rx_init, 2735 .rx_remove = efx_farch_rx_remove, 2736 .rx_write = efx_farch_rx_write, 2737 .rx_defer_refill = efx_farch_rx_defer_refill, 2738 .ev_probe = efx_farch_ev_probe, 2739 .ev_init = efx_farch_ev_init, 2740 .ev_fini = efx_farch_ev_fini, 2741 .ev_remove = efx_farch_ev_remove, 2742 .ev_process = efx_farch_ev_process, 2743 .ev_read_ack = efx_farch_ev_read_ack, 2744 .ev_test_generate = efx_farch_ev_test_generate, 2745 2746 /* We don't expose the filter table on Falcon A1 as it is not 2747 * mapped into function 0, but these implementations still 2748 * work with a degenerate case of all tables set to size 0. 2749 */ 2750 .filter_table_probe = efx_farch_filter_table_probe, 2751 .filter_table_restore = efx_farch_filter_table_restore, 2752 .filter_table_remove = efx_farch_filter_table_remove, 2753 .filter_insert = efx_farch_filter_insert, 2754 .filter_remove_safe = efx_farch_filter_remove_safe, 2755 .filter_get_safe = efx_farch_filter_get_safe, 2756 .filter_clear_rx = efx_farch_filter_clear_rx, 2757 .filter_count_rx_used = efx_farch_filter_count_rx_used, 2758 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit, 2759 .filter_get_rx_ids = efx_farch_filter_get_rx_ids, 2760 2761#ifdef CONFIG_SFC_MTD 2762 .mtd_probe = falcon_mtd_probe, 2763 .mtd_rename = falcon_mtd_rename, 2764 .mtd_read = falcon_mtd_read, 2765 .mtd_erase = falcon_mtd_erase, 2766 .mtd_write = falcon_mtd_write, 2767 .mtd_sync = falcon_mtd_sync, 2768#endif 2769 .sriov_init = efx_falcon_sriov_init, 2770 .sriov_fini = efx_falcon_sriov_fini, 2771 .sriov_mac_address_changed = efx_falcon_sriov_mac_address_changed, 2772 .sriov_wanted = efx_falcon_sriov_wanted, 2773 .sriov_reset = efx_falcon_sriov_reset, 2774 2775 .revision = EFX_REV_FALCON_A1, 2776 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, 2777 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, 2778 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, 2779 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, 2780 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, 2781 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), 2782 .rx_buffer_padding = 0x24, 2783 .can_rx_scatter = false, 2784 .max_interrupt_mode = EFX_INT_MODE_MSI, 2785 .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, 2786 .offload_features = NETIF_F_IP_CSUM, 2787 .mcdi_max_ver = -1, 2788}; 2789 2790const struct efx_nic_type falcon_b0_nic_type = { 2791 .mem_map_size = falcon_b0_mem_map_size, 2792 .probe = falcon_probe_nic, 2793 .remove = falcon_remove_nic, 2794 .init = falcon_init_nic, 2795 .dimension_resources = falcon_dimension_resources, 2796 .fini = efx_port_dummy_op_void, 2797 .monitor = falcon_monitor, 2798 .map_reset_reason = falcon_map_reset_reason, 2799 .map_reset_flags = falcon_map_reset_flags, 2800 .reset = falcon_reset_hw, 2801 .probe_port = falcon_probe_port, 2802 .remove_port = falcon_remove_port, 2803 .handle_global_event = falcon_handle_global_event, 2804 .fini_dmaq = efx_farch_fini_dmaq, 2805 .prepare_flush = falcon_prepare_flush, 2806 .finish_flush = efx_port_dummy_op_void, 2807 .prepare_flr = efx_port_dummy_op_void, 2808 .finish_flr = efx_farch_finish_flr, 2809 .describe_stats = falcon_describe_nic_stats, 2810 .update_stats = falcon_update_nic_stats, 2811 .start_stats = falcon_start_nic_stats, 2812 .pull_stats = falcon_pull_nic_stats, 2813 .stop_stats = falcon_stop_nic_stats, 2814 .set_id_led = falcon_set_id_led, 2815 .push_irq_moderation = falcon_push_irq_moderation, 2816 .reconfigure_port = falcon_reconfigure_port, 2817 .prepare_enable_fc_tx = falcon_b0_prepare_enable_fc_tx, 2818 .reconfigure_mac = falcon_reconfigure_xmac, 2819 .check_mac_fault = falcon_xmac_check_fault, 2820 .get_wol = falcon_get_wol, 2821 .set_wol = falcon_set_wol, 2822 .resume_wol = efx_port_dummy_op_void, 2823 .test_chip = falcon_b0_test_chip, 2824 .test_nvram = falcon_test_nvram, 2825 .irq_enable_master = efx_farch_irq_enable_master, 2826 .irq_test_generate = efx_farch_irq_test_generate, 2827 .irq_disable_non_ev = efx_farch_irq_disable_master, 2828 .irq_handle_msi = efx_farch_msi_interrupt, 2829 .irq_handle_legacy = efx_farch_legacy_interrupt, 2830 .tx_probe = efx_farch_tx_probe, 2831 .tx_init = efx_farch_tx_init, 2832 .tx_remove = efx_farch_tx_remove, 2833 .tx_write = efx_farch_tx_write, 2834 .rx_push_rss_config = falcon_b0_rx_push_rss_config, 2835 .rx_probe = efx_farch_rx_probe, 2836 .rx_init = efx_farch_rx_init, 2837 .rx_remove = efx_farch_rx_remove, 2838 .rx_write = efx_farch_rx_write, 2839 .rx_defer_refill = efx_farch_rx_defer_refill, 2840 .ev_probe = efx_farch_ev_probe, 2841 .ev_init = efx_farch_ev_init, 2842 .ev_fini = efx_farch_ev_fini, 2843 .ev_remove = efx_farch_ev_remove, 2844 .ev_process = efx_farch_ev_process, 2845 .ev_read_ack = efx_farch_ev_read_ack, 2846 .ev_test_generate = efx_farch_ev_test_generate, 2847 .filter_table_probe = efx_farch_filter_table_probe, 2848 .filter_table_restore = efx_farch_filter_table_restore, 2849 .filter_table_remove = efx_farch_filter_table_remove, 2850 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter, 2851 .filter_insert = efx_farch_filter_insert, 2852 .filter_remove_safe = efx_farch_filter_remove_safe, 2853 .filter_get_safe = efx_farch_filter_get_safe, 2854 .filter_clear_rx = efx_farch_filter_clear_rx, 2855 .filter_count_rx_used = efx_farch_filter_count_rx_used, 2856 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit, 2857 .filter_get_rx_ids = efx_farch_filter_get_rx_ids, 2858#ifdef CONFIG_RFS_ACCEL 2859 .filter_rfs_insert = efx_farch_filter_rfs_insert, 2860 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one, 2861#endif 2862#ifdef CONFIG_SFC_MTD 2863 .mtd_probe = falcon_mtd_probe, 2864 .mtd_rename = falcon_mtd_rename, 2865 .mtd_read = falcon_mtd_read, 2866 .mtd_erase = falcon_mtd_erase, 2867 .mtd_write = falcon_mtd_write, 2868 .mtd_sync = falcon_mtd_sync, 2869#endif 2870 .sriov_init = efx_falcon_sriov_init, 2871 .sriov_fini = efx_falcon_sriov_fini, 2872 .sriov_mac_address_changed = efx_falcon_sriov_mac_address_changed, 2873 .sriov_wanted = efx_falcon_sriov_wanted, 2874 .sriov_reset = efx_falcon_sriov_reset, 2875 2876 .revision = EFX_REV_FALCON_B0, 2877 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, 2878 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, 2879 .buf_tbl_base = FR_BZ_BUF_FULL_TBL, 2880 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, 2881 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, 2882 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), 2883 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE, 2884 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST, 2885 .rx_buffer_padding = 0, 2886 .can_rx_scatter = true, 2887 .max_interrupt_mode = EFX_INT_MODE_MSIX, 2888 .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, 2889 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE, 2890 .mcdi_max_ver = -1, 2891 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS, 2892}; 2893