1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11#include <linux/bitops.h> 12#include <linux/delay.h> 13#include <linux/pci.h> 14#include <linux/module.h> 15#include <linux/slab.h> 16#include <linux/random.h> 17#include "net_driver.h" 18#include "bitfield.h" 19#include "efx.h" 20#include "nic.h" 21#include "farch_regs.h" 22#include "io.h" 23#include "phy.h" 24#include "workarounds.h" 25#include "mcdi.h" 26#include "mcdi_pcol.h" 27#include "selftest.h" 28 29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ 30 31static void siena_init_wol(struct efx_nic *efx); 32 33 34static void siena_push_irq_moderation(struct efx_channel *channel) 35{ 36 efx_dword_t timer_cmd; 37 38 if (channel->irq_moderation) 39 EFX_POPULATE_DWORD_2(timer_cmd, 40 FRF_CZ_TC_TIMER_MODE, 41 FFE_CZ_TIMER_MODE_INT_HLDOFF, 42 FRF_CZ_TC_TIMER_VAL, 43 channel->irq_moderation - 1); 44 else 45 EFX_POPULATE_DWORD_2(timer_cmd, 46 FRF_CZ_TC_TIMER_MODE, 47 FFE_CZ_TIMER_MODE_DIS, 48 FRF_CZ_TC_TIMER_VAL, 0); 49 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, 50 channel->channel); 51} 52 53void siena_prepare_flush(struct efx_nic *efx) 54{ 55 if (efx->fc_disable++ == 0) 56 efx_mcdi_set_mac(efx); 57} 58 59void siena_finish_flush(struct efx_nic *efx) 60{ 61 if (--efx->fc_disable == 0) 62 efx_mcdi_set_mac(efx); 63} 64 65static const struct efx_farch_register_test siena_register_tests[] = { 66 { FR_AZ_ADR_REGION, 67 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, 68 { FR_CZ_USR_EV_CFG, 69 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, 70 { FR_AZ_RX_CFG, 71 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, 72 { FR_AZ_TX_CFG, 73 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, 74 { FR_AZ_TX_RESERVED, 75 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, 76 { FR_AZ_SRM_TX_DC_CFG, 77 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, 78 { FR_AZ_RX_DC_CFG, 79 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, 80 { FR_AZ_RX_DC_PF_WM, 81 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, 82 { FR_BZ_DP_CTRL, 83 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, 84 { FR_BZ_RX_RSS_TKEY, 85 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, 86 { FR_CZ_RX_RSS_IPV6_REG1, 87 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, 88 { FR_CZ_RX_RSS_IPV6_REG2, 89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, 90 { FR_CZ_RX_RSS_IPV6_REG3, 91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, 92}; 93 94static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 95{ 96 enum reset_type reset_method = RESET_TYPE_ALL; 97 int rc, rc2; 98 99 efx_reset_down(efx, reset_method); 100 101 /* Reset the chip immediately so that it is completely 102 * quiescent regardless of what any VF driver does. 103 */ 104 rc = efx_mcdi_reset(efx, reset_method); 105 if (rc) 106 goto out; 107 108 tests->registers = 109 efx_farch_test_registers(efx, siena_register_tests, 110 ARRAY_SIZE(siena_register_tests)) 111 ? -1 : 1; 112 113 rc = efx_mcdi_reset(efx, reset_method); 114out: 115 rc2 = efx_reset_up(efx, reset_method, rc == 0); 116 return rc ? rc : rc2; 117} 118 119/************************************************************************** 120 * 121 * PTP 122 * 123 ************************************************************************** 124 */ 125 126static void siena_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 127{ 128 _efx_writed(efx, cpu_to_le32(host_time), 129 FR_CZ_MC_TREG_SMEM + MC_SMEM_P0_PTP_TIME_OFST); 130} 131 132static int siena_ptp_set_ts_config(struct efx_nic *efx, 133 struct hwtstamp_config *init) 134{ 135 int rc; 136 137 switch (init->rx_filter) { 138 case HWTSTAMP_FILTER_NONE: 139 /* if TX timestamping is still requested then leave PTP on */ 140 return efx_ptp_change_mode(efx, 141 init->tx_type != HWTSTAMP_TX_OFF, 142 efx_ptp_get_mode(efx)); 143 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 144 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 145 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 146 init->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 147 return efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V1); 148 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 149 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 150 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 151 init->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 152 rc = efx_ptp_change_mode(efx, true, 153 MC_CMD_PTP_MODE_V2_ENHANCED); 154 /* bug 33070 - old versions of the firmware do not support the 155 * improved UUID filtering option. Similarly old versions of the 156 * application do not expect it to be enabled. If the firmware 157 * does not accept the enhanced mode, fall back to the standard 158 * PTP v2 UUID filtering. */ 159 if (rc != 0) 160 rc = efx_ptp_change_mode(efx, true, MC_CMD_PTP_MODE_V2); 161 return rc; 162 default: 163 return -ERANGE; 164 } 165} 166 167/************************************************************************** 168 * 169 * Device reset 170 * 171 ************************************************************************** 172 */ 173 174static int siena_map_reset_flags(u32 *flags) 175{ 176 enum { 177 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER | 178 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 179 ETH_RESET_PHY), 180 SIENA_RESET_MC = (SIENA_RESET_PORT | 181 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT), 182 }; 183 184 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) { 185 *flags &= ~SIENA_RESET_MC; 186 return RESET_TYPE_WORLD; 187 } 188 189 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) { 190 *flags &= ~SIENA_RESET_PORT; 191 return RESET_TYPE_ALL; 192 } 193 194 /* no invisible reset implemented */ 195 196 return -EINVAL; 197} 198 199#ifdef CONFIG_EEH 200/* When a PCI device is isolated from the bus, a subsequent MMIO read is 201 * required for the kernel EEH mechanisms to notice. As the Solarflare driver 202 * was written to minimise MMIO read (for latency) then a periodic call to check 203 * the EEH status of the device is required so that device recovery can happen 204 * in a timely fashion. 205 */ 206static void siena_monitor(struct efx_nic *efx) 207{ 208 struct eeh_dev *eehdev = pci_dev_to_eeh_dev(efx->pci_dev); 209 210 eeh_dev_check_failure(eehdev); 211} 212#endif 213 214static int siena_probe_nvconfig(struct efx_nic *efx) 215{ 216 u32 caps = 0; 217 int rc; 218 219 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps); 220 221 efx->timer_quantum_ns = 222 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ? 223 3072 : 6144; /* 768 cycles */ 224 return rc; 225} 226 227static int siena_dimension_resources(struct efx_nic *efx) 228{ 229 /* Each port has a small block of internal SRAM dedicated to 230 * the buffer table and descriptor caches. In theory we can 231 * map both blocks to one port, but we don't. 232 */ 233 efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2); 234 return 0; 235} 236 237static unsigned int siena_mem_map_size(struct efx_nic *efx) 238{ 239 return FR_CZ_MC_TREG_SMEM + 240 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS; 241} 242 243static int siena_probe_nic(struct efx_nic *efx) 244{ 245 struct siena_nic_data *nic_data; 246 efx_oword_t reg; 247 int rc; 248 249 /* Allocate storage for hardware specific data */ 250 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); 251 if (!nic_data) 252 return -ENOMEM; 253 nic_data->efx = efx; 254 efx->nic_data = nic_data; 255 256 if (efx_farch_fpga_ver(efx) != 0) { 257 netif_err(efx, probe, efx->net_dev, 258 "Siena FPGA not supported\n"); 259 rc = -ENODEV; 260 goto fail1; 261 } 262 263 efx->max_channels = EFX_MAX_CHANNELS; 264 265 efx_reado(efx, ®, FR_AZ_CS_DEBUG); 266 efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; 267 268 rc = efx_mcdi_init(efx); 269 if (rc) 270 goto fail1; 271 272 /* Now we can reset the NIC */ 273 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 274 if (rc) { 275 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); 276 goto fail3; 277 } 278 279 siena_init_wol(efx); 280 281 /* Allocate memory for INT_KER */ 282 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t), 283 GFP_KERNEL); 284 if (rc) 285 goto fail4; 286 BUG_ON(efx->irq_status.dma_addr & 0x0f); 287 288 netif_dbg(efx, probe, efx->net_dev, 289 "INT_KER at %llx (virt %p phys %llx)\n", 290 (unsigned long long)efx->irq_status.dma_addr, 291 efx->irq_status.addr, 292 (unsigned long long)virt_to_phys(efx->irq_status.addr)); 293 294 /* Read in the non-volatile configuration */ 295 rc = siena_probe_nvconfig(efx); 296 if (rc == -EINVAL) { 297 netif_err(efx, probe, efx->net_dev, 298 "NVRAM is invalid therefore using defaults\n"); 299 efx->phy_type = PHY_TYPE_NONE; 300 efx->mdio.prtad = MDIO_PRTAD_NONE; 301 } else if (rc) { 302 goto fail5; 303 } 304 305 rc = efx_mcdi_mon_probe(efx); 306 if (rc) 307 goto fail5; 308 309 efx_siena_sriov_probe(efx); 310 efx_ptp_defer_probe_with_channel(efx); 311 312 return 0; 313 314fail5: 315 efx_nic_free_buffer(efx, &efx->irq_status); 316fail4: 317fail3: 318 efx_mcdi_fini(efx); 319fail1: 320 kfree(efx->nic_data); 321 return rc; 322} 323 324static void siena_rx_push_rss_config(struct efx_nic *efx) 325{ 326 efx_oword_t temp; 327 328 /* Set hash key for IPv4 */ 329 memcpy(&temp, efx->rx_hash_key, sizeof(temp)); 330 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); 331 332 /* Enable IPv6 RSS */ 333 BUILD_BUG_ON(sizeof(efx->rx_hash_key) < 334 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || 335 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); 336 memcpy(&temp, efx->rx_hash_key, sizeof(temp)); 337 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); 338 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp)); 339 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); 340 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, 341 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); 342 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp), 343 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); 344 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); 345 346 efx_farch_rx_push_indir_table(efx); 347} 348 349/* This call performs hardware-specific global initialisation, such as 350 * defining the descriptor cache sizes and number of RSS channels. 351 * It does not set up any buffers, descriptor rings or event queues. 352 */ 353static int siena_init_nic(struct efx_nic *efx) 354{ 355 efx_oword_t temp; 356 int rc; 357 358 /* Recover from a failed assertion post-reset */ 359 rc = efx_mcdi_handle_assertion(efx); 360 if (rc) 361 return rc; 362 363 /* Squash TX of packets of 16 bytes or less */ 364 efx_reado(efx, &temp, FR_AZ_TX_RESERVED); 365 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); 366 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); 367 368 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 369 * descriptors (which is bad). 370 */ 371 efx_reado(efx, &temp, FR_AZ_TX_CFG); 372 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); 373 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); 374 efx_writeo(efx, &temp, FR_AZ_TX_CFG); 375 376 efx_reado(efx, &temp, FR_AZ_RX_CFG); 377 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); 378 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); 379 /* Enable hash insertion. This is broken for the 'Falcon' hash 380 * if IPv6 hashing is also enabled, so also select Toeplitz 381 * TCP/IPv4 and IPv4 hashes. */ 382 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1); 383 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1); 384 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1); 385 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE, 386 EFX_RX_USR_BUF_SIZE >> 5); 387 efx_writeo(efx, &temp, FR_AZ_RX_CFG); 388 389 siena_rx_push_rss_config(efx); 390 391 /* Enable event logging */ 392 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 393 if (rc) 394 return rc; 395 396 /* Set destination of both TX and RX Flush events */ 397 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); 398 efx_writeo(efx, &temp, FR_BZ_DP_CTRL); 399 400 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); 401 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); 402 403 efx_farch_init_common(efx); 404 return 0; 405} 406 407static void siena_remove_nic(struct efx_nic *efx) 408{ 409 efx_mcdi_mon_remove(efx); 410 411 efx_nic_free_buffer(efx, &efx->irq_status); 412 413 efx_mcdi_reset(efx, RESET_TYPE_ALL); 414 415 efx_mcdi_fini(efx); 416 417 /* Tear down the private nic state */ 418 kfree(efx->nic_data); 419 efx->nic_data = NULL; 420} 421 422#define SIENA_DMA_STAT(ext_name, mcdi_name) \ 423 [SIENA_STAT_ ## ext_name] = \ 424 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 425#define SIENA_OTHER_STAT(ext_name) \ 426 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 } 427#define GENERIC_SW_STAT(ext_name) \ 428 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 429 430static const struct efx_hw_stat_desc siena_stat_desc[SIENA_STAT_COUNT] = { 431 SIENA_DMA_STAT(tx_bytes, TX_BYTES), 432 SIENA_OTHER_STAT(tx_good_bytes), 433 SIENA_DMA_STAT(tx_bad_bytes, TX_BAD_BYTES), 434 SIENA_DMA_STAT(tx_packets, TX_PKTS), 435 SIENA_DMA_STAT(tx_bad, TX_BAD_FCS_PKTS), 436 SIENA_DMA_STAT(tx_pause, TX_PAUSE_PKTS), 437 SIENA_DMA_STAT(tx_control, TX_CONTROL_PKTS), 438 SIENA_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), 439 SIENA_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), 440 SIENA_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), 441 SIENA_DMA_STAT(tx_lt64, TX_LT64_PKTS), 442 SIENA_DMA_STAT(tx_64, TX_64_PKTS), 443 SIENA_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), 444 SIENA_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), 445 SIENA_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), 446 SIENA_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), 447 SIENA_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 448 SIENA_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 449 SIENA_DMA_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS), 450 SIENA_OTHER_STAT(tx_collision), 451 SIENA_DMA_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS), 452 SIENA_DMA_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS), 453 SIENA_DMA_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS), 454 SIENA_DMA_STAT(tx_deferred, TX_DEFERRED_PKTS), 455 SIENA_DMA_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS), 456 SIENA_DMA_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS), 457 SIENA_DMA_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS), 458 SIENA_DMA_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS), 459 SIENA_DMA_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS), 460 SIENA_DMA_STAT(rx_bytes, RX_BYTES), 461 SIENA_OTHER_STAT(rx_good_bytes), 462 SIENA_DMA_STAT(rx_bad_bytes, RX_BAD_BYTES), 463 SIENA_DMA_STAT(rx_packets, RX_PKTS), 464 SIENA_DMA_STAT(rx_good, RX_GOOD_PKTS), 465 SIENA_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), 466 SIENA_DMA_STAT(rx_pause, RX_PAUSE_PKTS), 467 SIENA_DMA_STAT(rx_control, RX_CONTROL_PKTS), 468 SIENA_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), 469 SIENA_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), 470 SIENA_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), 471 SIENA_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), 472 SIENA_DMA_STAT(rx_64, RX_64_PKTS), 473 SIENA_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), 474 SIENA_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), 475 SIENA_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), 476 SIENA_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), 477 SIENA_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 478 SIENA_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 479 SIENA_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), 480 SIENA_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), 481 SIENA_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), 482 SIENA_DMA_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS), 483 SIENA_DMA_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS), 484 SIENA_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), 485 SIENA_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), 486 SIENA_DMA_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS), 487 SIENA_DMA_STAT(rx_nodesc_drop_cnt, RX_NODESC_DROPS), 488 GENERIC_SW_STAT(rx_nodesc_trunc), 489 GENERIC_SW_STAT(rx_noskb_drops), 490}; 491static const unsigned long siena_stat_mask[] = { 492 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL, 493}; 494 495static size_t siena_describe_nic_stats(struct efx_nic *efx, u8 *names) 496{ 497 return efx_nic_describe_stats(siena_stat_desc, SIENA_STAT_COUNT, 498 siena_stat_mask, names); 499} 500 501static int siena_try_update_nic_stats(struct efx_nic *efx) 502{ 503 struct siena_nic_data *nic_data = efx->nic_data; 504 u64 *stats = nic_data->stats; 505 __le64 *dma_stats; 506 __le64 generation_start, generation_end; 507 508 dma_stats = efx->stats_buffer.addr; 509 510 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 511 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 512 return 0; 513 rmb(); 514 efx_nic_update_stats(siena_stat_desc, SIENA_STAT_COUNT, siena_stat_mask, 515 stats, efx->stats_buffer.addr, false); 516 rmb(); 517 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 518 if (generation_end != generation_start) 519 return -EAGAIN; 520 521 /* Update derived statistics */ 522 efx_nic_fix_nodesc_drop_stat(efx, 523 &stats[SIENA_STAT_rx_nodesc_drop_cnt]); 524 efx_update_diff_stat(&stats[SIENA_STAT_tx_good_bytes], 525 stats[SIENA_STAT_tx_bytes] - 526 stats[SIENA_STAT_tx_bad_bytes]); 527 stats[SIENA_STAT_tx_collision] = 528 stats[SIENA_STAT_tx_single_collision] + 529 stats[SIENA_STAT_tx_multiple_collision] + 530 stats[SIENA_STAT_tx_excessive_collision] + 531 stats[SIENA_STAT_tx_late_collision]; 532 efx_update_diff_stat(&stats[SIENA_STAT_rx_good_bytes], 533 stats[SIENA_STAT_rx_bytes] - 534 stats[SIENA_STAT_rx_bad_bytes]); 535 efx_update_sw_stats(efx, stats); 536 return 0; 537} 538 539static size_t siena_update_nic_stats(struct efx_nic *efx, u64 *full_stats, 540 struct rtnl_link_stats64 *core_stats) 541{ 542 struct siena_nic_data *nic_data = efx->nic_data; 543 u64 *stats = nic_data->stats; 544 int retry; 545 546 /* If we're unlucky enough to read statistics wduring the DMA, wait 547 * up to 10ms for it to finish (typically takes <500us) */ 548 for (retry = 0; retry < 100; ++retry) { 549 if (siena_try_update_nic_stats(efx) == 0) 550 break; 551 udelay(100); 552 } 553 554 if (full_stats) 555 memcpy(full_stats, stats, sizeof(u64) * SIENA_STAT_COUNT); 556 557 if (core_stats) { 558 core_stats->rx_packets = stats[SIENA_STAT_rx_packets]; 559 core_stats->tx_packets = stats[SIENA_STAT_tx_packets]; 560 core_stats->rx_bytes = stats[SIENA_STAT_rx_bytes]; 561 core_stats->tx_bytes = stats[SIENA_STAT_tx_bytes]; 562 core_stats->rx_dropped = stats[SIENA_STAT_rx_nodesc_drop_cnt] + 563 stats[GENERIC_STAT_rx_nodesc_trunc] + 564 stats[GENERIC_STAT_rx_noskb_drops]; 565 core_stats->multicast = stats[SIENA_STAT_rx_multicast]; 566 core_stats->collisions = stats[SIENA_STAT_tx_collision]; 567 core_stats->rx_length_errors = 568 stats[SIENA_STAT_rx_gtjumbo] + 569 stats[SIENA_STAT_rx_length_error]; 570 core_stats->rx_crc_errors = stats[SIENA_STAT_rx_bad]; 571 core_stats->rx_frame_errors = stats[SIENA_STAT_rx_align_error]; 572 core_stats->rx_fifo_errors = stats[SIENA_STAT_rx_overflow]; 573 core_stats->tx_window_errors = 574 stats[SIENA_STAT_tx_late_collision]; 575 576 core_stats->rx_errors = (core_stats->rx_length_errors + 577 core_stats->rx_crc_errors + 578 core_stats->rx_frame_errors + 579 stats[SIENA_STAT_rx_symbol_error]); 580 core_stats->tx_errors = (core_stats->tx_window_errors + 581 stats[SIENA_STAT_tx_bad]); 582 } 583 584 return SIENA_STAT_COUNT; 585} 586 587static int siena_mac_reconfigure(struct efx_nic *efx) 588{ 589 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN); 590 int rc; 591 592 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN != 593 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST + 594 sizeof(efx->multicast_hash)); 595 596 efx_farch_filter_sync_rx_mode(efx); 597 598 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 599 600 rc = efx_mcdi_set_mac(efx); 601 if (rc != 0) 602 return rc; 603 604 memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0), 605 efx->multicast_hash.byte, sizeof(efx->multicast_hash)); 606 return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH, 607 inbuf, sizeof(inbuf), NULL, 0, NULL); 608} 609 610/************************************************************************** 611 * 612 * Wake on LAN 613 * 614 ************************************************************************** 615 */ 616 617static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 618{ 619 struct siena_nic_data *nic_data = efx->nic_data; 620 621 wol->supported = WAKE_MAGIC; 622 if (nic_data->wol_filter_id != -1) 623 wol->wolopts = WAKE_MAGIC; 624 else 625 wol->wolopts = 0; 626 memset(&wol->sopass, 0, sizeof(wol->sopass)); 627} 628 629 630static int siena_set_wol(struct efx_nic *efx, u32 type) 631{ 632 struct siena_nic_data *nic_data = efx->nic_data; 633 int rc; 634 635 if (type & ~WAKE_MAGIC) 636 return -EINVAL; 637 638 if (type & WAKE_MAGIC) { 639 if (nic_data->wol_filter_id != -1) 640 efx_mcdi_wol_filter_remove(efx, 641 nic_data->wol_filter_id); 642 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr, 643 &nic_data->wol_filter_id); 644 if (rc) 645 goto fail; 646 647 pci_wake_from_d3(efx->pci_dev, true); 648 } else { 649 rc = efx_mcdi_wol_filter_reset(efx); 650 nic_data->wol_filter_id = -1; 651 pci_wake_from_d3(efx->pci_dev, false); 652 if (rc) 653 goto fail; 654 } 655 656 return 0; 657 fail: 658 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n", 659 __func__, type, rc); 660 return rc; 661} 662 663 664static void siena_init_wol(struct efx_nic *efx) 665{ 666 struct siena_nic_data *nic_data = efx->nic_data; 667 int rc; 668 669 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); 670 671 if (rc != 0) { 672 /* If it failed, attempt to get into a synchronised 673 * state with MC by resetting any set WoL filters */ 674 efx_mcdi_wol_filter_reset(efx); 675 nic_data->wol_filter_id = -1; 676 } else if (nic_data->wol_filter_id != -1) { 677 pci_wake_from_d3(efx->pci_dev, true); 678 } 679} 680 681/************************************************************************** 682 * 683 * MCDI 684 * 685 ************************************************************************** 686 */ 687 688#define MCDI_PDU(efx) \ 689 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST) 690#define MCDI_DOORBELL(efx) \ 691 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST) 692#define MCDI_STATUS(efx) \ 693 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST) 694 695static void siena_mcdi_request(struct efx_nic *efx, 696 const efx_dword_t *hdr, size_t hdr_len, 697 const efx_dword_t *sdu, size_t sdu_len) 698{ 699 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); 700 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx); 701 unsigned int i; 702 unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4); 703 704 EFX_BUG_ON_PARANOID(hdr_len != 4); 705 706 efx_writed(efx, hdr, pdu); 707 708 for (i = 0; i < inlen_dw; i++) 709 efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i); 710 711 /* Ensure the request is written out before the doorbell */ 712 wmb(); 713 714 /* ring the doorbell with a distinctive value */ 715 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell); 716} 717 718static bool siena_mcdi_poll_response(struct efx_nic *efx) 719{ 720 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); 721 efx_dword_t hdr; 722 723 efx_readd(efx, &hdr, pdu); 724 725 /* All 1's indicates that shared memory is in reset (and is 726 * not a valid hdr). Wait for it to come out reset before 727 * completing the command 728 */ 729 return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff && 730 EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 731} 732 733static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 734 size_t offset, size_t outlen) 735{ 736 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); 737 unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4); 738 int i; 739 740 for (i = 0; i < outlen_dw; i++) 741 efx_readd(efx, &outbuf[i], pdu + offset + 4 * i); 742} 743 744static int siena_mcdi_poll_reboot(struct efx_nic *efx) 745{ 746 struct siena_nic_data *nic_data = efx->nic_data; 747 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx); 748 efx_dword_t reg; 749 u32 value; 750 751 efx_readd(efx, ®, addr); 752 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 753 754 if (value == 0) 755 return 0; 756 757 EFX_ZERO_DWORD(reg); 758 efx_writed(efx, ®, addr); 759 760 /* MAC statistics have been cleared on the NIC; clear the local 761 * copies that we update with efx_update_diff_stat(). 762 */ 763 nic_data->stats[SIENA_STAT_tx_good_bytes] = 0; 764 nic_data->stats[SIENA_STAT_rx_good_bytes] = 0; 765 766 if (value == MC_STATUS_DWORD_ASSERT) 767 return -EINTR; 768 else 769 return -EIO; 770} 771 772/************************************************************************** 773 * 774 * MTD 775 * 776 ************************************************************************** 777 */ 778 779#ifdef CONFIG_SFC_MTD 780 781struct siena_nvram_type_info { 782 int port; 783 const char *name; 784}; 785 786static const struct siena_nvram_type_info siena_nvram_types[] = { 787 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO] = { 0, "sfc_dummy_phy" }, 788 [MC_CMD_NVRAM_TYPE_MC_FW] = { 0, "sfc_mcfw" }, 789 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP] = { 0, "sfc_mcfw_backup" }, 790 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0] = { 0, "sfc_static_cfg" }, 791 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1] = { 1, "sfc_static_cfg" }, 792 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0] = { 0, "sfc_dynamic_cfg" }, 793 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1] = { 1, "sfc_dynamic_cfg" }, 794 [MC_CMD_NVRAM_TYPE_EXP_ROM] = { 0, "sfc_exp_rom" }, 795 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0] = { 0, "sfc_exp_rom_cfg" }, 796 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1] = { 1, "sfc_exp_rom_cfg" }, 797 [MC_CMD_NVRAM_TYPE_PHY_PORT0] = { 0, "sfc_phy_fw" }, 798 [MC_CMD_NVRAM_TYPE_PHY_PORT1] = { 1, "sfc_phy_fw" }, 799 [MC_CMD_NVRAM_TYPE_FPGA] = { 0, "sfc_fpga" }, 800}; 801 802static int siena_mtd_probe_partition(struct efx_nic *efx, 803 struct efx_mcdi_mtd_partition *part, 804 unsigned int type) 805{ 806 const struct siena_nvram_type_info *info; 807 size_t size, erase_size; 808 bool protected; 809 int rc; 810 811 if (type >= ARRAY_SIZE(siena_nvram_types) || 812 siena_nvram_types[type].name == NULL) 813 return -ENODEV; 814 815 info = &siena_nvram_types[type]; 816 817 if (info->port != efx_port_num(efx)) 818 return -ENODEV; 819 820 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 821 if (rc) 822 return rc; 823 if (protected) 824 return -ENODEV; /* hide it */ 825 826 part->nvram_type = type; 827 part->common.dev_type_name = "Siena NVRAM manager"; 828 part->common.type_name = info->name; 829 830 part->common.mtd.type = MTD_NORFLASH; 831 part->common.mtd.flags = MTD_CAP_NORFLASH; 832 part->common.mtd.size = size; 833 part->common.mtd.erasesize = erase_size; 834 835 return 0; 836} 837 838static int siena_mtd_get_fw_subtypes(struct efx_nic *efx, 839 struct efx_mcdi_mtd_partition *parts, 840 size_t n_parts) 841{ 842 uint16_t fw_subtype_list[ 843 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM]; 844 size_t i; 845 int rc; 846 847 rc = efx_mcdi_get_board_cfg(efx, NULL, fw_subtype_list, NULL); 848 if (rc) 849 return rc; 850 851 for (i = 0; i < n_parts; i++) 852 parts[i].fw_subtype = fw_subtype_list[parts[i].nvram_type]; 853 854 return 0; 855} 856 857static int siena_mtd_probe(struct efx_nic *efx) 858{ 859 struct efx_mcdi_mtd_partition *parts; 860 u32 nvram_types; 861 unsigned int type; 862 size_t n_parts; 863 int rc; 864 865 ASSERT_RTNL(); 866 867 rc = efx_mcdi_nvram_types(efx, &nvram_types); 868 if (rc) 869 return rc; 870 871 parts = kcalloc(hweight32(nvram_types), sizeof(*parts), GFP_KERNEL); 872 if (!parts) 873 return -ENOMEM; 874 875 type = 0; 876 n_parts = 0; 877 878 while (nvram_types != 0) { 879 if (nvram_types & 1) { 880 rc = siena_mtd_probe_partition(efx, &parts[n_parts], 881 type); 882 if (rc == 0) 883 n_parts++; 884 else if (rc != -ENODEV) 885 goto fail; 886 } 887 type++; 888 nvram_types >>= 1; 889 } 890 891 rc = siena_mtd_get_fw_subtypes(efx, parts, n_parts); 892 if (rc) 893 goto fail; 894 895 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 896fail: 897 if (rc) 898 kfree(parts); 899 return rc; 900} 901 902#endif /* CONFIG_SFC_MTD */ 903 904/************************************************************************** 905 * 906 * Revision-dependent attributes used by efx.c and nic.c 907 * 908 ************************************************************************** 909 */ 910 911const struct efx_nic_type siena_a0_nic_type = { 912 .mem_map_size = siena_mem_map_size, 913 .probe = siena_probe_nic, 914 .remove = siena_remove_nic, 915 .init = siena_init_nic, 916 .dimension_resources = siena_dimension_resources, 917 .fini = efx_port_dummy_op_void, 918#ifdef CONFIG_EEH 919 .monitor = siena_monitor, 920#else 921 .monitor = NULL, 922#endif 923 .map_reset_reason = efx_mcdi_map_reset_reason, 924 .map_reset_flags = siena_map_reset_flags, 925 .reset = efx_mcdi_reset, 926 .probe_port = efx_mcdi_port_probe, 927 .remove_port = efx_mcdi_port_remove, 928 .fini_dmaq = efx_farch_fini_dmaq, 929 .prepare_flush = siena_prepare_flush, 930 .finish_flush = siena_finish_flush, 931 .prepare_flr = efx_port_dummy_op_void, 932 .finish_flr = efx_farch_finish_flr, 933 .describe_stats = siena_describe_nic_stats, 934 .update_stats = siena_update_nic_stats, 935 .start_stats = efx_mcdi_mac_start_stats, 936 .pull_stats = efx_mcdi_mac_pull_stats, 937 .stop_stats = efx_mcdi_mac_stop_stats, 938 .set_id_led = efx_mcdi_set_id_led, 939 .push_irq_moderation = siena_push_irq_moderation, 940 .reconfigure_mac = siena_mac_reconfigure, 941 .check_mac_fault = efx_mcdi_mac_check_fault, 942 .reconfigure_port = efx_mcdi_port_reconfigure, 943 .get_wol = siena_get_wol, 944 .set_wol = siena_set_wol, 945 .resume_wol = siena_init_wol, 946 .test_chip = siena_test_chip, 947 .test_nvram = efx_mcdi_nvram_test_all, 948 .mcdi_request = siena_mcdi_request, 949 .mcdi_poll_response = siena_mcdi_poll_response, 950 .mcdi_read_response = siena_mcdi_read_response, 951 .mcdi_poll_reboot = siena_mcdi_poll_reboot, 952 .irq_enable_master = efx_farch_irq_enable_master, 953 .irq_test_generate = efx_farch_irq_test_generate, 954 .irq_disable_non_ev = efx_farch_irq_disable_master, 955 .irq_handle_msi = efx_farch_msi_interrupt, 956 .irq_handle_legacy = efx_farch_legacy_interrupt, 957 .tx_probe = efx_farch_tx_probe, 958 .tx_init = efx_farch_tx_init, 959 .tx_remove = efx_farch_tx_remove, 960 .tx_write = efx_farch_tx_write, 961 .rx_push_rss_config = siena_rx_push_rss_config, 962 .rx_probe = efx_farch_rx_probe, 963 .rx_init = efx_farch_rx_init, 964 .rx_remove = efx_farch_rx_remove, 965 .rx_write = efx_farch_rx_write, 966 .rx_defer_refill = efx_farch_rx_defer_refill, 967 .ev_probe = efx_farch_ev_probe, 968 .ev_init = efx_farch_ev_init, 969 .ev_fini = efx_farch_ev_fini, 970 .ev_remove = efx_farch_ev_remove, 971 .ev_process = efx_farch_ev_process, 972 .ev_read_ack = efx_farch_ev_read_ack, 973 .ev_test_generate = efx_farch_ev_test_generate, 974 .filter_table_probe = efx_farch_filter_table_probe, 975 .filter_table_restore = efx_farch_filter_table_restore, 976 .filter_table_remove = efx_farch_filter_table_remove, 977 .filter_update_rx_scatter = efx_farch_filter_update_rx_scatter, 978 .filter_insert = efx_farch_filter_insert, 979 .filter_remove_safe = efx_farch_filter_remove_safe, 980 .filter_get_safe = efx_farch_filter_get_safe, 981 .filter_clear_rx = efx_farch_filter_clear_rx, 982 .filter_count_rx_used = efx_farch_filter_count_rx_used, 983 .filter_get_rx_id_limit = efx_farch_filter_get_rx_id_limit, 984 .filter_get_rx_ids = efx_farch_filter_get_rx_ids, 985#ifdef CONFIG_RFS_ACCEL 986 .filter_rfs_insert = efx_farch_filter_rfs_insert, 987 .filter_rfs_expire_one = efx_farch_filter_rfs_expire_one, 988#endif 989#ifdef CONFIG_SFC_MTD 990 .mtd_probe = siena_mtd_probe, 991 .mtd_rename = efx_mcdi_mtd_rename, 992 .mtd_read = efx_mcdi_mtd_read, 993 .mtd_erase = efx_mcdi_mtd_erase, 994 .mtd_write = efx_mcdi_mtd_write, 995 .mtd_sync = efx_mcdi_mtd_sync, 996#endif 997 .ptp_write_host_time = siena_ptp_write_host_time, 998 .ptp_set_ts_config = siena_ptp_set_ts_config, 999 .sriov_init = efx_siena_sriov_init, 1000 .sriov_fini = efx_siena_sriov_fini, 1001 .sriov_mac_address_changed = efx_siena_sriov_mac_address_changed, 1002 .sriov_wanted = efx_siena_sriov_wanted, 1003 .sriov_reset = efx_siena_sriov_reset, 1004 1005 .revision = EFX_REV_SIENA_A0, 1006 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, 1007 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, 1008 .buf_tbl_base = FR_BZ_BUF_FULL_TBL, 1009 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, 1010 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, 1011 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), 1012 .rx_prefix_size = FS_BZ_RX_PREFIX_SIZE, 1013 .rx_hash_offset = FS_BZ_RX_PREFIX_HASH_OFST, 1014 .rx_buffer_padding = 0, 1015 .can_rx_scatter = true, 1016 .max_interrupt_mode = EFX_INT_MODE_MSIX, 1017 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH, 1018 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1019 NETIF_F_RXHASH | NETIF_F_NTUPLE), 1020 .mcdi_max_ver = 1, 1021 .max_rx_ip_filters = FR_BZ_RX_FILTER_TBL0_ROWS, 1022 .hwtstamp_filters = (1 << HWTSTAMP_FILTER_NONE | 1023 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT | 1024 1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC | 1025 1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ | 1026 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT | 1027 1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC | 1028 1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ), 1029}; 1030