1/*******************************************************************************
2  Header File to describe the DMA descriptors.
3  Enhanced descriptors have been in case of DWMAC1000 Cores.
4
5  This program is free software; you can redistribute it and/or modify it
6  under the terms and conditions of the GNU General Public License,
7  version 2, as published by the Free Software Foundation.
8
9  This program is distributed in the hope it will be useful, but WITHOUT
10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  more details.
13
14  You should have received a copy of the GNU General Public License along with
15  this program; if not, write to the Free Software Foundation, Inc.,
16  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17
18  The full GNU General Public License is included in this distribution in
19  the file called "COPYING".
20
21  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
22*******************************************************************************/
23
24#ifndef __DESCS_H__
25#define __DESCS_H__
26
27/* Basic descriptor structure for normal and alternate descriptors */
28struct dma_desc {
29	/* Receive descriptor */
30	union {
31		struct {
32			/* RDES0 */
33			u32 payload_csum_error:1;
34			u32 crc_error:1;
35			u32 dribbling:1;
36			u32 mii_error:1;
37			u32 receive_watchdog:1;
38			u32 frame_type:1;
39			u32 collision:1;
40			u32 ipc_csum_error:1;
41			u32 last_descriptor:1;
42			u32 first_descriptor:1;
43			u32 vlan_tag:1;
44			u32 overflow_error:1;
45			u32 length_error:1;
46			u32 sa_filter_fail:1;
47			u32 descriptor_error:1;
48			u32 error_summary:1;
49			u32 frame_length:14;
50			u32 da_filter_fail:1;
51			u32 own:1;
52			/* RDES1 */
53			u32 buffer1_size:11;
54			u32 buffer2_size:11;
55			u32 reserved1:2;
56			u32 second_address_chained:1;
57			u32 end_ring:1;
58			u32 reserved2:5;
59			u32 disable_ic:1;
60
61		} rx;
62		struct {
63			/* RDES0 */
64			u32 rx_mac_addr:1;
65			u32 crc_error:1;
66			u32 dribbling:1;
67			u32 error_gmii:1;
68			u32 receive_watchdog:1;
69			u32 frame_type:1;
70			u32 late_collision:1;
71			u32 ipc_csum_error:1;
72			u32 last_descriptor:1;
73			u32 first_descriptor:1;
74			u32 vlan_tag:1;
75			u32 overflow_error:1;
76			u32 length_error:1;
77			u32 sa_filter_fail:1;
78			u32 descriptor_error:1;
79			u32 error_summary:1;
80			u32 frame_length:14;
81			u32 da_filter_fail:1;
82			u32 own:1;
83			/* RDES1 */
84			u32 buffer1_size:13;
85			u32 reserved1:1;
86			u32 second_address_chained:1;
87			u32 end_ring:1;
88			u32 buffer2_size:13;
89			u32 reserved2:2;
90			u32 disable_ic:1;
91		} erx;		/* -- enhanced -- */
92
93		/* Transmit descriptor */
94		struct {
95			/* TDES0 */
96			u32 deferred:1;
97			u32 underflow_error:1;
98			u32 excessive_deferral:1;
99			u32 collision_count:4;
100			u32 vlan_frame:1;
101			u32 excessive_collisions:1;
102			u32 late_collision:1;
103			u32 no_carrier:1;
104			u32 loss_carrier:1;
105			u32 payload_error:1;
106			u32 frame_flushed:1;
107			u32 jabber_timeout:1;
108			u32 error_summary:1;
109			u32 ip_header_error:1;
110			u32 time_stamp_status:1;
111			u32 reserved1:13;
112			u32 own:1;
113			/* TDES1 */
114			u32 buffer1_size:11;
115			u32 buffer2_size:11;
116			u32 time_stamp_enable:1;
117			u32 disable_padding:1;
118			u32 second_address_chained:1;
119			u32 end_ring:1;
120			u32 crc_disable:1;
121			u32 checksum_insertion:2;
122			u32 first_segment:1;
123			u32 last_segment:1;
124			u32 interrupt:1;
125		} tx;
126		struct {
127			/* TDES0 */
128			u32 deferred:1;
129			u32 underflow_error:1;
130			u32 excessive_deferral:1;
131			u32 collision_count:4;
132			u32 vlan_frame:1;
133			u32 excessive_collisions:1;
134			u32 late_collision:1;
135			u32 no_carrier:1;
136			u32 loss_carrier:1;
137			u32 payload_error:1;
138			u32 frame_flushed:1;
139			u32 jabber_timeout:1;
140			u32 error_summary:1;
141			u32 ip_header_error:1;
142			u32 time_stamp_status:1;
143			u32 reserved1:2;
144			u32 second_address_chained:1;
145			u32 end_ring:1;
146			u32 checksum_insertion:2;
147			u32 reserved2:1;
148			u32 time_stamp_enable:1;
149			u32 disable_padding:1;
150			u32 crc_disable:1;
151			u32 first_segment:1;
152			u32 last_segment:1;
153			u32 interrupt:1;
154			u32 own:1;
155			/* TDES1 */
156			u32 buffer1_size:13;
157			u32 reserved3:3;
158			u32 buffer2_size:13;
159			u32 reserved4:3;
160		} etx;		/* -- enhanced -- */
161
162		u64 all_flags;
163	} des01;
164	unsigned int des2;
165	unsigned int des3;
166};
167
168/* Extended descriptor structure (supported by new SYNP GMAC generations) */
169struct dma_extended_desc {
170	struct dma_desc basic;
171	union {
172		struct {
173			u32 ip_payload_type:3;
174			u32 ip_hdr_err:1;
175			u32 ip_payload_err:1;
176			u32 ip_csum_bypassed:1;
177			u32 ipv4_pkt_rcvd:1;
178			u32 ipv6_pkt_rcvd:1;
179			u32 msg_type:4;
180			u32 ptp_frame_type:1;
181			u32 ptp_ver:1;
182			u32 timestamp_dropped:1;
183			u32 reserved:1;
184			u32 av_pkt_rcvd:1;
185			u32 av_tagged_pkt_rcvd:1;
186			u32 vlan_tag_priority_val:3;
187			u32 reserved3:3;
188			u32 l3_filter_match:1;
189			u32 l4_filter_match:1;
190			u32 l3_l4_filter_no_match:2;
191			u32 reserved4:4;
192		} erx;
193		struct {
194			u32 reserved;
195		} etx;
196	} des4;
197	unsigned int des5;	/* Reserved */
198	unsigned int des6;	/* Tx/Rx Timestamp Low */
199	unsigned int des7;	/* Tx/Rx Timestamp High */
200};
201
202/* Transmit checksum insertion control */
203enum tdes_csum_insertion {
204	cic_disabled = 0,	/* Checksum Insertion Control */
205	cic_only_ip = 1,	/* Only IP header */
206	/* IP header but pseudoheader is not calculated */
207	cic_no_pseudoheader = 2,
208	cic_full = 3,		/* IP header and pseudoheader */
209};
210
211/* Extended RDES4 definitions */
212#define RDES_EXT_NO_PTP			0
213#define RDES_EXT_SYNC			0x1
214#define RDES_EXT_FOLLOW_UP		0x2
215#define RDES_EXT_DELAY_REQ		0x3
216#define RDES_EXT_DELAY_RESP		0x4
217#define RDES_EXT_PDELAY_REQ		0x5
218#define RDES_EXT_PDELAY_RESP		0x6
219#define RDES_EXT_PDELAY_FOLLOW_UP	0x7
220
221#endif /* __DESCS_H__ */
222