1/** 2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer 3 * 4 * Copyright (C) 2014 Chen-Zhi (Roger Chen) 5 * 6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/stmmac.h> 20#include <linux/bitops.h> 21#include <linux/clk.h> 22#include <linux/phy.h> 23#include <linux/of_net.h> 24#include <linux/gpio.h> 25#include <linux/of_gpio.h> 26#include <linux/of_device.h> 27#include <linux/regulator/consumer.h> 28#include <linux/delay.h> 29#include <linux/mfd/syscon.h> 30#include <linux/regmap.h> 31 32struct rk_priv_data { 33 struct platform_device *pdev; 34 int phy_iface; 35 struct regulator *regulator; 36 37 bool clk_enabled; 38 bool clock_input; 39 40 struct clk *clk_mac; 41 struct clk *gmac_clkin; 42 struct clk *mac_clk_rx; 43 struct clk *mac_clk_tx; 44 struct clk *clk_mac_ref; 45 struct clk *clk_mac_refout; 46 struct clk *aclk_mac; 47 struct clk *pclk_mac; 48 49 int tx_delay; 50 int rx_delay; 51 52 struct regmap *grf; 53}; 54 55#define HIWORD_UPDATE(val, mask, shift) \ 56 ((val) << (shift) | (mask) << ((shift) + 16)) 57 58#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 59#define GRF_CLR_BIT(nr) (BIT(nr+16)) 60 61#define RK3288_GRF_SOC_CON1 0x0248 62#define RK3288_GRF_SOC_CON3 0x0250 63#define RK3288_GRF_GPIO3D_E 0x01ec 64#define RK3288_GRF_GPIO4A_E 0x01f0 65#define RK3288_GRF_GPIO4B_E 0x01f4 66 67/*RK3288_GRF_SOC_CON1*/ 68#define GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) 69#define GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) 70#define GMAC_FLOW_CTRL GRF_BIT(9) 71#define GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 72#define GMAC_SPEED_10M GRF_CLR_BIT(10) 73#define GMAC_SPEED_100M GRF_BIT(10) 74#define GMAC_RMII_CLK_25M GRF_BIT(11) 75#define GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 76#define GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) 77#define GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) 78#define GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) 79#define GMAC_RMII_MODE GRF_BIT(14) 80#define GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 81 82/*RK3288_GRF_SOC_CON3*/ 83#define GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) 84#define GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) 85#define GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) 86#define GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) 87#define GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) 88#define GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) 89 90static void set_to_rgmii(struct rk_priv_data *bsp_priv, 91 int tx_delay, int rx_delay) 92{ 93 struct device *dev = &bsp_priv->pdev->dev; 94 95 if (IS_ERR(bsp_priv->grf)) { 96 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 97 return; 98 } 99 100 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 101 GMAC_PHY_INTF_SEL_RGMII | GMAC_RMII_MODE_CLR); 102 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 103 GMAC_RXCLK_DLY_ENABLE | GMAC_TXCLK_DLY_ENABLE | 104 GMAC_CLK_RX_DL_CFG(rx_delay) | 105 GMAC_CLK_TX_DL_CFG(tx_delay)); 106} 107 108static void set_to_rmii(struct rk_priv_data *bsp_priv) 109{ 110 struct device *dev = &bsp_priv->pdev->dev; 111 112 if (IS_ERR(bsp_priv->grf)) { 113 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 114 return; 115 } 116 117 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 118 GMAC_PHY_INTF_SEL_RMII | GMAC_RMII_MODE); 119} 120 121static void set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) 122{ 123 struct device *dev = &bsp_priv->pdev->dev; 124 125 if (IS_ERR(bsp_priv->grf)) { 126 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 127 return; 128 } 129 130 if (speed == 10) 131 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_2_5M); 132 else if (speed == 100) 133 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_25M); 134 else if (speed == 1000) 135 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_125M); 136 else 137 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed); 138} 139 140static void set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) 141{ 142 struct device *dev = &bsp_priv->pdev->dev; 143 144 if (IS_ERR(bsp_priv->grf)) { 145 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__); 146 return; 147 } 148 149 if (speed == 10) { 150 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 151 GMAC_RMII_CLK_2_5M | GMAC_SPEED_10M); 152 } else if (speed == 100) { 153 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 154 GMAC_RMII_CLK_25M | GMAC_SPEED_100M); 155 } else { 156 dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 157 } 158} 159 160static int gmac_clk_init(struct rk_priv_data *bsp_priv) 161{ 162 struct device *dev = &bsp_priv->pdev->dev; 163 164 bsp_priv->clk_enabled = false; 165 166 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx"); 167 if (IS_ERR(bsp_priv->mac_clk_rx)) 168 dev_err(dev, "%s: cannot get clock %s\n", 169 __func__, "mac_clk_rx"); 170 171 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx"); 172 if (IS_ERR(bsp_priv->mac_clk_tx)) 173 dev_err(dev, "%s: cannot get clock %s\n", 174 __func__, "mac_clk_tx"); 175 176 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac"); 177 if (IS_ERR(bsp_priv->aclk_mac)) 178 dev_err(dev, "%s: cannot get clock %s\n", 179 __func__, "aclk_mac"); 180 181 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac"); 182 if (IS_ERR(bsp_priv->pclk_mac)) 183 dev_err(dev, "%s: cannot get clock %s\n", 184 __func__, "pclk_mac"); 185 186 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth"); 187 if (IS_ERR(bsp_priv->clk_mac)) 188 dev_err(dev, "%s: cannot get clock %s\n", 189 __func__, "stmmaceth"); 190 191 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 192 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref"); 193 if (IS_ERR(bsp_priv->clk_mac_ref)) 194 dev_err(dev, "%s: cannot get clock %s\n", 195 __func__, "clk_mac_ref"); 196 197 if (!bsp_priv->clock_input) { 198 bsp_priv->clk_mac_refout = 199 devm_clk_get(dev, "clk_mac_refout"); 200 if (IS_ERR(bsp_priv->clk_mac_refout)) 201 dev_err(dev, "%s: cannot get clock %s\n", 202 __func__, "clk_mac_refout"); 203 } 204 } 205 206 if (bsp_priv->clock_input) { 207 dev_info(dev, "%s: clock input from PHY\n", __func__); 208 } else { 209 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 210 clk_set_rate(bsp_priv->clk_mac, 50000000); 211 } 212 213 return 0; 214} 215 216static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) 217{ 218 int phy_iface = phy_iface = bsp_priv->phy_iface; 219 220 if (enable) { 221 if (!bsp_priv->clk_enabled) { 222 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 223 if (!IS_ERR(bsp_priv->mac_clk_rx)) 224 clk_prepare_enable( 225 bsp_priv->mac_clk_rx); 226 227 if (!IS_ERR(bsp_priv->clk_mac_ref)) 228 clk_prepare_enable( 229 bsp_priv->clk_mac_ref); 230 231 if (!IS_ERR(bsp_priv->clk_mac_refout)) 232 clk_prepare_enable( 233 bsp_priv->clk_mac_refout); 234 } 235 236 if (!IS_ERR(bsp_priv->aclk_mac)) 237 clk_prepare_enable(bsp_priv->aclk_mac); 238 239 if (!IS_ERR(bsp_priv->pclk_mac)) 240 clk_prepare_enable(bsp_priv->pclk_mac); 241 242 if (!IS_ERR(bsp_priv->mac_clk_tx)) 243 clk_prepare_enable(bsp_priv->mac_clk_tx); 244 245 /** 246 * if (!IS_ERR(bsp_priv->clk_mac)) 247 * clk_prepare_enable(bsp_priv->clk_mac); 248 */ 249 mdelay(5); 250 bsp_priv->clk_enabled = true; 251 } 252 } else { 253 if (bsp_priv->clk_enabled) { 254 if (phy_iface == PHY_INTERFACE_MODE_RMII) { 255 if (!IS_ERR(bsp_priv->mac_clk_rx)) 256 clk_disable_unprepare( 257 bsp_priv->mac_clk_rx); 258 259 if (!IS_ERR(bsp_priv->clk_mac_ref)) 260 clk_disable_unprepare( 261 bsp_priv->clk_mac_ref); 262 263 if (!IS_ERR(bsp_priv->clk_mac_refout)) 264 clk_disable_unprepare( 265 bsp_priv->clk_mac_refout); 266 } 267 268 if (!IS_ERR(bsp_priv->aclk_mac)) 269 clk_disable_unprepare(bsp_priv->aclk_mac); 270 271 if (!IS_ERR(bsp_priv->pclk_mac)) 272 clk_disable_unprepare(bsp_priv->pclk_mac); 273 274 if (!IS_ERR(bsp_priv->mac_clk_tx)) 275 clk_disable_unprepare(bsp_priv->mac_clk_tx); 276 /** 277 * if (!IS_ERR(bsp_priv->clk_mac)) 278 * clk_disable_unprepare(bsp_priv->clk_mac); 279 */ 280 bsp_priv->clk_enabled = false; 281 } 282 } 283 284 return 0; 285} 286 287static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) 288{ 289 struct regulator *ldo = bsp_priv->regulator; 290 int ret; 291 struct device *dev = &bsp_priv->pdev->dev; 292 293 if (!ldo) { 294 dev_err(dev, "%s: no regulator found\n", __func__); 295 return -1; 296 } 297 298 if (enable) { 299 ret = regulator_enable(ldo); 300 if (ret) 301 dev_err(dev, "%s: fail to enable phy-supply\n", 302 __func__); 303 } else { 304 ret = regulator_disable(ldo); 305 if (ret) 306 dev_err(dev, "%s: fail to disable phy-supply\n", 307 __func__); 308 } 309 310 return 0; 311} 312 313static void *rk_gmac_setup(struct platform_device *pdev) 314{ 315 struct rk_priv_data *bsp_priv; 316 struct device *dev = &pdev->dev; 317 int ret; 318 const char *strings = NULL; 319 int value; 320 321 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); 322 if (!bsp_priv) 323 return ERR_PTR(-ENOMEM); 324 325 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node); 326 327 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy"); 328 if (IS_ERR(bsp_priv->regulator)) { 329 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) { 330 dev_err(dev, "phy regulator is not available yet, deferred probing\n"); 331 return ERR_PTR(-EPROBE_DEFER); 332 } 333 dev_err(dev, "no regulator found\n"); 334 bsp_priv->regulator = NULL; 335 } 336 337 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings); 338 if (ret) { 339 dev_err(dev, "%s: Can not read property: clock_in_out.\n", 340 __func__); 341 bsp_priv->clock_input = true; 342 } else { 343 dev_info(dev, "%s: clock input or output? (%s).\n", 344 __func__, strings); 345 if (!strcmp(strings, "input")) 346 bsp_priv->clock_input = true; 347 else 348 bsp_priv->clock_input = false; 349 } 350 351 ret = of_property_read_u32(dev->of_node, "tx_delay", &value); 352 if (ret) { 353 bsp_priv->tx_delay = 0x30; 354 dev_err(dev, "%s: Can not read property: tx_delay.", __func__); 355 dev_err(dev, "%s: set tx_delay to 0x%x\n", 356 __func__, bsp_priv->tx_delay); 357 } else { 358 dev_info(dev, "%s: TX delay(0x%x).\n", __func__, value); 359 bsp_priv->tx_delay = value; 360 } 361 362 ret = of_property_read_u32(dev->of_node, "rx_delay", &value); 363 if (ret) { 364 bsp_priv->rx_delay = 0x10; 365 dev_err(dev, "%s: Can not read property: rx_delay.", __func__); 366 dev_err(dev, "%s: set rx_delay to 0x%x\n", 367 __func__, bsp_priv->rx_delay); 368 } else { 369 dev_info(dev, "%s: RX delay(0x%x).\n", __func__, value); 370 bsp_priv->rx_delay = value; 371 } 372 373 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 374 "rockchip,grf"); 375 bsp_priv->pdev = pdev; 376 377 /*rmii or rgmii*/ 378 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) { 379 dev_info(dev, "%s: init for RGMII\n", __func__); 380 set_to_rgmii(bsp_priv, bsp_priv->tx_delay, bsp_priv->rx_delay); 381 } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) { 382 dev_info(dev, "%s: init for RMII\n", __func__); 383 set_to_rmii(bsp_priv); 384 } else { 385 dev_err(dev, "%s: NO interface defined!\n", __func__); 386 } 387 388 gmac_clk_init(bsp_priv); 389 390 return bsp_priv; 391} 392 393static int rk_gmac_init(struct platform_device *pdev, void *priv) 394{ 395 struct rk_priv_data *bsp_priv = priv; 396 int ret; 397 398 ret = phy_power_on(bsp_priv, true); 399 if (ret) 400 return ret; 401 402 ret = gmac_clk_enable(bsp_priv, true); 403 if (ret) 404 return ret; 405 406 return 0; 407} 408 409static void rk_gmac_exit(struct platform_device *pdev, void *priv) 410{ 411 struct rk_priv_data *gmac = priv; 412 413 phy_power_on(gmac, false); 414 gmac_clk_enable(gmac, false); 415} 416 417static void rk_fix_speed(void *priv, unsigned int speed) 418{ 419 struct rk_priv_data *bsp_priv = priv; 420 struct device *dev = &bsp_priv->pdev->dev; 421 422 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) 423 set_rgmii_speed(bsp_priv, speed); 424 else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) 425 set_rmii_speed(bsp_priv, speed); 426 else 427 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface); 428} 429 430const struct stmmac_of_data rk3288_gmac_data = { 431 .has_gmac = 1, 432 .fix_mac_speed = rk_fix_speed, 433 .setup = rk_gmac_setup, 434 .init = rk_gmac_init, 435 .exit = rk_gmac_exit, 436}; 437