1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
27#include <linux/net_tstamp.h>
28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/of.h>
33#include <linux/of_net.h>
34#include <linux/of_device.h>
35#include <linux/if_vlan.h>
36
37#include <linux/pinctrl/consumer.h>
38
39#include "cpsw.h"
40#include "cpsw_ale.h"
41#include "cpts.h"
42#include "davinci_cpdma.h"
43
44#define CPSW_DEBUG	(NETIF_MSG_HW		| NETIF_MSG_WOL		| \
45			 NETIF_MSG_DRV		| NETIF_MSG_LINK	| \
46			 NETIF_MSG_IFUP		| NETIF_MSG_INTR	| \
47			 NETIF_MSG_PROBE	| NETIF_MSG_TIMER	| \
48			 NETIF_MSG_IFDOWN	| NETIF_MSG_RX_ERR	| \
49			 NETIF_MSG_TX_ERR	| NETIF_MSG_TX_DONE	| \
50			 NETIF_MSG_PKTDATA	| NETIF_MSG_TX_QUEUED	| \
51			 NETIF_MSG_RX_STATUS)
52
53#define cpsw_info(priv, type, format, ...)		\
54do {								\
55	if (netif_msg_##type(priv) && net_ratelimit())		\
56		dev_info(priv->dev, format, ## __VA_ARGS__);	\
57} while (0)
58
59#define cpsw_err(priv, type, format, ...)		\
60do {								\
61	if (netif_msg_##type(priv) && net_ratelimit())		\
62		dev_err(priv->dev, format, ## __VA_ARGS__);	\
63} while (0)
64
65#define cpsw_dbg(priv, type, format, ...)		\
66do {								\
67	if (netif_msg_##type(priv) && net_ratelimit())		\
68		dev_dbg(priv->dev, format, ## __VA_ARGS__);	\
69} while (0)
70
71#define cpsw_notice(priv, type, format, ...)		\
72do {								\
73	if (netif_msg_##type(priv) && net_ratelimit())		\
74		dev_notice(priv->dev, format, ## __VA_ARGS__);	\
75} while (0)
76
77#define ALE_ALL_PORTS		0x7
78
79#define CPSW_MAJOR_VERSION(reg)		(reg >> 8 & 0x7)
80#define CPSW_MINOR_VERSION(reg)		(reg & 0xff)
81#define CPSW_RTL_VERSION(reg)		((reg >> 11) & 0x1f)
82
83#define CPSW_VERSION_1		0x19010a
84#define CPSW_VERSION_2		0x19010c
85#define CPSW_VERSION_3		0x19010f
86#define CPSW_VERSION_4		0x190112
87
88#define HOST_PORT_NUM		0
89#define SLIVER_SIZE		0x40
90
91#define CPSW1_HOST_PORT_OFFSET	0x028
92#define CPSW1_SLAVE_OFFSET	0x050
93#define CPSW1_SLAVE_SIZE	0x040
94#define CPSW1_CPDMA_OFFSET	0x100
95#define CPSW1_STATERAM_OFFSET	0x200
96#define CPSW1_HW_STATS		0x400
97#define CPSW1_CPTS_OFFSET	0x500
98#define CPSW1_ALE_OFFSET	0x600
99#define CPSW1_SLIVER_OFFSET	0x700
100
101#define CPSW2_HOST_PORT_OFFSET	0x108
102#define CPSW2_SLAVE_OFFSET	0x200
103#define CPSW2_SLAVE_SIZE	0x100
104#define CPSW2_CPDMA_OFFSET	0x800
105#define CPSW2_HW_STATS		0x900
106#define CPSW2_STATERAM_OFFSET	0xa00
107#define CPSW2_CPTS_OFFSET	0xc00
108#define CPSW2_ALE_OFFSET	0xd00
109#define CPSW2_SLIVER_OFFSET	0xd80
110#define CPSW2_BD_OFFSET		0x2000
111
112#define CPDMA_RXTHRESH		0x0c0
113#define CPDMA_RXFREE		0x0e0
114#define CPDMA_TXHDP		0x00
115#define CPDMA_RXHDP		0x20
116#define CPDMA_TXCP		0x40
117#define CPDMA_RXCP		0x60
118
119#define CPSW_POLL_WEIGHT	64
120#define CPSW_MIN_PACKET_SIZE	60
121#define CPSW_MAX_PACKET_SIZE	(1500 + 14 + 4 + 4)
122
123#define RX_PRIORITY_MAPPING	0x76543210
124#define TX_PRIORITY_MAPPING	0x33221100
125#define CPDMA_TX_PRIORITY_MAP	0x76543210
126
127#define CPSW_VLAN_AWARE		BIT(1)
128#define CPSW_ALE_VLAN_AWARE	1
129
130#define CPSW_FIFO_NORMAL_MODE		(0 << 16)
131#define CPSW_FIFO_DUAL_MAC_MODE		(1 << 16)
132#define CPSW_FIFO_RATE_LIMIT_MODE	(2 << 16)
133
134#define CPSW_INTPACEEN		(0x3f << 16)
135#define CPSW_INTPRESCALE_MASK	(0x7FF << 0)
136#define CPSW_CMINTMAX_CNT	63
137#define CPSW_CMINTMIN_CNT	2
138#define CPSW_CMINTMAX_INTVL	(1000 / CPSW_CMINTMIN_CNT)
139#define CPSW_CMINTMIN_INTVL	((1000 / CPSW_CMINTMAX_CNT) + 1)
140
141#define cpsw_enable_irq(priv)	\
142	do {			\
143		u32 i;		\
144		for (i = 0; i < priv->num_irqs; i++) \
145			enable_irq(priv->irqs_table[i]); \
146	} while (0)
147#define cpsw_disable_irq(priv)	\
148	do {			\
149		u32 i;		\
150		for (i = 0; i < priv->num_irqs; i++) \
151			disable_irq_nosync(priv->irqs_table[i]); \
152	} while (0)
153
154#define cpsw_slave_index(priv)				\
155		((priv->data.dual_emac) ? priv->emac_port :	\
156		priv->data.active_slave)
157
158static int debug_level;
159module_param(debug_level, int, 0);
160MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
161
162static int ale_ageout = 10;
163module_param(ale_ageout, int, 0);
164MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
165
166static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
167module_param(rx_packet_max, int, 0);
168MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
169
170struct cpsw_wr_regs {
171	u32	id_ver;
172	u32	soft_reset;
173	u32	control;
174	u32	int_control;
175	u32	rx_thresh_en;
176	u32	rx_en;
177	u32	tx_en;
178	u32	misc_en;
179	u32	mem_allign1[8];
180	u32	rx_thresh_stat;
181	u32	rx_stat;
182	u32	tx_stat;
183	u32	misc_stat;
184	u32	mem_allign2[8];
185	u32	rx_imax;
186	u32	tx_imax;
187
188};
189
190struct cpsw_ss_regs {
191	u32	id_ver;
192	u32	control;
193	u32	soft_reset;
194	u32	stat_port_en;
195	u32	ptype;
196	u32	soft_idle;
197	u32	thru_rate;
198	u32	gap_thresh;
199	u32	tx_start_wds;
200	u32	flow_control;
201	u32	vlan_ltype;
202	u32	ts_ltype;
203	u32	dlr_ltype;
204};
205
206/* CPSW_PORT_V1 */
207#define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
208#define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
209#define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
210#define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
211#define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW1_TS_CTL        0x14 /* Time Sync Control */
213#define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
214#define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
215
216/* CPSW_PORT_V2 */
217#define CPSW2_CONTROL       0x00 /* Control Register */
218#define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
219#define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
220#define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
221#define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
222#define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
223#define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
224
225/* CPSW_PORT_V1 and V2 */
226#define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
227#define SA_HI               0x24 /* CPGMAC_SL Source Address High */
228#define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
229
230/* CPSW_PORT_V2 only */
231#define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
232#define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
233#define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
234#define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
235#define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
236#define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
237#define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
238#define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
239
240/* Bit definitions for the CPSW2_CONTROL register */
241#define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
242#define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
243#define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
244#define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
245#define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
246#define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
247#define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
248#define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
249#define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
250#define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
251#define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
252#define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
253#define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
254#define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
255#define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
256#define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
257#define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
258
259#define CTRL_V2_TS_BITS \
260	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261	 TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
262
263#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
264#define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
265#define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
266
267
268#define CTRL_V3_TS_BITS \
269	(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
270	 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
271	 TS_LTYPE1_EN)
272
273#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
274#define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
275#define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
276
277/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
278#define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
279#define TS_SEQ_ID_OFFSET_MASK    (0x3f)
280#define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
281#define TS_MSG_TYPE_EN_MASK      (0xffff)
282
283/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
284#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
285
286/* Bit definitions for the CPSW1_TS_CTL register */
287#define CPSW_V1_TS_RX_EN		BIT(0)
288#define CPSW_V1_TS_TX_EN		BIT(4)
289#define CPSW_V1_MSG_TYPE_OFS		16
290
291/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
292#define CPSW_V1_SEQ_ID_OFS_SHIFT	16
293
294struct cpsw_host_regs {
295	u32	max_blks;
296	u32	blk_cnt;
297	u32	tx_in_ctl;
298	u32	port_vlan;
299	u32	tx_pri_map;
300	u32	cpdma_tx_pri_map;
301	u32	cpdma_rx_chan_map;
302};
303
304struct cpsw_sliver_regs {
305	u32	id_ver;
306	u32	mac_control;
307	u32	mac_status;
308	u32	soft_reset;
309	u32	rx_maxlen;
310	u32	__reserved_0;
311	u32	rx_pause;
312	u32	tx_pause;
313	u32	__reserved_1;
314	u32	rx_pri_map;
315};
316
317struct cpsw_hw_stats {
318	u32	rxgoodframes;
319	u32	rxbroadcastframes;
320	u32	rxmulticastframes;
321	u32	rxpauseframes;
322	u32	rxcrcerrors;
323	u32	rxaligncodeerrors;
324	u32	rxoversizedframes;
325	u32	rxjabberframes;
326	u32	rxundersizedframes;
327	u32	rxfragments;
328	u32	__pad_0[2];
329	u32	rxoctets;
330	u32	txgoodframes;
331	u32	txbroadcastframes;
332	u32	txmulticastframes;
333	u32	txpauseframes;
334	u32	txdeferredframes;
335	u32	txcollisionframes;
336	u32	txsinglecollframes;
337	u32	txmultcollframes;
338	u32	txexcessivecollisions;
339	u32	txlatecollisions;
340	u32	txunderrun;
341	u32	txcarriersenseerrors;
342	u32	txoctets;
343	u32	octetframes64;
344	u32	octetframes65t127;
345	u32	octetframes128t255;
346	u32	octetframes256t511;
347	u32	octetframes512t1023;
348	u32	octetframes1024tup;
349	u32	netoctets;
350	u32	rxsofoverruns;
351	u32	rxmofoverruns;
352	u32	rxdmaoverruns;
353};
354
355struct cpsw_slave {
356	void __iomem			*regs;
357	struct cpsw_sliver_regs __iomem	*sliver;
358	int				slave_num;
359	u32				mac_control;
360	struct cpsw_slave_data		*data;
361	struct phy_device		*phy;
362	struct net_device		*ndev;
363	u32				port_vlan;
364	u32				open_stat;
365};
366
367static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
368{
369	return __raw_readl(slave->regs + offset);
370}
371
372static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
373{
374	__raw_writel(val, slave->regs + offset);
375}
376
377struct cpsw_priv {
378	spinlock_t			lock;
379	struct platform_device		*pdev;
380	struct net_device		*ndev;
381	struct napi_struct		napi;
382	struct device			*dev;
383	struct cpsw_platform_data	data;
384	struct cpsw_ss_regs __iomem	*regs;
385	struct cpsw_wr_regs __iomem	*wr_regs;
386	u8 __iomem			*hw_stats;
387	struct cpsw_host_regs __iomem	*host_port_regs;
388	u32				msg_enable;
389	u32				version;
390	u32				coal_intvl;
391	u32				bus_freq_mhz;
392	int				rx_packet_max;
393	int				host_port;
394	struct clk			*clk;
395	u8				mac_addr[ETH_ALEN];
396	struct cpsw_slave		*slaves;
397	struct cpdma_ctlr		*dma;
398	struct cpdma_chan		*txch, *rxch;
399	struct cpsw_ale			*ale;
400	bool				rx_pause;
401	bool				tx_pause;
402	/* snapshot of IRQ numbers */
403	u32 irqs_table[4];
404	u32 num_irqs;
405	bool irq_enabled;
406	struct cpts *cpts;
407	u32 emac_port;
408};
409
410struct cpsw_stats {
411	char stat_string[ETH_GSTRING_LEN];
412	int type;
413	int sizeof_stat;
414	int stat_offset;
415};
416
417enum {
418	CPSW_STATS,
419	CPDMA_RX_STATS,
420	CPDMA_TX_STATS,
421};
422
423#define CPSW_STAT(m)		CPSW_STATS,				\
424				sizeof(((struct cpsw_hw_stats *)0)->m), \
425				offsetof(struct cpsw_hw_stats, m)
426#define CPDMA_RX_STAT(m)	CPDMA_RX_STATS,				   \
427				sizeof(((struct cpdma_chan_stats *)0)->m), \
428				offsetof(struct cpdma_chan_stats, m)
429#define CPDMA_TX_STAT(m)	CPDMA_TX_STATS,				   \
430				sizeof(((struct cpdma_chan_stats *)0)->m), \
431				offsetof(struct cpdma_chan_stats, m)
432
433static const struct cpsw_stats cpsw_gstrings_stats[] = {
434	{ "Good Rx Frames", CPSW_STAT(rxgoodframes) },
435	{ "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
436	{ "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
437	{ "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
438	{ "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
439	{ "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
440	{ "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
441	{ "Rx Jabbers", CPSW_STAT(rxjabberframes) },
442	{ "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
443	{ "Rx Fragments", CPSW_STAT(rxfragments) },
444	{ "Rx Octets", CPSW_STAT(rxoctets) },
445	{ "Good Tx Frames", CPSW_STAT(txgoodframes) },
446	{ "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
447	{ "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
448	{ "Pause Tx Frames", CPSW_STAT(txpauseframes) },
449	{ "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
450	{ "Collisions", CPSW_STAT(txcollisionframes) },
451	{ "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
452	{ "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
453	{ "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
454	{ "Late Collisions", CPSW_STAT(txlatecollisions) },
455	{ "Tx Underrun", CPSW_STAT(txunderrun) },
456	{ "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
457	{ "Tx Octets", CPSW_STAT(txoctets) },
458	{ "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
459	{ "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
460	{ "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
461	{ "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
462	{ "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
463	{ "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
464	{ "Net Octets", CPSW_STAT(netoctets) },
465	{ "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
466	{ "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
467	{ "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
468	{ "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
469	{ "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
470	{ "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
471	{ "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
472	{ "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
473	{ "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
474	{ "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
475	{ "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
476	{ "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
477	{ "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
478	{ "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
479	{ "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
480	{ "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
481	{ "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
482	{ "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
483	{ "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
484	{ "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
485	{ "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
486	{ "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
487	{ "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
488	{ "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
489	{ "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
490	{ "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
491	{ "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
492	{ "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
493	{ "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
494};
495
496#define CPSW_STATS_LEN	ARRAY_SIZE(cpsw_gstrings_stats)
497
498#define napi_to_priv(napi)	container_of(napi, struct cpsw_priv, napi)
499#define for_each_slave(priv, func, arg...)				\
500	do {								\
501		struct cpsw_slave *slave;				\
502		int n;							\
503		if (priv->data.dual_emac)				\
504			(func)((priv)->slaves + priv->emac_port, ##arg);\
505		else							\
506			for (n = (priv)->data.slaves,			\
507					slave = (priv)->slaves;		\
508					n; n--)				\
509				(func)(slave++, ##arg);			\
510	} while (0)
511#define cpsw_get_slave_ndev(priv, __slave_no__)				\
512	(priv->slaves[__slave_no__].ndev)
513#define cpsw_get_slave_priv(priv, __slave_no__)				\
514	((priv->slaves[__slave_no__].ndev) ?				\
515		netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)	\
516
517#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)		\
518	do {								\
519		if (!priv->data.dual_emac)				\
520			break;						\
521		if (CPDMA_RX_SOURCE_PORT(status) == 1) {		\
522			ndev = cpsw_get_slave_ndev(priv, 0);		\
523			priv = netdev_priv(ndev);			\
524			skb->dev = ndev;				\
525		} else if (CPDMA_RX_SOURCE_PORT(status) == 2) {		\
526			ndev = cpsw_get_slave_ndev(priv, 1);		\
527			priv = netdev_priv(ndev);			\
528			skb->dev = ndev;				\
529		}							\
530	} while (0)
531#define cpsw_add_mcast(priv, addr)					\
532	do {								\
533		if (priv->data.dual_emac) {				\
534			struct cpsw_slave *slave = priv->slaves +	\
535						priv->emac_port;	\
536			int slave_port = cpsw_get_slave_port(priv,	\
537						slave->slave_num);	\
538			cpsw_ale_add_mcast(priv->ale, addr,		\
539				1 << slave_port | 1 << priv->host_port,	\
540				ALE_VLAN, slave->port_vlan, 0);		\
541		} else {						\
542			cpsw_ale_add_mcast(priv->ale, addr,		\
543				ALE_ALL_PORTS << priv->host_port,	\
544				0, 0, 0);				\
545		}							\
546	} while (0)
547
548static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
549{
550	if (priv->host_port == 0)
551		return slave_num + 1;
552	else
553		return slave_num;
554}
555
556static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
557{
558	struct cpsw_priv *priv = netdev_priv(ndev);
559	struct cpsw_ale *ale = priv->ale;
560	int i;
561
562	if (priv->data.dual_emac) {
563		bool flag = false;
564
565		/* Enabling promiscuous mode for one interface will be
566		 * common for both the interface as the interface shares
567		 * the same hardware resource.
568		 */
569		for (i = 0; i < priv->data.slaves; i++)
570			if (priv->slaves[i].ndev->flags & IFF_PROMISC)
571				flag = true;
572
573		if (!enable && flag) {
574			enable = true;
575			dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
576		}
577
578		if (enable) {
579			/* Enable Bypass */
580			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
581
582			dev_dbg(&ndev->dev, "promiscuity enabled\n");
583		} else {
584			/* Disable Bypass */
585			cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
586			dev_dbg(&ndev->dev, "promiscuity disabled\n");
587		}
588	} else {
589		if (enable) {
590			unsigned long timeout = jiffies + HZ;
591
592			/* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
593			for (i = 0; i <= priv->data.slaves; i++) {
594				cpsw_ale_control_set(ale, i,
595						     ALE_PORT_NOLEARN, 1);
596				cpsw_ale_control_set(ale, i,
597						     ALE_PORT_NO_SA_UPDATE, 1);
598			}
599
600			/* Clear All Untouched entries */
601			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
602			do {
603				cpu_relax();
604				if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
605					break;
606			} while (time_after(timeout, jiffies));
607			cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
608
609			/* Clear all mcast from ALE */
610			cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
611						 priv->host_port, -1);
612
613			/* Flood All Unicast Packets to Host port */
614			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
615			dev_dbg(&ndev->dev, "promiscuity enabled\n");
616		} else {
617			/* Don't Flood All Unicast Packets to Host port */
618			cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
619
620			/* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
621			for (i = 0; i <= priv->data.slaves; i++) {
622				cpsw_ale_control_set(ale, i,
623						     ALE_PORT_NOLEARN, 0);
624				cpsw_ale_control_set(ale, i,
625						     ALE_PORT_NO_SA_UPDATE, 0);
626			}
627			dev_dbg(&ndev->dev, "promiscuity disabled\n");
628		}
629	}
630}
631
632static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
633{
634	struct cpsw_priv *priv = netdev_priv(ndev);
635	int vid;
636
637	if (priv->data.dual_emac)
638		vid = priv->slaves[priv->emac_port].port_vlan;
639	else
640		vid = priv->data.default_vlan;
641
642	if (ndev->flags & IFF_PROMISC) {
643		/* Enable promiscuous mode */
644		cpsw_set_promiscious(ndev, true);
645		cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
646		return;
647	} else {
648		/* Disable promiscuous mode */
649		cpsw_set_promiscious(ndev, false);
650	}
651
652	/* Restore allmulti on vlans if necessary */
653	cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
654
655	/* Clear all mcast from ALE */
656	cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
657				 vid);
658
659	if (!netdev_mc_empty(ndev)) {
660		struct netdev_hw_addr *ha;
661
662		/* program multicast address list into ALE register */
663		netdev_for_each_mc_addr(ha, ndev) {
664			cpsw_add_mcast(priv, (u8 *)ha->addr);
665		}
666	}
667}
668
669static void cpsw_intr_enable(struct cpsw_priv *priv)
670{
671	__raw_writel(0xFF, &priv->wr_regs->tx_en);
672	__raw_writel(0xFF, &priv->wr_regs->rx_en);
673
674	cpdma_ctlr_int_ctrl(priv->dma, true);
675	return;
676}
677
678static void cpsw_intr_disable(struct cpsw_priv *priv)
679{
680	__raw_writel(0, &priv->wr_regs->tx_en);
681	__raw_writel(0, &priv->wr_regs->rx_en);
682
683	cpdma_ctlr_int_ctrl(priv->dma, false);
684	return;
685}
686
687static void cpsw_tx_handler(void *token, int len, int status)
688{
689	struct sk_buff		*skb = token;
690	struct net_device	*ndev = skb->dev;
691	struct cpsw_priv	*priv = netdev_priv(ndev);
692
693	/* Check whether the queue is stopped due to stalled tx dma, if the
694	 * queue is stopped then start the queue as we have free desc for tx
695	 */
696	if (unlikely(netif_queue_stopped(ndev)))
697		netif_wake_queue(ndev);
698	cpts_tx_timestamp(priv->cpts, skb);
699	ndev->stats.tx_packets++;
700	ndev->stats.tx_bytes += len;
701	dev_kfree_skb_any(skb);
702}
703
704static void cpsw_rx_handler(void *token, int len, int status)
705{
706	struct sk_buff		*skb = token;
707	struct sk_buff		*new_skb;
708	struct net_device	*ndev = skb->dev;
709	struct cpsw_priv	*priv = netdev_priv(ndev);
710	int			ret = 0;
711
712	cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
713
714	if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
715		bool ndev_status = false;
716		struct cpsw_slave *slave = priv->slaves;
717		int n;
718
719		if (priv->data.dual_emac) {
720			/* In dual emac mode check for all interfaces */
721			for (n = priv->data.slaves; n; n--, slave++)
722				if (netif_running(slave->ndev))
723					ndev_status = true;
724		}
725
726		if (ndev_status && (status >= 0)) {
727			/* The packet received is for the interface which
728			 * is already down and the other interface is up
729			 * and running, instead of freeing which results
730			 * in reducing of the number of rx descriptor in
731			 * DMA engine, requeue skb back to cpdma.
732			 */
733			new_skb = skb;
734			goto requeue;
735		}
736
737		/* the interface is going down, skbs are purged */
738		dev_kfree_skb_any(skb);
739		return;
740	}
741
742	new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
743	if (new_skb) {
744		skb_put(skb, len);
745		cpts_rx_timestamp(priv->cpts, skb);
746		skb->protocol = eth_type_trans(skb, ndev);
747		netif_receive_skb(skb);
748		ndev->stats.rx_bytes += len;
749		ndev->stats.rx_packets++;
750	} else {
751		ndev->stats.rx_dropped++;
752		new_skb = skb;
753	}
754
755requeue:
756	ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
757			skb_tailroom(new_skb), 0);
758	if (WARN_ON(ret < 0))
759		dev_kfree_skb_any(new_skb);
760}
761
762static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
763{
764	struct cpsw_priv *priv = dev_id;
765
766	cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
767	cpdma_chan_process(priv->txch, 128);
768
769	priv = cpsw_get_slave_priv(priv, 1);
770	if (priv)
771		cpdma_chan_process(priv->txch, 128);
772
773	return IRQ_HANDLED;
774}
775
776static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
777{
778	struct cpsw_priv *priv = dev_id;
779
780	cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
781
782	cpsw_intr_disable(priv);
783	if (priv->irq_enabled == true) {
784		cpsw_disable_irq(priv);
785		priv->irq_enabled = false;
786	}
787
788	if (netif_running(priv->ndev)) {
789		napi_schedule(&priv->napi);
790		return IRQ_HANDLED;
791	}
792
793	priv = cpsw_get_slave_priv(priv, 1);
794	if (!priv)
795		return IRQ_NONE;
796
797	if (netif_running(priv->ndev)) {
798		napi_schedule(&priv->napi);
799		return IRQ_HANDLED;
800	}
801	return IRQ_NONE;
802}
803
804static int cpsw_poll(struct napi_struct *napi, int budget)
805{
806	struct cpsw_priv	*priv = napi_to_priv(napi);
807	int			num_tx, num_rx;
808
809	num_tx = cpdma_chan_process(priv->txch, 128);
810
811	num_rx = cpdma_chan_process(priv->rxch, budget);
812	if (num_rx < budget) {
813		struct cpsw_priv *prim_cpsw;
814
815		napi_complete(napi);
816		cpsw_intr_enable(priv);
817		prim_cpsw = cpsw_get_slave_priv(priv, 0);
818		if (prim_cpsw->irq_enabled == false) {
819			prim_cpsw->irq_enabled = true;
820			cpsw_enable_irq(priv);
821		}
822	}
823
824	if (num_rx || num_tx)
825		cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
826			 num_rx, num_tx);
827
828	return num_rx;
829}
830
831static inline void soft_reset(const char *module, void __iomem *reg)
832{
833	unsigned long timeout = jiffies + HZ;
834
835	__raw_writel(1, reg);
836	do {
837		cpu_relax();
838	} while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
839
840	WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
841}
842
843#define mac_hi(mac)	(((mac)[0] << 0) | ((mac)[1] << 8) |	\
844			 ((mac)[2] << 16) | ((mac)[3] << 24))
845#define mac_lo(mac)	(((mac)[4] << 0) | ((mac)[5] << 8))
846
847static void cpsw_set_slave_mac(struct cpsw_slave *slave,
848			       struct cpsw_priv *priv)
849{
850	slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
851	slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
852}
853
854static void _cpsw_adjust_link(struct cpsw_slave *slave,
855			      struct cpsw_priv *priv, bool *link)
856{
857	struct phy_device	*phy = slave->phy;
858	u32			mac_control = 0;
859	u32			slave_port;
860
861	if (!phy)
862		return;
863
864	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
865
866	if (phy->link) {
867		mac_control = priv->data.mac_control;
868
869		/* enable forwarding */
870		cpsw_ale_control_set(priv->ale, slave_port,
871				     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
872
873		if (phy->speed == 1000)
874			mac_control |= BIT(7);	/* GIGABITEN	*/
875		if (phy->duplex)
876			mac_control |= BIT(0);	/* FULLDUPLEXEN	*/
877
878		/* set speed_in input in case RMII mode is used in 100Mbps */
879		if (phy->speed == 100)
880			mac_control |= BIT(15);
881		else if (phy->speed == 10)
882			mac_control |= BIT(18); /* In Band mode */
883
884		if (priv->rx_pause)
885			mac_control |= BIT(3);
886
887		if (priv->tx_pause)
888			mac_control |= BIT(4);
889
890		*link = true;
891	} else {
892		mac_control = 0;
893		/* disable forwarding */
894		cpsw_ale_control_set(priv->ale, slave_port,
895				     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
896	}
897
898	if (mac_control != slave->mac_control) {
899		phy_print_status(phy);
900		__raw_writel(mac_control, &slave->sliver->mac_control);
901	}
902
903	slave->mac_control = mac_control;
904}
905
906static void cpsw_adjust_link(struct net_device *ndev)
907{
908	struct cpsw_priv	*priv = netdev_priv(ndev);
909	bool			link = false;
910
911	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
912
913	if (link) {
914		netif_carrier_on(ndev);
915		if (netif_running(ndev))
916			netif_wake_queue(ndev);
917	} else {
918		netif_carrier_off(ndev);
919		netif_stop_queue(ndev);
920	}
921}
922
923static int cpsw_get_coalesce(struct net_device *ndev,
924				struct ethtool_coalesce *coal)
925{
926	struct cpsw_priv *priv = netdev_priv(ndev);
927
928	coal->rx_coalesce_usecs = priv->coal_intvl;
929	return 0;
930}
931
932static int cpsw_set_coalesce(struct net_device *ndev,
933				struct ethtool_coalesce *coal)
934{
935	struct cpsw_priv *priv = netdev_priv(ndev);
936	u32 int_ctrl;
937	u32 num_interrupts = 0;
938	u32 prescale = 0;
939	u32 addnl_dvdr = 1;
940	u32 coal_intvl = 0;
941
942	coal_intvl = coal->rx_coalesce_usecs;
943
944	int_ctrl =  readl(&priv->wr_regs->int_control);
945	prescale = priv->bus_freq_mhz * 4;
946
947	if (!coal->rx_coalesce_usecs) {
948		int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
949		goto update_return;
950	}
951
952	if (coal_intvl < CPSW_CMINTMIN_INTVL)
953		coal_intvl = CPSW_CMINTMIN_INTVL;
954
955	if (coal_intvl > CPSW_CMINTMAX_INTVL) {
956		/* Interrupt pacer works with 4us Pulse, we can
957		 * throttle further by dilating the 4us pulse.
958		 */
959		addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
960
961		if (addnl_dvdr > 1) {
962			prescale *= addnl_dvdr;
963			if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
964				coal_intvl = (CPSW_CMINTMAX_INTVL
965						* addnl_dvdr);
966		} else {
967			addnl_dvdr = 1;
968			coal_intvl = CPSW_CMINTMAX_INTVL;
969		}
970	}
971
972	num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
973	writel(num_interrupts, &priv->wr_regs->rx_imax);
974	writel(num_interrupts, &priv->wr_regs->tx_imax);
975
976	int_ctrl |= CPSW_INTPACEEN;
977	int_ctrl &= (~CPSW_INTPRESCALE_MASK);
978	int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
979
980update_return:
981	writel(int_ctrl, &priv->wr_regs->int_control);
982
983	cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
984	if (priv->data.dual_emac) {
985		int i;
986
987		for (i = 0; i < priv->data.slaves; i++) {
988			priv = netdev_priv(priv->slaves[i].ndev);
989			priv->coal_intvl = coal_intvl;
990		}
991	} else {
992		priv->coal_intvl = coal_intvl;
993	}
994
995	return 0;
996}
997
998static int cpsw_get_sset_count(struct net_device *ndev, int sset)
999{
1000	switch (sset) {
1001	case ETH_SS_STATS:
1002		return CPSW_STATS_LEN;
1003	default:
1004		return -EOPNOTSUPP;
1005	}
1006}
1007
1008static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1009{
1010	u8 *p = data;
1011	int i;
1012
1013	switch (stringset) {
1014	case ETH_SS_STATS:
1015		for (i = 0; i < CPSW_STATS_LEN; i++) {
1016			memcpy(p, cpsw_gstrings_stats[i].stat_string,
1017			       ETH_GSTRING_LEN);
1018			p += ETH_GSTRING_LEN;
1019		}
1020		break;
1021	}
1022}
1023
1024static void cpsw_get_ethtool_stats(struct net_device *ndev,
1025				    struct ethtool_stats *stats, u64 *data)
1026{
1027	struct cpsw_priv *priv = netdev_priv(ndev);
1028	struct cpdma_chan_stats rx_stats;
1029	struct cpdma_chan_stats tx_stats;
1030	u32 val;
1031	u8 *p;
1032	int i;
1033
1034	/* Collect Davinci CPDMA stats for Rx and Tx Channel */
1035	cpdma_chan_get_stats(priv->rxch, &rx_stats);
1036	cpdma_chan_get_stats(priv->txch, &tx_stats);
1037
1038	for (i = 0; i < CPSW_STATS_LEN; i++) {
1039		switch (cpsw_gstrings_stats[i].type) {
1040		case CPSW_STATS:
1041			val = readl(priv->hw_stats +
1042				    cpsw_gstrings_stats[i].stat_offset);
1043			data[i] = val;
1044			break;
1045
1046		case CPDMA_RX_STATS:
1047			p = (u8 *)&rx_stats +
1048				cpsw_gstrings_stats[i].stat_offset;
1049			data[i] = *(u32 *)p;
1050			break;
1051
1052		case CPDMA_TX_STATS:
1053			p = (u8 *)&tx_stats +
1054				cpsw_gstrings_stats[i].stat_offset;
1055			data[i] = *(u32 *)p;
1056			break;
1057		}
1058	}
1059}
1060
1061static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1062{
1063	u32 i;
1064	u32 usage_count = 0;
1065
1066	if (!priv->data.dual_emac)
1067		return 0;
1068
1069	for (i = 0; i < priv->data.slaves; i++)
1070		if (priv->slaves[i].open_stat)
1071			usage_count++;
1072
1073	return usage_count;
1074}
1075
1076static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1077			struct cpsw_priv *priv, struct sk_buff *skb)
1078{
1079	if (!priv->data.dual_emac)
1080		return cpdma_chan_submit(priv->txch, skb, skb->data,
1081				  skb->len, 0);
1082
1083	if (ndev == cpsw_get_slave_ndev(priv, 0))
1084		return cpdma_chan_submit(priv->txch, skb, skb->data,
1085				  skb->len, 1);
1086	else
1087		return cpdma_chan_submit(priv->txch, skb, skb->data,
1088				  skb->len, 2);
1089}
1090
1091static inline void cpsw_add_dual_emac_def_ale_entries(
1092		struct cpsw_priv *priv, struct cpsw_slave *slave,
1093		u32 slave_port)
1094{
1095	u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1096
1097	if (priv->version == CPSW_VERSION_1)
1098		slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1099	else
1100		slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1101	cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1102			  port_mask, port_mask, 0);
1103	cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1104			   port_mask, ALE_VLAN, slave->port_vlan, 0);
1105	cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1106		priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1107}
1108
1109static void soft_reset_slave(struct cpsw_slave *slave)
1110{
1111	char name[32];
1112
1113	snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1114	soft_reset(name, &slave->sliver->soft_reset);
1115}
1116
1117static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1118{
1119	u32 slave_port;
1120
1121	soft_reset_slave(slave);
1122
1123	/* setup priority mapping */
1124	__raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1125
1126	switch (priv->version) {
1127	case CPSW_VERSION_1:
1128		slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1129		break;
1130	case CPSW_VERSION_2:
1131	case CPSW_VERSION_3:
1132	case CPSW_VERSION_4:
1133		slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1134		break;
1135	}
1136
1137	/* setup max packet size, and mac address */
1138	__raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1139	cpsw_set_slave_mac(slave, priv);
1140
1141	slave->mac_control = 0;	/* no link yet */
1142
1143	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1144
1145	if (priv->data.dual_emac)
1146		cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1147	else
1148		cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1149				   1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1150
1151	slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1152				 &cpsw_adjust_link, slave->data->phy_if);
1153	if (IS_ERR(slave->phy)) {
1154		dev_err(priv->dev, "phy %s not found on slave %d\n",
1155			slave->data->phy_id, slave->slave_num);
1156		slave->phy = NULL;
1157	} else {
1158		dev_info(priv->dev, "phy found : id is : 0x%x\n",
1159			 slave->phy->phy_id);
1160		phy_start(slave->phy);
1161
1162		/* Configure GMII_SEL register */
1163		cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1164			     slave->slave_num);
1165	}
1166}
1167
1168static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1169{
1170	const int vlan = priv->data.default_vlan;
1171	const int port = priv->host_port;
1172	u32 reg;
1173	int i;
1174	int unreg_mcast_mask;
1175
1176	reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1177	       CPSW2_PORT_VLAN;
1178
1179	writel(vlan, &priv->host_port_regs->port_vlan);
1180
1181	for (i = 0; i < priv->data.slaves; i++)
1182		slave_write(priv->slaves + i, vlan, reg);
1183
1184	if (priv->ndev->flags & IFF_ALLMULTI)
1185		unreg_mcast_mask = ALE_ALL_PORTS;
1186	else
1187		unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1188
1189	cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1190			  ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1191			  unreg_mcast_mask << port);
1192}
1193
1194static void cpsw_init_host_port(struct cpsw_priv *priv)
1195{
1196	u32 control_reg;
1197	u32 fifo_mode;
1198
1199	/* soft reset the controller and initialize ale */
1200	soft_reset("cpsw", &priv->regs->soft_reset);
1201	cpsw_ale_start(priv->ale);
1202
1203	/* switch to vlan unaware mode */
1204	cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1205			     CPSW_ALE_VLAN_AWARE);
1206	control_reg = readl(&priv->regs->control);
1207	control_reg |= CPSW_VLAN_AWARE;
1208	writel(control_reg, &priv->regs->control);
1209	fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1210		     CPSW_FIFO_NORMAL_MODE;
1211	writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1212
1213	/* setup host port priority mapping */
1214	__raw_writel(CPDMA_TX_PRIORITY_MAP,
1215		     &priv->host_port_regs->cpdma_tx_pri_map);
1216	__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1217
1218	cpsw_ale_control_set(priv->ale, priv->host_port,
1219			     ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1220
1221	if (!priv->data.dual_emac) {
1222		cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1223				   0, 0);
1224		cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1225				   1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1226	}
1227}
1228
1229static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1230{
1231	u32 slave_port;
1232
1233	slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1234
1235	if (!slave->phy)
1236		return;
1237	phy_stop(slave->phy);
1238	phy_disconnect(slave->phy);
1239	slave->phy = NULL;
1240	cpsw_ale_control_set(priv->ale, slave_port,
1241			     ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1242}
1243
1244static int cpsw_ndo_open(struct net_device *ndev)
1245{
1246	struct cpsw_priv *priv = netdev_priv(ndev);
1247	struct cpsw_priv *prim_cpsw;
1248	int i, ret;
1249	u32 reg;
1250
1251	if (!cpsw_common_res_usage_state(priv))
1252		cpsw_intr_disable(priv);
1253	netif_carrier_off(ndev);
1254
1255	pm_runtime_get_sync(&priv->pdev->dev);
1256
1257	reg = priv->version;
1258
1259	dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1260		 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1261		 CPSW_RTL_VERSION(reg));
1262
1263	/* initialize host and slave ports */
1264	if (!cpsw_common_res_usage_state(priv))
1265		cpsw_init_host_port(priv);
1266	for_each_slave(priv, cpsw_slave_open, priv);
1267
1268	/* Add default VLAN */
1269	if (!priv->data.dual_emac)
1270		cpsw_add_default_vlan(priv);
1271	else
1272		cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1273				  ALE_ALL_PORTS << priv->host_port,
1274				  ALE_ALL_PORTS << priv->host_port, 0, 0);
1275
1276	if (!cpsw_common_res_usage_state(priv)) {
1277		/* setup tx dma to fixed prio and zero offset */
1278		cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1279		cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1280
1281		/* disable priority elevation */
1282		__raw_writel(0, &priv->regs->ptype);
1283
1284		/* enable statistics collection only on all ports */
1285		__raw_writel(0x7, &priv->regs->stat_port_en);
1286
1287		/* Enable internal fifo flow control */
1288		writel(0x7, &priv->regs->flow_control);
1289
1290		if (WARN_ON(!priv->data.rx_descs))
1291			priv->data.rx_descs = 128;
1292
1293		for (i = 0; i < priv->data.rx_descs; i++) {
1294			struct sk_buff *skb;
1295
1296			ret = -ENOMEM;
1297			skb = __netdev_alloc_skb_ip_align(priv->ndev,
1298					priv->rx_packet_max, GFP_KERNEL);
1299			if (!skb)
1300				goto err_cleanup;
1301			ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1302					skb_tailroom(skb), 0);
1303			if (ret < 0) {
1304				kfree_skb(skb);
1305				goto err_cleanup;
1306			}
1307		}
1308		/* continue even if we didn't manage to submit all
1309		 * receive descs
1310		 */
1311		cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1312
1313		if (cpts_register(&priv->pdev->dev, priv->cpts,
1314				  priv->data.cpts_clock_mult,
1315				  priv->data.cpts_clock_shift))
1316			dev_err(priv->dev, "error registering cpts device\n");
1317
1318	}
1319
1320	/* Enable Interrupt pacing if configured */
1321	if (priv->coal_intvl != 0) {
1322		struct ethtool_coalesce coal;
1323
1324		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1325		cpsw_set_coalesce(ndev, &coal);
1326	}
1327
1328	napi_enable(&priv->napi);
1329	cpdma_ctlr_start(priv->dma);
1330	cpsw_intr_enable(priv);
1331
1332	prim_cpsw = cpsw_get_slave_priv(priv, 0);
1333	if (prim_cpsw->irq_enabled == false) {
1334		if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1335			prim_cpsw->irq_enabled = true;
1336			cpsw_enable_irq(prim_cpsw);
1337		}
1338	}
1339
1340	if (priv->data.dual_emac)
1341		priv->slaves[priv->emac_port].open_stat = true;
1342	return 0;
1343
1344err_cleanup:
1345	cpdma_ctlr_stop(priv->dma);
1346	for_each_slave(priv, cpsw_slave_stop, priv);
1347	pm_runtime_put_sync(&priv->pdev->dev);
1348	netif_carrier_off(priv->ndev);
1349	return ret;
1350}
1351
1352static int cpsw_ndo_stop(struct net_device *ndev)
1353{
1354	struct cpsw_priv *priv = netdev_priv(ndev);
1355
1356	cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1357	netif_stop_queue(priv->ndev);
1358	napi_disable(&priv->napi);
1359	netif_carrier_off(priv->ndev);
1360
1361	if (cpsw_common_res_usage_state(priv) <= 1) {
1362		cpts_unregister(priv->cpts);
1363		cpsw_intr_disable(priv);
1364		cpdma_ctlr_int_ctrl(priv->dma, false);
1365		cpdma_ctlr_stop(priv->dma);
1366		cpsw_ale_stop(priv->ale);
1367	}
1368	for_each_slave(priv, cpsw_slave_stop, priv);
1369	pm_runtime_put_sync(&priv->pdev->dev);
1370	if (priv->data.dual_emac)
1371		priv->slaves[priv->emac_port].open_stat = false;
1372	return 0;
1373}
1374
1375static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1376				       struct net_device *ndev)
1377{
1378	struct cpsw_priv *priv = netdev_priv(ndev);
1379	int ret;
1380
1381	ndev->trans_start = jiffies;
1382
1383	if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1384		cpsw_err(priv, tx_err, "packet pad failed\n");
1385		ndev->stats.tx_dropped++;
1386		return NETDEV_TX_OK;
1387	}
1388
1389	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1390				priv->cpts->tx_enable)
1391		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1392
1393	skb_tx_timestamp(skb);
1394
1395	ret = cpsw_tx_packet_submit(ndev, priv, skb);
1396	if (unlikely(ret != 0)) {
1397		cpsw_err(priv, tx_err, "desc submit failed\n");
1398		goto fail;
1399	}
1400
1401	/* If there is no more tx desc left free then we need to
1402	 * tell the kernel to stop sending us tx frames.
1403	 */
1404	if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1405		netif_stop_queue(ndev);
1406
1407	return NETDEV_TX_OK;
1408fail:
1409	ndev->stats.tx_dropped++;
1410	netif_stop_queue(ndev);
1411	return NETDEV_TX_BUSY;
1412}
1413
1414#ifdef CONFIG_TI_CPTS
1415
1416static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1417{
1418	struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1419	u32 ts_en, seq_id;
1420
1421	if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1422		slave_write(slave, 0, CPSW1_TS_CTL);
1423		return;
1424	}
1425
1426	seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1427	ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1428
1429	if (priv->cpts->tx_enable)
1430		ts_en |= CPSW_V1_TS_TX_EN;
1431
1432	if (priv->cpts->rx_enable)
1433		ts_en |= CPSW_V1_TS_RX_EN;
1434
1435	slave_write(slave, ts_en, CPSW1_TS_CTL);
1436	slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1437}
1438
1439static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1440{
1441	struct cpsw_slave *slave;
1442	u32 ctrl, mtype;
1443
1444	if (priv->data.dual_emac)
1445		slave = &priv->slaves[priv->emac_port];
1446	else
1447		slave = &priv->slaves[priv->data.active_slave];
1448
1449	ctrl = slave_read(slave, CPSW2_CONTROL);
1450	switch (priv->version) {
1451	case CPSW_VERSION_2:
1452		ctrl &= ~CTRL_V2_ALL_TS_MASK;
1453
1454		if (priv->cpts->tx_enable)
1455			ctrl |= CTRL_V2_TX_TS_BITS;
1456
1457		if (priv->cpts->rx_enable)
1458			ctrl |= CTRL_V2_RX_TS_BITS;
1459	break;
1460	case CPSW_VERSION_3:
1461	default:
1462		ctrl &= ~CTRL_V3_ALL_TS_MASK;
1463
1464		if (priv->cpts->tx_enable)
1465			ctrl |= CTRL_V3_TX_TS_BITS;
1466
1467		if (priv->cpts->rx_enable)
1468			ctrl |= CTRL_V3_RX_TS_BITS;
1469	break;
1470	}
1471
1472	mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1473
1474	slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1475	slave_write(slave, ctrl, CPSW2_CONTROL);
1476	__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1477}
1478
1479static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1480{
1481	struct cpsw_priv *priv = netdev_priv(dev);
1482	struct cpts *cpts = priv->cpts;
1483	struct hwtstamp_config cfg;
1484
1485	if (priv->version != CPSW_VERSION_1 &&
1486	    priv->version != CPSW_VERSION_2 &&
1487	    priv->version != CPSW_VERSION_3)
1488		return -EOPNOTSUPP;
1489
1490	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1491		return -EFAULT;
1492
1493	/* reserved for future extensions */
1494	if (cfg.flags)
1495		return -EINVAL;
1496
1497	if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1498		return -ERANGE;
1499
1500	switch (cfg.rx_filter) {
1501	case HWTSTAMP_FILTER_NONE:
1502		cpts->rx_enable = 0;
1503		break;
1504	case HWTSTAMP_FILTER_ALL:
1505	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1506	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1507	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1508		return -ERANGE;
1509	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1510	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1511	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1512	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1513	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1514	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1515	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1516	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1517	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1518		cpts->rx_enable = 1;
1519		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1520		break;
1521	default:
1522		return -ERANGE;
1523	}
1524
1525	cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1526
1527	switch (priv->version) {
1528	case CPSW_VERSION_1:
1529		cpsw_hwtstamp_v1(priv);
1530		break;
1531	case CPSW_VERSION_2:
1532	case CPSW_VERSION_3:
1533		cpsw_hwtstamp_v2(priv);
1534		break;
1535	default:
1536		WARN_ON(1);
1537	}
1538
1539	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1540}
1541
1542static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1543{
1544	struct cpsw_priv *priv = netdev_priv(dev);
1545	struct cpts *cpts = priv->cpts;
1546	struct hwtstamp_config cfg;
1547
1548	if (priv->version != CPSW_VERSION_1 &&
1549	    priv->version != CPSW_VERSION_2 &&
1550	    priv->version != CPSW_VERSION_3)
1551		return -EOPNOTSUPP;
1552
1553	cfg.flags = 0;
1554	cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1555	cfg.rx_filter = (cpts->rx_enable ?
1556			 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1557
1558	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1559}
1560
1561#endif /*CONFIG_TI_CPTS*/
1562
1563static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1564{
1565	struct cpsw_priv *priv = netdev_priv(dev);
1566	int slave_no = cpsw_slave_index(priv);
1567
1568	if (!netif_running(dev))
1569		return -EINVAL;
1570
1571	switch (cmd) {
1572#ifdef CONFIG_TI_CPTS
1573	case SIOCSHWTSTAMP:
1574		return cpsw_hwtstamp_set(dev, req);
1575	case SIOCGHWTSTAMP:
1576		return cpsw_hwtstamp_get(dev, req);
1577#endif
1578	}
1579
1580	if (!priv->slaves[slave_no].phy)
1581		return -EOPNOTSUPP;
1582	return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1583}
1584
1585static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1586{
1587	struct cpsw_priv *priv = netdev_priv(ndev);
1588
1589	cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1590	ndev->stats.tx_errors++;
1591	cpsw_intr_disable(priv);
1592	cpdma_ctlr_int_ctrl(priv->dma, false);
1593	cpdma_chan_stop(priv->txch);
1594	cpdma_chan_start(priv->txch);
1595	cpdma_ctlr_int_ctrl(priv->dma, true);
1596	cpsw_intr_enable(priv);
1597}
1598
1599static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1600{
1601	struct cpsw_priv *priv = netdev_priv(ndev);
1602	struct sockaddr *addr = (struct sockaddr *)p;
1603	int flags = 0;
1604	u16 vid = 0;
1605
1606	if (!is_valid_ether_addr(addr->sa_data))
1607		return -EADDRNOTAVAIL;
1608
1609	if (priv->data.dual_emac) {
1610		vid = priv->slaves[priv->emac_port].port_vlan;
1611		flags = ALE_VLAN;
1612	}
1613
1614	cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1615			   flags, vid);
1616	cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1617			   flags, vid);
1618
1619	memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1620	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1621	for_each_slave(priv, cpsw_set_slave_mac, priv);
1622
1623	return 0;
1624}
1625
1626#ifdef CONFIG_NET_POLL_CONTROLLER
1627static void cpsw_ndo_poll_controller(struct net_device *ndev)
1628{
1629	struct cpsw_priv *priv = netdev_priv(ndev);
1630
1631	cpsw_intr_disable(priv);
1632	cpdma_ctlr_int_ctrl(priv->dma, false);
1633	cpsw_rx_interrupt(priv->irqs_table[0], priv);
1634	cpsw_tx_interrupt(priv->irqs_table[1], priv);
1635	cpdma_ctlr_int_ctrl(priv->dma, true);
1636	cpsw_intr_enable(priv);
1637}
1638#endif
1639
1640static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1641				unsigned short vid)
1642{
1643	int ret;
1644	int unreg_mcast_mask = 0;
1645	u32 port_mask;
1646
1647	if (priv->data.dual_emac) {
1648		port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1649
1650		if (priv->ndev->flags & IFF_ALLMULTI)
1651			unreg_mcast_mask = port_mask;
1652	} else {
1653		port_mask = ALE_ALL_PORTS;
1654
1655		if (priv->ndev->flags & IFF_ALLMULTI)
1656			unreg_mcast_mask = ALE_ALL_PORTS;
1657		else
1658			unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1659	}
1660
1661	ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1662				unreg_mcast_mask << priv->host_port);
1663	if (ret != 0)
1664		return ret;
1665
1666	ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1667				 priv->host_port, ALE_VLAN, vid);
1668	if (ret != 0)
1669		goto clean_vid;
1670
1671	ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1672				 port_mask, ALE_VLAN, vid, 0);
1673	if (ret != 0)
1674		goto clean_vlan_ucast;
1675	return 0;
1676
1677clean_vlan_ucast:
1678	cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1679			    priv->host_port, ALE_VLAN, vid);
1680clean_vid:
1681	cpsw_ale_del_vlan(priv->ale, vid, 0);
1682	return ret;
1683}
1684
1685static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1686				    __be16 proto, u16 vid)
1687{
1688	struct cpsw_priv *priv = netdev_priv(ndev);
1689
1690	if (vid == priv->data.default_vlan)
1691		return 0;
1692
1693	if (priv->data.dual_emac) {
1694		/* In dual EMAC, reserved VLAN id should not be used for
1695		 * creating VLAN interfaces as this can break the dual
1696		 * EMAC port separation
1697		 */
1698		int i;
1699
1700		for (i = 0; i < priv->data.slaves; i++) {
1701			if (vid == priv->slaves[i].port_vlan)
1702				return -EINVAL;
1703		}
1704	}
1705
1706	dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1707	return cpsw_add_vlan_ale_entry(priv, vid);
1708}
1709
1710static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1711				     __be16 proto, u16 vid)
1712{
1713	struct cpsw_priv *priv = netdev_priv(ndev);
1714	int ret;
1715
1716	if (vid == priv->data.default_vlan)
1717		return 0;
1718
1719	if (priv->data.dual_emac) {
1720		int i;
1721
1722		for (i = 0; i < priv->data.slaves; i++) {
1723			if (vid == priv->slaves[i].port_vlan)
1724				return -EINVAL;
1725		}
1726	}
1727
1728	dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1729	ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1730	if (ret != 0)
1731		return ret;
1732
1733	ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1734				 priv->host_port, ALE_VLAN, vid);
1735	if (ret != 0)
1736		return ret;
1737
1738	return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1739				  0, ALE_VLAN, vid);
1740}
1741
1742static const struct net_device_ops cpsw_netdev_ops = {
1743	.ndo_open		= cpsw_ndo_open,
1744	.ndo_stop		= cpsw_ndo_stop,
1745	.ndo_start_xmit		= cpsw_ndo_start_xmit,
1746	.ndo_set_mac_address	= cpsw_ndo_set_mac_address,
1747	.ndo_do_ioctl		= cpsw_ndo_ioctl,
1748	.ndo_validate_addr	= eth_validate_addr,
1749	.ndo_change_mtu		= eth_change_mtu,
1750	.ndo_tx_timeout		= cpsw_ndo_tx_timeout,
1751	.ndo_set_rx_mode	= cpsw_ndo_set_rx_mode,
1752#ifdef CONFIG_NET_POLL_CONTROLLER
1753	.ndo_poll_controller	= cpsw_ndo_poll_controller,
1754#endif
1755	.ndo_vlan_rx_add_vid	= cpsw_ndo_vlan_rx_add_vid,
1756	.ndo_vlan_rx_kill_vid	= cpsw_ndo_vlan_rx_kill_vid,
1757};
1758
1759static int cpsw_get_regs_len(struct net_device *ndev)
1760{
1761	struct cpsw_priv *priv = netdev_priv(ndev);
1762
1763	return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1764}
1765
1766static void cpsw_get_regs(struct net_device *ndev,
1767			  struct ethtool_regs *regs, void *p)
1768{
1769	struct cpsw_priv *priv = netdev_priv(ndev);
1770	u32 *reg = p;
1771
1772	/* update CPSW IP version */
1773	regs->version = priv->version;
1774
1775	cpsw_ale_dump(priv->ale, reg);
1776}
1777
1778static void cpsw_get_drvinfo(struct net_device *ndev,
1779			     struct ethtool_drvinfo *info)
1780{
1781	struct cpsw_priv *priv = netdev_priv(ndev);
1782
1783	strlcpy(info->driver, "cpsw", sizeof(info->driver));
1784	strlcpy(info->version, "1.0", sizeof(info->version));
1785	strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1786	info->regdump_len = cpsw_get_regs_len(ndev);
1787}
1788
1789static u32 cpsw_get_msglevel(struct net_device *ndev)
1790{
1791	struct cpsw_priv *priv = netdev_priv(ndev);
1792	return priv->msg_enable;
1793}
1794
1795static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1796{
1797	struct cpsw_priv *priv = netdev_priv(ndev);
1798	priv->msg_enable = value;
1799}
1800
1801static int cpsw_get_ts_info(struct net_device *ndev,
1802			    struct ethtool_ts_info *info)
1803{
1804#ifdef CONFIG_TI_CPTS
1805	struct cpsw_priv *priv = netdev_priv(ndev);
1806
1807	info->so_timestamping =
1808		SOF_TIMESTAMPING_TX_HARDWARE |
1809		SOF_TIMESTAMPING_TX_SOFTWARE |
1810		SOF_TIMESTAMPING_RX_HARDWARE |
1811		SOF_TIMESTAMPING_RX_SOFTWARE |
1812		SOF_TIMESTAMPING_SOFTWARE |
1813		SOF_TIMESTAMPING_RAW_HARDWARE;
1814	info->phc_index = priv->cpts->phc_index;
1815	info->tx_types =
1816		(1 << HWTSTAMP_TX_OFF) |
1817		(1 << HWTSTAMP_TX_ON);
1818	info->rx_filters =
1819		(1 << HWTSTAMP_FILTER_NONE) |
1820		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1821#else
1822	info->so_timestamping =
1823		SOF_TIMESTAMPING_TX_SOFTWARE |
1824		SOF_TIMESTAMPING_RX_SOFTWARE |
1825		SOF_TIMESTAMPING_SOFTWARE;
1826	info->phc_index = -1;
1827	info->tx_types = 0;
1828	info->rx_filters = 0;
1829#endif
1830	return 0;
1831}
1832
1833static int cpsw_get_settings(struct net_device *ndev,
1834			     struct ethtool_cmd *ecmd)
1835{
1836	struct cpsw_priv *priv = netdev_priv(ndev);
1837	int slave_no = cpsw_slave_index(priv);
1838
1839	if (priv->slaves[slave_no].phy)
1840		return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1841	else
1842		return -EOPNOTSUPP;
1843}
1844
1845static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1846{
1847	struct cpsw_priv *priv = netdev_priv(ndev);
1848	int slave_no = cpsw_slave_index(priv);
1849
1850	if (priv->slaves[slave_no].phy)
1851		return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1852	else
1853		return -EOPNOTSUPP;
1854}
1855
1856static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1857{
1858	struct cpsw_priv *priv = netdev_priv(ndev);
1859	int slave_no = cpsw_slave_index(priv);
1860
1861	wol->supported = 0;
1862	wol->wolopts = 0;
1863
1864	if (priv->slaves[slave_no].phy)
1865		phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1866}
1867
1868static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1869{
1870	struct cpsw_priv *priv = netdev_priv(ndev);
1871	int slave_no = cpsw_slave_index(priv);
1872
1873	if (priv->slaves[slave_no].phy)
1874		return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1875	else
1876		return -EOPNOTSUPP;
1877}
1878
1879static void cpsw_get_pauseparam(struct net_device *ndev,
1880				struct ethtool_pauseparam *pause)
1881{
1882	struct cpsw_priv *priv = netdev_priv(ndev);
1883
1884	pause->autoneg = AUTONEG_DISABLE;
1885	pause->rx_pause = priv->rx_pause ? true : false;
1886	pause->tx_pause = priv->tx_pause ? true : false;
1887}
1888
1889static int cpsw_set_pauseparam(struct net_device *ndev,
1890			       struct ethtool_pauseparam *pause)
1891{
1892	struct cpsw_priv *priv = netdev_priv(ndev);
1893	bool link;
1894
1895	priv->rx_pause = pause->rx_pause ? true : false;
1896	priv->tx_pause = pause->tx_pause ? true : false;
1897
1898	for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1899
1900	return 0;
1901}
1902
1903static const struct ethtool_ops cpsw_ethtool_ops = {
1904	.get_drvinfo	= cpsw_get_drvinfo,
1905	.get_msglevel	= cpsw_get_msglevel,
1906	.set_msglevel	= cpsw_set_msglevel,
1907	.get_link	= ethtool_op_get_link,
1908	.get_ts_info	= cpsw_get_ts_info,
1909	.get_settings	= cpsw_get_settings,
1910	.set_settings	= cpsw_set_settings,
1911	.get_coalesce	= cpsw_get_coalesce,
1912	.set_coalesce	= cpsw_set_coalesce,
1913	.get_sset_count		= cpsw_get_sset_count,
1914	.get_strings		= cpsw_get_strings,
1915	.get_ethtool_stats	= cpsw_get_ethtool_stats,
1916	.get_pauseparam		= cpsw_get_pauseparam,
1917	.set_pauseparam		= cpsw_set_pauseparam,
1918	.get_wol	= cpsw_get_wol,
1919	.set_wol	= cpsw_set_wol,
1920	.get_regs_len	= cpsw_get_regs_len,
1921	.get_regs	= cpsw_get_regs,
1922};
1923
1924static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1925			    u32 slave_reg_ofs, u32 sliver_reg_ofs)
1926{
1927	void __iomem		*regs = priv->regs;
1928	int			slave_num = slave->slave_num;
1929	struct cpsw_slave_data	*data = priv->data.slave_data + slave_num;
1930
1931	slave->data	= data;
1932	slave->regs	= regs + slave_reg_ofs;
1933	slave->sliver	= regs + sliver_reg_ofs;
1934	slave->port_vlan = data->dual_emac_res_vlan;
1935}
1936
1937static int cpsw_probe_dt(struct cpsw_platform_data *data,
1938			 struct platform_device *pdev)
1939{
1940	struct device_node *node = pdev->dev.of_node;
1941	struct device_node *slave_node;
1942	int i = 0, ret;
1943	u32 prop;
1944
1945	if (!node)
1946		return -EINVAL;
1947
1948	if (of_property_read_u32(node, "slaves", &prop)) {
1949		dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1950		return -EINVAL;
1951	}
1952	data->slaves = prop;
1953
1954	if (of_property_read_u32(node, "active_slave", &prop)) {
1955		dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1956		return -EINVAL;
1957	}
1958	data->active_slave = prop;
1959
1960	if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1961		dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1962		return -EINVAL;
1963	}
1964	data->cpts_clock_mult = prop;
1965
1966	if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1967		dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1968		return -EINVAL;
1969	}
1970	data->cpts_clock_shift = prop;
1971
1972	data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1973					* sizeof(struct cpsw_slave_data),
1974					GFP_KERNEL);
1975	if (!data->slave_data)
1976		return -ENOMEM;
1977
1978	if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1979		dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1980		return -EINVAL;
1981	}
1982	data->channels = prop;
1983
1984	if (of_property_read_u32(node, "ale_entries", &prop)) {
1985		dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1986		return -EINVAL;
1987	}
1988	data->ale_entries = prop;
1989
1990	if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1991		dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1992		return -EINVAL;
1993	}
1994	data->bd_ram_size = prop;
1995
1996	if (of_property_read_u32(node, "rx_descs", &prop)) {
1997		dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1998		return -EINVAL;
1999	}
2000	data->rx_descs = prop;
2001
2002	if (of_property_read_u32(node, "mac_control", &prop)) {
2003		dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2004		return -EINVAL;
2005	}
2006	data->mac_control = prop;
2007
2008	if (of_property_read_bool(node, "dual_emac"))
2009		data->dual_emac = 1;
2010
2011	/*
2012	 * Populate all the child nodes here...
2013	 */
2014	ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2015	/* We do not want to force this, as in some cases may not have child */
2016	if (ret)
2017		dev_warn(&pdev->dev, "Doesn't have any child node\n");
2018
2019	for_each_child_of_node(node, slave_node) {
2020		struct cpsw_slave_data *slave_data = data->slave_data + i;
2021		const void *mac_addr = NULL;
2022		u32 phyid;
2023		int lenp;
2024		const __be32 *parp;
2025		struct device_node *mdio_node;
2026		struct platform_device *mdio;
2027
2028		/* This is no slave child node, continue */
2029		if (strcmp(slave_node->name, "slave"))
2030			continue;
2031
2032		parp = of_get_property(slave_node, "phy_id", &lenp);
2033		if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2034			dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2035			goto no_phy_slave;
2036		}
2037		mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2038		phyid = be32_to_cpup(parp+1);
2039		mdio = of_find_device_by_node(mdio_node);
2040		of_node_put(mdio_node);
2041		if (!mdio) {
2042			dev_err(&pdev->dev, "Missing mdio platform device\n");
2043			return -EINVAL;
2044		}
2045		snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2046			 PHY_ID_FMT, mdio->name, phyid);
2047
2048		slave_data->phy_if = of_get_phy_mode(slave_node);
2049		if (slave_data->phy_if < 0) {
2050			dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2051				i);
2052			return slave_data->phy_if;
2053		}
2054
2055no_phy_slave:
2056		mac_addr = of_get_mac_address(slave_node);
2057		if (mac_addr) {
2058			memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2059		} else {
2060			if (of_machine_is_compatible("ti,am33xx")) {
2061				ret = cpsw_am33xx_cm_get_macid(&pdev->dev,
2062							0x630, i,
2063							slave_data->mac_addr);
2064				if (ret)
2065					return ret;
2066			}
2067		}
2068		if (data->dual_emac) {
2069			if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2070						 &prop)) {
2071				dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2072				slave_data->dual_emac_res_vlan = i+1;
2073				dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2074					slave_data->dual_emac_res_vlan, i);
2075			} else {
2076				slave_data->dual_emac_res_vlan = prop;
2077			}
2078		}
2079
2080		i++;
2081		if (i == data->slaves)
2082			break;
2083	}
2084
2085	return 0;
2086}
2087
2088static int cpsw_probe_dual_emac(struct platform_device *pdev,
2089				struct cpsw_priv *priv)
2090{
2091	struct cpsw_platform_data	*data = &priv->data;
2092	struct net_device		*ndev;
2093	struct cpsw_priv		*priv_sl2;
2094	int ret = 0, i;
2095
2096	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2097	if (!ndev) {
2098		dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2099		return -ENOMEM;
2100	}
2101
2102	priv_sl2 = netdev_priv(ndev);
2103	spin_lock_init(&priv_sl2->lock);
2104	priv_sl2->data = *data;
2105	priv_sl2->pdev = pdev;
2106	priv_sl2->ndev = ndev;
2107	priv_sl2->dev  = &ndev->dev;
2108	priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2109	priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2110
2111	if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2112		memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2113			ETH_ALEN);
2114		dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2115	} else {
2116		random_ether_addr(priv_sl2->mac_addr);
2117		dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2118	}
2119	memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2120
2121	priv_sl2->slaves = priv->slaves;
2122	priv_sl2->clk = priv->clk;
2123
2124	priv_sl2->coal_intvl = 0;
2125	priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2126
2127	priv_sl2->regs = priv->regs;
2128	priv_sl2->host_port = priv->host_port;
2129	priv_sl2->host_port_regs = priv->host_port_regs;
2130	priv_sl2->wr_regs = priv->wr_regs;
2131	priv_sl2->hw_stats = priv->hw_stats;
2132	priv_sl2->dma = priv->dma;
2133	priv_sl2->txch = priv->txch;
2134	priv_sl2->rxch = priv->rxch;
2135	priv_sl2->ale = priv->ale;
2136	priv_sl2->emac_port = 1;
2137	priv->slaves[1].ndev = ndev;
2138	priv_sl2->cpts = priv->cpts;
2139	priv_sl2->version = priv->version;
2140
2141	for (i = 0; i < priv->num_irqs; i++) {
2142		priv_sl2->irqs_table[i] = priv->irqs_table[i];
2143		priv_sl2->num_irqs = priv->num_irqs;
2144	}
2145	ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2146
2147	ndev->netdev_ops = &cpsw_netdev_ops;
2148	ndev->ethtool_ops = &cpsw_ethtool_ops;
2149	netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2150
2151	/* register the network device */
2152	SET_NETDEV_DEV(ndev, &pdev->dev);
2153	ret = register_netdev(ndev);
2154	if (ret) {
2155		dev_err(&pdev->dev, "cpsw: error registering net device\n");
2156		free_netdev(ndev);
2157		ret = -ENODEV;
2158	}
2159
2160	return ret;
2161}
2162
2163static int cpsw_probe(struct platform_device *pdev)
2164{
2165	struct cpsw_platform_data	*data;
2166	struct net_device		*ndev;
2167	struct cpsw_priv		*priv;
2168	struct cpdma_params		dma_params;
2169	struct cpsw_ale_params		ale_params;
2170	void __iomem			*ss_regs;
2171	struct resource			*res, *ss_res;
2172	u32 slave_offset, sliver_offset, slave_size;
2173	int ret = 0, i;
2174	int irq;
2175
2176	ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2177	if (!ndev) {
2178		dev_err(&pdev->dev, "error allocating net_device\n");
2179		return -ENOMEM;
2180	}
2181
2182	platform_set_drvdata(pdev, ndev);
2183	priv = netdev_priv(ndev);
2184	spin_lock_init(&priv->lock);
2185	priv->pdev = pdev;
2186	priv->ndev = ndev;
2187	priv->dev  = &ndev->dev;
2188	priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2189	priv->rx_packet_max = max(rx_packet_max, 128);
2190	priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2191	priv->irq_enabled = true;
2192	if (!priv->cpts) {
2193		dev_err(&pdev->dev, "error allocating cpts\n");
2194		ret = -ENOMEM;
2195		goto clean_ndev_ret;
2196	}
2197
2198	/*
2199	 * This may be required here for child devices.
2200	 */
2201	pm_runtime_enable(&pdev->dev);
2202
2203	/* Select default pin state */
2204	pinctrl_pm_select_default_state(&pdev->dev);
2205
2206	if (cpsw_probe_dt(&priv->data, pdev)) {
2207		dev_err(&pdev->dev, "cpsw: platform data missing\n");
2208		ret = -ENODEV;
2209		goto clean_runtime_disable_ret;
2210	}
2211	data = &priv->data;
2212
2213	if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2214		memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2215		dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2216	} else {
2217		eth_random_addr(priv->mac_addr);
2218		dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2219	}
2220
2221	memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2222
2223	priv->slaves = devm_kzalloc(&pdev->dev,
2224				    sizeof(struct cpsw_slave) * data->slaves,
2225				    GFP_KERNEL);
2226	if (!priv->slaves) {
2227		ret = -ENOMEM;
2228		goto clean_runtime_disable_ret;
2229	}
2230	for (i = 0; i < data->slaves; i++)
2231		priv->slaves[i].slave_num = i;
2232
2233	priv->slaves[0].ndev = ndev;
2234	priv->emac_port = 0;
2235
2236	priv->clk = devm_clk_get(&pdev->dev, "fck");
2237	if (IS_ERR(priv->clk)) {
2238		dev_err(priv->dev, "fck is not found\n");
2239		ret = -ENODEV;
2240		goto clean_runtime_disable_ret;
2241	}
2242	priv->coal_intvl = 0;
2243	priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2244
2245	ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2246	ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2247	if (IS_ERR(ss_regs)) {
2248		ret = PTR_ERR(ss_regs);
2249		goto clean_runtime_disable_ret;
2250	}
2251	priv->regs = ss_regs;
2252	priv->host_port = HOST_PORT_NUM;
2253
2254	/* Need to enable clocks with runtime PM api to access module
2255	 * registers
2256	 */
2257	pm_runtime_get_sync(&pdev->dev);
2258	priv->version = readl(&priv->regs->id_ver);
2259	pm_runtime_put_sync(&pdev->dev);
2260
2261	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2262	priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2263	if (IS_ERR(priv->wr_regs)) {
2264		ret = PTR_ERR(priv->wr_regs);
2265		goto clean_runtime_disable_ret;
2266	}
2267
2268	memset(&dma_params, 0, sizeof(dma_params));
2269	memset(&ale_params, 0, sizeof(ale_params));
2270
2271	switch (priv->version) {
2272	case CPSW_VERSION_1:
2273		priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2274		priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2275		priv->hw_stats	     = ss_regs + CPSW1_HW_STATS;
2276		dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2277		dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2278		ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2279		slave_offset         = CPSW1_SLAVE_OFFSET;
2280		slave_size           = CPSW1_SLAVE_SIZE;
2281		sliver_offset        = CPSW1_SLIVER_OFFSET;
2282		dma_params.desc_mem_phys = 0;
2283		break;
2284	case CPSW_VERSION_2:
2285	case CPSW_VERSION_3:
2286	case CPSW_VERSION_4:
2287		priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2288		priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2289		priv->hw_stats	     = ss_regs + CPSW2_HW_STATS;
2290		dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2291		dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2292		ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2293		slave_offset         = CPSW2_SLAVE_OFFSET;
2294		slave_size           = CPSW2_SLAVE_SIZE;
2295		sliver_offset        = CPSW2_SLIVER_OFFSET;
2296		dma_params.desc_mem_phys =
2297			(u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2298		break;
2299	default:
2300		dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2301		ret = -ENODEV;
2302		goto clean_runtime_disable_ret;
2303	}
2304	for (i = 0; i < priv->data.slaves; i++) {
2305		struct cpsw_slave *slave = &priv->slaves[i];
2306		cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2307		slave_offset  += slave_size;
2308		sliver_offset += SLIVER_SIZE;
2309	}
2310
2311	dma_params.dev		= &pdev->dev;
2312	dma_params.rxthresh	= dma_params.dmaregs + CPDMA_RXTHRESH;
2313	dma_params.rxfree	= dma_params.dmaregs + CPDMA_RXFREE;
2314	dma_params.rxhdp	= dma_params.txhdp + CPDMA_RXHDP;
2315	dma_params.txcp		= dma_params.txhdp + CPDMA_TXCP;
2316	dma_params.rxcp		= dma_params.txhdp + CPDMA_RXCP;
2317
2318	dma_params.num_chan		= data->channels;
2319	dma_params.has_soft_reset	= true;
2320	dma_params.min_packet_size	= CPSW_MIN_PACKET_SIZE;
2321	dma_params.desc_mem_size	= data->bd_ram_size;
2322	dma_params.desc_align		= 16;
2323	dma_params.has_ext_regs		= true;
2324	dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2325
2326	priv->dma = cpdma_ctlr_create(&dma_params);
2327	if (!priv->dma) {
2328		dev_err(priv->dev, "error initializing dma\n");
2329		ret = -ENOMEM;
2330		goto clean_runtime_disable_ret;
2331	}
2332
2333	priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2334				       cpsw_tx_handler);
2335	priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2336				       cpsw_rx_handler);
2337
2338	if (WARN_ON(!priv->txch || !priv->rxch)) {
2339		dev_err(priv->dev, "error initializing dma channels\n");
2340		ret = -ENOMEM;
2341		goto clean_dma_ret;
2342	}
2343
2344	ale_params.dev			= &ndev->dev;
2345	ale_params.ale_ageout		= ale_ageout;
2346	ale_params.ale_entries		= data->ale_entries;
2347	ale_params.ale_ports		= data->slaves;
2348
2349	priv->ale = cpsw_ale_create(&ale_params);
2350	if (!priv->ale) {
2351		dev_err(priv->dev, "error initializing ale engine\n");
2352		ret = -ENODEV;
2353		goto clean_dma_ret;
2354	}
2355
2356	ndev->irq = platform_get_irq(pdev, 1);
2357	if (ndev->irq < 0) {
2358		dev_err(priv->dev, "error getting irq resource\n");
2359		ret = -ENOENT;
2360		goto clean_ale_ret;
2361	}
2362
2363	/* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2364	 * MISC IRQs which are always kept disabled with this driver so
2365	 * we will not request them.
2366	 *
2367	 * If anyone wants to implement support for those, make sure to
2368	 * first request and append them to irqs_table array.
2369	 */
2370
2371	/* RX IRQ */
2372	irq = platform_get_irq(pdev, 1);
2373	if (irq < 0)
2374		goto clean_ale_ret;
2375
2376	priv->irqs_table[0] = irq;
2377	ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2378			       0, dev_name(&pdev->dev), priv);
2379	if (ret < 0) {
2380		dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2381		goto clean_ale_ret;
2382	}
2383
2384	/* TX IRQ */
2385	irq = platform_get_irq(pdev, 2);
2386	if (irq < 0)
2387		goto clean_ale_ret;
2388
2389	priv->irqs_table[1] = irq;
2390	ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2391			       0, dev_name(&pdev->dev), priv);
2392	if (ret < 0) {
2393		dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2394		goto clean_ale_ret;
2395	}
2396	priv->num_irqs = 2;
2397
2398	ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2399
2400	ndev->netdev_ops = &cpsw_netdev_ops;
2401	ndev->ethtool_ops = &cpsw_ethtool_ops;
2402	netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2403
2404	/* register the network device */
2405	SET_NETDEV_DEV(ndev, &pdev->dev);
2406	ret = register_netdev(ndev);
2407	if (ret) {
2408		dev_err(priv->dev, "error registering net device\n");
2409		ret = -ENODEV;
2410		goto clean_ale_ret;
2411	}
2412
2413	cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2414		    &ss_res->start, ndev->irq);
2415
2416	if (priv->data.dual_emac) {
2417		ret = cpsw_probe_dual_emac(pdev, priv);
2418		if (ret) {
2419			cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2420			goto clean_ale_ret;
2421		}
2422	}
2423
2424	return 0;
2425
2426clean_ale_ret:
2427	cpsw_ale_destroy(priv->ale);
2428clean_dma_ret:
2429	cpdma_chan_destroy(priv->txch);
2430	cpdma_chan_destroy(priv->rxch);
2431	cpdma_ctlr_destroy(priv->dma);
2432clean_runtime_disable_ret:
2433	pm_runtime_disable(&pdev->dev);
2434clean_ndev_ret:
2435	free_netdev(priv->ndev);
2436	return ret;
2437}
2438
2439static int cpsw_remove_child_device(struct device *dev, void *c)
2440{
2441	struct platform_device *pdev = to_platform_device(dev);
2442
2443	of_device_unregister(pdev);
2444
2445	return 0;
2446}
2447
2448static int cpsw_remove(struct platform_device *pdev)
2449{
2450	struct net_device *ndev = platform_get_drvdata(pdev);
2451	struct cpsw_priv *priv = netdev_priv(ndev);
2452
2453	if (priv->data.dual_emac)
2454		unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2455	unregister_netdev(ndev);
2456
2457	cpsw_ale_destroy(priv->ale);
2458	cpdma_chan_destroy(priv->txch);
2459	cpdma_chan_destroy(priv->rxch);
2460	cpdma_ctlr_destroy(priv->dma);
2461	pm_runtime_disable(&pdev->dev);
2462	device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2463	if (priv->data.dual_emac)
2464		free_netdev(cpsw_get_slave_ndev(priv, 1));
2465	free_netdev(ndev);
2466	return 0;
2467}
2468
2469#ifdef CONFIG_PM_SLEEP
2470static int cpsw_suspend(struct device *dev)
2471{
2472	struct platform_device	*pdev = to_platform_device(dev);
2473	struct net_device	*ndev = platform_get_drvdata(pdev);
2474	struct cpsw_priv	*priv = netdev_priv(ndev);
2475
2476	if (priv->data.dual_emac) {
2477		int i;
2478
2479		for (i = 0; i < priv->data.slaves; i++) {
2480			if (netif_running(priv->slaves[i].ndev))
2481				cpsw_ndo_stop(priv->slaves[i].ndev);
2482			soft_reset_slave(priv->slaves + i);
2483		}
2484	} else {
2485		if (netif_running(ndev))
2486			cpsw_ndo_stop(ndev);
2487		for_each_slave(priv, soft_reset_slave);
2488	}
2489
2490	pm_runtime_put_sync(&pdev->dev);
2491
2492	/* Select sleep pin state */
2493	pinctrl_pm_select_sleep_state(&pdev->dev);
2494
2495	return 0;
2496}
2497
2498static int cpsw_resume(struct device *dev)
2499{
2500	struct platform_device	*pdev = to_platform_device(dev);
2501	struct net_device	*ndev = platform_get_drvdata(pdev);
2502	struct cpsw_priv	*priv = netdev_priv(ndev);
2503
2504	pm_runtime_get_sync(&pdev->dev);
2505
2506	/* Select default pin state */
2507	pinctrl_pm_select_default_state(&pdev->dev);
2508
2509	if (priv->data.dual_emac) {
2510		int i;
2511
2512		for (i = 0; i < priv->data.slaves; i++) {
2513			if (netif_running(priv->slaves[i].ndev))
2514				cpsw_ndo_open(priv->slaves[i].ndev);
2515		}
2516	} else {
2517		if (netif_running(ndev))
2518			cpsw_ndo_open(ndev);
2519	}
2520	return 0;
2521}
2522#endif
2523
2524static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2525
2526static const struct of_device_id cpsw_of_mtable[] = {
2527	{ .compatible = "ti,cpsw", },
2528	{ /* sentinel */ },
2529};
2530MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2531
2532static struct platform_driver cpsw_driver = {
2533	.driver = {
2534		.name	 = "cpsw",
2535		.pm	 = &cpsw_pm_ops,
2536		.of_match_table = cpsw_of_mtable,
2537	},
2538	.probe = cpsw_probe,
2539	.remove = cpsw_remove,
2540};
2541
2542static int __init cpsw_init(void)
2543{
2544	return platform_driver_register(&cpsw_driver);
2545}
2546late_initcall(cpsw_init);
2547
2548static void __exit cpsw_exit(void)
2549{
2550	platform_driver_unregister(&cpsw_driver);
2551}
2552module_exit(cpsw_exit);
2553
2554MODULE_LICENSE("GPL");
2555MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2556MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2557MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2558