1/********************************************************************* 2 * 3 * Filename: nsc-ircc.c 4 * Version: 1.0 5 * Description: Driver for the NSC PC'108 and PC'338 IrDA chipsets 6 * Status: Stable. 7 * Author: Dag Brattli <dagb@cs.uit.no> 8 * Created at: Sat Nov 7 21:43:15 1998 9 * Modified at: Wed Mar 1 11:29:34 2000 10 * Modified by: Dag Brattli <dagb@cs.uit.no> 11 * 12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no> 13 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com> 14 * Copyright (c) 1998 Actisys Corp., www.actisys.com 15 * Copyright (c) 2000-2004 Jean Tourrilhes <jt@hpl.hp.com> 16 * All Rights Reserved 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * Neither Dag Brattli nor University of Tromsø admit liability nor 24 * provide warranty for any of this software. This material is 25 * provided "AS-IS" and at no charge. 26 * 27 * Notice that all functions that needs to access the chip in _any_ 28 * way, must save BSR register on entry, and restore it on exit. 29 * It is _very_ important to follow this policy! 30 * 31 * __u8 bank; 32 * 33 * bank = inb(iobase+BSR); 34 * 35 * do_your_stuff_here(); 36 * 37 * outb(bank, iobase+BSR); 38 * 39 * If you find bugs in this file, its very likely that the same bug 40 * will also be in w83977af_ir.c since the implementations are quite 41 * similar. 42 * 43 ********************************************************************/ 44 45#include <linux/module.h> 46#include <linux/gfp.h> 47 48#include <linux/kernel.h> 49#include <linux/types.h> 50#include <linux/skbuff.h> 51#include <linux/netdevice.h> 52#include <linux/ioport.h> 53#include <linux/delay.h> 54#include <linux/init.h> 55#include <linux/interrupt.h> 56#include <linux/rtnetlink.h> 57#include <linux/dma-mapping.h> 58#include <linux/pnp.h> 59#include <linux/platform_device.h> 60 61#include <asm/io.h> 62#include <asm/dma.h> 63#include <asm/byteorder.h> 64 65#include <net/irda/wrapper.h> 66#include <net/irda/irda.h> 67#include <net/irda/irda_device.h> 68 69#include "nsc-ircc.h" 70 71#define CHIP_IO_EXTENT 8 72#define BROKEN_DONGLE_ID 73 74static char *driver_name = "nsc-ircc"; 75 76/* Power Management */ 77#define NSC_IRCC_DRIVER_NAME "nsc-ircc" 78static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state); 79static int nsc_ircc_resume(struct platform_device *dev); 80 81static struct platform_driver nsc_ircc_driver = { 82 .suspend = nsc_ircc_suspend, 83 .resume = nsc_ircc_resume, 84 .driver = { 85 .name = NSC_IRCC_DRIVER_NAME, 86 }, 87}; 88 89/* Module parameters */ 90static int qos_mtt_bits = 0x07; /* 1 ms or more */ 91static int dongle_id; 92 93/* Use BIOS settions by default, but user may supply module parameters */ 94static unsigned int io[] = { ~0, ~0, ~0, ~0, ~0 }; 95static unsigned int irq[] = { 0, 0, 0, 0, 0 }; 96static unsigned int dma[] = { 0, 0, 0, 0, 0 }; 97 98static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info); 99static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info); 100static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info); 101static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info); 102static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info); 103static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info); 104#ifdef CONFIG_PNP 105static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id); 106#endif 107 108/* These are the known NSC chips */ 109static nsc_chip_t chips[] = { 110/* Name, {cfg registers}, chip id index reg, chip id expected value, revision mask */ 111 { "PC87108", { 0x150, 0x398, 0xea }, 0x05, 0x10, 0xf0, 112 nsc_ircc_probe_108, nsc_ircc_init_108 }, 113 { "PC87338", { 0x398, 0x15c, 0x2e }, 0x08, 0xb0, 0xf8, 114 nsc_ircc_probe_338, nsc_ircc_init_338 }, 115 /* Contributed by Steffen Pingel - IBM X40 */ 116 { "PC8738x", { 0x164e, 0x4e, 0x2e }, 0x20, 0xf4, 0xff, 117 nsc_ircc_probe_39x, nsc_ircc_init_39x }, 118 /* Contributed by Jan Frey - IBM A30/A31 */ 119 { "PC8739x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xea, 0xff, 120 nsc_ircc_probe_39x, nsc_ircc_init_39x }, 121 /* IBM ThinkPads using PC8738x (T60/X60/Z60) */ 122 { "IBM-PC8738x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf4, 0xff, 123 nsc_ircc_probe_39x, nsc_ircc_init_39x }, 124 /* IBM ThinkPads using PC8394T (T43/R52/?) */ 125 { "IBM-PC8394T", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf9, 0xff, 126 nsc_ircc_probe_39x, nsc_ircc_init_39x }, 127 { NULL } 128}; 129 130static struct nsc_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL, NULL }; 131 132static char *dongle_types[] = { 133 "Differential serial interface", 134 "Differential serial interface", 135 "Reserved", 136 "Reserved", 137 "Sharp RY5HD01", 138 "Reserved", 139 "Single-ended serial interface", 140 "Consumer-IR only", 141 "HP HSDL-2300, HP HSDL-3600/HSDL-3610", 142 "IBM31T1100 or Temic TFDS6000/TFDS6500", 143 "Reserved", 144 "Reserved", 145 "HP HSDL-1100/HSDL-2100", 146 "HP HSDL-1100/HSDL-2100", 147 "Supports SIR Mode only", 148 "No dongle connected", 149}; 150 151/* PNP probing */ 152static chipio_t pnp_info; 153static const struct pnp_device_id nsc_ircc_pnp_table[] = { 154 { .id = "NSC6001", .driver_data = 0 }, 155 { .id = "HWPC224", .driver_data = 0 }, 156 { .id = "IBM0071", .driver_data = NSC_FORCE_DONGLE_TYPE9 }, 157 { } 158}; 159 160MODULE_DEVICE_TABLE(pnp, nsc_ircc_pnp_table); 161 162static struct pnp_driver nsc_ircc_pnp_driver = { 163#ifdef CONFIG_PNP 164 .name = "nsc-ircc", 165 .id_table = nsc_ircc_pnp_table, 166 .probe = nsc_ircc_pnp_probe, 167#endif 168}; 169 170/* Some prototypes */ 171static int nsc_ircc_open(chipio_t *info); 172static int nsc_ircc_close(struct nsc_ircc_cb *self); 173static int nsc_ircc_setup(chipio_t *info); 174static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self); 175static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self); 176static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase); 177static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb, 178 struct net_device *dev); 179static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb, 180 struct net_device *dev); 181static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size); 182static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase); 183static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 baud); 184static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self); 185static int nsc_ircc_read_dongle_id (int iobase); 186static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id); 187 188static int nsc_ircc_net_open(struct net_device *dev); 189static int nsc_ircc_net_close(struct net_device *dev); 190static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 191 192/* Globals */ 193static int pnp_registered; 194static int pnp_succeeded; 195 196/* 197 * Function nsc_ircc_init () 198 * 199 * Initialize chip. Just try to find out how many chips we are dealing with 200 * and where they are 201 */ 202static int __init nsc_ircc_init(void) 203{ 204 chipio_t info; 205 nsc_chip_t *chip; 206 int ret; 207 int cfg_base; 208 int cfg, id; 209 int reg; 210 int i = 0; 211 212 ret = platform_driver_register(&nsc_ircc_driver); 213 if (ret) { 214 net_err_ratelimited("%s, Can't register driver!\n", 215 driver_name); 216 return ret; 217 } 218 219 /* Register with PnP subsystem to detect disable ports */ 220 ret = pnp_register_driver(&nsc_ircc_pnp_driver); 221 222 if (!ret) 223 pnp_registered = 1; 224 225 ret = -ENODEV; 226 227 /* Probe for all the NSC chipsets we know about */ 228 for (chip = chips; chip->name ; chip++) { 229 pr_debug("%s(), Probing for %s ...\n", __func__, 230 chip->name); 231 232 /* Try all config registers for this chip */ 233 for (cfg = 0; cfg < ARRAY_SIZE(chip->cfg); cfg++) { 234 cfg_base = chip->cfg[cfg]; 235 if (!cfg_base) 236 continue; 237 238 /* Read index register */ 239 reg = inb(cfg_base); 240 if (reg == 0xff) { 241 pr_debug("%s() no chip at 0x%03x\n", 242 __func__, cfg_base); 243 continue; 244 } 245 246 /* Read chip identification register */ 247 outb(chip->cid_index, cfg_base); 248 id = inb(cfg_base+1); 249 if ((id & chip->cid_mask) == chip->cid_value) { 250 pr_debug("%s() Found %s chip, revision=%d\n", 251 __func__, chip->name, 252 id & ~chip->cid_mask); 253 254 /* 255 * If we found a correct PnP setting, 256 * we first try it. 257 */ 258 if (pnp_succeeded) { 259 memset(&info, 0, sizeof(chipio_t)); 260 info.cfg_base = cfg_base; 261 info.fir_base = pnp_info.fir_base; 262 info.dma = pnp_info.dma; 263 info.irq = pnp_info.irq; 264 265 if (info.fir_base < 0x2000) { 266 net_info_ratelimited("%s, chip->init\n", 267 driver_name); 268 chip->init(chip, &info); 269 } else 270 chip->probe(chip, &info); 271 272 if (nsc_ircc_open(&info) >= 0) 273 ret = 0; 274 } 275 276 /* 277 * Opening based on PnP values failed. 278 * Let's fallback to user values, or probe 279 * the chip. 280 */ 281 if (ret) { 282 pr_debug("%s, PnP init failed\n", 283 driver_name); 284 memset(&info, 0, sizeof(chipio_t)); 285 info.cfg_base = cfg_base; 286 info.fir_base = io[i]; 287 info.dma = dma[i]; 288 info.irq = irq[i]; 289 290 /* 291 * If the user supplies the base address, then 292 * we init the chip, if not we probe the values 293 * set by the BIOS 294 */ 295 if (io[i] < 0x2000) { 296 chip->init(chip, &info); 297 } else 298 chip->probe(chip, &info); 299 300 if (nsc_ircc_open(&info) >= 0) 301 ret = 0; 302 } 303 i++; 304 } else { 305 pr_debug("%s(), Wrong chip id=0x%02x\n", 306 __func__, id); 307 } 308 } 309 } 310 311 if (ret) { 312 platform_driver_unregister(&nsc_ircc_driver); 313 pnp_unregister_driver(&nsc_ircc_pnp_driver); 314 pnp_registered = 0; 315 } 316 317 return ret; 318} 319 320/* 321 * Function nsc_ircc_cleanup () 322 * 323 * Close all configured chips 324 * 325 */ 326static void __exit nsc_ircc_cleanup(void) 327{ 328 int i; 329 330 for (i = 0; i < ARRAY_SIZE(dev_self); i++) { 331 if (dev_self[i]) 332 nsc_ircc_close(dev_self[i]); 333 } 334 335 platform_driver_unregister(&nsc_ircc_driver); 336 337 if (pnp_registered) 338 pnp_unregister_driver(&nsc_ircc_pnp_driver); 339 340 pnp_registered = 0; 341} 342 343static const struct net_device_ops nsc_ircc_sir_ops = { 344 .ndo_open = nsc_ircc_net_open, 345 .ndo_stop = nsc_ircc_net_close, 346 .ndo_start_xmit = nsc_ircc_hard_xmit_sir, 347 .ndo_do_ioctl = nsc_ircc_net_ioctl, 348}; 349 350static const struct net_device_ops nsc_ircc_fir_ops = { 351 .ndo_open = nsc_ircc_net_open, 352 .ndo_stop = nsc_ircc_net_close, 353 .ndo_start_xmit = nsc_ircc_hard_xmit_fir, 354 .ndo_do_ioctl = nsc_ircc_net_ioctl, 355}; 356 357/* 358 * Function nsc_ircc_open (iobase, irq) 359 * 360 * Open driver instance 361 * 362 */ 363static int __init nsc_ircc_open(chipio_t *info) 364{ 365 struct net_device *dev; 366 struct nsc_ircc_cb *self; 367 void *ret; 368 int err, chip_index; 369 370 for (chip_index = 0; chip_index < ARRAY_SIZE(dev_self); chip_index++) { 371 if (!dev_self[chip_index]) 372 break; 373 } 374 375 if (chip_index == ARRAY_SIZE(dev_self)) { 376 net_err_ratelimited("%s(), maximum number of supported chips reached!\n", 377 __func__); 378 return -ENOMEM; 379 } 380 381 net_info_ratelimited("%s, Found chip at base=0x%03x\n", 382 driver_name, info->cfg_base); 383 384 if ((nsc_ircc_setup(info)) == -1) 385 return -1; 386 387 net_info_ratelimited("%s, driver loaded (Dag Brattli)\n", driver_name); 388 389 dev = alloc_irdadev(sizeof(struct nsc_ircc_cb)); 390 if (dev == NULL) { 391 net_err_ratelimited("%s(), can't allocate memory for control block!\n", 392 __func__); 393 return -ENOMEM; 394 } 395 396 self = netdev_priv(dev); 397 self->netdev = dev; 398 spin_lock_init(&self->lock); 399 400 /* Need to store self somewhere */ 401 dev_self[chip_index] = self; 402 self->index = chip_index; 403 404 /* Initialize IO */ 405 self->io.cfg_base = info->cfg_base; 406 self->io.fir_base = info->fir_base; 407 self->io.irq = info->irq; 408 self->io.fir_ext = CHIP_IO_EXTENT; 409 self->io.dma = info->dma; 410 self->io.fifo_size = 32; 411 412 /* Reserve the ioports that we need */ 413 ret = request_region(self->io.fir_base, self->io.fir_ext, driver_name); 414 if (!ret) { 415 net_warn_ratelimited("%s(), can't get iobase of 0x%03x\n", 416 __func__, self->io.fir_base); 417 err = -ENODEV; 418 goto out1; 419 } 420 421 /* Initialize QoS for this device */ 422 irda_init_max_qos_capabilies(&self->qos); 423 424 /* The only value we must override it the baudrate */ 425 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 426 IR_115200|IR_576000|IR_1152000 |(IR_4000000 << 8); 427 428 self->qos.min_turn_time.bits = qos_mtt_bits; 429 irda_qos_bits_to_value(&self->qos); 430 431 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */ 432 self->rx_buff.truesize = 14384; 433 self->tx_buff.truesize = 14384; 434 435 /* Allocate memory if needed */ 436 self->rx_buff.head = 437 dma_zalloc_coherent(NULL, self->rx_buff.truesize, 438 &self->rx_buff_dma, GFP_KERNEL); 439 if (self->rx_buff.head == NULL) { 440 err = -ENOMEM; 441 goto out2; 442 443 } 444 445 self->tx_buff.head = 446 dma_zalloc_coherent(NULL, self->tx_buff.truesize, 447 &self->tx_buff_dma, GFP_KERNEL); 448 if (self->tx_buff.head == NULL) { 449 err = -ENOMEM; 450 goto out3; 451 } 452 453 self->rx_buff.in_frame = FALSE; 454 self->rx_buff.state = OUTSIDE_FRAME; 455 self->tx_buff.data = self->tx_buff.head; 456 self->rx_buff.data = self->rx_buff.head; 457 458 /* Reset Tx queue info */ 459 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0; 460 self->tx_fifo.tail = self->tx_buff.head; 461 462 /* Override the network functions we need to use */ 463 dev->netdev_ops = &nsc_ircc_sir_ops; 464 465 err = register_netdev(dev); 466 if (err) { 467 net_err_ratelimited("%s(), register_netdev() failed!\n", 468 __func__); 469 goto out4; 470 } 471 net_info_ratelimited("IrDA: Registered device %s\n", dev->name); 472 473 /* Check if user has supplied a valid dongle id or not */ 474 if ((dongle_id <= 0) || 475 (dongle_id >= ARRAY_SIZE(dongle_types))) { 476 dongle_id = nsc_ircc_read_dongle_id(self->io.fir_base); 477 478 net_info_ratelimited("%s, Found dongle: %s\n", 479 driver_name, dongle_types[dongle_id]); 480 } else { 481 net_info_ratelimited("%s, Using dongle: %s\n", 482 driver_name, dongle_types[dongle_id]); 483 } 484 485 self->io.dongle_id = dongle_id; 486 nsc_ircc_init_dongle_interface(self->io.fir_base, dongle_id); 487 488 self->pldev = platform_device_register_simple(NSC_IRCC_DRIVER_NAME, 489 self->index, NULL, 0); 490 if (IS_ERR(self->pldev)) { 491 err = PTR_ERR(self->pldev); 492 goto out5; 493 } 494 platform_set_drvdata(self->pldev, self); 495 496 return chip_index; 497 498 out5: 499 unregister_netdev(dev); 500 out4: 501 dma_free_coherent(NULL, self->tx_buff.truesize, 502 self->tx_buff.head, self->tx_buff_dma); 503 out3: 504 dma_free_coherent(NULL, self->rx_buff.truesize, 505 self->rx_buff.head, self->rx_buff_dma); 506 out2: 507 release_region(self->io.fir_base, self->io.fir_ext); 508 out1: 509 free_netdev(dev); 510 dev_self[chip_index] = NULL; 511 return err; 512} 513 514/* 515 * Function nsc_ircc_close (self) 516 * 517 * Close driver instance 518 * 519 */ 520static int __exit nsc_ircc_close(struct nsc_ircc_cb *self) 521{ 522 int iobase; 523 524 IRDA_ASSERT(self != NULL, return -1;); 525 526 iobase = self->io.fir_base; 527 528 platform_device_unregister(self->pldev); 529 530 /* Remove netdevice */ 531 unregister_netdev(self->netdev); 532 533 /* Release the PORT that this driver is using */ 534 pr_debug("%s(), Releasing Region %03x\n", 535 __func__, self->io.fir_base); 536 release_region(self->io.fir_base, self->io.fir_ext); 537 538 if (self->tx_buff.head) 539 dma_free_coherent(NULL, self->tx_buff.truesize, 540 self->tx_buff.head, self->tx_buff_dma); 541 542 if (self->rx_buff.head) 543 dma_free_coherent(NULL, self->rx_buff.truesize, 544 self->rx_buff.head, self->rx_buff_dma); 545 546 dev_self[self->index] = NULL; 547 free_netdev(self->netdev); 548 549 return 0; 550} 551 552/* 553 * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma) 554 * 555 * Initialize the NSC '108 chip 556 * 557 */ 558static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info) 559{ 560 int cfg_base = info->cfg_base; 561 __u8 temp=0; 562 563 outb(2, cfg_base); /* Mode Control Register (MCTL) */ 564 outb(0x00, cfg_base+1); /* Disable device */ 565 566 /* Base Address and Interrupt Control Register (BAIC) */ 567 outb(CFG_108_BAIC, cfg_base); 568 switch (info->fir_base) { 569 case 0x3e8: outb(0x14, cfg_base+1); break; 570 case 0x2e8: outb(0x15, cfg_base+1); break; 571 case 0x3f8: outb(0x16, cfg_base+1); break; 572 case 0x2f8: outb(0x17, cfg_base+1); break; 573 default: net_err_ratelimited("%s(), invalid base_address\n", __func__); 574 } 575 576 /* Control Signal Routing Register (CSRT) */ 577 switch (info->irq) { 578 case 3: temp = 0x01; break; 579 case 4: temp = 0x02; break; 580 case 5: temp = 0x03; break; 581 case 7: temp = 0x04; break; 582 case 9: temp = 0x05; break; 583 case 11: temp = 0x06; break; 584 case 15: temp = 0x07; break; 585 default: net_err_ratelimited("%s(), invalid irq\n", __func__); 586 } 587 outb(CFG_108_CSRT, cfg_base); 588 589 switch (info->dma) { 590 case 0: outb(0x08+temp, cfg_base+1); break; 591 case 1: outb(0x10+temp, cfg_base+1); break; 592 case 3: outb(0x18+temp, cfg_base+1); break; 593 default: net_err_ratelimited("%s(), invalid dma\n", __func__); 594 } 595 596 outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */ 597 outb(0x03, cfg_base+1); /* Enable device */ 598 599 return 0; 600} 601 602/* 603 * Function nsc_ircc_probe_108 (chip, info) 604 * 605 * 606 * 607 */ 608static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info) 609{ 610 int cfg_base = info->cfg_base; 611 int reg; 612 613 /* Read address and interrupt control register (BAIC) */ 614 outb(CFG_108_BAIC, cfg_base); 615 reg = inb(cfg_base+1); 616 617 switch (reg & 0x03) { 618 case 0: 619 info->fir_base = 0x3e8; 620 break; 621 case 1: 622 info->fir_base = 0x2e8; 623 break; 624 case 2: 625 info->fir_base = 0x3f8; 626 break; 627 case 3: 628 info->fir_base = 0x2f8; 629 break; 630 } 631 info->sir_base = info->fir_base; 632 pr_debug("%s(), probing fir_base=0x%03x\n", __func__, 633 info->fir_base); 634 635 /* Read control signals routing register (CSRT) */ 636 outb(CFG_108_CSRT, cfg_base); 637 reg = inb(cfg_base+1); 638 639 switch (reg & 0x07) { 640 case 0: 641 info->irq = -1; 642 break; 643 case 1: 644 info->irq = 3; 645 break; 646 case 2: 647 info->irq = 4; 648 break; 649 case 3: 650 info->irq = 5; 651 break; 652 case 4: 653 info->irq = 7; 654 break; 655 case 5: 656 info->irq = 9; 657 break; 658 case 6: 659 info->irq = 11; 660 break; 661 case 7: 662 info->irq = 15; 663 break; 664 } 665 pr_debug("%s(), probing irq=%d\n", __func__, info->irq); 666 667 /* Currently we only read Rx DMA but it will also be used for Tx */ 668 switch ((reg >> 3) & 0x03) { 669 case 0: 670 info->dma = -1; 671 break; 672 case 1: 673 info->dma = 0; 674 break; 675 case 2: 676 info->dma = 1; 677 break; 678 case 3: 679 info->dma = 3; 680 break; 681 } 682 pr_debug("%s(), probing dma=%d\n", __func__, info->dma); 683 684 /* Read mode control register (MCTL) */ 685 outb(CFG_108_MCTL, cfg_base); 686 reg = inb(cfg_base+1); 687 688 info->enabled = reg & 0x01; 689 info->suspended = !((reg >> 1) & 0x01); 690 691 return 0; 692} 693 694/* 695 * Function nsc_ircc_init_338 (chip, info) 696 * 697 * Initialize the NSC '338 chip. Remember that the 87338 needs two 698 * consecutive writes to the data registers while CPU interrupts are 699 * disabled. The 97338 does not require this, but shouldn't be any 700 * harm if we do it anyway. 701 */ 702static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info) 703{ 704 /* No init yet */ 705 706 return 0; 707} 708 709/* 710 * Function nsc_ircc_probe_338 (chip, info) 711 * 712 * 713 * 714 */ 715static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info) 716{ 717 int cfg_base = info->cfg_base; 718 int reg, com = 0; 719 int pnp; 720 721 /* Read function enable register (FER) */ 722 outb(CFG_338_FER, cfg_base); 723 reg = inb(cfg_base+1); 724 725 info->enabled = (reg >> 2) & 0x01; 726 727 /* Check if we are in Legacy or PnP mode */ 728 outb(CFG_338_PNP0, cfg_base); 729 reg = inb(cfg_base+1); 730 731 pnp = (reg >> 3) & 0x01; 732 if (pnp) { 733 pr_debug("(), Chip is in PnP mode\n"); 734 outb(0x46, cfg_base); 735 reg = (inb(cfg_base+1) & 0xfe) << 2; 736 737 outb(0x47, cfg_base); 738 reg |= ((inb(cfg_base+1) & 0xfc) << 8); 739 740 info->fir_base = reg; 741 } else { 742 /* Read function address register (FAR) */ 743 outb(CFG_338_FAR, cfg_base); 744 reg = inb(cfg_base+1); 745 746 switch ((reg >> 4) & 0x03) { 747 case 0: 748 info->fir_base = 0x3f8; 749 break; 750 case 1: 751 info->fir_base = 0x2f8; 752 break; 753 case 2: 754 com = 3; 755 break; 756 case 3: 757 com = 4; 758 break; 759 } 760 761 if (com) { 762 switch ((reg >> 6) & 0x03) { 763 case 0: 764 if (com == 3) 765 info->fir_base = 0x3e8; 766 else 767 info->fir_base = 0x2e8; 768 break; 769 case 1: 770 if (com == 3) 771 info->fir_base = 0x338; 772 else 773 info->fir_base = 0x238; 774 break; 775 case 2: 776 if (com == 3) 777 info->fir_base = 0x2e8; 778 else 779 info->fir_base = 0x2e0; 780 break; 781 case 3: 782 if (com == 3) 783 info->fir_base = 0x220; 784 else 785 info->fir_base = 0x228; 786 break; 787 } 788 } 789 } 790 info->sir_base = info->fir_base; 791 792 /* Read PnP register 1 (PNP1) */ 793 outb(CFG_338_PNP1, cfg_base); 794 reg = inb(cfg_base+1); 795 796 info->irq = reg >> 4; 797 798 /* Read PnP register 3 (PNP3) */ 799 outb(CFG_338_PNP3, cfg_base); 800 reg = inb(cfg_base+1); 801 802 info->dma = (reg & 0x07) - 1; 803 804 /* Read power and test register (PTR) */ 805 outb(CFG_338_PTR, cfg_base); 806 reg = inb(cfg_base+1); 807 808 info->suspended = reg & 0x01; 809 810 return 0; 811} 812 813 814/* 815 * Function nsc_ircc_init_39x (chip, info) 816 * 817 * Now that we know it's a '39x (see probe below), we need to 818 * configure it so we can use it. 819 * 820 * The NSC '338 chip is a Super I/O chip with a "bank" architecture, 821 * the configuration of the different functionality (serial, parallel, 822 * floppy...) are each in a different bank (Logical Device Number). 823 * The base address, irq and dma configuration registers are common 824 * to all functionalities (index 0x30 to 0x7F). 825 * There is only one configuration register specific to the 826 * serial port, CFG_39X_SPC. 827 * JeanII 828 * 829 * Note : this code was written by Jan Frey <janfrey@web.de> 830 */ 831static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info) 832{ 833 int cfg_base = info->cfg_base; 834 int enabled; 835 836 /* User is sure about his config... accept it. */ 837 pr_debug("%s(): nsc_ircc_init_39x (user settings): io=0x%04x, irq=%d, dma=%d\n", 838 __func__, info->fir_base, info->irq, info->dma); 839 840 /* Access bank for SP2 */ 841 outb(CFG_39X_LDN, cfg_base); 842 outb(0x02, cfg_base+1); 843 844 /* Configure SP2 */ 845 846 /* We want to enable the device if not enabled */ 847 outb(CFG_39X_ACT, cfg_base); 848 enabled = inb(cfg_base+1) & 0x01; 849 850 if (!enabled) { 851 /* Enable the device */ 852 outb(CFG_39X_SIOCF1, cfg_base); 853 outb(0x01, cfg_base+1); 854 /* May want to update info->enabled. Jean II */ 855 } 856 857 /* Enable UART bank switching (bit 7) ; Sets the chip to normal 858 * power mode (wake up from sleep mode) (bit 1) */ 859 outb(CFG_39X_SPC, cfg_base); 860 outb(0x82, cfg_base+1); 861 862 return 0; 863} 864 865/* 866 * Function nsc_ircc_probe_39x (chip, info) 867 * 868 * Test if we really have a '39x chip at the given address 869 * 870 * Note : this code was written by Jan Frey <janfrey@web.de> 871 */ 872static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info) 873{ 874 int cfg_base = info->cfg_base; 875 int reg1, reg2, irq, irqt, dma1, dma2; 876 int enabled, susp; 877 878 pr_debug("%s(), nsc_ircc_probe_39x, base=%d\n", 879 __func__, cfg_base); 880 881 /* This function should be executed with irq off to avoid 882 * another driver messing with the Super I/O bank - Jean II */ 883 884 /* Access bank for SP2 */ 885 outb(CFG_39X_LDN, cfg_base); 886 outb(0x02, cfg_base+1); 887 888 /* Read infos about SP2 ; store in info struct */ 889 outb(CFG_39X_BASEH, cfg_base); 890 reg1 = inb(cfg_base+1); 891 outb(CFG_39X_BASEL, cfg_base); 892 reg2 = inb(cfg_base+1); 893 info->fir_base = (reg1 << 8) | reg2; 894 895 outb(CFG_39X_IRQNUM, cfg_base); 896 irq = inb(cfg_base+1); 897 outb(CFG_39X_IRQSEL, cfg_base); 898 irqt = inb(cfg_base+1); 899 info->irq = irq; 900 901 outb(CFG_39X_DMA0, cfg_base); 902 dma1 = inb(cfg_base+1); 903 outb(CFG_39X_DMA1, cfg_base); 904 dma2 = inb(cfg_base+1); 905 info->dma = dma1 -1; 906 907 outb(CFG_39X_ACT, cfg_base); 908 info->enabled = enabled = inb(cfg_base+1) & 0x01; 909 910 outb(CFG_39X_SPC, cfg_base); 911 susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1); 912 913 pr_debug("%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n", 914 __func__, reg1, reg2, irq, irqt, dma1, dma2, enabled, susp); 915 916 /* Configure SP2 */ 917 918 /* We want to enable the device if not enabled */ 919 outb(CFG_39X_ACT, cfg_base); 920 enabled = inb(cfg_base+1) & 0x01; 921 922 if (!enabled) { 923 /* Enable the device */ 924 outb(CFG_39X_SIOCF1, cfg_base); 925 outb(0x01, cfg_base+1); 926 /* May want to update info->enabled. Jean II */ 927 } 928 929 /* Enable UART bank switching (bit 7) ; Sets the chip to normal 930 * power mode (wake up from sleep mode) (bit 1) */ 931 outb(CFG_39X_SPC, cfg_base); 932 outb(0x82, cfg_base+1); 933 934 return 0; 935} 936 937#ifdef CONFIG_PNP 938/* PNP probing */ 939static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) 940{ 941 memset(&pnp_info, 0, sizeof(chipio_t)); 942 pnp_info.irq = -1; 943 pnp_info.dma = -1; 944 pnp_succeeded = 1; 945 946 if (id->driver_data & NSC_FORCE_DONGLE_TYPE9) 947 dongle_id = 0x9; 948 949 /* There doesn't seem to be any way of getting the cfg_base. 950 * On my box, cfg_base is in the PnP descriptor of the 951 * motherboard. Oh well... Jean II */ 952 953 if (pnp_port_valid(dev, 0) && 954 !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) 955 pnp_info.fir_base = pnp_port_start(dev, 0); 956 957 if (pnp_irq_valid(dev, 0) && 958 !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) 959 pnp_info.irq = pnp_irq(dev, 0); 960 961 if (pnp_dma_valid(dev, 0) && 962 !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) 963 pnp_info.dma = pnp_dma(dev, 0); 964 965 pr_debug("%s() : From PnP, found firbase 0x%03X ; irq %d ; dma %d.\n", 966 __func__, pnp_info.fir_base, pnp_info.irq, pnp_info.dma); 967 968 if((pnp_info.fir_base == 0) || 969 (pnp_info.irq == -1) || (pnp_info.dma == -1)) { 970 /* Returning an error will disable the device. Yuck ! */ 971 //return -EINVAL; 972 pnp_succeeded = 0; 973 } 974 975 return 0; 976} 977#endif 978 979/* 980 * Function nsc_ircc_setup (info) 981 * 982 * Returns non-negative on success. 983 * 984 */ 985static int nsc_ircc_setup(chipio_t *info) 986{ 987 int version; 988 int iobase = info->fir_base; 989 990 /* Read the Module ID */ 991 switch_bank(iobase, BANK3); 992 version = inb(iobase+MID); 993 994 pr_debug("%s() Driver %s Found chip version %02x\n", 995 __func__, driver_name, version); 996 997 /* Should be 0x2? */ 998 if (0x20 != (version & 0xf0)) { 999 net_err_ratelimited("%s, Wrong chip version %02x\n", 1000 driver_name, version); 1001 return -1; 1002 } 1003 1004 /* Switch to advanced mode */ 1005 switch_bank(iobase, BANK2); 1006 outb(ECR1_EXT_SL, iobase+ECR1); 1007 switch_bank(iobase, BANK0); 1008 1009 /* Set FIFO threshold to TX17, RX16, reset and enable FIFO's */ 1010 switch_bank(iobase, BANK0); 1011 outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR); 1012 1013 outb(0x03, iobase+LCR); /* 8 bit word length */ 1014 outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/ 1015 1016 /* Set FIFO size to 32 */ 1017 switch_bank(iobase, BANK2); 1018 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2); 1019 1020 /* IRCR2: FEND_MD is not set */ 1021 switch_bank(iobase, BANK5); 1022 outb(0x02, iobase+4); 1023 1024 /* Make sure that some defaults are OK */ 1025 switch_bank(iobase, BANK6); 1026 outb(0x20, iobase+0); /* Set 32 bits FIR CRC */ 1027 outb(0x0a, iobase+1); /* Set MIR pulse width */ 1028 outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */ 1029 outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */ 1030 1031 /* Enable receive interrupts */ 1032 switch_bank(iobase, BANK0); 1033 outb(IER_RXHDL_IE, iobase+IER); 1034 1035 return 0; 1036} 1037 1038/* 1039 * Function nsc_ircc_read_dongle_id (void) 1040 * 1041 * Try to read dongle identification. This procedure needs to be executed 1042 * once after power-on/reset. It also needs to be used whenever you suspect 1043 * that the user may have plugged/unplugged the IrDA Dongle. 1044 */ 1045static int nsc_ircc_read_dongle_id (int iobase) 1046{ 1047 int dongle_id; 1048 __u8 bank; 1049 1050 bank = inb(iobase+BSR); 1051 1052 /* Select Bank 7 */ 1053 switch_bank(iobase, BANK7); 1054 1055 /* IRCFG4: IRSL0_DS and IRSL21_DS are cleared */ 1056 outb(0x00, iobase+7); 1057 1058 /* ID0, 1, and 2 are pulled up/down very slowly */ 1059 udelay(50); 1060 1061 /* IRCFG1: read the ID bits */ 1062 dongle_id = inb(iobase+4) & 0x0f; 1063 1064#ifdef BROKEN_DONGLE_ID 1065 if (dongle_id == 0x0a) 1066 dongle_id = 0x09; 1067#endif 1068 /* Go back to bank 0 before returning */ 1069 switch_bank(iobase, BANK0); 1070 1071 outb(bank, iobase+BSR); 1072 1073 return dongle_id; 1074} 1075 1076/* 1077 * Function nsc_ircc_init_dongle_interface (iobase, dongle_id) 1078 * 1079 * This function initializes the dongle for the transceiver that is 1080 * used. This procedure needs to be executed once after 1081 * power-on/reset. It also needs to be used whenever you suspect that 1082 * the dongle is changed. 1083 */ 1084static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id) 1085{ 1086 int bank; 1087 1088 /* Save current bank */ 1089 bank = inb(iobase+BSR); 1090 1091 /* Select Bank 7 */ 1092 switch_bank(iobase, BANK7); 1093 1094 /* IRCFG4: set according to dongle_id */ 1095 switch (dongle_id) { 1096 case 0x00: /* same as */ 1097 case 0x01: /* Differential serial interface */ 1098 pr_debug("%s(), %s not defined by irda yet\n", 1099 __func__, dongle_types[dongle_id]); 1100 break; 1101 case 0x02: /* same as */ 1102 case 0x03: /* Reserved */ 1103 pr_debug("%s(), %s not defined by irda yet\n", 1104 __func__, dongle_types[dongle_id]); 1105 break; 1106 case 0x04: /* Sharp RY5HD01 */ 1107 break; 1108 case 0x05: /* Reserved, but this is what the Thinkpad reports */ 1109 pr_debug("%s(), %s not defined by irda yet\n", 1110 __func__, dongle_types[dongle_id]); 1111 break; 1112 case 0x06: /* Single-ended serial interface */ 1113 pr_debug("%s(), %s not defined by irda yet\n", 1114 __func__, dongle_types[dongle_id]); 1115 break; 1116 case 0x07: /* Consumer-IR only */ 1117 pr_debug("%s(), %s is not for IrDA mode\n", 1118 __func__, dongle_types[dongle_id]); 1119 break; 1120 case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */ 1121 pr_debug("%s(), %s\n", 1122 __func__, dongle_types[dongle_id]); 1123 break; 1124 case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */ 1125 outb(0x28, iobase+7); /* Set irsl[0-2] as output */ 1126 break; 1127 case 0x0A: /* same as */ 1128 case 0x0B: /* Reserved */ 1129 pr_debug("%s(), %s not defined by irda yet\n", 1130 __func__, dongle_types[dongle_id]); 1131 break; 1132 case 0x0C: /* same as */ 1133 case 0x0D: /* HP HSDL-1100/HSDL-2100 */ 1134 /* 1135 * Set irsl0 as input, irsl[1-2] as output, and separate 1136 * inputs are used for SIR and MIR/FIR 1137 */ 1138 outb(0x48, iobase+7); 1139 break; 1140 case 0x0E: /* Supports SIR Mode only */ 1141 outb(0x28, iobase+7); /* Set irsl[0-2] as output */ 1142 break; 1143 case 0x0F: /* No dongle connected */ 1144 pr_debug("%s(), %s\n", 1145 __func__, dongle_types[dongle_id]); 1146 1147 switch_bank(iobase, BANK0); 1148 outb(0x62, iobase+MCR); 1149 break; 1150 default: 1151 pr_debug("%s(), invalid dongle_id %#x", 1152 __func__, dongle_id); 1153 } 1154 1155 /* IRCFG1: IRSL1 and 2 are set to IrDA mode */ 1156 outb(0x00, iobase+4); 1157 1158 /* Restore bank register */ 1159 outb(bank, iobase+BSR); 1160 1161} /* set_up_dongle_interface */ 1162 1163/* 1164 * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id) 1165 * 1166 * Change speed of the attach dongle 1167 * 1168 */ 1169static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id) 1170{ 1171 __u8 bank; 1172 1173 /* Save current bank */ 1174 bank = inb(iobase+BSR); 1175 1176 /* Select Bank 7 */ 1177 switch_bank(iobase, BANK7); 1178 1179 /* IRCFG1: set according to dongle_id */ 1180 switch (dongle_id) { 1181 case 0x00: /* same as */ 1182 case 0x01: /* Differential serial interface */ 1183 pr_debug("%s(), %s not defined by irda yet\n", 1184 __func__, dongle_types[dongle_id]); 1185 break; 1186 case 0x02: /* same as */ 1187 case 0x03: /* Reserved */ 1188 pr_debug("%s(), %s not defined by irda yet\n", 1189 __func__, dongle_types[dongle_id]); 1190 break; 1191 case 0x04: /* Sharp RY5HD01 */ 1192 break; 1193 case 0x05: /* Reserved */ 1194 pr_debug("%s(), %s not defined by irda yet\n", 1195 __func__, dongle_types[dongle_id]); 1196 break; 1197 case 0x06: /* Single-ended serial interface */ 1198 pr_debug("%s(), %s not defined by irda yet\n", 1199 __func__, dongle_types[dongle_id]); 1200 break; 1201 case 0x07: /* Consumer-IR only */ 1202 pr_debug("%s(), %s is not for IrDA mode\n", 1203 __func__, dongle_types[dongle_id]); 1204 break; 1205 case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */ 1206 pr_debug("%s(), %s\n", 1207 __func__, dongle_types[dongle_id]); 1208 outb(0x00, iobase+4); 1209 if (speed > 115200) 1210 outb(0x01, iobase+4); 1211 break; 1212 case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */ 1213 outb(0x01, iobase+4); 1214 1215 if (speed == 4000000) { 1216 /* There was a cli() there, but we now are already 1217 * under spin_lock_irqsave() - JeanII */ 1218 outb(0x81, iobase+4); 1219 outb(0x80, iobase+4); 1220 } else 1221 outb(0x00, iobase+4); 1222 break; 1223 case 0x0A: /* same as */ 1224 case 0x0B: /* Reserved */ 1225 pr_debug("%s(), %s not defined by irda yet\n", 1226 __func__, dongle_types[dongle_id]); 1227 break; 1228 case 0x0C: /* same as */ 1229 case 0x0D: /* HP HSDL-1100/HSDL-2100 */ 1230 break; 1231 case 0x0E: /* Supports SIR Mode only */ 1232 break; 1233 case 0x0F: /* No dongle connected */ 1234 pr_debug("%s(), %s is not for IrDA mode\n", 1235 __func__, dongle_types[dongle_id]); 1236 1237 switch_bank(iobase, BANK0); 1238 outb(0x62, iobase+MCR); 1239 break; 1240 default: 1241 pr_debug("%s(), invalid data_rate\n", __func__); 1242 } 1243 /* Restore bank register */ 1244 outb(bank, iobase+BSR); 1245} 1246 1247/* 1248 * Function nsc_ircc_change_speed (self, baud) 1249 * 1250 * Change the speed of the device 1251 * 1252 * This function *must* be called with irq off and spin-lock. 1253 */ 1254static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 speed) 1255{ 1256 struct net_device *dev = self->netdev; 1257 __u8 mcr = MCR_SIR; 1258 int iobase; 1259 __u8 bank; 1260 __u8 ier; /* Interrupt enable register */ 1261 1262 pr_debug("%s(), speed=%d\n", __func__, speed); 1263 1264 IRDA_ASSERT(self != NULL, return 0;); 1265 1266 iobase = self->io.fir_base; 1267 1268 /* Update accounting for new speed */ 1269 self->io.speed = speed; 1270 1271 /* Save current bank */ 1272 bank = inb(iobase+BSR); 1273 1274 /* Disable interrupts */ 1275 switch_bank(iobase, BANK0); 1276 outb(0, iobase+IER); 1277 1278 /* Select Bank 2 */ 1279 switch_bank(iobase, BANK2); 1280 1281 outb(0x00, iobase+BGDH); 1282 switch (speed) { 1283 case 9600: outb(0x0c, iobase+BGDL); break; 1284 case 19200: outb(0x06, iobase+BGDL); break; 1285 case 38400: outb(0x03, iobase+BGDL); break; 1286 case 57600: outb(0x02, iobase+BGDL); break; 1287 case 115200: outb(0x01, iobase+BGDL); break; 1288 case 576000: 1289 switch_bank(iobase, BANK5); 1290 1291 /* IRCR2: MDRS is set */ 1292 outb(inb(iobase+4) | 0x04, iobase+4); 1293 1294 mcr = MCR_MIR; 1295 pr_debug("%s(), handling baud of 576000\n", __func__); 1296 break; 1297 case 1152000: 1298 mcr = MCR_MIR; 1299 pr_debug("%s(), handling baud of 1152000\n", __func__); 1300 break; 1301 case 4000000: 1302 mcr = MCR_FIR; 1303 pr_debug("%s(), handling baud of 4000000\n", __func__); 1304 break; 1305 default: 1306 mcr = MCR_FIR; 1307 pr_debug("%s(), unknown baud rate of %d\n", 1308 __func__, speed); 1309 break; 1310 } 1311 1312 /* Set appropriate speed mode */ 1313 switch_bank(iobase, BANK0); 1314 outb(mcr | MCR_TX_DFR, iobase+MCR); 1315 1316 /* Give some hits to the transceiver */ 1317 nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id); 1318 1319 /* Set FIFO threshold to TX17, RX16 */ 1320 switch_bank(iobase, BANK0); 1321 outb(0x00, iobase+FCR); 1322 outb(FCR_FIFO_EN, iobase+FCR); 1323 outb(FCR_RXTH| /* Set Rx FIFO threshold */ 1324 FCR_TXTH| /* Set Tx FIFO threshold */ 1325 FCR_TXSR| /* Reset Tx FIFO */ 1326 FCR_RXSR| /* Reset Rx FIFO */ 1327 FCR_FIFO_EN, /* Enable FIFOs */ 1328 iobase+FCR); 1329 1330 /* Set FIFO size to 32 */ 1331 switch_bank(iobase, BANK2); 1332 outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2); 1333 1334 /* Enable some interrupts so we can receive frames */ 1335 switch_bank(iobase, BANK0); 1336 if (speed > 115200) { 1337 /* Install FIR xmit handler */ 1338 dev->netdev_ops = &nsc_ircc_fir_ops; 1339 ier = IER_SFIF_IE; 1340 nsc_ircc_dma_receive(self); 1341 } else { 1342 /* Install SIR xmit handler */ 1343 dev->netdev_ops = &nsc_ircc_sir_ops; 1344 ier = IER_RXHDL_IE; 1345 } 1346 /* Set our current interrupt mask */ 1347 outb(ier, iobase+IER); 1348 1349 /* Restore BSR */ 1350 outb(bank, iobase+BSR); 1351 1352 /* Make sure interrupt handlers keep the proper interrupt mask */ 1353 return ier; 1354} 1355 1356/* 1357 * Function nsc_ircc_hard_xmit (skb, dev) 1358 * 1359 * Transmit the frame! 1360 * 1361 */ 1362static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb, 1363 struct net_device *dev) 1364{ 1365 struct nsc_ircc_cb *self; 1366 unsigned long flags; 1367 int iobase; 1368 __s32 speed; 1369 __u8 bank; 1370 1371 self = netdev_priv(dev); 1372 1373 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;); 1374 1375 iobase = self->io.fir_base; 1376 1377 netif_stop_queue(dev); 1378 1379 /* Make sure tests *& speed change are atomic */ 1380 spin_lock_irqsave(&self->lock, flags); 1381 1382 /* Check if we need to change the speed */ 1383 speed = irda_get_next_speed(skb); 1384 if ((speed != self->io.speed) && (speed != -1)) { 1385 /* Check for empty frame. */ 1386 if (!skb->len) { 1387 /* If we just sent a frame, we get called before 1388 * the last bytes get out (because of the SIR FIFO). 1389 * If this is the case, let interrupt handler change 1390 * the speed itself... Jean II */ 1391 if (self->io.direction == IO_RECV) { 1392 nsc_ircc_change_speed(self, speed); 1393 /* TODO : For SIR->SIR, the next packet 1394 * may get corrupted - Jean II */ 1395 netif_wake_queue(dev); 1396 } else { 1397 self->new_speed = speed; 1398 /* Queue will be restarted after speed change 1399 * to make sure packets gets through the 1400 * proper xmit handler - Jean II */ 1401 } 1402 dev->trans_start = jiffies; 1403 spin_unlock_irqrestore(&self->lock, flags); 1404 dev_kfree_skb(skb); 1405 return NETDEV_TX_OK; 1406 } else 1407 self->new_speed = speed; 1408 } 1409 1410 /* Save current bank */ 1411 bank = inb(iobase+BSR); 1412 1413 self->tx_buff.data = self->tx_buff.head; 1414 1415 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 1416 self->tx_buff.truesize); 1417 1418 dev->stats.tx_bytes += self->tx_buff.len; 1419 1420 /* Add interrupt on tx low level (will fire immediately) */ 1421 switch_bank(iobase, BANK0); 1422 outb(IER_TXLDL_IE, iobase+IER); 1423 1424 /* Restore bank register */ 1425 outb(bank, iobase+BSR); 1426 1427 dev->trans_start = jiffies; 1428 spin_unlock_irqrestore(&self->lock, flags); 1429 1430 dev_kfree_skb(skb); 1431 1432 return NETDEV_TX_OK; 1433} 1434 1435static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb, 1436 struct net_device *dev) 1437{ 1438 struct nsc_ircc_cb *self; 1439 unsigned long flags; 1440 int iobase; 1441 __s32 speed; 1442 __u8 bank; 1443 int mtt, diff; 1444 1445 self = netdev_priv(dev); 1446 iobase = self->io.fir_base; 1447 1448 netif_stop_queue(dev); 1449 1450 /* Make sure tests *& speed change are atomic */ 1451 spin_lock_irqsave(&self->lock, flags); 1452 1453 /* Check if we need to change the speed */ 1454 speed = irda_get_next_speed(skb); 1455 if ((speed != self->io.speed) && (speed != -1)) { 1456 /* Check for empty frame. */ 1457 if (!skb->len) { 1458 /* If we are currently transmitting, defer to 1459 * interrupt handler. - Jean II */ 1460 if(self->tx_fifo.len == 0) { 1461 nsc_ircc_change_speed(self, speed); 1462 netif_wake_queue(dev); 1463 } else { 1464 self->new_speed = speed; 1465 /* Keep queue stopped : 1466 * the speed change operation may change the 1467 * xmit handler, and we want to make sure 1468 * the next packet get through the proper 1469 * Tx path, so block the Tx queue until 1470 * the speed change has been done. 1471 * Jean II */ 1472 } 1473 dev->trans_start = jiffies; 1474 spin_unlock_irqrestore(&self->lock, flags); 1475 dev_kfree_skb(skb); 1476 return NETDEV_TX_OK; 1477 } else { 1478 /* Change speed after current frame */ 1479 self->new_speed = speed; 1480 } 1481 } 1482 1483 /* Save current bank */ 1484 bank = inb(iobase+BSR); 1485 1486 /* Register and copy this frame to DMA memory */ 1487 self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail; 1488 self->tx_fifo.queue[self->tx_fifo.free].len = skb->len; 1489 self->tx_fifo.tail += skb->len; 1490 1491 dev->stats.tx_bytes += skb->len; 1492 1493 skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start, 1494 skb->len); 1495 self->tx_fifo.len++; 1496 self->tx_fifo.free++; 1497 1498 /* Start transmit only if there is currently no transmit going on */ 1499 if (self->tx_fifo.len == 1) { 1500 /* Check if we must wait the min turn time or not */ 1501 mtt = irda_get_mtt(skb); 1502 if (mtt) { 1503 /* Check how much time we have used already */ 1504 diff = ktime_us_delta(ktime_get(), self->stamp); 1505 1506 /* Check if the mtt is larger than the time we have 1507 * already used by all the protocol processing 1508 */ 1509 if (mtt > diff) { 1510 mtt -= diff; 1511 1512 /* 1513 * Use timer if delay larger than 125 us, and 1514 * use udelay for smaller values which should 1515 * be acceptable 1516 */ 1517 if (mtt > 125) { 1518 /* Adjust for timer resolution */ 1519 mtt = mtt / 125; 1520 1521 /* Setup timer */ 1522 switch_bank(iobase, BANK4); 1523 outb(mtt & 0xff, iobase+TMRL); 1524 outb((mtt >> 8) & 0x0f, iobase+TMRH); 1525 1526 /* Start timer */ 1527 outb(IRCR1_TMR_EN, iobase+IRCR1); 1528 self->io.direction = IO_XMIT; 1529 1530 /* Enable timer interrupt */ 1531 switch_bank(iobase, BANK0); 1532 outb(IER_TMR_IE, iobase+IER); 1533 1534 /* Timer will take care of the rest */ 1535 goto out; 1536 } else 1537 udelay(mtt); 1538 } 1539 } 1540 /* Enable DMA interrupt */ 1541 switch_bank(iobase, BANK0); 1542 outb(IER_DMA_IE, iobase+IER); 1543 1544 /* Transmit frame */ 1545 nsc_ircc_dma_xmit(self, iobase); 1546 } 1547 out: 1548 /* Not busy transmitting anymore if window is not full, 1549 * and if we don't need to change speed */ 1550 if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) 1551 netif_wake_queue(self->netdev); 1552 1553 /* Restore bank register */ 1554 outb(bank, iobase+BSR); 1555 1556 dev->trans_start = jiffies; 1557 spin_unlock_irqrestore(&self->lock, flags); 1558 dev_kfree_skb(skb); 1559 1560 return NETDEV_TX_OK; 1561} 1562 1563/* 1564 * Function nsc_ircc_dma_xmit (self, iobase) 1565 * 1566 * Transmit data using DMA 1567 * 1568 */ 1569static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase) 1570{ 1571 int bsr; 1572 1573 /* Save current bank */ 1574 bsr = inb(iobase+BSR); 1575 1576 /* Disable DMA */ 1577 switch_bank(iobase, BANK0); 1578 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); 1579 1580 self->io.direction = IO_XMIT; 1581 1582 /* Choose transmit DMA channel */ 1583 switch_bank(iobase, BANK2); 1584 outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1); 1585 1586 irda_setup_dma(self->io.dma, 1587 ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start - 1588 self->tx_buff.head) + self->tx_buff_dma, 1589 self->tx_fifo.queue[self->tx_fifo.ptr].len, 1590 DMA_TX_MODE); 1591 1592 /* Enable DMA and SIR interaction pulse */ 1593 switch_bank(iobase, BANK0); 1594 outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR); 1595 1596 /* Restore bank register */ 1597 outb(bsr, iobase+BSR); 1598} 1599 1600/* 1601 * Function nsc_ircc_pio_xmit (self, iobase) 1602 * 1603 * Transmit data using PIO. Returns the number of bytes that actually 1604 * got transferred 1605 * 1606 */ 1607static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size) 1608{ 1609 int actual = 0; 1610 __u8 bank; 1611 1612 /* Save current bank */ 1613 bank = inb(iobase+BSR); 1614 1615 switch_bank(iobase, BANK0); 1616 if (!(inb_p(iobase+LSR) & LSR_TXEMP)) { 1617 pr_debug("%s(), warning, FIFO not empty yet!\n", 1618 __func__); 1619 1620 /* FIFO may still be filled to the Tx interrupt threshold */ 1621 fifo_size -= 17; 1622 } 1623 1624 /* Fill FIFO with current frame */ 1625 while ((fifo_size-- > 0) && (actual < len)) { 1626 /* Transmit next byte */ 1627 outb(buf[actual++], iobase+TXD); 1628 } 1629 1630 pr_debug("%s(), fifo_size %d ; %d sent of %d\n", 1631 __func__, fifo_size, actual, len); 1632 1633 /* Restore bank */ 1634 outb(bank, iobase+BSR); 1635 1636 return actual; 1637} 1638 1639/* 1640 * Function nsc_ircc_dma_xmit_complete (self) 1641 * 1642 * The transfer of a frame in finished. This function will only be called 1643 * by the interrupt handler 1644 * 1645 */ 1646static int nsc_ircc_dma_xmit_complete(struct nsc_ircc_cb *self) 1647{ 1648 int iobase; 1649 __u8 bank; 1650 int ret = TRUE; 1651 1652 iobase = self->io.fir_base; 1653 1654 /* Save current bank */ 1655 bank = inb(iobase+BSR); 1656 1657 /* Disable DMA */ 1658 switch_bank(iobase, BANK0); 1659 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); 1660 1661 /* Check for underrun! */ 1662 if (inb(iobase+ASCR) & ASCR_TXUR) { 1663 self->netdev->stats.tx_errors++; 1664 self->netdev->stats.tx_fifo_errors++; 1665 1666 /* Clear bit, by writing 1 into it */ 1667 outb(ASCR_TXUR, iobase+ASCR); 1668 } else { 1669 self->netdev->stats.tx_packets++; 1670 } 1671 1672 /* Finished with this frame, so prepare for next */ 1673 self->tx_fifo.ptr++; 1674 self->tx_fifo.len--; 1675 1676 /* Any frames to be sent back-to-back? */ 1677 if (self->tx_fifo.len) { 1678 nsc_ircc_dma_xmit(self, iobase); 1679 1680 /* Not finished yet! */ 1681 ret = FALSE; 1682 } else { 1683 /* Reset Tx FIFO info */ 1684 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0; 1685 self->tx_fifo.tail = self->tx_buff.head; 1686 } 1687 1688 /* Make sure we have room for more frames and 1689 * that we don't need to change speed */ 1690 if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) { 1691 /* Not busy transmitting anymore */ 1692 /* Tell the network layer, that we can accept more frames */ 1693 netif_wake_queue(self->netdev); 1694 } 1695 1696 /* Restore bank */ 1697 outb(bank, iobase+BSR); 1698 1699 return ret; 1700} 1701 1702/* 1703 * Function nsc_ircc_dma_receive (self) 1704 * 1705 * Get ready for receiving a frame. The device will initiate a DMA 1706 * if it starts to receive a frame. 1707 * 1708 */ 1709static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self) 1710{ 1711 int iobase; 1712 __u8 bsr; 1713 1714 iobase = self->io.fir_base; 1715 1716 /* Reset Tx FIFO info */ 1717 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0; 1718 self->tx_fifo.tail = self->tx_buff.head; 1719 1720 /* Save current bank */ 1721 bsr = inb(iobase+BSR); 1722 1723 /* Disable DMA */ 1724 switch_bank(iobase, BANK0); 1725 outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); 1726 1727 /* Choose DMA Rx, DMA Fairness, and Advanced mode */ 1728 switch_bank(iobase, BANK2); 1729 outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1); 1730 1731 self->io.direction = IO_RECV; 1732 self->rx_buff.data = self->rx_buff.head; 1733 1734 /* Reset Rx FIFO. This will also flush the ST_FIFO */ 1735 switch_bank(iobase, BANK0); 1736 outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR); 1737 1738 self->st_fifo.len = self->st_fifo.pending_bytes = 0; 1739 self->st_fifo.tail = self->st_fifo.head = 0; 1740 1741 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, 1742 DMA_RX_MODE); 1743 1744 /* Enable DMA */ 1745 switch_bank(iobase, BANK0); 1746 outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR); 1747 1748 /* Restore bank register */ 1749 outb(bsr, iobase+BSR); 1750 1751 return 0; 1752} 1753 1754/* 1755 * Function nsc_ircc_dma_receive_complete (self) 1756 * 1757 * Finished with receiving frames 1758 * 1759 * 1760 */ 1761static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase) 1762{ 1763 struct st_fifo *st_fifo; 1764 struct sk_buff *skb; 1765 __u8 status; 1766 __u8 bank; 1767 int len; 1768 1769 st_fifo = &self->st_fifo; 1770 1771 /* Save current bank */ 1772 bank = inb(iobase+BSR); 1773 1774 /* Read all entries in status FIFO */ 1775 switch_bank(iobase, BANK5); 1776 while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) { 1777 /* We must empty the status FIFO no matter what */ 1778 len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8); 1779 1780 if (st_fifo->tail >= MAX_RX_WINDOW) { 1781 pr_debug("%s(), window is full!\n", __func__); 1782 continue; 1783 } 1784 1785 st_fifo->entries[st_fifo->tail].status = status; 1786 st_fifo->entries[st_fifo->tail].len = len; 1787 st_fifo->pending_bytes += len; 1788 st_fifo->tail++; 1789 st_fifo->len++; 1790 } 1791 /* Try to process all entries in status FIFO */ 1792 while (st_fifo->len > 0) { 1793 /* Get first entry */ 1794 status = st_fifo->entries[st_fifo->head].status; 1795 len = st_fifo->entries[st_fifo->head].len; 1796 st_fifo->pending_bytes -= len; 1797 st_fifo->head++; 1798 st_fifo->len--; 1799 1800 /* Check for errors */ 1801 if (status & FRM_ST_ERR_MSK) { 1802 if (status & FRM_ST_LOST_FR) { 1803 /* Add number of lost frames to stats */ 1804 self->netdev->stats.rx_errors += len; 1805 } else { 1806 /* Skip frame */ 1807 self->netdev->stats.rx_errors++; 1808 1809 self->rx_buff.data += len; 1810 1811 if (status & FRM_ST_MAX_LEN) 1812 self->netdev->stats.rx_length_errors++; 1813 1814 if (status & FRM_ST_PHY_ERR) 1815 self->netdev->stats.rx_frame_errors++; 1816 1817 if (status & FRM_ST_BAD_CRC) 1818 self->netdev->stats.rx_crc_errors++; 1819 } 1820 /* The errors below can be reported in both cases */ 1821 if (status & FRM_ST_OVR1) 1822 self->netdev->stats.rx_fifo_errors++; 1823 1824 if (status & FRM_ST_OVR2) 1825 self->netdev->stats.rx_fifo_errors++; 1826 } else { 1827 /* 1828 * First we must make sure that the frame we 1829 * want to deliver is all in main memory. If we 1830 * cannot tell, then we check if the Rx FIFO is 1831 * empty. If not then we will have to take a nap 1832 * and try again later. 1833 */ 1834 if (st_fifo->pending_bytes < self->io.fifo_size) { 1835 switch_bank(iobase, BANK0); 1836 if (inb(iobase+LSR) & LSR_RXDA) { 1837 /* Put this entry back in fifo */ 1838 st_fifo->head--; 1839 st_fifo->len++; 1840 st_fifo->pending_bytes += len; 1841 st_fifo->entries[st_fifo->head].status = status; 1842 st_fifo->entries[st_fifo->head].len = len; 1843 /* 1844 * DMA not finished yet, so try again 1845 * later, set timer value, resolution 1846 * 125 us 1847 */ 1848 switch_bank(iobase, BANK4); 1849 outb(0x02, iobase+TMRL); /* x 125 us */ 1850 outb(0x00, iobase+TMRH); 1851 1852 /* Start timer */ 1853 outb(IRCR1_TMR_EN, iobase+IRCR1); 1854 1855 /* Restore bank register */ 1856 outb(bank, iobase+BSR); 1857 1858 return FALSE; /* I'll be back! */ 1859 } 1860 } 1861 1862 /* 1863 * Remember the time we received this frame, so we can 1864 * reduce the min turn time a bit since we will know 1865 * how much time we have used for protocol processing 1866 */ 1867 self->stamp = ktime_get(); 1868 1869 skb = dev_alloc_skb(len+1); 1870 if (skb == NULL) { 1871 self->netdev->stats.rx_dropped++; 1872 1873 /* Restore bank register */ 1874 outb(bank, iobase+BSR); 1875 1876 return FALSE; 1877 } 1878 1879 /* Make sure IP header gets aligned */ 1880 skb_reserve(skb, 1); 1881 1882 /* Copy frame without CRC */ 1883 if (self->io.speed < 4000000) { 1884 skb_put(skb, len-2); 1885 skb_copy_to_linear_data(skb, 1886 self->rx_buff.data, 1887 len - 2); 1888 } else { 1889 skb_put(skb, len-4); 1890 skb_copy_to_linear_data(skb, 1891 self->rx_buff.data, 1892 len - 4); 1893 } 1894 1895 /* Move to next frame */ 1896 self->rx_buff.data += len; 1897 self->netdev->stats.rx_bytes += len; 1898 self->netdev->stats.rx_packets++; 1899 1900 skb->dev = self->netdev; 1901 skb_reset_mac_header(skb); 1902 skb->protocol = htons(ETH_P_IRDA); 1903 netif_rx(skb); 1904 } 1905 } 1906 /* Restore bank register */ 1907 outb(bank, iobase+BSR); 1908 1909 return TRUE; 1910} 1911 1912/* 1913 * Function nsc_ircc_pio_receive (self) 1914 * 1915 * Receive all data in receiver FIFO 1916 * 1917 */ 1918static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self) 1919{ 1920 __u8 byte; 1921 int iobase; 1922 1923 iobase = self->io.fir_base; 1924 1925 /* Receive all characters in Rx FIFO */ 1926 do { 1927 byte = inb(iobase+RXD); 1928 async_unwrap_char(self->netdev, &self->netdev->stats, 1929 &self->rx_buff, byte); 1930 } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */ 1931} 1932 1933/* 1934 * Function nsc_ircc_sir_interrupt (self, eir) 1935 * 1936 * Handle SIR interrupt 1937 * 1938 */ 1939static void nsc_ircc_sir_interrupt(struct nsc_ircc_cb *self, int eir) 1940{ 1941 int actual; 1942 1943 /* Check if transmit FIFO is low on data */ 1944 if (eir & EIR_TXLDL_EV) { 1945 /* Write data left in transmit buffer */ 1946 actual = nsc_ircc_pio_write(self->io.fir_base, 1947 self->tx_buff.data, 1948 self->tx_buff.len, 1949 self->io.fifo_size); 1950 self->tx_buff.data += actual; 1951 self->tx_buff.len -= actual; 1952 1953 self->io.direction = IO_XMIT; 1954 1955 /* Check if finished */ 1956 if (self->tx_buff.len > 0) 1957 self->ier = IER_TXLDL_IE; 1958 else { 1959 1960 self->netdev->stats.tx_packets++; 1961 netif_wake_queue(self->netdev); 1962 self->ier = IER_TXEMP_IE; 1963 } 1964 1965 } 1966 /* Check if transmission has completed */ 1967 if (eir & EIR_TXEMP_EV) { 1968 /* Turn around and get ready to receive some data */ 1969 self->io.direction = IO_RECV; 1970 self->ier = IER_RXHDL_IE; 1971 /* Check if we need to change the speed? 1972 * Need to be after self->io.direction to avoid race with 1973 * nsc_ircc_hard_xmit_sir() - Jean II */ 1974 if (self->new_speed) { 1975 pr_debug("%s(), Changing speed!\n", __func__); 1976 self->ier = nsc_ircc_change_speed(self, 1977 self->new_speed); 1978 self->new_speed = 0; 1979 netif_wake_queue(self->netdev); 1980 1981 /* Check if we are going to FIR */ 1982 if (self->io.speed > 115200) { 1983 /* No need to do anymore SIR stuff */ 1984 return; 1985 } 1986 } 1987 } 1988 1989 /* Rx FIFO threshold or timeout */ 1990 if (eir & EIR_RXHDL_EV) { 1991 nsc_ircc_pio_receive(self); 1992 1993 /* Keep receiving */ 1994 self->ier = IER_RXHDL_IE; 1995 } 1996} 1997 1998/* 1999 * Function nsc_ircc_fir_interrupt (self, eir) 2000 * 2001 * Handle MIR/FIR interrupt 2002 * 2003 */ 2004static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase, 2005 int eir) 2006{ 2007 __u8 bank; 2008 2009 bank = inb(iobase+BSR); 2010 2011 /* Status FIFO event*/ 2012 if (eir & EIR_SFIF_EV) { 2013 /* Check if DMA has finished */ 2014 if (nsc_ircc_dma_receive_complete(self, iobase)) { 2015 /* Wait for next status FIFO interrupt */ 2016 self->ier = IER_SFIF_IE; 2017 } else { 2018 self->ier = IER_SFIF_IE | IER_TMR_IE; 2019 } 2020 } else if (eir & EIR_TMR_EV) { /* Timer finished */ 2021 /* Disable timer */ 2022 switch_bank(iobase, BANK4); 2023 outb(0, iobase+IRCR1); 2024 2025 /* Clear timer event */ 2026 switch_bank(iobase, BANK0); 2027 outb(ASCR_CTE, iobase+ASCR); 2028 2029 /* Check if this is a Tx timer interrupt */ 2030 if (self->io.direction == IO_XMIT) { 2031 nsc_ircc_dma_xmit(self, iobase); 2032 2033 /* Interrupt on DMA */ 2034 self->ier = IER_DMA_IE; 2035 } else { 2036 /* Check (again) if DMA has finished */ 2037 if (nsc_ircc_dma_receive_complete(self, iobase)) { 2038 self->ier = IER_SFIF_IE; 2039 } else { 2040 self->ier = IER_SFIF_IE | IER_TMR_IE; 2041 } 2042 } 2043 } else if (eir & EIR_DMA_EV) { 2044 /* Finished with all transmissions? */ 2045 if (nsc_ircc_dma_xmit_complete(self)) { 2046 if(self->new_speed != 0) { 2047 /* As we stop the Tx queue, the speed change 2048 * need to be done when the Tx fifo is 2049 * empty. Ask for a Tx done interrupt */ 2050 self->ier = IER_TXEMP_IE; 2051 } else { 2052 /* Check if there are more frames to be 2053 * transmitted */ 2054 if (irda_device_txqueue_empty(self->netdev)) { 2055 /* Prepare for receive */ 2056 nsc_ircc_dma_receive(self); 2057 self->ier = IER_SFIF_IE; 2058 } else 2059 net_warn_ratelimited("%s(), potential Tx queue lockup !\n", 2060 __func__); 2061 } 2062 } else { 2063 /* Not finished yet, so interrupt on DMA again */ 2064 self->ier = IER_DMA_IE; 2065 } 2066 } else if (eir & EIR_TXEMP_EV) { 2067 /* The Tx FIFO has totally drained out, so now we can change 2068 * the speed... - Jean II */ 2069 self->ier = nsc_ircc_change_speed(self, self->new_speed); 2070 self->new_speed = 0; 2071 netif_wake_queue(self->netdev); 2072 /* Note : nsc_ircc_change_speed() restarted Rx fifo */ 2073 } 2074 2075 outb(bank, iobase+BSR); 2076} 2077 2078/* 2079 * Function nsc_ircc_interrupt (irq, dev_id, regs) 2080 * 2081 * An interrupt from the chip has arrived. Time to do some work 2082 * 2083 */ 2084static irqreturn_t nsc_ircc_interrupt(int irq, void *dev_id) 2085{ 2086 struct net_device *dev = dev_id; 2087 struct nsc_ircc_cb *self; 2088 __u8 bsr, eir; 2089 int iobase; 2090 2091 self = netdev_priv(dev); 2092 2093 spin_lock(&self->lock); 2094 2095 iobase = self->io.fir_base; 2096 2097 bsr = inb(iobase+BSR); /* Save current bank */ 2098 2099 switch_bank(iobase, BANK0); 2100 self->ier = inb(iobase+IER); 2101 eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */ 2102 2103 outb(0, iobase+IER); /* Disable interrupts */ 2104 2105 if (eir) { 2106 /* Dispatch interrupt handler for the current speed */ 2107 if (self->io.speed > 115200) 2108 nsc_ircc_fir_interrupt(self, iobase, eir); 2109 else 2110 nsc_ircc_sir_interrupt(self, eir); 2111 } 2112 2113 outb(self->ier, iobase+IER); /* Restore interrupts */ 2114 outb(bsr, iobase+BSR); /* Restore bank register */ 2115 2116 spin_unlock(&self->lock); 2117 return IRQ_RETVAL(eir); 2118} 2119 2120/* 2121 * Function nsc_ircc_is_receiving (self) 2122 * 2123 * Return TRUE is we are currently receiving a frame 2124 * 2125 */ 2126static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self) 2127{ 2128 unsigned long flags; 2129 int status = FALSE; 2130 int iobase; 2131 __u8 bank; 2132 2133 IRDA_ASSERT(self != NULL, return FALSE;); 2134 2135 spin_lock_irqsave(&self->lock, flags); 2136 2137 if (self->io.speed > 115200) { 2138 iobase = self->io.fir_base; 2139 2140 /* Check if rx FIFO is not empty */ 2141 bank = inb(iobase+BSR); 2142 switch_bank(iobase, BANK2); 2143 if ((inb(iobase+RXFLV) & 0x3f) != 0) { 2144 /* We are receiving something */ 2145 status = TRUE; 2146 } 2147 outb(bank, iobase+BSR); 2148 } else 2149 status = (self->rx_buff.state != OUTSIDE_FRAME); 2150 2151 spin_unlock_irqrestore(&self->lock, flags); 2152 2153 return status; 2154} 2155 2156/* 2157 * Function nsc_ircc_net_open (dev) 2158 * 2159 * Start the device 2160 * 2161 */ 2162static int nsc_ircc_net_open(struct net_device *dev) 2163{ 2164 struct nsc_ircc_cb *self; 2165 int iobase; 2166 char hwname[32]; 2167 __u8 bank; 2168 2169 2170 IRDA_ASSERT(dev != NULL, return -1;); 2171 self = netdev_priv(dev); 2172 2173 IRDA_ASSERT(self != NULL, return 0;); 2174 2175 iobase = self->io.fir_base; 2176 2177 if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, dev->name, dev)) { 2178 net_warn_ratelimited("%s, unable to allocate irq=%d\n", 2179 driver_name, self->io.irq); 2180 return -EAGAIN; 2181 } 2182 /* 2183 * Always allocate the DMA channel after the IRQ, and clean up on 2184 * failure. 2185 */ 2186 if (request_dma(self->io.dma, dev->name)) { 2187 net_warn_ratelimited("%s, unable to allocate dma=%d\n", 2188 driver_name, self->io.dma); 2189 free_irq(self->io.irq, dev); 2190 return -EAGAIN; 2191 } 2192 2193 /* Save current bank */ 2194 bank = inb(iobase+BSR); 2195 2196 /* turn on interrupts */ 2197 switch_bank(iobase, BANK0); 2198 outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER); 2199 2200 /* Restore bank register */ 2201 outb(bank, iobase+BSR); 2202 2203 /* Ready to play! */ 2204 netif_start_queue(dev); 2205 2206 /* Give self a hardware name */ 2207 sprintf(hwname, "NSC-FIR @ 0x%03x", self->io.fir_base); 2208 2209 /* 2210 * Open new IrLAP layer instance, now that everything should be 2211 * initialized properly 2212 */ 2213 self->irlap = irlap_open(dev, &self->qos, hwname); 2214 2215 return 0; 2216} 2217 2218/* 2219 * Function nsc_ircc_net_close (dev) 2220 * 2221 * Stop the device 2222 * 2223 */ 2224static int nsc_ircc_net_close(struct net_device *dev) 2225{ 2226 struct nsc_ircc_cb *self; 2227 int iobase; 2228 __u8 bank; 2229 2230 2231 IRDA_ASSERT(dev != NULL, return -1;); 2232 2233 self = netdev_priv(dev); 2234 IRDA_ASSERT(self != NULL, return 0;); 2235 2236 /* Stop device */ 2237 netif_stop_queue(dev); 2238 2239 /* Stop and remove instance of IrLAP */ 2240 if (self->irlap) 2241 irlap_close(self->irlap); 2242 self->irlap = NULL; 2243 2244 iobase = self->io.fir_base; 2245 2246 disable_dma(self->io.dma); 2247 2248 /* Save current bank */ 2249 bank = inb(iobase+BSR); 2250 2251 /* Disable interrupts */ 2252 switch_bank(iobase, BANK0); 2253 outb(0, iobase+IER); 2254 2255 free_irq(self->io.irq, dev); 2256 free_dma(self->io.dma); 2257 2258 /* Restore bank register */ 2259 outb(bank, iobase+BSR); 2260 2261 return 0; 2262} 2263 2264/* 2265 * Function nsc_ircc_net_ioctl (dev, rq, cmd) 2266 * 2267 * Process IOCTL commands for this device 2268 * 2269 */ 2270static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2271{ 2272 struct if_irda_req *irq = (struct if_irda_req *) rq; 2273 struct nsc_ircc_cb *self; 2274 unsigned long flags; 2275 int ret = 0; 2276 2277 IRDA_ASSERT(dev != NULL, return -1;); 2278 2279 self = netdev_priv(dev); 2280 2281 IRDA_ASSERT(self != NULL, return -1;); 2282 2283 pr_debug("%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd); 2284 2285 switch (cmd) { 2286 case SIOCSBANDWIDTH: /* Set bandwidth */ 2287 if (!capable(CAP_NET_ADMIN)) { 2288 ret = -EPERM; 2289 break; 2290 } 2291 spin_lock_irqsave(&self->lock, flags); 2292 nsc_ircc_change_speed(self, irq->ifr_baudrate); 2293 spin_unlock_irqrestore(&self->lock, flags); 2294 break; 2295 case SIOCSMEDIABUSY: /* Set media busy */ 2296 if (!capable(CAP_NET_ADMIN)) { 2297 ret = -EPERM; 2298 break; 2299 } 2300 irda_device_set_media_busy(self->netdev, TRUE); 2301 break; 2302 case SIOCGRECEIVING: /* Check if we are receiving right now */ 2303 /* This is already protected */ 2304 irq->ifr_receiving = nsc_ircc_is_receiving(self); 2305 break; 2306 default: 2307 ret = -EOPNOTSUPP; 2308 } 2309 return ret; 2310} 2311 2312static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state) 2313{ 2314 struct nsc_ircc_cb *self = platform_get_drvdata(dev); 2315 int bank; 2316 unsigned long flags; 2317 int iobase = self->io.fir_base; 2318 2319 if (self->io.suspended) 2320 return 0; 2321 2322 pr_debug("%s, Suspending\n", driver_name); 2323 2324 rtnl_lock(); 2325 if (netif_running(self->netdev)) { 2326 netif_device_detach(self->netdev); 2327 spin_lock_irqsave(&self->lock, flags); 2328 /* Save current bank */ 2329 bank = inb(iobase+BSR); 2330 2331 /* Disable interrupts */ 2332 switch_bank(iobase, BANK0); 2333 outb(0, iobase+IER); 2334 2335 /* Restore bank register */ 2336 outb(bank, iobase+BSR); 2337 2338 spin_unlock_irqrestore(&self->lock, flags); 2339 free_irq(self->io.irq, self->netdev); 2340 disable_dma(self->io.dma); 2341 } 2342 self->io.suspended = 1; 2343 rtnl_unlock(); 2344 2345 return 0; 2346} 2347 2348static int nsc_ircc_resume(struct platform_device *dev) 2349{ 2350 struct nsc_ircc_cb *self = platform_get_drvdata(dev); 2351 unsigned long flags; 2352 2353 if (!self->io.suspended) 2354 return 0; 2355 2356 pr_debug("%s, Waking up\n", driver_name); 2357 2358 rtnl_lock(); 2359 nsc_ircc_setup(&self->io); 2360 nsc_ircc_init_dongle_interface(self->io.fir_base, self->io.dongle_id); 2361 2362 if (netif_running(self->netdev)) { 2363 if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, 2364 self->netdev->name, self->netdev)) { 2365 net_warn_ratelimited("%s, unable to allocate irq=%d\n", 2366 driver_name, self->io.irq); 2367 2368 /* 2369 * Don't fail resume process, just kill this 2370 * network interface 2371 */ 2372 unregister_netdevice(self->netdev); 2373 } else { 2374 spin_lock_irqsave(&self->lock, flags); 2375 nsc_ircc_change_speed(self, self->io.speed); 2376 spin_unlock_irqrestore(&self->lock, flags); 2377 netif_device_attach(self->netdev); 2378 } 2379 2380 } else { 2381 spin_lock_irqsave(&self->lock, flags); 2382 nsc_ircc_change_speed(self, 9600); 2383 spin_unlock_irqrestore(&self->lock, flags); 2384 } 2385 self->io.suspended = 0; 2386 rtnl_unlock(); 2387 2388 return 0; 2389} 2390 2391MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>"); 2392MODULE_DESCRIPTION("NSC IrDA Device Driver"); 2393MODULE_LICENSE("GPL"); 2394 2395 2396module_param(qos_mtt_bits, int, 0); 2397MODULE_PARM_DESC(qos_mtt_bits, "Minimum Turn Time"); 2398module_param_array(io, int, NULL, 0); 2399MODULE_PARM_DESC(io, "Base I/O addresses"); 2400module_param_array(irq, int, NULL, 0); 2401MODULE_PARM_DESC(irq, "IRQ lines"); 2402module_param_array(dma, int, NULL, 0); 2403MODULE_PARM_DESC(dma, "DMA channels"); 2404module_param(dongle_id, int, 0); 2405MODULE_PARM_DESC(dongle_id, "Type-id of used dongle"); 2406 2407module_init(nsc_ircc_init); 2408module_exit(nsc_ircc_cleanup); 2409 2410