1/* 2 * linux/drivers/net/irda/pxaficp_ir.c 3 * 4 * Based on sa1100_ir.c by Russell King 5 * 6 * Changes copyright (C) 2003-2005 MontaVista Software, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Infra-red driver (SIR/FIR) for the PXA2xx embedded microprocessor 13 * 14 */ 15#include <linux/dma-mapping.h> 16#include <linux/interrupt.h> 17#include <linux/module.h> 18#include <linux/netdevice.h> 19#include <linux/etherdevice.h> 20#include <linux/platform_device.h> 21#include <linux/clk.h> 22#include <linux/gpio.h> 23#include <linux/slab.h> 24 25#include <net/irda/irda.h> 26#include <net/irda/irmod.h> 27#include <net/irda/wrapper.h> 28#include <net/irda/irda_device.h> 29 30#include <mach/dma.h> 31#include <linux/platform_data/irda-pxaficp.h> 32#include <mach/regs-ost.h> 33#include <mach/regs-uart.h> 34 35#define FICP __REG(0x40800000) /* Start of FICP area */ 36#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ 37#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ 38#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ 39#define ICDR __REG(0x4080000c) /* ICP Data Register */ 40#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ 41#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ 42 43#define ICCR0_AME (1 << 7) /* Address match enable */ 44#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ 45#define ICCR0_RIE (1 << 5) /* Receive FIFO interrupt enable */ 46#define ICCR0_RXE (1 << 4) /* Receive enable */ 47#define ICCR0_TXE (1 << 3) /* Transmit enable */ 48#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ 49#define ICCR0_LBM (1 << 1) /* Loopback mode */ 50#define ICCR0_ITR (1 << 0) /* IrDA transmission */ 51 52#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ 53#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ 54#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ 55#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ 56#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ 57#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ 58 59#ifdef CONFIG_PXA27x 60#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ 61#endif 62#define ICSR0_FRE (1 << 5) /* Framing error */ 63#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ 64#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ 65#define ICSR0_RAB (1 << 2) /* Receiver abort */ 66#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ 67#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ 68 69#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ 70#define ICSR1_CRE (1 << 5) /* CRC error */ 71#define ICSR1_EOF (1 << 4) /* End of frame */ 72#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ 73#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ 74#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ 75#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ 76 77#define IrSR_RXPL_NEG_IS_ZERO (1<<4) 78#define IrSR_RXPL_POS_IS_ZERO 0x0 79#define IrSR_TXPL_NEG_IS_ZERO (1<<3) 80#define IrSR_TXPL_POS_IS_ZERO 0x0 81#define IrSR_XMODE_PULSE_1_6 (1<<2) 82#define IrSR_XMODE_PULSE_3_16 0x0 83#define IrSR_RCVEIR_IR_MODE (1<<1) 84#define IrSR_RCVEIR_UART_MODE 0x0 85#define IrSR_XMITIR_IR_MODE (1<<0) 86#define IrSR_XMITIR_UART_MODE 0x0 87 88#define IrSR_IR_RECEIVE_ON (\ 89 IrSR_RXPL_NEG_IS_ZERO | \ 90 IrSR_TXPL_POS_IS_ZERO | \ 91 IrSR_XMODE_PULSE_3_16 | \ 92 IrSR_RCVEIR_IR_MODE | \ 93 IrSR_XMITIR_UART_MODE) 94 95#define IrSR_IR_TRANSMIT_ON (\ 96 IrSR_RXPL_NEG_IS_ZERO | \ 97 IrSR_TXPL_POS_IS_ZERO | \ 98 IrSR_XMODE_PULSE_3_16 | \ 99 IrSR_RCVEIR_UART_MODE | \ 100 IrSR_XMITIR_IR_MODE) 101 102struct pxa_irda { 103 int speed; 104 int newspeed; 105 unsigned long last_oscr; 106 107 unsigned char *dma_rx_buff; 108 unsigned char *dma_tx_buff; 109 dma_addr_t dma_rx_buff_phy; 110 dma_addr_t dma_tx_buff_phy; 111 unsigned int dma_tx_buff_len; 112 int txdma; 113 int rxdma; 114 115 int uart_irq; 116 int icp_irq; 117 118 struct irlap_cb *irlap; 119 struct qos_info qos; 120 121 iobuff_t tx_buff; 122 iobuff_t rx_buff; 123 124 struct device *dev; 125 struct pxaficp_platform_data *pdata; 126 struct clk *fir_clk; 127 struct clk *sir_clk; 128 struct clk *cur_clk; 129}; 130 131static inline void pxa_irda_disable_clk(struct pxa_irda *si) 132{ 133 if (si->cur_clk) 134 clk_disable_unprepare(si->cur_clk); 135 si->cur_clk = NULL; 136} 137 138static inline void pxa_irda_enable_firclk(struct pxa_irda *si) 139{ 140 si->cur_clk = si->fir_clk; 141 clk_prepare_enable(si->fir_clk); 142} 143 144static inline void pxa_irda_enable_sirclk(struct pxa_irda *si) 145{ 146 si->cur_clk = si->sir_clk; 147 clk_prepare_enable(si->sir_clk); 148} 149 150 151#define IS_FIR(si) ((si)->speed >= 4000000) 152#define IRDA_FRAME_SIZE_LIMIT 2047 153 154inline static void pxa_irda_fir_dma_rx_start(struct pxa_irda *si) 155{ 156 DCSR(si->rxdma) = DCSR_NODESC; 157 DSADR(si->rxdma) = __PREG(ICDR); 158 DTADR(si->rxdma) = si->dma_rx_buff_phy; 159 DCMD(si->rxdma) = DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_WIDTH1 | DCMD_BURST32 | IRDA_FRAME_SIZE_LIMIT; 160 DCSR(si->rxdma) |= DCSR_RUN; 161} 162 163inline static void pxa_irda_fir_dma_tx_start(struct pxa_irda *si) 164{ 165 DCSR(si->txdma) = DCSR_NODESC; 166 DSADR(si->txdma) = si->dma_tx_buff_phy; 167 DTADR(si->txdma) = __PREG(ICDR); 168 DCMD(si->txdma) = DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_ENDIRQEN | DCMD_WIDTH1 | DCMD_BURST32 | si->dma_tx_buff_len; 169 DCSR(si->txdma) |= DCSR_RUN; 170} 171 172/* 173 * Set the IrDA communications mode. 174 */ 175static void pxa_irda_set_mode(struct pxa_irda *si, int mode) 176{ 177 if (si->pdata->transceiver_mode) 178 si->pdata->transceiver_mode(si->dev, mode); 179 else { 180 if (gpio_is_valid(si->pdata->gpio_pwdown)) 181 gpio_set_value(si->pdata->gpio_pwdown, 182 !(mode & IR_OFF) ^ 183 !si->pdata->gpio_pwdown_inverted); 184 pxa2xx_transceiver_mode(si->dev, mode); 185 } 186} 187 188/* 189 * Set the IrDA communications speed. 190 */ 191static int pxa_irda_set_speed(struct pxa_irda *si, int speed) 192{ 193 unsigned long flags; 194 unsigned int divisor; 195 196 switch (speed) { 197 case 9600: case 19200: case 38400: 198 case 57600: case 115200: 199 200 /* refer to PXA250/210 Developer's Manual 10-7 */ 201 /* BaudRate = 14.7456 MHz / (16*Divisor) */ 202 divisor = 14745600 / (16 * speed); 203 204 local_irq_save(flags); 205 206 if (IS_FIR(si)) { 207 /* stop RX DMA */ 208 DCSR(si->rxdma) &= ~DCSR_RUN; 209 /* disable FICP */ 210 ICCR0 = 0; 211 pxa_irda_disable_clk(si); 212 213 /* set board transceiver to SIR mode */ 214 pxa_irda_set_mode(si, IR_SIRMODE); 215 216 /* enable the STUART clock */ 217 pxa_irda_enable_sirclk(si); 218 } 219 220 /* disable STUART first */ 221 STIER = 0; 222 223 /* access DLL & DLH */ 224 STLCR |= LCR_DLAB; 225 STDLL = divisor & 0xff; 226 STDLH = divisor >> 8; 227 STLCR &= ~LCR_DLAB; 228 229 si->speed = speed; 230 STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; 231 STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; 232 233 local_irq_restore(flags); 234 break; 235 236 case 4000000: 237 local_irq_save(flags); 238 239 /* disable STUART */ 240 STIER = 0; 241 STISR = 0; 242 pxa_irda_disable_clk(si); 243 244 /* disable FICP first */ 245 ICCR0 = 0; 246 247 /* set board transceiver to FIR mode */ 248 pxa_irda_set_mode(si, IR_FIRMODE); 249 250 /* enable the FICP clock */ 251 pxa_irda_enable_firclk(si); 252 253 si->speed = speed; 254 pxa_irda_fir_dma_rx_start(si); 255 ICCR0 = ICCR0_ITR | ICCR0_RXE; 256 257 local_irq_restore(flags); 258 break; 259 260 default: 261 return -EINVAL; 262 } 263 264 return 0; 265} 266 267/* SIR interrupt service routine. */ 268static irqreturn_t pxa_irda_sir_irq(int irq, void *dev_id) 269{ 270 struct net_device *dev = dev_id; 271 struct pxa_irda *si = netdev_priv(dev); 272 int iir, lsr, data; 273 274 iir = STIIR; 275 276 switch (iir & 0x0F) { 277 case 0x06: /* Receiver Line Status */ 278 lsr = STLSR; 279 while (lsr & LSR_FIFOE) { 280 data = STRBR; 281 if (lsr & (LSR_OE | LSR_PE | LSR_FE | LSR_BI)) { 282 printk(KERN_DEBUG "pxa_ir: sir receiving error\n"); 283 dev->stats.rx_errors++; 284 if (lsr & LSR_FE) 285 dev->stats.rx_frame_errors++; 286 if (lsr & LSR_OE) 287 dev->stats.rx_fifo_errors++; 288 } else { 289 dev->stats.rx_bytes++; 290 async_unwrap_char(dev, &dev->stats, 291 &si->rx_buff, data); 292 } 293 lsr = STLSR; 294 } 295 si->last_oscr = readl_relaxed(OSCR); 296 break; 297 298 case 0x04: /* Received Data Available */ 299 /* forth through */ 300 301 case 0x0C: /* Character Timeout Indication */ 302 do { 303 dev->stats.rx_bytes++; 304 async_unwrap_char(dev, &dev->stats, &si->rx_buff, STRBR); 305 } while (STLSR & LSR_DR); 306 si->last_oscr = readl_relaxed(OSCR); 307 break; 308 309 case 0x02: /* Transmit FIFO Data Request */ 310 while ((si->tx_buff.len) && (STLSR & LSR_TDRQ)) { 311 STTHR = *si->tx_buff.data++; 312 si->tx_buff.len -= 1; 313 } 314 315 if (si->tx_buff.len == 0) { 316 dev->stats.tx_packets++; 317 dev->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head; 318 319 /* We need to ensure that the transmitter has finished. */ 320 while ((STLSR & LSR_TEMT) == 0) 321 cpu_relax(); 322 si->last_oscr = readl_relaxed(OSCR); 323 324 /* 325 * Ok, we've finished transmitting. Now enable 326 * the receiver. Sometimes we get a receive IRQ 327 * immediately after a transmit... 328 */ 329 if (si->newspeed) { 330 pxa_irda_set_speed(si, si->newspeed); 331 si->newspeed = 0; 332 } else { 333 /* enable IR Receiver, disable IR Transmitter */ 334 STISR = IrSR_IR_RECEIVE_ON | IrSR_XMODE_PULSE_1_6; 335 /* enable STUART and receive interrupts */ 336 STIER = IER_UUE | IER_RLSE | IER_RAVIE | IER_RTIOE; 337 } 338 /* I'm hungry! */ 339 netif_wake_queue(dev); 340 } 341 break; 342 } 343 344 return IRQ_HANDLED; 345} 346 347/* FIR Receive DMA interrupt handler */ 348static void pxa_irda_fir_dma_rx_irq(int channel, void *data) 349{ 350 int dcsr = DCSR(channel); 351 352 DCSR(channel) = dcsr & ~DCSR_RUN; 353 354 printk(KERN_DEBUG "pxa_ir: fir rx dma bus error %#x\n", dcsr); 355} 356 357/* FIR Transmit DMA interrupt handler */ 358static void pxa_irda_fir_dma_tx_irq(int channel, void *data) 359{ 360 struct net_device *dev = data; 361 struct pxa_irda *si = netdev_priv(dev); 362 int dcsr; 363 364 dcsr = DCSR(channel); 365 DCSR(channel) = dcsr & ~DCSR_RUN; 366 367 if (dcsr & DCSR_ENDINTR) { 368 dev->stats.tx_packets++; 369 dev->stats.tx_bytes += si->dma_tx_buff_len; 370 } else { 371 dev->stats.tx_errors++; 372 } 373 374 while (ICSR1 & ICSR1_TBY) 375 cpu_relax(); 376 si->last_oscr = readl_relaxed(OSCR); 377 378 /* 379 * HACK: It looks like the TBY bit is dropped too soon. 380 * Without this delay things break. 381 */ 382 udelay(120); 383 384 if (si->newspeed) { 385 pxa_irda_set_speed(si, si->newspeed); 386 si->newspeed = 0; 387 } else { 388 int i = 64; 389 390 ICCR0 = 0; 391 pxa_irda_fir_dma_rx_start(si); 392 while ((ICSR1 & ICSR1_RNE) && i--) 393 (void)ICDR; 394 ICCR0 = ICCR0_ITR | ICCR0_RXE; 395 396 if (i < 0) 397 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 398 } 399 netif_wake_queue(dev); 400} 401 402/* EIF(Error in FIFO/End in Frame) handler for FIR */ 403static void pxa_irda_fir_irq_eif(struct pxa_irda *si, struct net_device *dev, int icsr0) 404{ 405 unsigned int len, stat, data; 406 407 /* Get the current data position. */ 408 len = DTADR(si->rxdma) - si->dma_rx_buff_phy; 409 410 do { 411 /* Read Status, and then Data. */ 412 stat = ICSR1; 413 rmb(); 414 data = ICDR; 415 416 if (stat & (ICSR1_CRE | ICSR1_ROR)) { 417 dev->stats.rx_errors++; 418 if (stat & ICSR1_CRE) { 419 printk(KERN_DEBUG "pxa_ir: fir receive CRC error\n"); 420 dev->stats.rx_crc_errors++; 421 } 422 if (stat & ICSR1_ROR) { 423 printk(KERN_DEBUG "pxa_ir: fir receive overrun\n"); 424 dev->stats.rx_over_errors++; 425 } 426 } else { 427 si->dma_rx_buff[len++] = data; 428 } 429 /* If we hit the end of frame, there's no point in continuing. */ 430 if (stat & ICSR1_EOF) 431 break; 432 } while (ICSR0 & ICSR0_EIF); 433 434 if (stat & ICSR1_EOF) { 435 /* end of frame. */ 436 struct sk_buff *skb; 437 438 if (icsr0 & ICSR0_FRE) { 439 printk(KERN_ERR "pxa_ir: dropping erroneous frame\n"); 440 dev->stats.rx_dropped++; 441 return; 442 } 443 444 skb = alloc_skb(len+1,GFP_ATOMIC); 445 if (!skb) { 446 printk(KERN_ERR "pxa_ir: fir out of memory for receive skb\n"); 447 dev->stats.rx_dropped++; 448 return; 449 } 450 451 /* Align IP header to 20 bytes */ 452 skb_reserve(skb, 1); 453 skb_copy_to_linear_data(skb, si->dma_rx_buff, len); 454 skb_put(skb, len); 455 456 /* Feed it to IrLAP */ 457 skb->dev = dev; 458 skb_reset_mac_header(skb); 459 skb->protocol = htons(ETH_P_IRDA); 460 netif_rx(skb); 461 462 dev->stats.rx_packets++; 463 dev->stats.rx_bytes += len; 464 } 465} 466 467/* FIR interrupt handler */ 468static irqreturn_t pxa_irda_fir_irq(int irq, void *dev_id) 469{ 470 struct net_device *dev = dev_id; 471 struct pxa_irda *si = netdev_priv(dev); 472 int icsr0, i = 64; 473 474 /* stop RX DMA */ 475 DCSR(si->rxdma) &= ~DCSR_RUN; 476 si->last_oscr = readl_relaxed(OSCR); 477 icsr0 = ICSR0; 478 479 if (icsr0 & (ICSR0_FRE | ICSR0_RAB)) { 480 if (icsr0 & ICSR0_FRE) { 481 printk(KERN_DEBUG "pxa_ir: fir receive frame error\n"); 482 dev->stats.rx_frame_errors++; 483 } else { 484 printk(KERN_DEBUG "pxa_ir: fir receive abort\n"); 485 dev->stats.rx_errors++; 486 } 487 ICSR0 = icsr0 & (ICSR0_FRE | ICSR0_RAB); 488 } 489 490 if (icsr0 & ICSR0_EIF) { 491 /* An error in FIFO occurred, or there is a end of frame */ 492 pxa_irda_fir_irq_eif(si, dev, icsr0); 493 } 494 495 ICCR0 = 0; 496 pxa_irda_fir_dma_rx_start(si); 497 while ((ICSR1 & ICSR1_RNE) && i--) 498 (void)ICDR; 499 ICCR0 = ICCR0_ITR | ICCR0_RXE; 500 501 if (i < 0) 502 printk(KERN_ERR "pxa_ir: cannot clear Rx FIFO!\n"); 503 504 return IRQ_HANDLED; 505} 506 507/* hard_xmit interface of irda device */ 508static int pxa_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) 509{ 510 struct pxa_irda *si = netdev_priv(dev); 511 int speed = irda_get_next_speed(skb); 512 513 /* 514 * Does this packet contain a request to change the interface 515 * speed? If so, remember it until we complete the transmission 516 * of this frame. 517 */ 518 if (speed != si->speed && speed != -1) 519 si->newspeed = speed; 520 521 /* 522 * If this is an empty frame, we can bypass a lot. 523 */ 524 if (skb->len == 0) { 525 if (si->newspeed) { 526 si->newspeed = 0; 527 pxa_irda_set_speed(si, speed); 528 } 529 dev_kfree_skb(skb); 530 return NETDEV_TX_OK; 531 } 532 533 netif_stop_queue(dev); 534 535 if (!IS_FIR(si)) { 536 si->tx_buff.data = si->tx_buff.head; 537 si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, si->tx_buff.truesize); 538 539 /* Disable STUART interrupts and switch to transmit mode. */ 540 STIER = 0; 541 STISR = IrSR_IR_TRANSMIT_ON | IrSR_XMODE_PULSE_1_6; 542 543 /* enable STUART and transmit interrupts */ 544 STIER = IER_UUE | IER_TIE; 545 } else { 546 unsigned long mtt = irda_get_mtt(skb); 547 548 si->dma_tx_buff_len = skb->len; 549 skb_copy_from_linear_data(skb, si->dma_tx_buff, skb->len); 550 551 if (mtt) 552 while ((unsigned)(readl_relaxed(OSCR) - si->last_oscr)/4 < mtt) 553 cpu_relax(); 554 555 /* stop RX DMA, disable FICP */ 556 DCSR(si->rxdma) &= ~DCSR_RUN; 557 ICCR0 = 0; 558 559 pxa_irda_fir_dma_tx_start(si); 560 ICCR0 = ICCR0_ITR | ICCR0_TXE; 561 } 562 563 dev_kfree_skb(skb); 564 return NETDEV_TX_OK; 565} 566 567static int pxa_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) 568{ 569 struct if_irda_req *rq = (struct if_irda_req *)ifreq; 570 struct pxa_irda *si = netdev_priv(dev); 571 int ret; 572 573 switch (cmd) { 574 case SIOCSBANDWIDTH: 575 ret = -EPERM; 576 if (capable(CAP_NET_ADMIN)) { 577 /* 578 * We are unable to set the speed if the 579 * device is not running. 580 */ 581 if (netif_running(dev)) { 582 ret = pxa_irda_set_speed(si, 583 rq->ifr_baudrate); 584 } else { 585 printk(KERN_INFO "pxa_ir: SIOCSBANDWIDTH: !netif_running\n"); 586 ret = 0; 587 } 588 } 589 break; 590 591 case SIOCSMEDIABUSY: 592 ret = -EPERM; 593 if (capable(CAP_NET_ADMIN)) { 594 irda_device_set_media_busy(dev, TRUE); 595 ret = 0; 596 } 597 break; 598 599 case SIOCGRECEIVING: 600 ret = 0; 601 rq->ifr_receiving = IS_FIR(si) ? 0 602 : si->rx_buff.state != OUTSIDE_FRAME; 603 break; 604 605 default: 606 ret = -EOPNOTSUPP; 607 break; 608 } 609 610 return ret; 611} 612 613static void pxa_irda_startup(struct pxa_irda *si) 614{ 615 /* Disable STUART interrupts */ 616 STIER = 0; 617 /* enable STUART interrupt to the processor */ 618 STMCR = MCR_OUT2; 619 /* configure SIR frame format: StartBit - Data 7 ... Data 0 - Stop Bit */ 620 STLCR = LCR_WLS0 | LCR_WLS1; 621 /* enable FIFO, we use FIFO to improve performance */ 622 STFCR = FCR_TRFIFOE | FCR_ITL_32; 623 624 /* disable FICP */ 625 ICCR0 = 0; 626 /* configure FICP ICCR2 */ 627 ICCR2 = ICCR2_TXP | ICCR2_TRIG_32; 628 629 /* configure DMAC */ 630 DRCMR(17) = si->rxdma | DRCMR_MAPVLD; 631 DRCMR(18) = si->txdma | DRCMR_MAPVLD; 632 633 /* force SIR reinitialization */ 634 si->speed = 4000000; 635 pxa_irda_set_speed(si, 9600); 636 637 printk(KERN_DEBUG "pxa_ir: irda startup\n"); 638} 639 640static void pxa_irda_shutdown(struct pxa_irda *si) 641{ 642 unsigned long flags; 643 644 local_irq_save(flags); 645 646 /* disable STUART and interrupt */ 647 STIER = 0; 648 /* disable STUART SIR mode */ 649 STISR = 0; 650 651 /* disable DMA */ 652 DCSR(si->txdma) &= ~DCSR_RUN; 653 DCSR(si->rxdma) &= ~DCSR_RUN; 654 /* disable FICP */ 655 ICCR0 = 0; 656 657 /* disable the STUART or FICP clocks */ 658 pxa_irda_disable_clk(si); 659 660 DRCMR(17) = 0; 661 DRCMR(18) = 0; 662 663 local_irq_restore(flags); 664 665 /* power off board transceiver */ 666 pxa_irda_set_mode(si, IR_OFF); 667 668 printk(KERN_DEBUG "pxa_ir: irda shutdown\n"); 669} 670 671static int pxa_irda_start(struct net_device *dev) 672{ 673 struct pxa_irda *si = netdev_priv(dev); 674 int err; 675 676 si->speed = 9600; 677 678 err = request_irq(si->uart_irq, pxa_irda_sir_irq, 0, dev->name, dev); 679 if (err) 680 goto err_irq1; 681 682 err = request_irq(si->icp_irq, pxa_irda_fir_irq, 0, dev->name, dev); 683 if (err) 684 goto err_irq2; 685 686 /* 687 * The interrupt must remain disabled for now. 688 */ 689 disable_irq(si->uart_irq); 690 disable_irq(si->icp_irq); 691 692 err = -EBUSY; 693 si->rxdma = pxa_request_dma("FICP_RX",DMA_PRIO_LOW, pxa_irda_fir_dma_rx_irq, dev); 694 if (si->rxdma < 0) 695 goto err_rx_dma; 696 697 si->txdma = pxa_request_dma("FICP_TX",DMA_PRIO_LOW, pxa_irda_fir_dma_tx_irq, dev); 698 if (si->txdma < 0) 699 goto err_tx_dma; 700 701 err = -ENOMEM; 702 si->dma_rx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 703 &si->dma_rx_buff_phy, GFP_KERNEL); 704 if (!si->dma_rx_buff) 705 goto err_dma_rx_buff; 706 707 si->dma_tx_buff = dma_alloc_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, 708 &si->dma_tx_buff_phy, GFP_KERNEL); 709 if (!si->dma_tx_buff) 710 goto err_dma_tx_buff; 711 712 /* Setup the serial port for the initial speed. */ 713 pxa_irda_startup(si); 714 715 /* 716 * Open a new IrLAP layer instance. 717 */ 718 si->irlap = irlap_open(dev, &si->qos, "pxa"); 719 err = -ENOMEM; 720 if (!si->irlap) 721 goto err_irlap; 722 723 /* 724 * Now enable the interrupt and start the queue 725 */ 726 enable_irq(si->uart_irq); 727 enable_irq(si->icp_irq); 728 netif_start_queue(dev); 729 730 printk(KERN_DEBUG "pxa_ir: irda driver opened\n"); 731 732 return 0; 733 734err_irlap: 735 pxa_irda_shutdown(si); 736 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 737err_dma_tx_buff: 738 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 739err_dma_rx_buff: 740 pxa_free_dma(si->txdma); 741err_tx_dma: 742 pxa_free_dma(si->rxdma); 743err_rx_dma: 744 free_irq(si->icp_irq, dev); 745err_irq2: 746 free_irq(si->uart_irq, dev); 747err_irq1: 748 749 return err; 750} 751 752static int pxa_irda_stop(struct net_device *dev) 753{ 754 struct pxa_irda *si = netdev_priv(dev); 755 756 netif_stop_queue(dev); 757 758 pxa_irda_shutdown(si); 759 760 /* Stop IrLAP */ 761 if (si->irlap) { 762 irlap_close(si->irlap); 763 si->irlap = NULL; 764 } 765 766 free_irq(si->uart_irq, dev); 767 free_irq(si->icp_irq, dev); 768 769 pxa_free_dma(si->rxdma); 770 pxa_free_dma(si->txdma); 771 772 if (si->dma_rx_buff) 773 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_tx_buff, si->dma_tx_buff_phy); 774 if (si->dma_tx_buff) 775 dma_free_coherent(si->dev, IRDA_FRAME_SIZE_LIMIT, si->dma_rx_buff, si->dma_rx_buff_phy); 776 777 printk(KERN_DEBUG "pxa_ir: irda driver closed\n"); 778 return 0; 779} 780 781static int pxa_irda_suspend(struct platform_device *_dev, pm_message_t state) 782{ 783 struct net_device *dev = platform_get_drvdata(_dev); 784 struct pxa_irda *si; 785 786 if (dev && netif_running(dev)) { 787 si = netdev_priv(dev); 788 netif_device_detach(dev); 789 pxa_irda_shutdown(si); 790 } 791 792 return 0; 793} 794 795static int pxa_irda_resume(struct platform_device *_dev) 796{ 797 struct net_device *dev = platform_get_drvdata(_dev); 798 struct pxa_irda *si; 799 800 if (dev && netif_running(dev)) { 801 si = netdev_priv(dev); 802 pxa_irda_startup(si); 803 netif_device_attach(dev); 804 netif_wake_queue(dev); 805 } 806 807 return 0; 808} 809 810 811static int pxa_irda_init_iobuf(iobuff_t *io, int size) 812{ 813 io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); 814 if (io->head != NULL) { 815 io->truesize = size; 816 io->in_frame = FALSE; 817 io->state = OUTSIDE_FRAME; 818 io->data = io->head; 819 } 820 return io->head ? 0 : -ENOMEM; 821} 822 823static const struct net_device_ops pxa_irda_netdev_ops = { 824 .ndo_open = pxa_irda_start, 825 .ndo_stop = pxa_irda_stop, 826 .ndo_start_xmit = pxa_irda_hard_xmit, 827 .ndo_do_ioctl = pxa_irda_ioctl, 828}; 829 830static int pxa_irda_probe(struct platform_device *pdev) 831{ 832 struct net_device *dev; 833 struct pxa_irda *si; 834 unsigned int baudrate_mask; 835 int err; 836 837 if (!pdev->dev.platform_data) 838 return -ENODEV; 839 840 err = request_mem_region(__PREG(STUART), 0x24, "IrDA") ? 0 : -EBUSY; 841 if (err) 842 goto err_mem_1; 843 844 err = request_mem_region(__PREG(FICP), 0x1c, "IrDA") ? 0 : -EBUSY; 845 if (err) 846 goto err_mem_2; 847 848 dev = alloc_irdadev(sizeof(struct pxa_irda)); 849 if (!dev) { 850 err = -ENOMEM; 851 goto err_mem_3; 852 } 853 854 SET_NETDEV_DEV(dev, &pdev->dev); 855 si = netdev_priv(dev); 856 si->dev = &pdev->dev; 857 si->pdata = pdev->dev.platform_data; 858 859 si->uart_irq = platform_get_irq(pdev, 0); 860 si->icp_irq = platform_get_irq(pdev, 1); 861 862 si->sir_clk = clk_get(&pdev->dev, "UARTCLK"); 863 si->fir_clk = clk_get(&pdev->dev, "FICPCLK"); 864 if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) { 865 err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk); 866 goto err_mem_4; 867 } 868 869 /* 870 * Initialise the SIR buffers 871 */ 872 err = pxa_irda_init_iobuf(&si->rx_buff, 14384); 873 if (err) 874 goto err_mem_4; 875 err = pxa_irda_init_iobuf(&si->tx_buff, 4000); 876 if (err) 877 goto err_mem_5; 878 879 if (gpio_is_valid(si->pdata->gpio_pwdown)) { 880 err = gpio_request(si->pdata->gpio_pwdown, "IrDA switch"); 881 if (err) 882 goto err_startup; 883 err = gpio_direction_output(si->pdata->gpio_pwdown, 884 !si->pdata->gpio_pwdown_inverted); 885 if (err) { 886 gpio_free(si->pdata->gpio_pwdown); 887 goto err_startup; 888 } 889 } 890 891 if (si->pdata->startup) { 892 err = si->pdata->startup(si->dev); 893 if (err) 894 goto err_startup; 895 } 896 897 if (gpio_is_valid(si->pdata->gpio_pwdown) && si->pdata->startup) 898 dev_warn(si->dev, "gpio_pwdown and startup() both defined!\n"); 899 900 dev->netdev_ops = &pxa_irda_netdev_ops; 901 902 irda_init_max_qos_capabilies(&si->qos); 903 904 baudrate_mask = 0; 905 if (si->pdata->transceiver_cap & IR_SIRMODE) 906 baudrate_mask |= IR_9600|IR_19200|IR_38400|IR_57600|IR_115200; 907 if (si->pdata->transceiver_cap & IR_FIRMODE) 908 baudrate_mask |= IR_4000000 << 8; 909 910 si->qos.baud_rate.bits &= baudrate_mask; 911 si->qos.min_turn_time.bits = 7; /* 1ms or more */ 912 913 irda_qos_bits_to_value(&si->qos); 914 915 err = register_netdev(dev); 916 917 if (err == 0) 918 platform_set_drvdata(pdev, dev); 919 920 if (err) { 921 if (si->pdata->shutdown) 922 si->pdata->shutdown(si->dev); 923err_startup: 924 kfree(si->tx_buff.head); 925err_mem_5: 926 kfree(si->rx_buff.head); 927err_mem_4: 928 if (si->sir_clk && !IS_ERR(si->sir_clk)) 929 clk_put(si->sir_clk); 930 if (si->fir_clk && !IS_ERR(si->fir_clk)) 931 clk_put(si->fir_clk); 932 free_netdev(dev); 933err_mem_3: 934 release_mem_region(__PREG(FICP), 0x1c); 935err_mem_2: 936 release_mem_region(__PREG(STUART), 0x24); 937 } 938err_mem_1: 939 return err; 940} 941 942static int pxa_irda_remove(struct platform_device *_dev) 943{ 944 struct net_device *dev = platform_get_drvdata(_dev); 945 946 if (dev) { 947 struct pxa_irda *si = netdev_priv(dev); 948 unregister_netdev(dev); 949 if (gpio_is_valid(si->pdata->gpio_pwdown)) 950 gpio_free(si->pdata->gpio_pwdown); 951 if (si->pdata->shutdown) 952 si->pdata->shutdown(si->dev); 953 kfree(si->tx_buff.head); 954 kfree(si->rx_buff.head); 955 clk_put(si->fir_clk); 956 clk_put(si->sir_clk); 957 free_netdev(dev); 958 } 959 960 release_mem_region(__PREG(STUART), 0x24); 961 release_mem_region(__PREG(FICP), 0x1c); 962 963 return 0; 964} 965 966static struct platform_driver pxa_ir_driver = { 967 .driver = { 968 .name = "pxa2xx-ir", 969 }, 970 .probe = pxa_irda_probe, 971 .remove = pxa_irda_remove, 972 .suspend = pxa_irda_suspend, 973 .resume = pxa_irda_resume, 974}; 975 976module_platform_driver(pxa_ir_driver); 977 978MODULE_LICENSE("GPL"); 979MODULE_ALIAS("platform:pxa2xx-ir"); 980