1/* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#ifndef _HW_H_ 19#define _HW_H_ 20 21#include "targaddrs.h" 22 23#define ATH10K_FW_DIR "ath10k" 24 25/* QCA988X 1.0 definitions (unsupported) */ 26#define QCA988X_HW_1_0_CHIP_ID_REV 0x0 27 28/* QCA988X 2.0 definitions */ 29#define QCA988X_HW_2_0_VERSION 0x4100016c 30#define QCA988X_HW_2_0_CHIP_ID_REV 0x2 31#define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" 32#define QCA988X_HW_2_0_FW_FILE "firmware.bin" 33#define QCA988X_HW_2_0_OTP_FILE "otp.bin" 34#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" 35#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 36 37/* QCA6174 target BMI version signatures */ 38#define QCA6174_HW_1_0_VERSION 0x05000000 39#define QCA6174_HW_1_1_VERSION 0x05000001 40#define QCA6174_HW_1_3_VERSION 0x05000003 41#define QCA6174_HW_2_1_VERSION 0x05010000 42#define QCA6174_HW_3_0_VERSION 0x05020000 43#define QCA6174_HW_3_2_VERSION 0x05030000 44 45enum qca6174_pci_rev { 46 QCA6174_PCI_REV_1_1 = 0x11, 47 QCA6174_PCI_REV_1_3 = 0x13, 48 QCA6174_PCI_REV_2_0 = 0x20, 49 QCA6174_PCI_REV_3_0 = 0x30, 50}; 51 52enum qca6174_chip_id_rev { 53 QCA6174_HW_1_0_CHIP_ID_REV = 0, 54 QCA6174_HW_1_1_CHIP_ID_REV = 1, 55 QCA6174_HW_1_3_CHIP_ID_REV = 2, 56 QCA6174_HW_2_1_CHIP_ID_REV = 4, 57 QCA6174_HW_2_2_CHIP_ID_REV = 5, 58 QCA6174_HW_3_0_CHIP_ID_REV = 8, 59 QCA6174_HW_3_1_CHIP_ID_REV = 9, 60 QCA6174_HW_3_2_CHIP_ID_REV = 10, 61}; 62 63#define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" 64#define QCA6174_HW_2_1_FW_FILE "firmware.bin" 65#define QCA6174_HW_2_1_OTP_FILE "otp.bin" 66#define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" 67#define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 68 69#define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" 70#define QCA6174_HW_3_0_FW_FILE "firmware.bin" 71#define QCA6174_HW_3_0_OTP_FILE "otp.bin" 72#define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" 73#define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 74 75#define ATH10K_FW_API2_FILE "firmware-2.bin" 76#define ATH10K_FW_API3_FILE "firmware-3.bin" 77 78/* added support for ATH10K_FW_IE_WMI_OP_VERSION */ 79#define ATH10K_FW_API4_FILE "firmware-4.bin" 80 81#define ATH10K_FW_UTF_FILE "utf.bin" 82 83/* includes also the null byte */ 84#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" 85 86#define REG_DUMP_COUNT_QCA988X 60 87 88#define QCA988X_CAL_DATA_LEN 2116 89 90struct ath10k_fw_ie { 91 __le32 id; 92 __le32 len; 93 u8 data[0]; 94}; 95 96enum ath10k_fw_ie_type { 97 ATH10K_FW_IE_FW_VERSION = 0, 98 ATH10K_FW_IE_TIMESTAMP = 1, 99 ATH10K_FW_IE_FEATURES = 2, 100 ATH10K_FW_IE_FW_IMAGE = 3, 101 ATH10K_FW_IE_OTP_IMAGE = 4, 102 103 /* WMI "operations" interface version, 32 bit value. Supported from 104 * FW API 4 and above. 105 */ 106 ATH10K_FW_IE_WMI_OP_VERSION = 5, 107}; 108 109enum ath10k_fw_wmi_op_version { 110 ATH10K_FW_WMI_OP_VERSION_UNSET = 0, 111 112 ATH10K_FW_WMI_OP_VERSION_MAIN = 1, 113 ATH10K_FW_WMI_OP_VERSION_10_1 = 2, 114 ATH10K_FW_WMI_OP_VERSION_10_2 = 3, 115 ATH10K_FW_WMI_OP_VERSION_TLV = 4, 116 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, 117 118 /* keep last */ 119 ATH10K_FW_WMI_OP_VERSION_MAX, 120}; 121 122enum ath10k_hw_rev { 123 ATH10K_HW_QCA988X, 124 ATH10K_HW_QCA6174, 125}; 126 127struct ath10k_hw_regs { 128 u32 rtc_state_cold_reset_mask; 129 u32 rtc_soc_base_address; 130 u32 rtc_wmac_base_address; 131 u32 soc_core_base_address; 132 u32 ce_wrapper_base_address; 133 u32 ce0_base_address; 134 u32 ce1_base_address; 135 u32 ce2_base_address; 136 u32 ce3_base_address; 137 u32 ce4_base_address; 138 u32 ce5_base_address; 139 u32 ce6_base_address; 140 u32 ce7_base_address; 141 u32 soc_reset_control_si0_rst_mask; 142 u32 soc_reset_control_ce_rst_mask; 143 u32 soc_chip_id_address; 144 u32 scratch_3_address; 145}; 146 147extern const struct ath10k_hw_regs qca988x_regs; 148extern const struct ath10k_hw_regs qca6174_regs; 149 150#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) 151#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) 152 153/* Known pecularities: 154 * - current FW doesn't support raw rx mode (last tested v599) 155 * - current FW dumps upon raw tx mode (last tested v599) 156 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap 157 * - raw have FCS, nwifi doesn't 158 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher 159 * param, llc/snap) are aligned to 4byte boundaries each */ 160enum ath10k_hw_txrx_mode { 161 ATH10K_HW_TXRX_RAW = 0, 162 ATH10K_HW_TXRX_NATIVE_WIFI = 1, 163 ATH10K_HW_TXRX_ETHERNET = 2, 164 165 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ 166 ATH10K_HW_TXRX_MGMT = 3, 167}; 168 169enum ath10k_mcast2ucast_mode { 170 ATH10K_MCAST2UCAST_DISABLED = 0, 171 ATH10K_MCAST2UCAST_ENABLED = 1, 172}; 173 174struct ath10k_pktlog_hdr { 175 __le16 flags; 176 __le16 missed_cnt; 177 __le16 log_type; 178 __le16 size; 179 __le32 timestamp; 180 u8 payload[0]; 181} __packed; 182 183/* Target specific defines for MAIN firmware */ 184#define TARGET_NUM_VDEVS 8 185#define TARGET_NUM_PEER_AST 2 186#define TARGET_NUM_WDS_ENTRIES 32 187#define TARGET_DMA_BURST_SIZE 0 188#define TARGET_MAC_AGGR_DELIM 0 189#define TARGET_AST_SKID_LIMIT 16 190#define TARGET_NUM_STATIONS 16 191#define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ 192 (TARGET_NUM_VDEVS)) 193#define TARGET_NUM_OFFLOAD_PEERS 0 194#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 195#define TARGET_NUM_PEER_KEYS 2 196#define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) 197#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 198#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 199#define TARGET_RX_TIMEOUT_LO_PRI 100 200#define TARGET_RX_TIMEOUT_HI_PRI 40 201 202/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and 203 * avoid a very expensive re-alignment in mac80211. */ 204#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 205 206#define TARGET_SCAN_MAX_PENDING_REQS 4 207#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 208#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 209#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 210#define TARGET_GTK_OFFLOAD_MAX_VDEV 3 211#define TARGET_NUM_MCAST_GROUPS 0 212#define TARGET_NUM_MCAST_TABLE_ELEMS 0 213#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 214#define TARGET_TX_DBG_LOG_SIZE 1024 215#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 216#define TARGET_VOW_CONFIG 0 217#define TARGET_NUM_MSDU_DESC (1024 + 400) 218#define TARGET_MAX_FRAG_ENTRIES 0 219 220/* Target specific defines for 10.X firmware */ 221#define TARGET_10X_NUM_VDEVS 16 222#define TARGET_10X_NUM_PEER_AST 2 223#define TARGET_10X_NUM_WDS_ENTRIES 32 224#define TARGET_10X_DMA_BURST_SIZE 0 225#define TARGET_10X_MAC_AGGR_DELIM 0 226#define TARGET_10X_AST_SKID_LIMIT 16 227#define TARGET_10X_NUM_STATIONS 128 228#define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ 229 (TARGET_10X_NUM_VDEVS)) 230#define TARGET_10X_NUM_OFFLOAD_PEERS 0 231#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 232#define TARGET_10X_NUM_PEER_KEYS 2 233#define TARGET_10X_NUM_TIDS_MAX 256 234#define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ 235 (TARGET_10X_NUM_PEERS) * 2) 236#define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 237#define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) 238#define TARGET_10X_RX_TIMEOUT_LO_PRI 100 239#define TARGET_10X_RX_TIMEOUT_HI_PRI 40 240#define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI 241#define TARGET_10X_SCAN_MAX_PENDING_REQS 4 242#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 243#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 244#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 245#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 246#define TARGET_10X_NUM_MCAST_GROUPS 0 247#define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 248#define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED 249#define TARGET_10X_TX_DBG_LOG_SIZE 1024 250#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 251#define TARGET_10X_VOW_CONFIG 0 252#define TARGET_10X_NUM_MSDU_DESC (1024 + 400) 253#define TARGET_10X_MAX_FRAG_ENTRIES 0 254 255/* 10.2 parameters */ 256#define TARGET_10_2_DMA_BURST_SIZE 1 257 258/* Target specific defines for WMI-TLV firmware */ 259#define TARGET_TLV_NUM_VDEVS 3 260#define TARGET_TLV_NUM_STATIONS 32 261#define TARGET_TLV_NUM_PEERS ((TARGET_TLV_NUM_STATIONS) + \ 262 (TARGET_TLV_NUM_VDEVS) + \ 263 2) 264#define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) 265#define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) 266 267/* Number of Copy Engines supported */ 268#define CE_COUNT 8 269 270/* 271 * Total number of PCIe MSI interrupts requested for all interrupt sources. 272 * PCIe standard forces this to be a power of 2. 273 * Some Host OS's limit MSI requests that can be granted to 8 274 * so for now we abide by this limit and avoid requesting more 275 * than that. 276 */ 277#define MSI_NUM_REQUEST_LOG2 3 278#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) 279 280/* 281 * Granted MSIs are assigned as follows: 282 * Firmware uses the first 283 * Remaining MSIs, if any, are used by Copy Engines 284 * This mapping is known to both Target firmware and Host software. 285 * It may be changed as long as Host and Target are kept in sync. 286 */ 287/* MSI for firmware (errors, etc.) */ 288#define MSI_ASSIGN_FW 0 289 290/* MSIs for Copy Engines */ 291#define MSI_ASSIGN_CE_INITIAL 1 292#define MSI_ASSIGN_CE_MAX 7 293 294/* as of IP3.7.1 */ 295#define RTC_STATE_V_ON 3 296 297#define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask 298#define RTC_STATE_V_LSB 0 299#define RTC_STATE_V_MASK 0x00000007 300#define RTC_STATE_ADDRESS 0x0000 301#define PCIE_SOC_WAKE_V_MASK 0x00000001 302#define PCIE_SOC_WAKE_ADDRESS 0x0004 303#define PCIE_SOC_WAKE_RESET 0x00000000 304#define SOC_GLOBAL_RESET_ADDRESS 0x0008 305 306#define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address 307#define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address 308#define MAC_COEX_BASE_ADDRESS 0x00006000 309#define BT_COEX_BASE_ADDRESS 0x00007000 310#define SOC_PCIE_BASE_ADDRESS 0x00008000 311#define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address 312#define WLAN_UART_BASE_ADDRESS 0x0000c000 313#define WLAN_SI_BASE_ADDRESS 0x00010000 314#define WLAN_GPIO_BASE_ADDRESS 0x00014000 315#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 316#define WLAN_MAC_BASE_ADDRESS 0x00020000 317#define EFUSE_BASE_ADDRESS 0x00030000 318#define FPGA_REG_BASE_ADDRESS 0x00039000 319#define WLAN_UART2_BASE_ADDRESS 0x00054c00 320#define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address 321#define CE0_BASE_ADDRESS ar->regs->ce0_base_address 322#define CE1_BASE_ADDRESS ar->regs->ce1_base_address 323#define CE2_BASE_ADDRESS ar->regs->ce2_base_address 324#define CE3_BASE_ADDRESS ar->regs->ce3_base_address 325#define CE4_BASE_ADDRESS ar->regs->ce4_base_address 326#define CE5_BASE_ADDRESS ar->regs->ce5_base_address 327#define CE6_BASE_ADDRESS ar->regs->ce6_base_address 328#define CE7_BASE_ADDRESS ar->regs->ce7_base_address 329#define DBI_BASE_ADDRESS 0x00060000 330#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 331#define PCIE_LOCAL_BASE_ADDRESS 0x00080000 332 333#define SOC_RESET_CONTROL_ADDRESS 0x00000000 334#define SOC_RESET_CONTROL_OFFSET 0x00000000 335#define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask 336#define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask 337#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 338#define SOC_CPU_CLOCK_OFFSET 0x00000020 339#define SOC_CPU_CLOCK_STANDARD_LSB 0 340#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 341#define SOC_CLOCK_CONTROL_OFFSET 0x00000028 342#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 343#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 344#define SOC_LPO_CAL_OFFSET 0x000000e0 345#define SOC_LPO_CAL_ENABLE_LSB 20 346#define SOC_LPO_CAL_ENABLE_MASK 0x00100000 347#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 348#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 349 350#define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address 351#define SOC_CHIP_ID_REV_LSB 8 352#define SOC_CHIP_ID_REV_MASK 0x00000f00 353 354#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 355#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 356#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 357#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 358 359#define WLAN_GPIO_PIN0_ADDRESS 0x00000028 360#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 361#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c 362#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 363#define WLAN_GPIO_PIN10_ADDRESS 0x00000050 364#define WLAN_GPIO_PIN11_ADDRESS 0x00000054 365#define WLAN_GPIO_PIN12_ADDRESS 0x00000058 366#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c 367 368#define CLOCK_GPIO_OFFSET 0xffffffff 369#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 370#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 371 372#define SI_CONFIG_OFFSET 0x00000000 373#define SI_CONFIG_BIDIR_OD_DATA_LSB 18 374#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 375#define SI_CONFIG_I2C_LSB 16 376#define SI_CONFIG_I2C_MASK 0x00010000 377#define SI_CONFIG_POS_SAMPLE_LSB 7 378#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 379#define SI_CONFIG_INACTIVE_DATA_LSB 5 380#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 381#define SI_CONFIG_INACTIVE_CLK_LSB 4 382#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 383#define SI_CONFIG_DIVIDER_LSB 0 384#define SI_CONFIG_DIVIDER_MASK 0x0000000f 385#define SI_CS_OFFSET 0x00000004 386#define SI_CS_DONE_ERR_MASK 0x00000400 387#define SI_CS_DONE_INT_MASK 0x00000200 388#define SI_CS_START_LSB 8 389#define SI_CS_START_MASK 0x00000100 390#define SI_CS_RX_CNT_LSB 4 391#define SI_CS_RX_CNT_MASK 0x000000f0 392#define SI_CS_TX_CNT_LSB 0 393#define SI_CS_TX_CNT_MASK 0x0000000f 394 395#define SI_TX_DATA0_OFFSET 0x00000008 396#define SI_TX_DATA1_OFFSET 0x0000000c 397#define SI_RX_DATA0_OFFSET 0x00000010 398#define SI_RX_DATA1_OFFSET 0x00000014 399 400#define CORE_CTRL_CPU_INTR_MASK 0x00002000 401#define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 402#define CORE_CTRL_ADDRESS 0x0000 403#define PCIE_INTR_ENABLE_ADDRESS 0x0008 404#define PCIE_INTR_CAUSE_ADDRESS 0x000c 405#define PCIE_INTR_CLR_ADDRESS 0x0014 406#define SCRATCH_3_ADDRESS ar->regs->scratch_3_address 407#define CPU_INTR_ADDRESS 0x0010 408 409/* Firmware indications to the Host via SCRATCH_3 register. */ 410#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) 411#define FW_IND_EVENT_PENDING 1 412#define FW_IND_INITIALIZED 2 413 414/* HOST_REG interrupt from firmware */ 415#define PCIE_INTR_FIRMWARE_MASK 0x00000400 416#define PCIE_INTR_CE_MASK_ALL 0x0007f800 417 418#define DRAM_BASE_ADDRESS 0x00400000 419 420#define MISSING 0 421 422#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 423#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET 424#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET 425#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET 426#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK 427#define RESET_CONTROL_MBOX_RST_MASK MISSING 428#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK 429#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS 430#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS 431#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS 432#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK 433#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK 434#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS 435#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS 436#define LOCAL_SCRATCH_OFFSET 0x18 437#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET 438#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET 439#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS 440#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS 441#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS 442#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS 443#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB 444#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK 445#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB 446#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK 447#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS 448#define MBOX_BASE_ADDRESS MISSING 449#define INT_STATUS_ENABLE_ERROR_LSB MISSING 450#define INT_STATUS_ENABLE_ERROR_MASK MISSING 451#define INT_STATUS_ENABLE_CPU_LSB MISSING 452#define INT_STATUS_ENABLE_CPU_MASK MISSING 453#define INT_STATUS_ENABLE_COUNTER_LSB MISSING 454#define INT_STATUS_ENABLE_COUNTER_MASK MISSING 455#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 456#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 457#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 458#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 459#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 460#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 461#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 462#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 463#define INT_STATUS_ENABLE_ADDRESS MISSING 464#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 465#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 466#define HOST_INT_STATUS_ADDRESS MISSING 467#define CPU_INT_STATUS_ADDRESS MISSING 468#define ERROR_INT_STATUS_ADDRESS MISSING 469#define ERROR_INT_STATUS_WAKEUP_MASK MISSING 470#define ERROR_INT_STATUS_WAKEUP_LSB MISSING 471#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 472#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 473#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 474#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 475#define COUNT_DEC_ADDRESS MISSING 476#define HOST_INT_STATUS_CPU_MASK MISSING 477#define HOST_INT_STATUS_CPU_LSB MISSING 478#define HOST_INT_STATUS_ERROR_MASK MISSING 479#define HOST_INT_STATUS_ERROR_LSB MISSING 480#define HOST_INT_STATUS_COUNTER_MASK MISSING 481#define HOST_INT_STATUS_COUNTER_LSB MISSING 482#define RX_LOOKAHEAD_VALID_ADDRESS MISSING 483#define WINDOW_DATA_ADDRESS MISSING 484#define WINDOW_READ_ADDR_ADDRESS MISSING 485#define WINDOW_WRITE_ADDR_ADDRESS MISSING 486 487#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) 488 489#endif /* _HW_H_ */ 490