1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _PCI_H_
19#define _PCI_H_
20
21#include <linux/interrupt.h>
22
23#include "hw.h"
24#include "ce.h"
25
26/*
27 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
28 */
29#define DIAG_TRANSFER_LIMIT 2048
30
31/*
32 * maximum number of bytes that can be
33 * handled atomically by DiagRead/DiagWrite
34 */
35#define DIAG_TRANSFER_LIMIT 2048
36
37struct bmi_xfer {
38	bool tx_done;
39	bool rx_done;
40	bool wait_for_resp;
41	u32 resp_len;
42};
43
44/*
45 * PCI-specific Target state
46 *
47 * NOTE: Structure is shared between Host software and Target firmware!
48 *
49 * Much of this may be of interest to the Host so
50 * HOST_INTEREST->hi_interconnect_state points here
51 * (and all members are 32-bit quantities in order to
52 * facilitate Host access). In particular, Host software is
53 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
54 */
55struct pcie_state {
56	/* Pipe configuration Target address */
57	/* NB: ce_pipe_config[CE_COUNT] */
58	u32 pipe_cfg_addr;
59
60	/* Service to pipe map Target address */
61	/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
62	u32 svc_to_pipe_map;
63
64	/* number of MSI interrupts requested */
65	u32 msi_requested;
66
67	/* number of MSI interrupts granted */
68	u32 msi_granted;
69
70	/* Message Signalled Interrupt address */
71	u32 msi_addr;
72
73	/* Base data */
74	u32 msi_data;
75
76	/*
77	 * Data for firmware interrupt;
78	 * MSI data for other interrupts are
79	 * in various SoC registers
80	 */
81	u32 msi_fw_intr_data;
82
83	/* PCIE_PWR_METHOD_* */
84	u32 power_mgmt_method;
85
86	/* PCIE_CONFIG_FLAG_* */
87	u32 config_flags;
88};
89
90/* PCIE_CONFIG_FLAG definitions */
91#define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
92
93/* Host software's Copy Engine configuration. */
94#define CE_ATTR_FLAGS 0
95
96/*
97 * Configuration information for a Copy Engine pipe.
98 * Passed from Host to Target during startup (one per CE).
99 *
100 * NOTE: Structure is shared between Host software and Target firmware!
101 */
102struct ce_pipe_config {
103	__le32 pipenum;
104	__le32 pipedir;
105	__le32 nentries;
106	__le32 nbytes_max;
107	__le32 flags;
108	__le32 reserved;
109};
110
111/*
112 * Directions for interconnect pipe configuration.
113 * These definitions may be used during configuration and are shared
114 * between Host and Target.
115 *
116 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
117 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
118 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
119 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
120 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
121 * over the interconnect.
122 */
123#define PIPEDIR_NONE    0
124#define PIPEDIR_IN      1  /* Target-->Host, WiFi Rx direction */
125#define PIPEDIR_OUT     2  /* Host->Target, WiFi Tx direction */
126#define PIPEDIR_INOUT   3  /* bidirectional */
127
128/* Establish a mapping between a service/direction and a pipe. */
129struct service_to_pipe {
130	__le32 service_id;
131	__le32 pipedir;
132	__le32 pipenum;
133};
134
135/* Per-pipe state. */
136struct ath10k_pci_pipe {
137	/* Handle of underlying Copy Engine */
138	struct ath10k_ce_pipe *ce_hdl;
139
140	/* Our pipe number; facilitiates use of pipe_info ptrs. */
141	u8 pipe_num;
142
143	/* Convenience back pointer to hif_ce_state. */
144	struct ath10k *hif_ce_state;
145
146	size_t buf_sz;
147
148	/* protects compl_free and num_send_allowed */
149	spinlock_t pipe_lock;
150
151	struct ath10k_pci *ar_pci;
152	struct tasklet_struct intr;
153};
154
155struct ath10k_pci_supp_chip {
156	u32 dev_id;
157	u32 rev_id;
158};
159
160struct ath10k_pci {
161	struct pci_dev *pdev;
162	struct device *dev;
163	struct ath10k *ar;
164	void __iomem *mem;
165
166	/*
167	 * Number of MSI interrupts granted, 0 --> using legacy PCI line
168	 * interrupts.
169	 */
170	int num_msi_intrs;
171
172	struct tasklet_struct intr_tq;
173	struct tasklet_struct msi_fw_err;
174
175	struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
176
177	struct ath10k_hif_cb msg_callbacks_current;
178
179	/* Copy Engine used for Diagnostic Accesses */
180	struct ath10k_ce_pipe *ce_diag;
181
182	/* FIXME: document what this really protects */
183	spinlock_t ce_lock;
184
185	/* Map CE id to ce_state */
186	struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
187	struct timer_list rx_post_retry;
188};
189
190static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
191{
192	return (struct ath10k_pci *)ar->drv_priv;
193}
194
195#define ATH10K_PCI_RX_POST_RETRY_MS 50
196#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
197#define PCIE_WAKE_TIMEOUT 10000	/* 10ms */
198
199#define BAR_NUM 0
200
201#define CDC_WAR_MAGIC_STR   0xceef0000
202#define CDC_WAR_DATA_CE     4
203
204/*
205 * TODO: Should be a function call specific to each Target-type.
206 * This convoluted macro converts from Target CPU Virtual Address Space to CE
207 * Address Space. As part of this process, we conservatively fetch the current
208 * PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
209 * for this device; but that's not guaranteed.
210 */
211#define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr)			\
212	(((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS|			\
213	  CORE_CTRL_ADDRESS)) & 0x7ff) << 21) |				\
214	 0x100000 | ((addr) & 0xfffff))
215
216/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
217#define DIAG_ACCESS_CE_TIMEOUT_MS 10
218
219/* Target exposes its registers for direct access. However before host can
220 * access them it needs to make sure the target is awake (ath10k_pci_wake,
221 * ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go
222 * to sleep unless host tells it to (ath10k_pci_sleep).
223 *
224 * If host tries to access target registers without waking it up it can
225 * scribble over host memory.
226 *
227 * If target is asleep waking it up may take up to even 2ms.
228 */
229
230static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
231				      u32 value)
232{
233	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
234
235	iowrite32(value, ar_pci->mem + offset);
236}
237
238static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
239{
240	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
241
242	return ioread32(ar_pci->mem + offset);
243}
244
245static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
246{
247	return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
248}
249
250static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
251{
252	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
253}
254
255static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
256{
257	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
258
259	return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
260}
261
262static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
263{
264	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
265
266	iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
267}
268
269#endif /* _PCI_H_ */
270