1/* 2 * Copyright (c) 2012-2015 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef __WIL6210_H__ 18#define __WIL6210_H__ 19 20#include <linux/netdevice.h> 21#include <linux/wireless.h> 22#include <net/cfg80211.h> 23#include <linux/timex.h> 24#include "wil_platform.h" 25 26extern bool no_fw_recovery; 27extern unsigned int mtu_max; 28extern unsigned short rx_ring_overflow_thrsh; 29extern int agg_wsize; 30extern u32 vring_idle_trsh; 31extern bool rx_align_2; 32 33#define WIL_NAME "wil6210" 34#define WIL_FW_NAME "wil6210.fw" /* code */ 35#define WIL_FW2_NAME "wil6210.board" /* board & radio parameters */ 36 37#define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 38 39/** 40 * extract bits [@b0:@b1] (inclusive) from the value @x 41 * it should be @b0 <= @b1, or result is incorrect 42 */ 43static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 44{ 45 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 46} 47 48#define WIL6210_MEM_SIZE (2*1024*1024UL) 49 50#define WIL_TX_Q_LEN_DEFAULT (4000) 51#define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 52#define WIL_TX_RING_SIZE_ORDER_DEFAULT (10) 53#define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 54#define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 55/* limit ring size in range [32..32k] */ 56#define WIL_RING_SIZE_ORDER_MIN (5) 57#define WIL_RING_SIZE_ORDER_MAX (15) 58#define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 59#define WIL6210_MAX_CID (8) /* HW limit */ 60#define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 61#define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 62#define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 63/* Hardware offload block adds the following: 64 * 26 bytes - 3-address QoS data header 65 * 8 bytes - IV + EIV (for GCMP) 66 * 8 bytes - SNAP 67 * 16 bytes - MIC (for GCMP) 68 * 4 bytes - CRC 69 */ 70#define WIL_MAX_MPDU_OVERHEAD (62) 71 72/* Calculate MAC buffer size for the firmware. It includes all overhead, 73 * as it will go over the air, and need to be 8 byte aligned 74 */ 75static inline u32 wil_mtu2macbuf(u32 mtu) 76{ 77 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 78} 79 80/* MTU for Ethernet need to take into account 8-byte SNAP header 81 * to be added when encapsulating Ethernet frame into 802.11 82 */ 83#define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 84/* Max supported by wil6210 value for interrupt threshold is 5sec. */ 85#define WIL6210_ITR_TRSH_MAX (5000000) 86#define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 87#define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 88#define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 89#define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 90#define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 91#define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 92#define WIL6210_SCAN_TO msecs_to_jiffies(10000) 93#define WIL6210_RX_HIGH_TRSH_INIT (0) 94#define WIL6210_RX_HIGH_TRSH_DEFAULT \ 95 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 96/* Hardware definitions begin */ 97 98/* 99 * Mapping 100 * RGF File | Host addr | FW addr 101 * | | 102 * user_rgf | 0x000000 | 0x880000 103 * dma_rgf | 0x001000 | 0x881000 104 * pcie_rgf | 0x002000 | 0x882000 105 * | | 106 */ 107 108/* Where various structures placed in host address space */ 109#define WIL6210_FW_HOST_OFF (0x880000UL) 110 111#define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 112 113/* 114 * Interrupt control registers block 115 * 116 * each interrupt controlled by the same bit in all registers 117 */ 118struct RGF_ICR { 119 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 120 u32 ICR; /* Cause, W1C/COR depending on ICC */ 121 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 122 u32 ICS; /* Cause Set, WO */ 123 u32 IMV; /* Mask, RW+S/C */ 124 u32 IMS; /* Mask Set, write 1 to set */ 125 u32 IMC; /* Mask Clear, write 1 to clear */ 126} __packed; 127 128struct RGF_BL { 129 u32 ready; /* 0x880A3C bit [0] */ 130#define BIT_BL_READY BIT(0) 131 u32 version; /* 0x880A40 version of the BL struct */ 132 u32 rf_type; /* 0x880A44 ID of the connected RF */ 133 u32 baseband_type; /* 0x880A48 ID of the baseband */ 134 u8 mac_address[ETH_ALEN]; /* 0x880A4C permanent MAC */ 135 u8 pad[2]; 136} __packed; 137 138/* registers - FW addresses */ 139#define RGF_USER_USAGE_1 (0x880004) 140#define RGF_USER_USAGE_6 (0x880018) 141#define RGF_USER_HW_MACHINE_STATE (0x8801dc) 142 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 143#define RGF_USER_USER_CPU_0 (0x8801e0) 144 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 145#define RGF_USER_MAC_CPU_0 (0x8801fc) 146 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 147#define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 148#define RGF_USER_BL (0x880A3C) /* Boot Loader */ 149#define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 150#define RGF_USER_CLKS_CTL_0 (0x880abc) 151 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 152 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 153#define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 154#define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 155#define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 156#define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 157#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 158 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 159 #define BIT_CAR_PERST_RST BIT(7) 160#define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 161 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 162#define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 163#define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 164#define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 165 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 166 167#define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 168 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 169 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 170#define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 171 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 172 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 173#define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 174 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 175 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 176 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 177 178/* Legacy interrupt moderation control (before Sparrow v2)*/ 179#define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 180#define RGF_DMA_ITR_CNT_DATA (0x881c60) 181#define RGF_DMA_ITR_CNT_CRL (0x881c64) 182 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 183 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 184 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 185 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 186 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 187 188/* Offload control (Sparrow B0+) */ 189#define RGF_DMA_OFUL_NID_0 (0x881cd4) 190 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 191 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 192 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 193 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 194 195/* New (sparrow v2+) interrupt moderation control */ 196#define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 197#define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 198#define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 199#define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 200 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 201 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 202 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 203 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 204 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 205 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 206 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 207#define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 208#define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 209#define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 210 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 211 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 212 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 213 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 214 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 215#define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 216#define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 217#define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 218#define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 219 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 220 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 221 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 222 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 223 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 224 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 225 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 226#define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 227#define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 228#define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 229 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 230 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 231 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 232 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 233 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 234 235#define RGF_DMA_PSEUDO_CAUSE (0x881c68) 236#define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 237#define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 238 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 239 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 240 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 241 242#define RGF_HP_CTRL (0x88265c) 243#define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 244 245/* MAC timer, usec, for packet lifetime */ 246#define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 247 248#define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 249#define RGF_CAF_OSC_CONTROL (0x88afa4) 250 #define BIT_CAF_OSC_XTAL_EN BIT(0) 251#define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 252 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 253 254#define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 255 #define JTAG_DEV_ID_SPARROW_B0 (0x2632072f) 256 257enum { 258 HW_VER_UNKNOWN, 259 HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */ 260}; 261 262/* popular locations */ 263#define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD) 264#define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \ 265 offsetof(struct RGF_ICR, ICS)) 266#define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 267 268/* ISR register bits */ 269#define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 270#define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 271#define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 272 273/* Hardware definitions end */ 274struct fw_map { 275 u32 from; /* linker address - from, inclusive */ 276 u32 to; /* linker address - to, exclusive */ 277 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 278 const char *name; /* for debugfs */ 279}; 280 281/* array size should be in sync with actual definition in the wmi.c */ 282extern const struct fw_map fw_mapping[7]; 283 284/** 285 * mk_cidxtid - construct @cidxtid field 286 * @cid: CID value 287 * @tid: TID value 288 * 289 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 290 */ 291static inline u8 mk_cidxtid(u8 cid, u8 tid) 292{ 293 return ((tid & 0xf) << 4) | (cid & 0xf); 294} 295 296/** 297 * parse_cidxtid - parse @cidxtid field 298 * @cid: store CID value here 299 * @tid: store TID value here 300 * 301 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 302 */ 303static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 304{ 305 *cid = cidxtid & 0xf; 306 *tid = (cidxtid >> 4) & 0xf; 307} 308 309struct wil6210_mbox_ring { 310 u32 base; 311 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 312 u16 size; 313 u32 tail; 314 u32 head; 315} __packed; 316 317struct wil6210_mbox_ring_desc { 318 __le32 sync; 319 __le32 addr; 320} __packed; 321 322/* at HOST_OFF_WIL6210_MBOX_CTL */ 323struct wil6210_mbox_ctl { 324 struct wil6210_mbox_ring tx; 325 struct wil6210_mbox_ring rx; 326} __packed; 327 328struct wil6210_mbox_hdr { 329 __le16 seq; 330 __le16 len; /* payload, bytes after this header */ 331 __le16 type; 332 u8 flags; 333 u8 reserved; 334} __packed; 335 336#define WIL_MBOX_HDR_TYPE_WMI (0) 337 338/* max. value for wil6210_mbox_hdr.len */ 339#define MAX_MBOXITEM_SIZE (240) 340 341/** 342 * struct wil6210_mbox_hdr_wmi - WMI header 343 * 344 * @mid: MAC ID 345 * 00 - default, created by FW 346 * 01..0f - WiFi ports, driver to create 347 * 10..fe - debug 348 * ff - broadcast 349 * @id: command/event ID 350 * @timestamp: FW fills for events, free-running msec timer 351 */ 352struct wil6210_mbox_hdr_wmi { 353 u8 mid; 354 u8 reserved; 355 __le16 id; 356 __le32 timestamp; 357} __packed; 358 359struct pending_wmi_event { 360 struct list_head list; 361 struct { 362 struct wil6210_mbox_hdr hdr; 363 struct wil6210_mbox_hdr_wmi wmi; 364 u8 data[0]; 365 } __packed event; 366}; 367 368enum { /* for wil_ctx.mapped_as */ 369 wil_mapped_as_none = 0, 370 wil_mapped_as_single = 1, 371 wil_mapped_as_page = 2, 372}; 373 374/** 375 * struct wil_ctx - software context for Vring descriptor 376 */ 377struct wil_ctx { 378 struct sk_buff *skb; 379 u8 nr_frags; 380 u8 mapped_as; 381}; 382 383union vring_desc; 384 385struct vring { 386 dma_addr_t pa; 387 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */ 388 u16 size; /* number of vring_desc elements */ 389 u32 swtail; 390 u32 swhead; 391 u32 hwtail; /* write here to inform hw */ 392 struct wil_ctx *ctx; /* ctx[size] - software context */ 393}; 394 395/** 396 * Additional data for Tx Vring 397 */ 398struct vring_tx_data { 399 int enabled; 400 cycles_t idle, last_idle, begin; 401 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 402 u16 agg_timeout; 403 u8 agg_amsdu; 404 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 405 spinlock_t lock; 406}; 407 408enum { /* for wil6210_priv.status */ 409 wil_status_fwready = 0, 410 wil_status_fwconnecting, 411 wil_status_fwconnected, 412 wil_status_dontscan, 413 wil_status_reset_done, 414 wil_status_irqen, /* FIXME: interrupts enabled - for debug */ 415 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 416 wil_status_last /* keep last */ 417}; 418 419struct pci_dev; 420 421/** 422 * struct tid_ampdu_rx - TID aggregation information (Rx). 423 * 424 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 425 * @reorder_time: jiffies when skb was added 426 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value) 427 * @reorder_timer: releases expired frames from the reorder buffer. 428 * @last_rx: jiffies of last rx activity 429 * @head_seq_num: head sequence number in reordering buffer. 430 * @stored_mpdu_num: number of MPDUs in reordering buffer 431 * @ssn: Starting Sequence Number expected to be aggregated. 432 * @buf_size: buffer size for incoming A-MPDUs 433 * @timeout: reset timer value (in TUs). 434 * @dialog_token: dialog token for aggregation session 435 * @rcu_head: RCU head used for freeing this struct 436 * 437 * This structure's lifetime is managed by RCU, assignments to 438 * the array holding it must hold the aggregation mutex. 439 * 440 */ 441struct wil_tid_ampdu_rx { 442 struct sk_buff **reorder_buf; 443 unsigned long *reorder_time; 444 struct timer_list session_timer; 445 struct timer_list reorder_timer; 446 unsigned long last_rx; 447 u16 head_seq_num; 448 u16 stored_mpdu_num; 449 u16 ssn; 450 u16 buf_size; 451 u16 timeout; 452 u16 ssn_last_drop; 453 u8 dialog_token; 454 bool first_time; /* is it 1-st time this buffer used? */ 455}; 456 457enum wil_sta_status { 458 wil_sta_unused = 0, 459 wil_sta_conn_pending = 1, 460 wil_sta_connected = 2, 461}; 462 463#define WIL_STA_TID_NUM (16) 464 465struct wil_net_stats { 466 unsigned long rx_packets; 467 unsigned long tx_packets; 468 unsigned long rx_bytes; 469 unsigned long tx_bytes; 470 unsigned long tx_errors; 471 unsigned long rx_dropped; 472 u16 last_mcs_rx; 473}; 474 475/** 476 * struct wil_sta_info - data for peer 477 * 478 * Peer identified by its CID (connection ID) 479 * NIC performs beam forming for each peer; 480 * if no beam forming done, frame exchange is not 481 * possible. 482 */ 483struct wil_sta_info { 484 u8 addr[ETH_ALEN]; 485 enum wil_sta_status status; 486 struct wil_net_stats stats; 487 bool data_port_open; /* can send any data, not only EAPOL */ 488 /* Rx BACK */ 489 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 490 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 491 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 492 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 493}; 494 495enum { 496 fw_recovery_idle = 0, 497 fw_recovery_pending = 1, 498 fw_recovery_running = 2, 499}; 500 501enum { 502 hw_capability_last 503}; 504 505struct wil_back_rx { 506 struct list_head list; 507 /* request params, converted to CPU byte order - what we asked for */ 508 u8 cidxtid; 509 u8 dialog_token; 510 u16 ba_param_set; 511 u16 ba_timeout; 512 u16 ba_seq_ctrl; 513}; 514 515struct wil_back_tx { 516 struct list_head list; 517 /* request params, converted to CPU byte order - what we asked for */ 518 u8 ringid; 519 u8 agg_wsize; 520 u16 agg_timeout; 521}; 522 523struct wil_probe_client_req { 524 struct list_head list; 525 u64 cookie; 526 u8 cid; 527}; 528 529struct wil6210_priv { 530 struct pci_dev *pdev; 531 int n_msi; 532 struct wireless_dev *wdev; 533 void __iomem *csr; 534 DECLARE_BITMAP(status, wil_status_last); 535 u32 fw_version; 536 u32 hw_version; 537 const char *hw_name; 538 DECLARE_BITMAP(hw_capabilities, hw_capability_last); 539 u8 n_mids; /* number of additional MIDs as reported by FW */ 540 u32 recovery_count; /* num of FW recovery attempts in a short time */ 541 u32 recovery_state; /* FW recovery state machine */ 542 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 543 wait_queue_head_t wq; /* for all wait_event() use */ 544 /* profile */ 545 u32 monitor_flags; 546 u32 privacy; /* secure connection? */ 547 int sinfo_gen; 548 u32 ap_isolate; /* no intra-BSS communication */ 549 /* interrupt moderation */ 550 u32 tx_max_burst_duration; 551 u32 tx_interframe_timeout; 552 u32 rx_max_burst_duration; 553 u32 rx_interframe_timeout; 554 /* cached ISR registers */ 555 u32 isr_misc; 556 /* mailbox related */ 557 struct mutex wmi_mutex; 558 struct wil6210_mbox_ctl mbox_ctl; 559 struct completion wmi_ready; 560 struct completion wmi_call; 561 u16 wmi_seq; 562 u16 reply_id; /**< wait for this WMI event */ 563 void *reply_buf; 564 u16 reply_size; 565 struct workqueue_struct *wmi_wq; /* for deferred calls */ 566 struct work_struct wmi_event_worker; 567 struct workqueue_struct *wq_service; 568 struct work_struct connect_worker; 569 struct work_struct disconnect_worker; 570 struct work_struct fw_error_worker; /* for FW error recovery */ 571 struct timer_list connect_timer; 572 struct timer_list scan_timer; /* detect scan timeout */ 573 int pending_connect_cid; 574 struct list_head pending_wmi_ev; 575 /* 576 * protect pending_wmi_ev 577 * - fill in IRQ from wil6210_irq_misc, 578 * - consumed in thread by wmi_event_worker 579 */ 580 spinlock_t wmi_ev_lock; 581 struct napi_struct napi_rx; 582 struct napi_struct napi_tx; 583 /* BACK */ 584 struct list_head back_rx_pending; 585 struct mutex back_rx_mutex; /* protect @back_rx_pending */ 586 struct work_struct back_rx_worker; 587 struct list_head back_tx_pending; 588 struct mutex back_tx_mutex; /* protect @back_tx_pending */ 589 struct work_struct back_tx_worker; 590 /* keep alive */ 591 struct list_head probe_client_pending; 592 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 593 struct work_struct probe_client_worker; 594 /* DMA related */ 595 struct vring vring_rx; 596 struct vring vring_tx[WIL6210_MAX_TX_RINGS]; 597 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS]; 598 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 599 struct wil_sta_info sta[WIL6210_MAX_CID]; 600 int bcast_vring; 601 /* scan */ 602 struct cfg80211_scan_request *scan_request; 603 604 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 605 /* statistics */ 606 atomic_t isr_count_rx, isr_count_tx; 607 /* debugfs */ 608 struct dentry *debug; 609 struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)]; 610 611 void *platform_handle; 612 struct wil_platform_ops platform_ops; 613}; 614 615#define wil_to_wiphy(i) (i->wdev->wiphy) 616#define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 617#define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 618#define wil_to_wdev(i) (i->wdev) 619#define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 620#define wil_to_ndev(i) (wil_to_wdev(i)->netdev) 621#define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 622 623__printf(2, 3) 624void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 625__printf(2, 3) 626void wil_err(struct wil6210_priv *wil, const char *fmt, ...); 627__printf(2, 3) 628void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 629__printf(2, 3) 630void wil_info(struct wil6210_priv *wil, const char *fmt, ...); 631#define wil_dbg(wil, fmt, arg...) do { \ 632 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \ 633 wil_dbg_trace(wil, fmt, ##arg); \ 634} while (0) 635 636#define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 637#define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 638#define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 639#define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 640 641#if defined(CONFIG_DYNAMIC_DEBUG) 642#define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 643 groupsize, buf, len, ascii) \ 644 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 645 prefix_type, rowsize, \ 646 groupsize, buf, len, ascii) 647 648#define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 649 groupsize, buf, len, ascii) \ 650 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 651 prefix_type, rowsize, \ 652 groupsize, buf, len, ascii) 653#else /* defined(CONFIG_DYNAMIC_DEBUG) */ 654static inline 655void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 656 int groupsize, const void *buf, size_t len, bool ascii) 657{ 658} 659 660static inline 661void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 662 int groupsize, const void *buf, size_t len, bool ascii) 663{ 664} 665#endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 666 667void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 668 size_t count); 669void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 670 size_t count); 671 672void *wil_if_alloc(struct device *dev, void __iomem *csr); 673void wil_if_free(struct wil6210_priv *wil); 674int wil_if_add(struct wil6210_priv *wil); 675void wil_if_remove(struct wil6210_priv *wil); 676int wil_priv_init(struct wil6210_priv *wil); 677void wil_priv_deinit(struct wil6210_priv *wil); 678int wil_reset(struct wil6210_priv *wil, bool no_fw); 679void wil_fw_error_recovery(struct wil6210_priv *wil); 680void wil_set_recovery_state(struct wil6210_priv *wil, int state); 681int wil_up(struct wil6210_priv *wil); 682int __wil_up(struct wil6210_priv *wil); 683int wil_down(struct wil6210_priv *wil); 684int __wil_down(struct wil6210_priv *wil); 685void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 686int wil_find_cid(struct wil6210_priv *wil, const u8 *mac); 687void wil_set_ethtoolops(struct net_device *ndev); 688 689void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 690void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 691int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 692 struct wil6210_mbox_hdr *hdr); 693int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len); 694void wmi_recv_cmd(struct wil6210_priv *wil); 695int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len, 696 u16 reply_id, void *reply, u8 reply_size, int to_msec); 697void wmi_event_worker(struct work_struct *work); 698void wmi_event_flush(struct wil6210_priv *wil); 699int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid); 700int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid); 701int wmi_set_channel(struct wil6210_priv *wil, int channel); 702int wmi_get_channel(struct wil6210_priv *wil, int *channel); 703int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index, 704 const void *mac_addr); 705int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index, 706 const void *mac_addr, int key_len, const void *key); 707int wmi_echo(struct wil6210_priv *wil); 708int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie); 709int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring); 710int wmi_p2p_cfg(struct wil6210_priv *wil, int channel); 711int wmi_rxon(struct wil6210_priv *wil, bool on); 712int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 713int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason); 714int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout); 715int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason); 716int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason); 717int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token, 718 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 719int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid, 720 u8 dialog_token, __le16 ba_param_set, 721 __le16 ba_timeout, __le16 ba_seq_ctrl); 722void wil_back_rx_worker(struct work_struct *work); 723void wil_back_rx_flush(struct wil6210_priv *wil); 724int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 725void wil_back_tx_worker(struct work_struct *work); 726void wil_back_tx_flush(struct wil6210_priv *wil); 727 728void wil6210_clear_irq(struct wil6210_priv *wil); 729int wil6210_init_irq(struct wil6210_priv *wil, int irq); 730void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 731void wil_mask_irq(struct wil6210_priv *wil); 732void wil_unmask_irq(struct wil6210_priv *wil); 733void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 734void wil_disable_irq(struct wil6210_priv *wil); 735void wil_enable_irq(struct wil6210_priv *wil); 736int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 737 struct cfg80211_mgmt_tx_params *params, 738 u64 *cookie); 739 740int wil6210_debugfs_init(struct wil6210_priv *wil); 741void wil6210_debugfs_remove(struct wil6210_priv *wil); 742int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid, 743 struct station_info *sinfo); 744 745struct wireless_dev *wil_cfg80211_init(struct device *dev); 746void wil_wdev_free(struct wil6210_priv *wil); 747 748int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 749int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan); 750int wmi_pcp_stop(struct wil6210_priv *wil); 751void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, 752 u16 reason_code, bool from_event); 753void wil_probe_client_flush(struct wil6210_priv *wil); 754void wil_probe_client_worker(struct work_struct *work); 755 756int wil_rx_init(struct wil6210_priv *wil, u16 size); 757void wil_rx_fini(struct wil6210_priv *wil); 758 759/* TX API */ 760int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size, 761 int cid, int tid); 762void wil_vring_fini_tx(struct wil6210_priv *wil, int id); 763int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size); 764int wil_bcast_init(struct wil6210_priv *wil); 765void wil_bcast_fini(struct wil6210_priv *wil); 766 767netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 768int wil_tx_complete(struct wil6210_priv *wil, int ringid); 769void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 770 771/* RX API */ 772void wil_rx_handle(struct wil6210_priv *wil, int *quota); 773void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 774 775int wil_iftype_nl2wmi(enum nl80211_iftype type); 776 777int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd); 778int wil_request_firmware(struct wil6210_priv *wil, const char *name); 779 780#endif /* __WIL6210_H__ */ 781