1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved. 4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5 * 6 * Portions of this file are derived from the ipw3945 project, as well 7 * as portions of the ieee80211 subsystem header files. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 21 * 22 * The full GNU General Public License is included in this distribution in the 23 * file called LICENSE. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <ilw@linux.intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 *****************************************************************************/ 30#ifndef __iwl_trans_int_pcie_h__ 31#define __iwl_trans_int_pcie_h__ 32 33#include <linux/spinlock.h> 34#include <linux/interrupt.h> 35#include <linux/skbuff.h> 36#include <linux/wait.h> 37#include <linux/pci.h> 38#include <linux/timer.h> 39 40#include "iwl-fh.h" 41#include "iwl-csr.h" 42#include "iwl-trans.h" 43#include "iwl-debug.h" 44#include "iwl-io.h" 45#include "iwl-op-mode.h" 46 47struct iwl_host_cmd; 48 49/*This file includes the declaration that are internal to the 50 * trans_pcie layer */ 51 52struct iwl_rx_mem_buffer { 53 dma_addr_t page_dma; 54 struct page *page; 55 struct list_head list; 56}; 57 58/** 59 * struct isr_statistics - interrupt statistics 60 * 61 */ 62struct isr_statistics { 63 u32 hw; 64 u32 sw; 65 u32 err_code; 66 u32 sch; 67 u32 alive; 68 u32 rfkill; 69 u32 ctkill; 70 u32 wakeup; 71 u32 rx; 72 u32 tx; 73 u32 unhandled; 74}; 75 76/** 77 * struct iwl_rxq - Rx queue 78 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) 79 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 80 * @pool: 81 * @queue: 82 * @read: Shared index to newest available Rx buffer 83 * @write: Shared index to oldest written Rx packet 84 * @free_count: Number of pre-allocated buffers in rx_free 85 * @write_actual: 86 * @rx_free: list of free SKBs for use 87 * @rx_used: List of Rx buffers with no SKB 88 * @need_update: flag to indicate we need to update read/write index 89 * @rb_stts: driver's pointer to receive buffer status 90 * @rb_stts_dma: bus address of receive buffer status 91 * @lock: 92 * 93 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 94 */ 95struct iwl_rxq { 96 __le32 *bd; 97 dma_addr_t bd_dma; 98 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 99 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 100 u32 read; 101 u32 write; 102 u32 free_count; 103 u32 write_actual; 104 struct list_head rx_free; 105 struct list_head rx_used; 106 bool need_update; 107 struct iwl_rb_status *rb_stts; 108 dma_addr_t rb_stts_dma; 109 spinlock_t lock; 110}; 111 112struct iwl_dma_ptr { 113 dma_addr_t dma; 114 void *addr; 115 size_t size; 116}; 117 118/** 119 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 120 * @index -- current index 121 */ 122static inline int iwl_queue_inc_wrap(int index) 123{ 124 return ++index & (TFD_QUEUE_SIZE_MAX - 1); 125} 126 127/** 128 * iwl_queue_dec_wrap - decrement queue index, wrap back to end 129 * @index -- current index 130 */ 131static inline int iwl_queue_dec_wrap(int index) 132{ 133 return --index & (TFD_QUEUE_SIZE_MAX - 1); 134} 135 136struct iwl_cmd_meta { 137 /* only for SYNC commands, iff the reply skb is wanted */ 138 struct iwl_host_cmd *source; 139 u32 flags; 140}; 141 142/* 143 * Generic queue structure 144 * 145 * Contains common data for Rx and Tx queues. 146 * 147 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 148 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 149 * there might be HW changes in the future). For the normal TX 150 * queues, n_window, which is the size of the software queue data 151 * is also 256; however, for the command queue, n_window is only 152 * 32 since we don't need so many commands pending. Since the HW 153 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result, 154 * the software buffers (in the variables @meta, @txb in struct 155 * iwl_txq) only have 32 entries, while the HW buffers (@tfds in 156 * the same struct) have 256. 157 * This means that we end up with the following: 158 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 159 * SW entries: | 0 | ... | 31 | 160 * where N is a number between 0 and 7. This means that the SW 161 * data is a window overlayed over the HW queue. 162 */ 163struct iwl_queue { 164 int write_ptr; /* 1-st empty entry (index) host_w*/ 165 int read_ptr; /* last used entry (index) host_r*/ 166 /* use for monitoring and recovering the stuck queue */ 167 dma_addr_t dma_addr; /* physical addr for BD's */ 168 int n_window; /* safe queue window */ 169 u32 id; 170 int low_mark; /* low watermark, resume queue if free 171 * space more than this */ 172 int high_mark; /* high watermark, stop queue if free 173 * space less than this */ 174}; 175 176#define TFD_TX_CMD_SLOTS 256 177#define TFD_CMD_SLOTS 32 178 179/* 180 * The FH will write back to the first TB only, so we need 181 * to copy some data into the buffer regardless of whether 182 * it should be mapped or not. This indicates how big the 183 * first TB must be to include the scratch buffer. Since 184 * the scratch is 4 bytes at offset 12, it's 16 now. If we 185 * make it bigger then allocations will be bigger and copy 186 * slower, so that's probably not useful. 187 */ 188#define IWL_HCMD_SCRATCHBUF_SIZE 16 189 190struct iwl_pcie_txq_entry { 191 struct iwl_device_cmd *cmd; 192 struct sk_buff *skb; 193 /* buffer to free after command completes */ 194 const void *free_buf; 195 struct iwl_cmd_meta meta; 196}; 197 198struct iwl_pcie_txq_scratch_buf { 199 struct iwl_cmd_header hdr; 200 u8 buf[8]; 201 __le32 scratch; 202}; 203 204/** 205 * struct iwl_txq - Tx Queue for DMA 206 * @q: generic Rx/Tx queue descriptor 207 * @tfds: transmit frame descriptors (DMA memory) 208 * @scratchbufs: start of command headers, including scratch buffers, for 209 * the writeback -- this is DMA memory and an array holding one buffer 210 * for each command on the queue 211 * @scratchbufs_dma: DMA address for the scratchbufs start 212 * @entries: transmit entries (driver state) 213 * @lock: queue lock 214 * @stuck_timer: timer that fires if queue gets stuck 215 * @trans_pcie: pointer back to transport (for timer) 216 * @need_update: indicates need to update read/write index 217 * @active: stores if queue is active 218 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 219 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 220 * @frozen: tx stuck queue timer is frozen 221 * @frozen_expiry_remainder: remember how long until the timer fires 222 * 223 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 224 * descriptors) and required locking structures. 225 */ 226struct iwl_txq { 227 struct iwl_queue q; 228 struct iwl_tfd *tfds; 229 struct iwl_pcie_txq_scratch_buf *scratchbufs; 230 dma_addr_t scratchbufs_dma; 231 struct iwl_pcie_txq_entry *entries; 232 spinlock_t lock; 233 unsigned long frozen_expiry_remainder; 234 struct timer_list stuck_timer; 235 struct iwl_trans_pcie *trans_pcie; 236 bool need_update; 237 bool frozen; 238 u8 active; 239 bool ampdu; 240 unsigned long wd_timeout; 241}; 242 243static inline dma_addr_t 244iwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx) 245{ 246 return txq->scratchbufs_dma + 247 sizeof(struct iwl_pcie_txq_scratch_buf) * idx; 248} 249 250/** 251 * struct iwl_trans_pcie - PCIe transport specific data 252 * @rxq: all the RX queue data 253 * @rx_replenish: work that will be called when buffers need to be allocated 254 * @drv - pointer to iwl_drv 255 * @trans: pointer to the generic transport area 256 * @scd_base_addr: scheduler sram base address in SRAM 257 * @scd_bc_tbls: pointer to the byte count table of the scheduler 258 * @kw: keep warm address 259 * @pci_dev: basic pci-network driver stuff 260 * @hw_base: pci hardware address support 261 * @ucode_write_complete: indicates that the ucode has been copied. 262 * @ucode_write_waitq: wait queue for uCode load 263 * @cmd_queue - command queue number 264 * @rx_buf_size_8k: 8 kB RX buffer size 265 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 266 * @scd_set_active: should the transport configure the SCD for HCMD queue 267 * @rx_page_order: page order for receive buffer size 268 * @reg_lock: protect hw register access 269 * @cmd_in_flight: true when we have a host command in flight 270 * @fw_mon_phys: physical address of the buffer for the firmware monitor 271 * @fw_mon_page: points to the first page of the buffer for the firmware monitor 272 * @fw_mon_size: size of the buffer for the firmware monitor 273 */ 274struct iwl_trans_pcie { 275 struct iwl_rxq rxq; 276 struct work_struct rx_replenish; 277 struct iwl_trans *trans; 278 struct iwl_drv *drv; 279 280 struct net_device napi_dev; 281 struct napi_struct napi; 282 283 /* INT ICT Table */ 284 __le32 *ict_tbl; 285 dma_addr_t ict_tbl_dma; 286 int ict_index; 287 bool use_ict; 288 struct isr_statistics isr_stats; 289 290 spinlock_t irq_lock; 291 u32 inta_mask; 292 u32 scd_base_addr; 293 struct iwl_dma_ptr scd_bc_tbls; 294 struct iwl_dma_ptr kw; 295 296 struct iwl_txq *txq; 297 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 298 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 299 300 /* PCI bus related data */ 301 struct pci_dev *pci_dev; 302 void __iomem *hw_base; 303 304 bool ucode_write_complete; 305 wait_queue_head_t ucode_write_waitq; 306 wait_queue_head_t wait_command_queue; 307 308 u8 cmd_queue; 309 u8 cmd_fifo; 310 unsigned int cmd_q_wdg_timeout; 311 u8 n_no_reclaim_cmds; 312 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 313 314 bool rx_buf_size_8k; 315 bool bc_table_dword; 316 bool scd_set_active; 317 u32 rx_page_order; 318 319 const char *const *command_names; 320 321 /*protect hw register */ 322 spinlock_t reg_lock; 323 bool cmd_hold_nic_awake; 324 bool ref_cmd_in_flight; 325 326 /* protect ref counter */ 327 spinlock_t ref_lock; 328 u32 ref_count; 329 330 dma_addr_t fw_mon_phys; 331 struct page *fw_mon_page; 332 u32 fw_mon_size; 333}; 334 335#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ 336 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) 337 338static inline struct iwl_trans * 339iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 340{ 341 return container_of((void *)trans_pcie, struct iwl_trans, 342 trans_specific); 343} 344 345/* 346 * Convention: trans API functions: iwl_trans_pcie_XXX 347 * Other functions: iwl_pcie_XXX 348 */ 349struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 350 const struct pci_device_id *ent, 351 const struct iwl_cfg *cfg); 352void iwl_trans_pcie_free(struct iwl_trans *trans); 353 354/***************************************************** 355* RX 356******************************************************/ 357int iwl_pcie_rx_init(struct iwl_trans *trans); 358irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 359int iwl_pcie_rx_stop(struct iwl_trans *trans); 360void iwl_pcie_rx_free(struct iwl_trans *trans); 361 362/***************************************************** 363* ICT - interrupt handling 364******************************************************/ 365irqreturn_t iwl_pcie_isr(int irq, void *data); 366int iwl_pcie_alloc_ict(struct iwl_trans *trans); 367void iwl_pcie_free_ict(struct iwl_trans *trans); 368void iwl_pcie_reset_ict(struct iwl_trans *trans); 369void iwl_pcie_disable_ict(struct iwl_trans *trans); 370 371/***************************************************** 372* TX / HCMD 373******************************************************/ 374int iwl_pcie_tx_init(struct iwl_trans *trans); 375void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 376int iwl_pcie_tx_stop(struct iwl_trans *trans); 377void iwl_pcie_tx_free(struct iwl_trans *trans); 378void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 379 const struct iwl_trans_txq_scd_cfg *cfg, 380 unsigned int wdg_timeout); 381void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 382 bool configure_scd); 383int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 384 struct iwl_device_cmd *dev_cmd, int txq_id); 385void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 386int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 387void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 388 struct iwl_rx_cmd_buffer *rxb, int handler_status); 389void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 390 struct sk_buff_head *skbs); 391void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 392 393void iwl_trans_pcie_ref(struct iwl_trans *trans); 394void iwl_trans_pcie_unref(struct iwl_trans *trans); 395 396static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) 397{ 398 struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 399 400 return le16_to_cpu(tb->hi_n_len) >> 4; 401} 402 403/***************************************************** 404* Error handling 405******************************************************/ 406void iwl_pcie_dump_csr(struct iwl_trans *trans); 407 408/***************************************************** 409* Helpers 410******************************************************/ 411static inline void iwl_disable_interrupts(struct iwl_trans *trans) 412{ 413 clear_bit(STATUS_INT_ENABLED, &trans->status); 414 415 /* disable interrupts from uCode/NIC to host */ 416 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 417 418 /* acknowledge/clear/reset any interrupts still pending 419 * from uCode or flow handler (Rx/Tx DMA) */ 420 iwl_write32(trans, CSR_INT, 0xffffffff); 421 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 422 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 423} 424 425static inline void iwl_enable_interrupts(struct iwl_trans *trans) 426{ 427 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 428 429 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 430 set_bit(STATUS_INT_ENABLED, &trans->status); 431 trans_pcie->inta_mask = CSR_INI_SET_MASK; 432 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 433} 434 435static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 436{ 437 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 438 439 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 440 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 441 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 442} 443 444static inline void iwl_wake_queue(struct iwl_trans *trans, 445 struct iwl_txq *txq) 446{ 447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 448 449 if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { 450 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); 451 iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); 452 } 453} 454 455static inline void iwl_stop_queue(struct iwl_trans *trans, 456 struct iwl_txq *txq) 457{ 458 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 459 460 if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { 461 iwl_op_mode_queue_full(trans->op_mode, txq->q.id); 462 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); 463 } else 464 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 465 txq->q.id); 466} 467 468static inline bool iwl_queue_used(const struct iwl_queue *q, int i) 469{ 470 return q->write_ptr >= q->read_ptr ? 471 (i >= q->read_ptr && i < q->write_ptr) : 472 !(i < q->read_ptr && i >= q->write_ptr); 473} 474 475static inline u8 get_cmd_index(struct iwl_queue *q, u32 index) 476{ 477 return index & (q->n_window - 1); 478} 479 480static inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie, 481 u8 cmd) 482{ 483 if (!trans_pcie->command_names || !trans_pcie->command_names[cmd]) 484 return "UNKNOWN"; 485 return trans_pcie->command_names[cmd]; 486} 487 488static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 489{ 490 return !(iwl_read32(trans, CSR_GP_CNTRL) & 491 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 492} 493 494static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 495 u32 reg, u32 mask, u32 value) 496{ 497 u32 v; 498 499#ifdef CONFIG_IWLWIFI_DEBUG 500 WARN_ON_ONCE(value & ~mask); 501#endif 502 503 v = iwl_read32(trans, reg); 504 v &= ~mask; 505 v |= value; 506 iwl_write32(trans, reg, v); 507} 508 509static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 510 u32 reg, u32 mask) 511{ 512 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 513} 514 515static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 516 u32 reg, u32 mask) 517{ 518 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 519} 520 521void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 522 523#endif /* __iwl_trans_int_pcie_h__ */ 524