1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL92C_DEF_H__ 31#define __RTL92C_DEF_H__ 32 33#define PHY_RSSI_SLID_WIN_MAX 100 34#define PHY_LINKQUALITY_SLID_WIN_MAX 20 35#define PHY_BEACON_RSSI_SLID_WIN_MAX 10 36 37#define RX_SMOOTH_FACTOR 20 38 39#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 40#define HAL_PRIME_CHNL_OFFSET_LOWER 1 41#define HAL_PRIME_CHNL_OFFSET_UPPER 2 42 43#define RX_MPDU_QUEUE 0 44#define RX_CMD_QUEUE 1 45 46#define C2H_RX_CMD_HDR_LEN 8 47#define GET_C2H_CMD_CMD_LEN(__prxhdr) \ 48 LE_BITS_TO_4BYTE((__prxhdr), 0, 16) 49#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \ 50 LE_BITS_TO_4BYTE((__prxhdr), 16, 8) 51#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \ 52 LE_BITS_TO_4BYTE((__prxhdr), 24, 7) 53#define GET_C2H_CMD_CONTINUE(__prxhdr) \ 54 LE_BITS_TO_4BYTE((__prxhdr), 31, 1) 55#define GET_C2H_CMD_CONTENT(__prxhdr) \ 56 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN) 57 58#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \ 59 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8) 60#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \ 61 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8) 62#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \ 63 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16) 64#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \ 65 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5) 66#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \ 67 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1) 68#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \ 69 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5) 70#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \ 71 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1) 72#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \ 73 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4) 74#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \ 75 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12) 76#define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc) \ 77 SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32) 78 79#define CHIP_VER_B BIT(4) 80#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3) 81#define CHIP_BONDING_92C_1T2R 0x1 82#define RF_TYPE_1T2R BIT(1) 83#define CHIP_92C_BITMASK BIT(0) 84#define CHIP_UNKNOWN BIT(7) 85#define CHIP_92C_1T2R 0x03 86#define CHIP_92C 0x01 87#define CHIP_88C 0x00 88 89enum version_8192c { 90 VERSION_A_CHIP_92C = 0x01, 91 VERSION_A_CHIP_88C = 0x00, 92 VERSION_B_CHIP_92C = 0x11, 93 VERSION_B_CHIP_88C = 0x10, 94 VERSION_TEST_CHIP_88C = 0x00, 95 VERSION_TEST_CHIP_92C = 0x01, 96 VERSION_NORMAL_TSMC_CHIP_88C = 0x10, 97 VERSION_NORMAL_TSMC_CHIP_92C = 0x11, 98 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13, 99 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30, 100 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31, 101 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33, 102 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34, 103 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c, 104 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70, 105 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71, 106 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73, 107 VERSION_UNKNOWN = 0x88, 108}; 109 110enum rtl819x_loopback_e { 111 RTL819X_NO_LOOPBACK = 0, 112 RTL819X_MAC_LOOPBACK = 1, 113 RTL819X_DMA_LOOPBACK = 2, 114 RTL819X_CCK_LOOPBACK = 3, 115}; 116 117enum rf_optype { 118 RF_OP_BY_SW_3WIRE = 0, 119 RF_OP_BY_FW, 120 RF_OP_MAX 121}; 122 123enum rf_power_state { 124 RF_ON, 125 RF_OFF, 126 RF_SLEEP, 127 RF_SHUT_DOWN, 128}; 129 130enum power_save_mode { 131 POWER_SAVE_MODE_ACTIVE, 132 POWER_SAVE_MODE_SAVE, 133}; 134 135enum power_polocy_config { 136 POWERCFG_MAX_POWER_SAVINGS, 137 POWERCFG_GLOBAL_POWER_SAVINGS, 138 POWERCFG_LOCAL_POWER_SAVINGS, 139 POWERCFG_LENOVO, 140}; 141 142enum interface_select_pci { 143 INTF_SEL1_MINICARD = 0, 144 INTF_SEL0_PCIE = 1, 145 INTF_SEL2_RSV = 2, 146 INTF_SEL3_RSV = 3, 147}; 148 149enum hal_fw_c2h_cmd_id { 150 HAL_FW_C2H_CMD_Read_MACREG = 0, 151 HAL_FW_C2H_CMD_Read_BBREG = 1, 152 HAL_FW_C2H_CMD_Read_RFREG = 2, 153 HAL_FW_C2H_CMD_Read_EEPROM = 3, 154 HAL_FW_C2H_CMD_Read_EFUSE = 4, 155 HAL_FW_C2H_CMD_Read_CAM = 5, 156 HAL_FW_C2H_CMD_Get_BasicRate = 6, 157 HAL_FW_C2H_CMD_Get_DataRate = 7, 158 HAL_FW_C2H_CMD_Survey = 8, 159 HAL_FW_C2H_CMD_SurveyDone = 9, 160 HAL_FW_C2H_CMD_JoinBss = 10, 161 HAL_FW_C2H_CMD_AddSTA = 11, 162 HAL_FW_C2H_CMD_DelSTA = 12, 163 HAL_FW_C2H_CMD_AtimDone = 13, 164 HAL_FW_C2H_CMD_TX_Report = 14, 165 HAL_FW_C2H_CMD_CCX_Report = 15, 166 HAL_FW_C2H_CMD_DTM_Report = 16, 167 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17, 168 HAL_FW_C2H_CMD_C2HLBK = 18, 169 HAL_FW_C2H_CMD_C2HDBG = 19, 170 HAL_FW_C2H_CMD_C2HFEEDBACK = 20, 171 HAL_FW_C2H_CMD_MAX 172}; 173 174enum rtl_desc_qsel { 175 QSLT_BK = 0x2, 176 QSLT_BE = 0x0, 177 QSLT_VI = 0x5, 178 QSLT_VO = 0x7, 179 QSLT_BEACON = 0x10, 180 QSLT_HIGH = 0x11, 181 QSLT_MGNT = 0x12, 182 QSLT_CMD = 0x13, 183}; 184 185struct phy_sts_cck_8192s_t { 186 u8 adc_pwdb_X[4]; 187 u8 sq_rpt; 188 u8 cck_agc_rpt; 189}; 190 191struct h2c_cmd_8192c { 192 u8 element_id; 193 u32 cmd_len; 194 u8 *p_cmdbuffer; 195}; 196 197#endif 198