1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012  Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL92C_PHY_H__
27#define __RTL92C_PHY_H__
28
29#define MAX_PRECMD_CNT				16
30#define MAX_RFDEPENDCMD_CNT			16
31#define MAX_POSTCMD_CNT				16
32
33#define MAX_DOZE_WAITING_TIMES_9x		64
34
35#define RT_CANNOT_IO(hw)			false
36#define HIGHPOWER_RADIOA_ARRAYLEN		22
37
38#define IQK_ADDA_REG_NUM			16
39#define MAX_TOLERANCE				5
40#define	IQK_DELAY_TIME				1
41
42#define	APK_BB_REG_NUM				5
43#define	APK_AFE_REG_NUM				16
44#define	APK_CURVE_REG_NUM			4
45#define	PATH_NUM				2
46
47#define LOOP_LIMIT				5
48#define MAX_STALL_TIME				50
49#define ANTENNADIVERSITYVALUE			0x80
50#define MAX_TXPWR_IDX_NMODE_92S			63
51#define Reset_Cnt_Limit				3
52
53#define IQK_ADDA_REG_NUM			16
54#define IQK_MAC_REG_NUM				4
55
56#define IQK_DELAY_TIME				1
57
58#define RF6052_MAX_PATH				2
59
60#define CT_OFFSET_MAC_ADDR			0X16
61
62#define CT_OFFSET_CCK_TX_PWR_IDX		0x5A
63#define CT_OFFSET_HT401S_TX_PWR_IDX		0x60
64#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF	0x66
65#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF		0x69
66#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF		0x6C
67
68#define CT_OFFSET_HT40_MAX_PWR_OFFSET		0x6F
69#define CT_OFFSET_HT20_MAX_PWR_OFFSET		0x72
70
71#define CT_OFFSET_CHANNEL_PLAH			0x75
72#define CT_OFFSET_THERMAL_METER			0x78
73#define CT_OFFSET_RF_OPTION			0x79
74#define CT_OFFSET_VERSION			0x7E
75#define CT_OFFSET_CUSTOMER_ID			0x7F
76
77#define RTL92C_MAX_PATH_NUM			2
78
79enum hw90_block_e {
80	HW90_BLOCK_MAC = 0,
81	HW90_BLOCK_PHY0 = 1,
82	HW90_BLOCK_PHY1 = 2,
83	HW90_BLOCK_RF = 3,
84	HW90_BLOCK_MAXIMUM = 4,
85};
86
87enum baseband_config_type {
88	BASEBAND_CONFIG_PHY_REG = 0,
89	BASEBAND_CONFIG_AGC_TAB = 1,
90};
91
92enum ra_offset_area {
93	RA_OFFSET_LEGACY_OFDM1,
94	RA_OFFSET_LEGACY_OFDM2,
95	RA_OFFSET_HT_OFDM1,
96	RA_OFFSET_HT_OFDM2,
97	RA_OFFSET_HT_OFDM3,
98	RA_OFFSET_HT_OFDM4,
99	RA_OFFSET_HT_CCK,
100};
101
102enum antenna_path {
103	ANTENNA_NONE,
104	ANTENNA_D,
105	ANTENNA_C,
106	ANTENNA_CD,
107	ANTENNA_B,
108	ANTENNA_BD,
109	ANTENNA_BC,
110	ANTENNA_BCD,
111	ANTENNA_A,
112	ANTENNA_AD,
113	ANTENNA_AC,
114	ANTENNA_ACD,
115	ANTENNA_AB,
116	ANTENNA_ABD,
117	ANTENNA_ABC,
118	ANTENNA_ABCD
119};
120
121struct r_antenna_select_ofdm {
122	u32 r_tx_antenna:4;
123	u32 r_ant_l:4;
124	u32 r_ant_non_ht:4;
125	u32 r_ant_ht1:4;
126	u32 r_ant_ht2:4;
127	u32 r_ant_ht_s1:4;
128	u32 r_ant_non_ht_s1:4;
129	u32 ofdm_txsc:2;
130	u32 reserved:2;
131};
132
133struct r_antenna_select_cck {
134	u8 r_cckrx_enable_2:2;
135	u8 r_cckrx_enable:2;
136	u8 r_ccktx_enable:4;
137};
138
139struct efuse_contents {
140	u8 mac_addr[ETH_ALEN];
141	u8 cck_tx_power_idx[6];
142	u8 ht40_1s_tx_power_idx[6];
143	u8 ht40_2s_tx_power_idx_diff[3];
144	u8 ht20_tx_power_idx_diff[3];
145	u8 ofdm_tx_power_idx_diff[3];
146	u8 ht40_max_power_offset[3];
147	u8 ht20_max_power_offset[3];
148	u8 channel_plan;
149	u8 thermal_meter;
150	u8 rf_option[5];
151	u8 version;
152	u8 oem_id;
153	u8 regulatory;
154};
155
156struct tx_power_struct {
157	u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
158	u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
159	u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
160	u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
161	u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
162	u8 legacy_ht_txpowerdiff;
163	u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
164	u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
165	u8 pwrgroup_cnt;
166	u32 mcs_original_offset[4][16];
167};
168
169u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
170			      enum radio_path rfpath, u32 regaddr,
171			      u32 bitmask);
172void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
173			     enum radio_path rfpath, u32 regaddr,
174			     u32 bitmask, u32 data);
175bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw);
176bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw);
177bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw);
178bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
179					  enum radio_path rfpath);
180void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
181void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw,
182				    long *powerlevel);
183void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
184bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw,
185				     long power_indbm);
186void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw,
187					u8 operation);
188void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
189void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
190			      enum nl80211_channel_type ch_type);
191void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
192u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw);
193void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
194void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw);
195void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
196bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
197					    enum radio_path rfpath);
198bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
199bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
200				     enum rf_pwrstate rfpwr_state);
201
202#endif
203