1/*
2 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
3 *
4 * SPEAr13xx PCIe Glue Layer Source Code
5 *
6 * Copyright (C) 2010-2014 ST Microelectronics
7 * Pratyush Anand <pratyush.anand@st.com>
8 * Mohit Kumar <mohit.kumar@st.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/pci.h>
22#include <linux/phy/phy.h>
23#include <linux/platform_device.h>
24#include <linux/resource.h>
25
26#include "pcie-designware.h"
27
28struct spear13xx_pcie {
29	void __iomem		*app_base;
30	struct phy		*phy;
31	struct clk		*clk;
32	struct pcie_port	pp;
33	bool			is_gen1;
34};
35
36struct pcie_app_reg {
37	u32	app_ctrl_0;		/* cr0 */
38	u32	app_ctrl_1;		/* cr1 */
39	u32	app_status_0;		/* cr2 */
40	u32	app_status_1;		/* cr3 */
41	u32	msg_status;		/* cr4 */
42	u32	msg_payload;		/* cr5 */
43	u32	int_sts;		/* cr6 */
44	u32	int_clr;		/* cr7 */
45	u32	int_mask;		/* cr8 */
46	u32	mst_bmisc;		/* cr9 */
47	u32	phy_ctrl;		/* cr10 */
48	u32	phy_status;		/* cr11 */
49	u32	cxpl_debug_info_0;	/* cr12 */
50	u32	cxpl_debug_info_1;	/* cr13 */
51	u32	ven_msg_ctrl_0;		/* cr14 */
52	u32	ven_msg_ctrl_1;		/* cr15 */
53	u32	ven_msg_data_0;		/* cr16 */
54	u32	ven_msg_data_1;		/* cr17 */
55	u32	ven_msi_0;		/* cr18 */
56	u32	ven_msi_1;		/* cr19 */
57	u32	mst_rmisc;		/* cr20 */
58};
59
60/* CR0 ID */
61#define RX_LANE_FLIP_EN_ID			0
62#define TX_LANE_FLIP_EN_ID			1
63#define SYS_AUX_PWR_DET_ID			2
64#define APP_LTSSM_ENABLE_ID			3
65#define SYS_ATTEN_BUTTON_PRESSED_ID		4
66#define SYS_MRL_SENSOR_STATE_ID			5
67#define SYS_PWR_FAULT_DET_ID			6
68#define SYS_MRL_SENSOR_CHGED_ID			7
69#define SYS_PRE_DET_CHGED_ID			8
70#define SYS_CMD_CPLED_INT_ID			9
71#define APP_INIT_RST_0_ID			11
72#define APP_REQ_ENTR_L1_ID			12
73#define APP_READY_ENTR_L23_ID			13
74#define APP_REQ_EXIT_L1_ID			14
75#define DEVICE_TYPE_EP				(0 << 25)
76#define DEVICE_TYPE_LEP				(1 << 25)
77#define DEVICE_TYPE_RC				(4 << 25)
78#define SYS_INT_ID				29
79#define MISCTRL_EN_ID				30
80#define REG_TRANSLATION_ENABLE			31
81
82/* CR1 ID */
83#define APPS_PM_XMT_TURNOFF_ID			2
84#define APPS_PM_XMT_PME_ID			5
85
86/* CR3 ID */
87#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
88#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
89#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
90#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
91#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
92#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
93#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
94#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
95#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
96#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
97#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
98#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
99#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
100#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
101#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
102#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
103#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
104#define XMLH_LTSSM_STATE_L0			0x11
105#define XMLH_LTSSM_STATE_L0S			0x12
106#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
107#define XMLH_LTSSM_STATE_L1_IDLE		0x14
108#define XMLH_LTSSM_STATE_L2_IDLE		0x15
109#define XMLH_LTSSM_STATE_L2_WAKE		0x16
110#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
111#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
112#define XMLH_LTSSM_STATE_DISABLED		0x19
113#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
114#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
115#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
116#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
117#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
118#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
119#define XMLH_LTSSM_STATE_MASK			0x3F
120#define XMLH_LINK_UP				(1 << 6)
121
122/* CR4 ID */
123#define CFG_MSI_EN_ID				18
124
125/* CR6 */
126#define INTA_CTRL_INT				(1 << 7)
127#define INTB_CTRL_INT				(1 << 8)
128#define INTC_CTRL_INT				(1 << 9)
129#define INTD_CTRL_INT				(1 << 10)
130#define MSI_CTRL_INT				(1 << 26)
131
132/* CR19 ID */
133#define VEN_MSI_REQ_ID				11
134#define VEN_MSI_FUN_NUM_ID			8
135#define VEN_MSI_TC_ID				5
136#define VEN_MSI_VECTOR_ID			0
137#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
138#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
139#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
140#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)
141
142#define EXP_CAP_ID_OFFSET			0x70
143
144#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)
145
146static int spear13xx_pcie_establish_link(struct pcie_port *pp)
147{
148	u32 val;
149	int count = 0;
150	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
151	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
152	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
153
154	if (dw_pcie_link_up(pp)) {
155		dev_err(pp->dev, "link already up\n");
156		return 0;
157	}
158
159	dw_pcie_setup_rc(pp);
160
161	/*
162	 * this controller support only 128 bytes read size, however its
163	 * default value in capability register is 512 bytes. So force
164	 * it to 128 here.
165	 */
166	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
167	val &= ~PCI_EXP_DEVCTL_READRQ;
168	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
169
170	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
171	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
172
173	/*
174	 * if is_gen1 is set then handle it, so that some buggy card
175	 * also works
176	 */
177	if (spear13xx_pcie->is_gen1) {
178		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
179				 &val);
180		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
181			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
182			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
183			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
184					  PCI_EXP_LNKCAP, 4, val);
185		}
186
187		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
188				 &val);
189		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
190			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
191			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
192			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
193					  PCI_EXP_LNKCTL2, 4, val);
194		}
195	}
196
197	/* enable ltssm */
198	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
199			| (1 << APP_LTSSM_ENABLE_ID)
200			| ((u32)1 << REG_TRANSLATION_ENABLE),
201			&app_reg->app_ctrl_0);
202
203	/* check if the link is up or not */
204	while (!dw_pcie_link_up(pp)) {
205		mdelay(100);
206		count++;
207		if (count == 10) {
208			dev_err(pp->dev, "link Fail\n");
209			return -EINVAL;
210		}
211	}
212	dev_info(pp->dev, "link up\n");
213
214	return 0;
215}
216
217static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
218{
219	struct pcie_port *pp = arg;
220	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
221	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
222	unsigned int status;
223
224	status = readl(&app_reg->int_sts);
225
226	if (status & MSI_CTRL_INT) {
227		if (!IS_ENABLED(CONFIG_PCI_MSI))
228			BUG();
229		dw_handle_msi_irq(pp);
230	}
231
232	writel(status, &app_reg->int_clr);
233
234	return IRQ_HANDLED;
235}
236
237static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
238{
239	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
240	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
241
242	/* Enable MSI interrupt */
243	if (IS_ENABLED(CONFIG_PCI_MSI)) {
244		dw_pcie_msi_init(pp);
245		writel(readl(&app_reg->int_mask) |
246				MSI_CTRL_INT, &app_reg->int_mask);
247	}
248}
249
250static int spear13xx_pcie_link_up(struct pcie_port *pp)
251{
252	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
253	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
254
255	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
256		return 1;
257
258	return 0;
259}
260
261static void spear13xx_pcie_host_init(struct pcie_port *pp)
262{
263	spear13xx_pcie_establish_link(pp);
264	spear13xx_pcie_enable_interrupts(pp);
265}
266
267static struct pcie_host_ops spear13xx_pcie_host_ops = {
268	.link_up = spear13xx_pcie_link_up,
269	.host_init = spear13xx_pcie_host_init,
270};
271
272static int spear13xx_add_pcie_port(struct pcie_port *pp,
273					 struct platform_device *pdev)
274{
275	struct device *dev = &pdev->dev;
276	int ret;
277
278	pp->irq = platform_get_irq(pdev, 0);
279	if (!pp->irq) {
280		dev_err(dev, "failed to get irq\n");
281		return -ENODEV;
282	}
283	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
284			       IRQF_SHARED | IRQF_NO_THREAD,
285			       "spear1340-pcie", pp);
286	if (ret) {
287		dev_err(dev, "failed to request irq %d\n", pp->irq);
288		return ret;
289	}
290
291	pp->root_bus_nr = -1;
292	pp->ops = &spear13xx_pcie_host_ops;
293
294	ret = dw_pcie_host_init(pp);
295	if (ret) {
296		dev_err(dev, "failed to initialize host\n");
297		return ret;
298	}
299
300	return 0;
301}
302
303static int spear13xx_pcie_probe(struct platform_device *pdev)
304{
305	struct spear13xx_pcie *spear13xx_pcie;
306	struct pcie_port *pp;
307	struct device *dev = &pdev->dev;
308	struct device_node *np = pdev->dev.of_node;
309	struct resource *dbi_base;
310	int ret;
311
312	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
313	if (!spear13xx_pcie)
314		return -ENOMEM;
315
316	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
317	if (IS_ERR(spear13xx_pcie->phy)) {
318		ret = PTR_ERR(spear13xx_pcie->phy);
319		if (ret == -EPROBE_DEFER)
320			dev_info(dev, "probe deferred\n");
321		else
322			dev_err(dev, "couldn't get pcie-phy\n");
323		return ret;
324	}
325
326	phy_init(spear13xx_pcie->phy);
327
328	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
329	if (IS_ERR(spear13xx_pcie->clk)) {
330		dev_err(dev, "couldn't get clk for pcie\n");
331		return PTR_ERR(spear13xx_pcie->clk);
332	}
333	ret = clk_prepare_enable(spear13xx_pcie->clk);
334	if (ret) {
335		dev_err(dev, "couldn't enable clk for pcie\n");
336		return ret;
337	}
338
339	pp = &spear13xx_pcie->pp;
340
341	pp->dev = dev;
342
343	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
344	pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
345	if (IS_ERR(pp->dbi_base)) {
346		dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
347		ret = PTR_ERR(pp->dbi_base);
348		goto fail_clk;
349	}
350	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
351
352	if (of_property_read_bool(np, "st,pcie-is-gen1"))
353		spear13xx_pcie->is_gen1 = true;
354
355	ret = spear13xx_add_pcie_port(pp, pdev);
356	if (ret < 0)
357		goto fail_clk;
358
359	platform_set_drvdata(pdev, spear13xx_pcie);
360	return 0;
361
362fail_clk:
363	clk_disable_unprepare(spear13xx_pcie->clk);
364
365	return ret;
366}
367
368static const struct of_device_id spear13xx_pcie_of_match[] = {
369	{ .compatible = "st,spear1340-pcie", },
370	{},
371};
372MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
373
374static struct platform_driver spear13xx_pcie_driver = {
375	.probe		= spear13xx_pcie_probe,
376	.driver = {
377		.name	= "spear-pcie",
378		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
379	},
380};
381
382/* SPEAr13xx PCIe driver does not allow module unload */
383
384static int __init spear13xx_pcie_init(void)
385{
386	return platform_driver_register(&spear13xx_pcie_driver);
387}
388module_init(spear13xx_pcie_init);
389
390MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
391MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
392MODULE_LICENSE("GPL v2");
393