1/* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30#include <linux/kernel.h> 31#include <linux/module.h> 32#include <linux/types.h> 33#include <linux/signal.h> 34#include <linux/jiffies.h> 35#include <linux/timer.h> 36#include <linux/pci.h> 37#include <linux/interrupt.h> 38#include <linux/time.h> 39#include <linux/slab.h> 40 41#include "../pci.h" 42#include "pciehp.h" 43 44static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 45{ 46 return ctrl->pcie->port; 47} 48 49static irqreturn_t pcie_isr(int irq, void *dev_id); 50static void start_int_poll_timer(struct controller *ctrl, int sec); 51 52/* This is the interrupt polling timeout function. */ 53static void int_poll_timeout(unsigned long data) 54{ 55 struct controller *ctrl = (struct controller *)data; 56 57 /* Poll for interrupt events. regs == NULL => polling */ 58 pcie_isr(0, ctrl); 59 60 init_timer(&ctrl->poll_timer); 61 if (!pciehp_poll_time) 62 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 63 64 start_int_poll_timer(ctrl, pciehp_poll_time); 65} 66 67/* This function starts the interrupt polling timer. */ 68static void start_int_poll_timer(struct controller *ctrl, int sec) 69{ 70 /* Clamp to sane value */ 71 if ((sec <= 0) || (sec > 60)) 72 sec = 2; 73 74 ctrl->poll_timer.function = &int_poll_timeout; 75 ctrl->poll_timer.data = (unsigned long)ctrl; 76 ctrl->poll_timer.expires = jiffies + sec * HZ; 77 add_timer(&ctrl->poll_timer); 78} 79 80static inline int pciehp_request_irq(struct controller *ctrl) 81{ 82 int retval, irq = ctrl->pcie->irq; 83 84 /* Install interrupt polling timer. Start with 10 sec delay */ 85 if (pciehp_poll_mode) { 86 init_timer(&ctrl->poll_timer); 87 start_int_poll_timer(ctrl, 10); 88 return 0; 89 } 90 91 /* Installs the interrupt handler */ 92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 93 if (retval) 94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 95 irq); 96 return retval; 97} 98 99static inline void pciehp_free_irq(struct controller *ctrl) 100{ 101 if (pciehp_poll_mode) 102 del_timer_sync(&ctrl->poll_timer); 103 else 104 free_irq(ctrl->pcie->irq, ctrl); 105} 106 107static int pcie_poll_cmd(struct controller *ctrl, int timeout) 108{ 109 struct pci_dev *pdev = ctrl_dev(ctrl); 110 u16 slot_status; 111 112 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 113 if (slot_status & PCI_EXP_SLTSTA_CC) { 114 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 115 PCI_EXP_SLTSTA_CC); 116 return 1; 117 } 118 while (timeout > 0) { 119 msleep(10); 120 timeout -= 10; 121 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 122 if (slot_status & PCI_EXP_SLTSTA_CC) { 123 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 124 PCI_EXP_SLTSTA_CC); 125 return 1; 126 } 127 } 128 return 0; /* timeout */ 129} 130 131static void pcie_wait_cmd(struct controller *ctrl) 132{ 133 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 134 unsigned long duration = msecs_to_jiffies(msecs); 135 unsigned long cmd_timeout = ctrl->cmd_started + duration; 136 unsigned long now, timeout; 137 int rc; 138 139 /* 140 * If the controller does not generate notifications for command 141 * completions, we never need to wait between writes. 142 */ 143 if (NO_CMD_CMPL(ctrl)) 144 return; 145 146 if (!ctrl->cmd_busy) 147 return; 148 149 /* 150 * Even if the command has already timed out, we want to call 151 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. 152 */ 153 now = jiffies; 154 if (time_before_eq(cmd_timeout, now)) 155 timeout = 1; 156 else 157 timeout = cmd_timeout - now; 158 159 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && 160 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) 161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 162 else 163 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); 164 165 /* 166 * Controllers with errata like Intel CF118 don't generate 167 * completion notifications unless the power/indicator/interlock 168 * control bits are changed. On such controllers, we'll emit this 169 * timeout message when we wait for completion of commands that 170 * don't change those bits, e.g., commands that merely enable 171 * interrupts. 172 */ 173 if (!rc) 174 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", 175 ctrl->slot_ctrl, 176 jiffies_to_msecs(jiffies - ctrl->cmd_started)); 177} 178 179static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, 180 u16 mask, bool wait) 181{ 182 struct pci_dev *pdev = ctrl_dev(ctrl); 183 u16 slot_ctrl; 184 185 mutex_lock(&ctrl->ctrl_lock); 186 187 /* 188 * Always wait for any previous command that might still be in progress 189 */ 190 pcie_wait_cmd(ctrl); 191 192 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 193 slot_ctrl &= ~mask; 194 slot_ctrl |= (cmd & mask); 195 ctrl->cmd_busy = 1; 196 smp_mb(); 197 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 198 ctrl->cmd_started = jiffies; 199 ctrl->slot_ctrl = slot_ctrl; 200 201 /* 202 * Optionally wait for the hardware to be ready for a new command, 203 * indicating completion of the above issued command. 204 */ 205 if (wait) 206 pcie_wait_cmd(ctrl); 207 208 mutex_unlock(&ctrl->ctrl_lock); 209} 210 211/** 212 * pcie_write_cmd - Issue controller command 213 * @ctrl: controller to which the command is issued 214 * @cmd: command value written to slot control register 215 * @mask: bitmask of slot control register to be modified 216 */ 217static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 218{ 219 pcie_do_write_cmd(ctrl, cmd, mask, true); 220} 221 222/* Same as above without waiting for the hardware to latch */ 223static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) 224{ 225 pcie_do_write_cmd(ctrl, cmd, mask, false); 226} 227 228bool pciehp_check_link_active(struct controller *ctrl) 229{ 230 struct pci_dev *pdev = ctrl_dev(ctrl); 231 u16 lnk_status; 232 bool ret; 233 234 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 235 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 236 237 if (ret) 238 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 239 240 return ret; 241} 242 243static void __pcie_wait_link_active(struct controller *ctrl, bool active) 244{ 245 int timeout = 1000; 246 247 if (pciehp_check_link_active(ctrl) == active) 248 return; 249 while (timeout > 0) { 250 msleep(10); 251 timeout -= 10; 252 if (pciehp_check_link_active(ctrl) == active) 253 return; 254 } 255 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", 256 active ? "set" : "cleared"); 257} 258 259static void pcie_wait_link_active(struct controller *ctrl) 260{ 261 __pcie_wait_link_active(ctrl, true); 262} 263 264static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 265{ 266 u32 l; 267 int count = 0; 268 int delay = 1000, step = 20; 269 bool found = false; 270 271 do { 272 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 273 count++; 274 275 if (found) 276 break; 277 278 msleep(step); 279 delay -= step; 280 } while (delay > 0); 281 282 if (count > 1 && pciehp_debug) 283 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 284 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 285 PCI_FUNC(devfn), count, step, l); 286 287 return found; 288} 289 290int pciehp_check_link_status(struct controller *ctrl) 291{ 292 struct pci_dev *pdev = ctrl_dev(ctrl); 293 bool found; 294 u16 lnk_status; 295 296 /* 297 * Data Link Layer Link Active Reporting must be capable for 298 * hot-plug capable downstream port. But old controller might 299 * not implement it. In this case, we wait for 1000 ms. 300 */ 301 if (ctrl->link_active_reporting) 302 pcie_wait_link_active(ctrl); 303 else 304 msleep(1000); 305 306 /* wait 100ms before read pci conf, and try in 1s */ 307 msleep(100); 308 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 309 PCI_DEVFN(0, 0)); 310 311 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 312 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 313 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 314 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 315 ctrl_err(ctrl, "Link Training Error occurs\n"); 316 return -1; 317 } 318 319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 320 321 if (!found) 322 return -1; 323 324 return 0; 325} 326 327static int __pciehp_link_set(struct controller *ctrl, bool enable) 328{ 329 struct pci_dev *pdev = ctrl_dev(ctrl); 330 u16 lnk_ctrl; 331 332 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 333 334 if (enable) 335 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 336 else 337 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 338 339 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 340 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 341 return 0; 342} 343 344static int pciehp_link_enable(struct controller *ctrl) 345{ 346 return __pciehp_link_set(ctrl, true); 347} 348 349void pciehp_get_attention_status(struct slot *slot, u8 *status) 350{ 351 struct controller *ctrl = slot->ctrl; 352 struct pci_dev *pdev = ctrl_dev(ctrl); 353 u16 slot_ctrl; 354 355 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 356 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 357 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 358 359 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 360 case PCI_EXP_SLTCTL_ATTN_IND_ON: 361 *status = 1; /* On */ 362 break; 363 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 364 *status = 2; /* Blink */ 365 break; 366 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 367 *status = 0; /* Off */ 368 break; 369 default: 370 *status = 0xFF; 371 break; 372 } 373} 374 375void pciehp_get_power_status(struct slot *slot, u8 *status) 376{ 377 struct controller *ctrl = slot->ctrl; 378 struct pci_dev *pdev = ctrl_dev(ctrl); 379 u16 slot_ctrl; 380 381 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 382 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 383 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 384 385 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 386 case PCI_EXP_SLTCTL_PWR_ON: 387 *status = 1; /* On */ 388 break; 389 case PCI_EXP_SLTCTL_PWR_OFF: 390 *status = 0; /* Off */ 391 break; 392 default: 393 *status = 0xFF; 394 break; 395 } 396} 397 398void pciehp_get_latch_status(struct slot *slot, u8 *status) 399{ 400 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 401 u16 slot_status; 402 403 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 404 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 405} 406 407void pciehp_get_adapter_status(struct slot *slot, u8 *status) 408{ 409 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 410 u16 slot_status; 411 412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 413 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 414} 415 416int pciehp_query_power_fault(struct slot *slot) 417{ 418 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 419 u16 slot_status; 420 421 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 422 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 423} 424 425void pciehp_set_attention_status(struct slot *slot, u8 value) 426{ 427 struct controller *ctrl = slot->ctrl; 428 u16 slot_cmd; 429 430 if (!ATTN_LED(ctrl)) 431 return; 432 433 switch (value) { 434 case 0: /* turn off */ 435 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; 436 break; 437 case 1: /* turn on */ 438 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; 439 break; 440 case 2: /* turn blink */ 441 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; 442 break; 443 default: 444 return; 445 } 446 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); 447 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 448 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 449} 450 451void pciehp_green_led_on(struct slot *slot) 452{ 453 struct controller *ctrl = slot->ctrl; 454 455 if (!PWR_LED(ctrl)) 456 return; 457 458 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, 459 PCI_EXP_SLTCTL_PIC); 460 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 461 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 462 PCI_EXP_SLTCTL_PWR_IND_ON); 463} 464 465void pciehp_green_led_off(struct slot *slot) 466{ 467 struct controller *ctrl = slot->ctrl; 468 469 if (!PWR_LED(ctrl)) 470 return; 471 472 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, 473 PCI_EXP_SLTCTL_PIC); 474 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 475 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 476 PCI_EXP_SLTCTL_PWR_IND_OFF); 477} 478 479void pciehp_green_led_blink(struct slot *slot) 480{ 481 struct controller *ctrl = slot->ctrl; 482 483 if (!PWR_LED(ctrl)) 484 return; 485 486 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, 487 PCI_EXP_SLTCTL_PIC); 488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 489 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 490 PCI_EXP_SLTCTL_PWR_IND_BLINK); 491} 492 493int pciehp_power_on_slot(struct slot *slot) 494{ 495 struct controller *ctrl = slot->ctrl; 496 struct pci_dev *pdev = ctrl_dev(ctrl); 497 u16 slot_status; 498 int retval; 499 500 /* Clear sticky power-fault bit from previous power failures */ 501 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 502 if (slot_status & PCI_EXP_SLTSTA_PFD) 503 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 504 PCI_EXP_SLTSTA_PFD); 505 ctrl->power_fault_detected = 0; 506 507 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 508 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 509 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 510 PCI_EXP_SLTCTL_PWR_ON); 511 512 retval = pciehp_link_enable(ctrl); 513 if (retval) 514 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 515 516 return retval; 517} 518 519void pciehp_power_off_slot(struct slot *slot) 520{ 521 struct controller *ctrl = slot->ctrl; 522 523 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 524 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 525 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 526 PCI_EXP_SLTCTL_PWR_OFF); 527} 528 529static irqreturn_t pcie_isr(int irq, void *dev_id) 530{ 531 struct controller *ctrl = (struct controller *)dev_id; 532 struct pci_dev *pdev = ctrl_dev(ctrl); 533 struct pci_bus *subordinate = pdev->subordinate; 534 struct pci_dev *dev; 535 struct slot *slot = ctrl->slot; 536 u16 detected, intr_loc; 537 538 /* 539 * In order to guarantee that all interrupt events are 540 * serviced, we need to re-inspect Slot Status register after 541 * clearing what is presumed to be the last pending interrupt. 542 */ 543 intr_loc = 0; 544 do { 545 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); 546 547 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 548 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 549 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); 550 detected &= ~intr_loc; 551 intr_loc |= detected; 552 if (!intr_loc) 553 return IRQ_NONE; 554 if (detected) 555 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 556 intr_loc); 557 } while (detected); 558 559 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 560 561 /* Check Command Complete Interrupt Pending */ 562 if (intr_loc & PCI_EXP_SLTSTA_CC) { 563 ctrl->cmd_busy = 0; 564 smp_mb(); 565 wake_up(&ctrl->queue); 566 } 567 568 if (subordinate) { 569 list_for_each_entry(dev, &subordinate->devices, bus_list) { 570 if (dev->ignore_hotplug) { 571 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", 572 intr_loc, pci_name(dev)); 573 return IRQ_HANDLED; 574 } 575 } 576 } 577 578 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 579 return IRQ_HANDLED; 580 581 /* Check MRL Sensor Changed */ 582 if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 583 pciehp_handle_switch_change(slot); 584 585 /* Check Attention Button Pressed */ 586 if (intr_loc & PCI_EXP_SLTSTA_ABP) 587 pciehp_handle_attention_button(slot); 588 589 /* Check Presence Detect Changed */ 590 if (intr_loc & PCI_EXP_SLTSTA_PDC) 591 pciehp_handle_presence_change(slot); 592 593 /* Check Power Fault Detected */ 594 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 595 ctrl->power_fault_detected = 1; 596 pciehp_handle_power_fault(slot); 597 } 598 599 if (intr_loc & PCI_EXP_SLTSTA_DLLSC) 600 pciehp_handle_linkstate_change(slot); 601 602 return IRQ_HANDLED; 603} 604 605void pcie_enable_notification(struct controller *ctrl) 606{ 607 u16 cmd, mask; 608 609 /* 610 * TBD: Power fault detected software notification support. 611 * 612 * Power fault detected software notification is not enabled 613 * now, because it caused power fault detected interrupt storm 614 * on some machines. On those machines, power fault detected 615 * bit in the slot status register was set again immediately 616 * when it is cleared in the interrupt service routine, and 617 * next power fault detected interrupt was notified again. 618 */ 619 620 /* 621 * Always enable link events: thus link-up and link-down shall 622 * always be treated as hotplug and unplug respectively. Enable 623 * presence detect only if Attention Button is not present. 624 */ 625 cmd = PCI_EXP_SLTCTL_DLLSCE; 626 if (ATTN_BUTTN(ctrl)) 627 cmd |= PCI_EXP_SLTCTL_ABPE; 628 else 629 cmd |= PCI_EXP_SLTCTL_PDCE; 630 if (MRL_SENS(ctrl)) 631 cmd |= PCI_EXP_SLTCTL_MRLSCE; 632 if (!pciehp_poll_mode) 633 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 634 635 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 636 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 637 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 638 PCI_EXP_SLTCTL_DLLSCE); 639 640 pcie_write_cmd_nowait(ctrl, cmd, mask); 641 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 642 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 643} 644 645static void pcie_disable_notification(struct controller *ctrl) 646{ 647 u16 mask; 648 649 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 650 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 651 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 652 PCI_EXP_SLTCTL_DLLSCE); 653 pcie_write_cmd(ctrl, 0, mask); 654 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 655 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 656} 657 658/* 659 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 660 * bus reset of the bridge, but at the same time we want to ensure that it is 661 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 662 * disable link state notification and presence detection change notification 663 * momentarily, if we see that they could interfere. Also, clear any spurious 664 * events after. 665 */ 666int pciehp_reset_slot(struct slot *slot, int probe) 667{ 668 struct controller *ctrl = slot->ctrl; 669 struct pci_dev *pdev = ctrl_dev(ctrl); 670 u16 stat_mask = 0, ctrl_mask = 0; 671 672 if (probe) 673 return 0; 674 675 if (!ATTN_BUTTN(ctrl)) { 676 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 677 stat_mask |= PCI_EXP_SLTSTA_PDC; 678 } 679 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 680 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 681 682 pcie_write_cmd(ctrl, 0, ctrl_mask); 683 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 684 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 685 if (pciehp_poll_mode) 686 del_timer_sync(&ctrl->poll_timer); 687 688 pci_reset_bridge_secondary_bus(ctrl->pcie->port); 689 690 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 691 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); 692 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 693 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); 694 if (pciehp_poll_mode) 695 int_poll_timeout(ctrl->poll_timer.data); 696 697 return 0; 698} 699 700int pcie_init_notification(struct controller *ctrl) 701{ 702 if (pciehp_request_irq(ctrl)) 703 return -1; 704 pcie_enable_notification(ctrl); 705 ctrl->notification_enabled = 1; 706 return 0; 707} 708 709static void pcie_shutdown_notification(struct controller *ctrl) 710{ 711 if (ctrl->notification_enabled) { 712 pcie_disable_notification(ctrl); 713 pciehp_free_irq(ctrl); 714 ctrl->notification_enabled = 0; 715 } 716} 717 718static int pcie_init_slot(struct controller *ctrl) 719{ 720 struct slot *slot; 721 722 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 723 if (!slot) 724 return -ENOMEM; 725 726 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); 727 if (!slot->wq) 728 goto abort; 729 730 slot->ctrl = ctrl; 731 mutex_init(&slot->lock); 732 mutex_init(&slot->hotplug_lock); 733 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 734 ctrl->slot = slot; 735 return 0; 736abort: 737 kfree(slot); 738 return -ENOMEM; 739} 740 741static void pcie_cleanup_slot(struct controller *ctrl) 742{ 743 struct slot *slot = ctrl->slot; 744 cancel_delayed_work(&slot->work); 745 destroy_workqueue(slot->wq); 746 kfree(slot); 747} 748 749static inline void dbg_ctrl(struct controller *ctrl) 750{ 751 int i; 752 u16 reg16; 753 struct pci_dev *pdev = ctrl->pcie->port; 754 755 if (!pciehp_debug) 756 return; 757 758 ctrl_info(ctrl, "Hotplug Controller:\n"); 759 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 760 pci_name(pdev), pdev->irq); 761 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 762 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 763 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 764 pdev->subsystem_device); 765 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 766 pdev->subsystem_vendor); 767 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", 768 pci_pcie_cap(pdev)); 769 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 770 if (!pci_resource_len(pdev, i)) 771 continue; 772 ctrl_info(ctrl, " PCI resource [%d] : %pR\n", 773 i, &pdev->resource[i]); 774 } 775 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 776 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 777 ctrl_info(ctrl, " Attention Button : %3s\n", 778 ATTN_BUTTN(ctrl) ? "yes" : "no"); 779 ctrl_info(ctrl, " Power Controller : %3s\n", 780 POWER_CTRL(ctrl) ? "yes" : "no"); 781 ctrl_info(ctrl, " MRL Sensor : %3s\n", 782 MRL_SENS(ctrl) ? "yes" : "no"); 783 ctrl_info(ctrl, " Attention Indicator : %3s\n", 784 ATTN_LED(ctrl) ? "yes" : "no"); 785 ctrl_info(ctrl, " Power Indicator : %3s\n", 786 PWR_LED(ctrl) ? "yes" : "no"); 787 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 788 HP_SUPR_RM(ctrl) ? "yes" : "no"); 789 ctrl_info(ctrl, " EMI Present : %3s\n", 790 EMI(ctrl) ? "yes" : "no"); 791 ctrl_info(ctrl, " Command Completed : %3s\n", 792 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 793 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 794 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 795 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 796 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 797} 798 799#define FLAG(x, y) (((x) & (y)) ? '+' : '-') 800 801struct controller *pcie_init(struct pcie_device *dev) 802{ 803 struct controller *ctrl; 804 u32 slot_cap, link_cap; 805 struct pci_dev *pdev = dev->port; 806 807 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 808 if (!ctrl) { 809 dev_err(&dev->device, "%s: Out of memory\n", __func__); 810 goto abort; 811 } 812 ctrl->pcie = dev; 813 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 814 ctrl->slot_cap = slot_cap; 815 mutex_init(&ctrl->ctrl_lock); 816 init_waitqueue_head(&ctrl->queue); 817 dbg_ctrl(ctrl); 818 819 /* Check if Data Link Layer Link Active Reporting is implemented */ 820 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 821 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 822 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 823 ctrl->link_active_reporting = 1; 824 } 825 826 /* Clear all remaining event bits in Slot Status register */ 827 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 828 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 829 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 830 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); 831 832 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", 833 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 834 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 835 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 836 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 837 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 838 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 839 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 840 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 841 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); 842 843 if (pcie_init_slot(ctrl)) 844 goto abort_ctrl; 845 846 return ctrl; 847 848abort_ctrl: 849 kfree(ctrl); 850abort: 851 return NULL; 852} 853 854void pciehp_release_ctrl(struct controller *ctrl) 855{ 856 pcie_shutdown_notification(ctrl); 857 pcie_cleanup_slot(ctrl); 858 kfree(ctrl); 859} 860