1/*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/bitmap.h>
22#include <linux/bug.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <linux/err.h>
26#include <linux/gpio.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/irqdesc.h>
31#include <linux/irqdomain.h>
32#include <linux/module.h>
33#include <linux/of_address.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/pinctrl/consumer.h>
37#include <linux/pinctrl/machine.h>
38#include <linux/pinctrl/pinconf.h>
39#include <linux/pinctrl/pinctrl.h>
40#include <linux/pinctrl/pinmux.h>
41#include <linux/platform_device.h>
42#include <linux/seq_file.h>
43#include <linux/slab.h>
44#include <linux/spinlock.h>
45#include <linux/types.h>
46
47#define MODULE_NAME "pinctrl-bcm2835"
48#define BCM2835_NUM_GPIOS 54
49#define BCM2835_NUM_BANKS 2
50
51#define BCM2835_PIN_BITMAP_SZ \
52	DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53
54/* GPIO register offsets */
55#define GPFSEL0		0x0	/* Function Select */
56#define GPSET0		0x1c	/* Pin Output Set */
57#define GPCLR0		0x28	/* Pin Output Clear */
58#define GPLEV0		0x34	/* Pin Level */
59#define GPEDS0		0x40	/* Pin Event Detect Status */
60#define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
61#define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
62#define GPHEN0		0x64	/* Pin High Detect Enable */
63#define GPLEN0		0x70	/* Pin Low Detect Enable */
64#define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
65#define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
66#define GPPUD		0x94	/* Pin Pull-up/down Enable */
67#define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
68
69#define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
70#define FSEL_SHIFT(p)		(((p) % 10) * 3)
71#define GPIO_REG_OFFSET(p)	((p) / 32)
72#define GPIO_REG_SHIFT(p)	((p) % 32)
73
74enum bcm2835_pinconf_param {
75	/* argument: bcm2835_pinconf_pull */
76	BCM2835_PINCONF_PARAM_PULL,
77};
78
79enum bcm2835_pinconf_pull {
80	BCM2835_PINCONFIG_PULL_NONE,
81	BCM2835_PINCONFIG_PULL_DOWN,
82	BCM2835_PINCONFIG_PULL_UP,
83};
84
85#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
86#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
87#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
88
89struct bcm2835_gpio_irqdata {
90	struct bcm2835_pinctrl *pc;
91	int bank;
92};
93
94struct bcm2835_pinctrl {
95	struct device *dev;
96	void __iomem *base;
97	int irq[BCM2835_NUM_BANKS];
98
99	/* note: locking assumes each bank will have its own unsigned long */
100	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
101	unsigned int irq_type[BCM2835_NUM_GPIOS];
102
103	struct pinctrl_dev *pctl_dev;
104	struct irq_domain *irq_domain;
105	struct gpio_chip gpio_chip;
106	struct pinctrl_gpio_range gpio_range;
107
108	struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
109	spinlock_t irq_lock[BCM2835_NUM_BANKS];
110};
111
112static struct lock_class_key gpio_lock_class;
113
114/* pins are just named GPIO0..GPIO53 */
115#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
116static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
117	BCM2835_GPIO_PIN(0),
118	BCM2835_GPIO_PIN(1),
119	BCM2835_GPIO_PIN(2),
120	BCM2835_GPIO_PIN(3),
121	BCM2835_GPIO_PIN(4),
122	BCM2835_GPIO_PIN(5),
123	BCM2835_GPIO_PIN(6),
124	BCM2835_GPIO_PIN(7),
125	BCM2835_GPIO_PIN(8),
126	BCM2835_GPIO_PIN(9),
127	BCM2835_GPIO_PIN(10),
128	BCM2835_GPIO_PIN(11),
129	BCM2835_GPIO_PIN(12),
130	BCM2835_GPIO_PIN(13),
131	BCM2835_GPIO_PIN(14),
132	BCM2835_GPIO_PIN(15),
133	BCM2835_GPIO_PIN(16),
134	BCM2835_GPIO_PIN(17),
135	BCM2835_GPIO_PIN(18),
136	BCM2835_GPIO_PIN(19),
137	BCM2835_GPIO_PIN(20),
138	BCM2835_GPIO_PIN(21),
139	BCM2835_GPIO_PIN(22),
140	BCM2835_GPIO_PIN(23),
141	BCM2835_GPIO_PIN(24),
142	BCM2835_GPIO_PIN(25),
143	BCM2835_GPIO_PIN(26),
144	BCM2835_GPIO_PIN(27),
145	BCM2835_GPIO_PIN(28),
146	BCM2835_GPIO_PIN(29),
147	BCM2835_GPIO_PIN(30),
148	BCM2835_GPIO_PIN(31),
149	BCM2835_GPIO_PIN(32),
150	BCM2835_GPIO_PIN(33),
151	BCM2835_GPIO_PIN(34),
152	BCM2835_GPIO_PIN(35),
153	BCM2835_GPIO_PIN(36),
154	BCM2835_GPIO_PIN(37),
155	BCM2835_GPIO_PIN(38),
156	BCM2835_GPIO_PIN(39),
157	BCM2835_GPIO_PIN(40),
158	BCM2835_GPIO_PIN(41),
159	BCM2835_GPIO_PIN(42),
160	BCM2835_GPIO_PIN(43),
161	BCM2835_GPIO_PIN(44),
162	BCM2835_GPIO_PIN(45),
163	BCM2835_GPIO_PIN(46),
164	BCM2835_GPIO_PIN(47),
165	BCM2835_GPIO_PIN(48),
166	BCM2835_GPIO_PIN(49),
167	BCM2835_GPIO_PIN(50),
168	BCM2835_GPIO_PIN(51),
169	BCM2835_GPIO_PIN(52),
170	BCM2835_GPIO_PIN(53),
171};
172
173/* one pin per group */
174static const char * const bcm2835_gpio_groups[] = {
175	"gpio0",
176	"gpio1",
177	"gpio2",
178	"gpio3",
179	"gpio4",
180	"gpio5",
181	"gpio6",
182	"gpio7",
183	"gpio8",
184	"gpio9",
185	"gpio10",
186	"gpio11",
187	"gpio12",
188	"gpio13",
189	"gpio14",
190	"gpio15",
191	"gpio16",
192	"gpio17",
193	"gpio18",
194	"gpio19",
195	"gpio20",
196	"gpio21",
197	"gpio22",
198	"gpio23",
199	"gpio24",
200	"gpio25",
201	"gpio26",
202	"gpio27",
203	"gpio28",
204	"gpio29",
205	"gpio30",
206	"gpio31",
207	"gpio32",
208	"gpio33",
209	"gpio34",
210	"gpio35",
211	"gpio36",
212	"gpio37",
213	"gpio38",
214	"gpio39",
215	"gpio40",
216	"gpio41",
217	"gpio42",
218	"gpio43",
219	"gpio44",
220	"gpio45",
221	"gpio46",
222	"gpio47",
223	"gpio48",
224	"gpio49",
225	"gpio50",
226	"gpio51",
227	"gpio52",
228	"gpio53",
229};
230
231enum bcm2835_fsel {
232	BCM2835_FSEL_GPIO_IN = 0,
233	BCM2835_FSEL_GPIO_OUT = 1,
234	BCM2835_FSEL_ALT0 = 4,
235	BCM2835_FSEL_ALT1 = 5,
236	BCM2835_FSEL_ALT2 = 6,
237	BCM2835_FSEL_ALT3 = 7,
238	BCM2835_FSEL_ALT4 = 3,
239	BCM2835_FSEL_ALT5 = 2,
240	BCM2835_FSEL_COUNT = 8,
241	BCM2835_FSEL_MASK = 0x7,
242};
243
244static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
245	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
246	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
247	[BCM2835_FSEL_ALT0] = "alt0",
248	[BCM2835_FSEL_ALT1] = "alt1",
249	[BCM2835_FSEL_ALT2] = "alt2",
250	[BCM2835_FSEL_ALT3] = "alt3",
251	[BCM2835_FSEL_ALT4] = "alt4",
252	[BCM2835_FSEL_ALT5] = "alt5",
253};
254
255static const char * const irq_type_names[] = {
256	[IRQ_TYPE_NONE] = "none",
257	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
258	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
259	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
260	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
261	[IRQ_TYPE_LEVEL_LOW] = "level-low",
262};
263
264static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
265{
266	return readl(pc->base + reg);
267}
268
269static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
270		u32 val)
271{
272	writel(val, pc->base + reg);
273}
274
275static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
276		unsigned bit)
277{
278	reg += GPIO_REG_OFFSET(bit) * 4;
279	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
280}
281
282/* note NOT a read/modify/write cycle */
283static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
284		unsigned reg, unsigned bit)
285{
286	reg += GPIO_REG_OFFSET(bit) * 4;
287	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
288}
289
290static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
291		struct bcm2835_pinctrl *pc, unsigned pin)
292{
293	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
294	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
295
296	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
297			bcm2835_functions[status]);
298
299	return status;
300}
301
302static inline void bcm2835_pinctrl_fsel_set(
303		struct bcm2835_pinctrl *pc, unsigned pin,
304		enum bcm2835_fsel fsel)
305{
306	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
307	enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
308
309	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
310			bcm2835_functions[cur]);
311
312	if (cur == fsel)
313		return;
314
315	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
316		/* always transition through GPIO_IN */
317		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
318		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
319
320		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
321				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
322		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
323	}
324
325	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
326	val |= fsel << FSEL_SHIFT(pin);
327
328	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
329			bcm2835_functions[fsel]);
330	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
331}
332
333static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset)
334{
335	return pinctrl_request_gpio(chip->base + offset);
336}
337
338static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset)
339{
340	pinctrl_free_gpio(chip->base + offset);
341}
342
343static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
344{
345	return pinctrl_gpio_direction_input(chip->base + offset);
346}
347
348static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
349{
350	struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
351
352	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
353}
354
355static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
356		unsigned offset, int value)
357{
358	return pinctrl_gpio_direction_output(chip->base + offset);
359}
360
361static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
362{
363	struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
364
365	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
366}
367
368static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
369{
370	struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
371
372	return irq_linear_revmap(pc->irq_domain, offset);
373}
374
375static struct gpio_chip bcm2835_gpio_chip = {
376	.label = MODULE_NAME,
377	.owner = THIS_MODULE,
378	.request = bcm2835_gpio_request,
379	.free = bcm2835_gpio_free,
380	.direction_input = bcm2835_gpio_direction_input,
381	.direction_output = bcm2835_gpio_direction_output,
382	.get = bcm2835_gpio_get,
383	.set = bcm2835_gpio_set,
384	.to_irq = bcm2835_gpio_to_irq,
385	.base = -1,
386	.ngpio = BCM2835_NUM_GPIOS,
387	.can_sleep = false,
388};
389
390static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
391{
392	struct bcm2835_gpio_irqdata *irqdata = dev_id;
393	struct bcm2835_pinctrl *pc = irqdata->pc;
394	int bank = irqdata->bank;
395	unsigned long events;
396	unsigned offset;
397	unsigned gpio;
398	unsigned int type;
399
400	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
401	events &= pc->enabled_irq_map[bank];
402	for_each_set_bit(offset, &events, 32) {
403		gpio = (32 * bank) + offset;
404		type = pc->irq_type[gpio];
405
406		generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
407	}
408	return events ? IRQ_HANDLED : IRQ_NONE;
409}
410
411static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
412	unsigned reg, unsigned offset, bool enable)
413{
414	u32 value;
415	reg += GPIO_REG_OFFSET(offset) * 4;
416	value = bcm2835_gpio_rd(pc, reg);
417	if (enable)
418		value |= BIT(GPIO_REG_SHIFT(offset));
419	else
420		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
421	bcm2835_gpio_wr(pc, reg, value);
422}
423
424/* fast path for IRQ handler */
425static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
426	unsigned offset, bool enable)
427{
428	switch (pc->irq_type[offset]) {
429	case IRQ_TYPE_EDGE_RISING:
430		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
431		break;
432
433	case IRQ_TYPE_EDGE_FALLING:
434		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
435		break;
436
437	case IRQ_TYPE_EDGE_BOTH:
438		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
439		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
440		break;
441
442	case IRQ_TYPE_LEVEL_HIGH:
443		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
444		break;
445
446	case IRQ_TYPE_LEVEL_LOW:
447		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
448		break;
449	}
450}
451
452static void bcm2835_gpio_irq_enable(struct irq_data *data)
453{
454	struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
455	unsigned gpio = irqd_to_hwirq(data);
456	unsigned offset = GPIO_REG_SHIFT(gpio);
457	unsigned bank = GPIO_REG_OFFSET(gpio);
458	unsigned long flags;
459
460	spin_lock_irqsave(&pc->irq_lock[bank], flags);
461	set_bit(offset, &pc->enabled_irq_map[bank]);
462	bcm2835_gpio_irq_config(pc, gpio, true);
463	spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
464}
465
466static void bcm2835_gpio_irq_disable(struct irq_data *data)
467{
468	struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
469	unsigned gpio = irqd_to_hwirq(data);
470	unsigned offset = GPIO_REG_SHIFT(gpio);
471	unsigned bank = GPIO_REG_OFFSET(gpio);
472	unsigned long flags;
473
474	spin_lock_irqsave(&pc->irq_lock[bank], flags);
475	bcm2835_gpio_irq_config(pc, gpio, false);
476	clear_bit(offset, &pc->enabled_irq_map[bank]);
477	spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
478}
479
480static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
481	unsigned offset, unsigned int type)
482{
483	switch (type) {
484	case IRQ_TYPE_NONE:
485	case IRQ_TYPE_EDGE_RISING:
486	case IRQ_TYPE_EDGE_FALLING:
487	case IRQ_TYPE_EDGE_BOTH:
488	case IRQ_TYPE_LEVEL_HIGH:
489	case IRQ_TYPE_LEVEL_LOW:
490		pc->irq_type[offset] = type;
491		break;
492
493	default:
494		return -EINVAL;
495	}
496	return 0;
497}
498
499/* slower path for reconfiguring IRQ type */
500static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
501	unsigned offset, unsigned int type)
502{
503	switch (type) {
504	case IRQ_TYPE_NONE:
505		if (pc->irq_type[offset] != type) {
506			bcm2835_gpio_irq_config(pc, offset, false);
507			pc->irq_type[offset] = type;
508		}
509		break;
510
511	case IRQ_TYPE_EDGE_RISING:
512		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
513			/* RISING already enabled, disable FALLING */
514			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
515			bcm2835_gpio_irq_config(pc, offset, false);
516			pc->irq_type[offset] = type;
517		} else if (pc->irq_type[offset] != type) {
518			bcm2835_gpio_irq_config(pc, offset, false);
519			pc->irq_type[offset] = type;
520			bcm2835_gpio_irq_config(pc, offset, true);
521		}
522		break;
523
524	case IRQ_TYPE_EDGE_FALLING:
525		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
526			/* FALLING already enabled, disable RISING */
527			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
528			bcm2835_gpio_irq_config(pc, offset, false);
529			pc->irq_type[offset] = type;
530		} else if (pc->irq_type[offset] != type) {
531			bcm2835_gpio_irq_config(pc, offset, false);
532			pc->irq_type[offset] = type;
533			bcm2835_gpio_irq_config(pc, offset, true);
534		}
535		break;
536
537	case IRQ_TYPE_EDGE_BOTH:
538		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
539			/* RISING already enabled, enable FALLING too */
540			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
541			bcm2835_gpio_irq_config(pc, offset, true);
542			pc->irq_type[offset] = type;
543		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
544			/* FALLING already enabled, enable RISING too */
545			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
546			bcm2835_gpio_irq_config(pc, offset, true);
547			pc->irq_type[offset] = type;
548		} else if (pc->irq_type[offset] != type) {
549			bcm2835_gpio_irq_config(pc, offset, false);
550			pc->irq_type[offset] = type;
551			bcm2835_gpio_irq_config(pc, offset, true);
552		}
553		break;
554
555	case IRQ_TYPE_LEVEL_HIGH:
556	case IRQ_TYPE_LEVEL_LOW:
557		if (pc->irq_type[offset] != type) {
558			bcm2835_gpio_irq_config(pc, offset, false);
559			pc->irq_type[offset] = type;
560			bcm2835_gpio_irq_config(pc, offset, true);
561		}
562		break;
563
564	default:
565		return -EINVAL;
566	}
567	return 0;
568}
569
570static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
571{
572	struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
573	unsigned gpio = irqd_to_hwirq(data);
574	unsigned offset = GPIO_REG_SHIFT(gpio);
575	unsigned bank = GPIO_REG_OFFSET(gpio);
576	unsigned long flags;
577	int ret;
578
579	spin_lock_irqsave(&pc->irq_lock[bank], flags);
580
581	if (test_bit(offset, &pc->enabled_irq_map[bank]))
582		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
583	else
584		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
585
586	if (type & IRQ_TYPE_EDGE_BOTH)
587		__irq_set_handler_locked(data->irq, handle_edge_irq);
588	else
589		__irq_set_handler_locked(data->irq, handle_level_irq);
590
591	spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
592
593	return ret;
594}
595
596static void bcm2835_gpio_irq_ack(struct irq_data *data)
597{
598	struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
599	unsigned gpio = irqd_to_hwirq(data);
600
601	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
602}
603
604static struct irq_chip bcm2835_gpio_irq_chip = {
605	.name = MODULE_NAME,
606	.irq_enable = bcm2835_gpio_irq_enable,
607	.irq_disable = bcm2835_gpio_irq_disable,
608	.irq_set_type = bcm2835_gpio_irq_set_type,
609	.irq_ack = bcm2835_gpio_irq_ack,
610	.irq_mask = bcm2835_gpio_irq_disable,
611	.irq_unmask = bcm2835_gpio_irq_enable,
612};
613
614static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
615{
616	return ARRAY_SIZE(bcm2835_gpio_groups);
617}
618
619static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
620		unsigned selector)
621{
622	return bcm2835_gpio_groups[selector];
623}
624
625static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
626		unsigned selector,
627		const unsigned **pins,
628		unsigned *num_pins)
629{
630	*pins = &bcm2835_gpio_pins[selector].number;
631	*num_pins = 1;
632
633	return 0;
634}
635
636static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
637		struct seq_file *s,
638		unsigned offset)
639{
640	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
641	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
642	const char *fname = bcm2835_functions[fsel];
643	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
644	int irq = irq_find_mapping(pc->irq_domain, offset);
645
646	seq_printf(s, "function %s in %s; irq %d (%s)",
647		fname, value ? "hi" : "lo",
648		irq, irq_type_names[pc->irq_type[offset]]);
649}
650
651static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
652		struct pinctrl_map *maps, unsigned num_maps)
653{
654	int i;
655
656	for (i = 0; i < num_maps; i++)
657		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
658			kfree(maps[i].data.configs.configs);
659
660	kfree(maps);
661}
662
663static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
664		struct device_node *np, u32 pin, u32 fnum,
665		struct pinctrl_map **maps)
666{
667	struct pinctrl_map *map = *maps;
668
669	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
670		dev_err(pc->dev, "%s: invalid brcm,function %d\n",
671			of_node_full_name(np), fnum);
672		return -EINVAL;
673	}
674
675	map->type = PIN_MAP_TYPE_MUX_GROUP;
676	map->data.mux.group = bcm2835_gpio_groups[pin];
677	map->data.mux.function = bcm2835_functions[fnum];
678	(*maps)++;
679
680	return 0;
681}
682
683static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
684		struct device_node *np, u32 pin, u32 pull,
685		struct pinctrl_map **maps)
686{
687	struct pinctrl_map *map = *maps;
688	unsigned long *configs;
689
690	if (pull > 2) {
691		dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
692			of_node_full_name(np), pull);
693		return -EINVAL;
694	}
695
696	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
697	if (!configs)
698		return -ENOMEM;
699	configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
700
701	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
702	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
703	map->data.configs.configs = configs;
704	map->data.configs.num_configs = 1;
705	(*maps)++;
706
707	return 0;
708}
709
710static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
711		struct device_node *np,
712		struct pinctrl_map **map, unsigned *num_maps)
713{
714	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
715	struct property *pins, *funcs, *pulls;
716	int num_pins, num_funcs, num_pulls, maps_per_pin;
717	struct pinctrl_map *maps, *cur_map;
718	int i, err;
719	u32 pin, func, pull;
720
721	pins = of_find_property(np, "brcm,pins", NULL);
722	if (!pins) {
723		dev_err(pc->dev, "%s: missing brcm,pins property\n",
724				of_node_full_name(np));
725		return -EINVAL;
726	}
727
728	funcs = of_find_property(np, "brcm,function", NULL);
729	pulls = of_find_property(np, "brcm,pull", NULL);
730
731	if (!funcs && !pulls) {
732		dev_err(pc->dev,
733			"%s: neither brcm,function nor brcm,pull specified\n",
734			of_node_full_name(np));
735		return -EINVAL;
736	}
737
738	num_pins = pins->length / 4;
739	num_funcs = funcs ? (funcs->length / 4) : 0;
740	num_pulls = pulls ? (pulls->length / 4) : 0;
741
742	if (num_funcs > 1 && num_funcs != num_pins) {
743		dev_err(pc->dev,
744			"%s: brcm,function must have 1 or %d entries\n",
745			of_node_full_name(np), num_pins);
746		return -EINVAL;
747	}
748
749	if (num_pulls > 1 && num_pulls != num_pins) {
750		dev_err(pc->dev,
751			"%s: brcm,pull must have 1 or %d entries\n",
752			of_node_full_name(np), num_pins);
753		return -EINVAL;
754	}
755
756	maps_per_pin = 0;
757	if (num_funcs)
758		maps_per_pin++;
759	if (num_pulls)
760		maps_per_pin++;
761	cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
762				GFP_KERNEL);
763	if (!maps)
764		return -ENOMEM;
765
766	for (i = 0; i < num_pins; i++) {
767		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
768		if (err)
769			goto out;
770		if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
771			dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
772				of_node_full_name(np), pin);
773			err = -EINVAL;
774			goto out;
775		}
776
777		if (num_funcs) {
778			err = of_property_read_u32_index(np, "brcm,function",
779					(num_funcs > 1) ? i : 0, &func);
780			if (err)
781				goto out;
782			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
783							func, &cur_map);
784			if (err)
785				goto out;
786		}
787		if (num_pulls) {
788			err = of_property_read_u32_index(np, "brcm,pull",
789					(num_pulls > 1) ? i : 0, &pull);
790			if (err)
791				goto out;
792			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
793							pull, &cur_map);
794			if (err)
795				goto out;
796		}
797	}
798
799	*map = maps;
800	*num_maps = num_pins * maps_per_pin;
801
802	return 0;
803
804out:
805	kfree(maps);
806	return err;
807}
808
809static const struct pinctrl_ops bcm2835_pctl_ops = {
810	.get_groups_count = bcm2835_pctl_get_groups_count,
811	.get_group_name = bcm2835_pctl_get_group_name,
812	.get_group_pins = bcm2835_pctl_get_group_pins,
813	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
814	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
815	.dt_free_map = bcm2835_pctl_dt_free_map,
816};
817
818static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
819{
820	return BCM2835_FSEL_COUNT;
821}
822
823static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
824		unsigned selector)
825{
826	return bcm2835_functions[selector];
827}
828
829static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
830		unsigned selector,
831		const char * const **groups,
832		unsigned * const num_groups)
833{
834	/* every pin can do every function */
835	*groups = bcm2835_gpio_groups;
836	*num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
837
838	return 0;
839}
840
841static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
842		unsigned func_selector,
843		unsigned group_selector)
844{
845	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
846
847	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
848
849	return 0;
850}
851
852static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
853		struct pinctrl_gpio_range *range,
854		unsigned offset)
855{
856	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
857
858	/* disable by setting to GPIO_IN */
859	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
860}
861
862static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
863		struct pinctrl_gpio_range *range,
864		unsigned offset,
865		bool input)
866{
867	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
868	enum bcm2835_fsel fsel = input ?
869		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
870
871	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
872
873	return 0;
874}
875
876static const struct pinmux_ops bcm2835_pmx_ops = {
877	.get_functions_count = bcm2835_pmx_get_functions_count,
878	.get_function_name = bcm2835_pmx_get_function_name,
879	.get_function_groups = bcm2835_pmx_get_function_groups,
880	.set_mux = bcm2835_pmx_set,
881	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
882	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
883};
884
885static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
886			unsigned pin, unsigned long *config)
887{
888	/* No way to read back config in HW */
889	return -ENOTSUPP;
890}
891
892static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
893			unsigned pin, unsigned long *configs,
894			unsigned num_configs)
895{
896	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
897	enum bcm2835_pinconf_param param;
898	u16 arg;
899	u32 off, bit;
900	int i;
901
902	for (i = 0; i < num_configs; i++) {
903		param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
904		arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
905
906		if (param != BCM2835_PINCONF_PARAM_PULL)
907			return -EINVAL;
908
909		off = GPIO_REG_OFFSET(pin);
910		bit = GPIO_REG_SHIFT(pin);
911
912		bcm2835_gpio_wr(pc, GPPUD, arg & 3);
913		/*
914		 * Docs say to wait 150 cycles, but not of what. We assume a
915		 * 1 MHz clock here, which is pretty slow...
916		 */
917		udelay(150);
918		bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
919		udelay(150);
920		bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
921	} /* for each config */
922
923	return 0;
924}
925
926static const struct pinconf_ops bcm2835_pinconf_ops = {
927	.pin_config_get = bcm2835_pinconf_get,
928	.pin_config_set = bcm2835_pinconf_set,
929};
930
931static struct pinctrl_desc bcm2835_pinctrl_desc = {
932	.name = MODULE_NAME,
933	.pins = bcm2835_gpio_pins,
934	.npins = ARRAY_SIZE(bcm2835_gpio_pins),
935	.pctlops = &bcm2835_pctl_ops,
936	.pmxops = &bcm2835_pmx_ops,
937	.confops = &bcm2835_pinconf_ops,
938	.owner = THIS_MODULE,
939};
940
941static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
942	.name = MODULE_NAME,
943	.npins = BCM2835_NUM_GPIOS,
944};
945
946static int bcm2835_pinctrl_probe(struct platform_device *pdev)
947{
948	struct device *dev = &pdev->dev;
949	struct device_node *np = dev->of_node;
950	struct bcm2835_pinctrl *pc;
951	struct resource iomem;
952	int err, i;
953	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
954	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
955
956	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
957	if (!pc)
958		return -ENOMEM;
959
960	platform_set_drvdata(pdev, pc);
961	pc->dev = dev;
962
963	err = of_address_to_resource(np, 0, &iomem);
964	if (err) {
965		dev_err(dev, "could not get IO memory\n");
966		return err;
967	}
968
969	pc->base = devm_ioremap_resource(dev, &iomem);
970	if (IS_ERR(pc->base))
971		return PTR_ERR(pc->base);
972
973	pc->gpio_chip = bcm2835_gpio_chip;
974	pc->gpio_chip.dev = dev;
975	pc->gpio_chip.of_node = np;
976
977	pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
978			&irq_domain_simple_ops, NULL);
979	if (!pc->irq_domain) {
980		dev_err(dev, "could not create IRQ domain\n");
981		return -ENOMEM;
982	}
983
984	for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
985		int irq = irq_create_mapping(pc->irq_domain, i);
986		irq_set_lockdep_class(irq, &gpio_lock_class);
987		irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
988				handle_level_irq);
989		irq_set_chip_data(irq, pc);
990		set_irq_flags(irq, IRQF_VALID);
991	}
992
993	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
994		unsigned long events;
995		unsigned offset;
996		int len;
997		char *name;
998
999		/* clear event detection flags */
1000		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1001		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1002		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1003		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1004		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1005		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1006
1007		/* clear all the events */
1008		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1009		for_each_set_bit(offset, &events, 32)
1010			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1011
1012		pc->irq[i] = irq_of_parse_and_map(np, i);
1013		pc->irq_data[i].pc = pc;
1014		pc->irq_data[i].bank = i;
1015		spin_lock_init(&pc->irq_lock[i]);
1016
1017		len = strlen(dev_name(pc->dev)) + 16;
1018		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1019		if (!name)
1020			return -ENOMEM;
1021		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1022
1023		err = devm_request_irq(dev, pc->irq[i],
1024			bcm2835_gpio_irq_handler, IRQF_SHARED,
1025			name, &pc->irq_data[i]);
1026		if (err) {
1027			dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1028			return err;
1029		}
1030	}
1031
1032	err = gpiochip_add(&pc->gpio_chip);
1033	if (err) {
1034		dev_err(dev, "could not add GPIO chip\n");
1035		return err;
1036	}
1037
1038	pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
1039	if (!pc->pctl_dev) {
1040		gpiochip_remove(&pc->gpio_chip);
1041		return -EINVAL;
1042	}
1043
1044	pc->gpio_range = bcm2835_pinctrl_gpio_range;
1045	pc->gpio_range.base = pc->gpio_chip.base;
1046	pc->gpio_range.gc = &pc->gpio_chip;
1047	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1048
1049	return 0;
1050}
1051
1052static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1053{
1054	struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1055
1056	pinctrl_unregister(pc->pctl_dev);
1057	gpiochip_remove(&pc->gpio_chip);
1058
1059	return 0;
1060}
1061
1062static const struct of_device_id bcm2835_pinctrl_match[] = {
1063	{ .compatible = "brcm,bcm2835-gpio" },
1064	{}
1065};
1066MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1067
1068static struct platform_driver bcm2835_pinctrl_driver = {
1069	.probe = bcm2835_pinctrl_probe,
1070	.remove = bcm2835_pinctrl_remove,
1071	.driver = {
1072		.name = MODULE_NAME,
1073		.of_match_table = bcm2835_pinctrl_match,
1074	},
1075};
1076module_platform_driver(bcm2835_pinctrl_driver);
1077
1078MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1079MODULE_DESCRIPTION("BCM2835 Pin control driver");
1080MODULE_LICENSE("GPL");
1081