1/*
2 * pinmux driver shared headfile for CSR SiRFsoc
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __PINMUX_SIRF_H__
10#define __PINMUX_SIRF_H__
11
12#define SIRFSOC_NUM_PADS		622
13#define SIRFSOC_RSC_USB_UART_SHARE	0
14#define SIRFSOC_RSC_PIN_MUX		0x4
15
16#define SIRFSOC_GPIO_PAD_EN(g)		((g)*0x100 + 0x84)
17#define SIRFSOC_GPIO_PAD_EN_CLR(g)	((g)*0x100 + 0x90)
18#define SIRFSOC_GPIO_CTRL(g, i)			((g)*0x100 + (i)*4)
19#define SIRFSOC_GPIO_DSP_EN0			(0x80)
20#define SIRFSOC_GPIO_INT_STATUS(g)		((g)*0x100 + 0x8C)
21
22#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK		0x1
23#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK		0x2
24#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK		0x4
25#define SIRFSOC_GPIO_CTL_INTR_EN_MASK		0x8
26#define SIRFSOC_GPIO_CTL_INTR_STS_MASK		0x10
27#define SIRFSOC_GPIO_CTL_OUT_EN_MASK		0x20
28#define SIRFSOC_GPIO_CTL_DATAOUT_MASK		0x40
29#define SIRFSOC_GPIO_CTL_DATAIN_MASK		0x80
30#define SIRFSOC_GPIO_CTL_PULL_MASK		0x100
31#define SIRFSOC_GPIO_CTL_PULL_HIGH		0x200
32#define SIRFSOC_GPIO_CTL_DSP_INT		0x400
33
34#define SIRFSOC_GPIO_NO_OF_BANKS        5
35#define SIRFSOC_GPIO_BANK_SIZE          32
36#define SIRFSOC_GPIO_NUM(bank, index)	(((bank)*(32)) + (index))
37
38/**
39 * @dev: a pointer back to containing device
40 * @virtbase: the offset to the controller in virtual memory
41 */
42struct sirfsoc_pmx {
43	struct device *dev;
44	struct pinctrl_dev *pmx;
45	void __iomem *gpio_virtbase;
46	void __iomem *rsc_virtbase;
47	u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
48	u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
49	u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
50	u32 dspen_regs;
51	u32 rsc_regs[3];
52};
53
54/* SIRFSOC_GPIO_PAD_EN set */
55struct sirfsoc_muxmask {
56	unsigned long group;
57	unsigned long mask;
58};
59
60struct sirfsoc_padmux {
61	unsigned long muxmask_counts;
62	const struct sirfsoc_muxmask *muxmask;
63	/* RSC_PIN_MUX set */
64	unsigned long ctrlreg;
65	unsigned long funcmask;
66	unsigned long funcval;
67};
68
69 /**
70 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
71 * @name: the name of this specific pin group
72 * @pins: an array of discrete physical pins used in this group, taken
73 *	from the driver-local pin enumeration space
74 * @num_pins: the number of pins in this group array, i.e. the number of
75 *	elements in .pins so we can iterate over that array
76 */
77struct sirfsoc_pin_group {
78	const char *name;
79	const unsigned int *pins;
80	const unsigned num_pins;
81};
82
83#define SIRFSOC_PIN_GROUP(n, p)  \
84	{			\
85		.name = n,	\
86		.pins = p,	\
87		.num_pins = ARRAY_SIZE(p),	\
88	}
89
90struct sirfsoc_pmx_func {
91	const char *name;
92	const char * const *groups;
93	const unsigned num_groups;
94	const struct sirfsoc_padmux *padmux;
95};
96
97#define SIRFSOC_PMX_FUNCTION(n, g, m)		\
98	{					\
99		.name = n,			\
100		.groups = g,			\
101		.num_groups = ARRAY_SIZE(g),	\
102		.padmux = &m,			\
103	}
104
105struct sirfsoc_pinctrl_data {
106	struct pinctrl_pin_desc *pads;
107	int pads_cnt;
108	struct sirfsoc_pin_group *grps;
109	int grps_cnt;
110	struct sirfsoc_pmx_func *funcs;
111	int funcs_cnt;
112};
113
114extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
115extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
116
117#endif
118