1/* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/io.h> 14#include <linux/clk.h> 15#include <linux/gpio.h> 16#include <linux/irqdomain.h> 17#include <linux/irqchip/chained_irq.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/of_address.h> 21#include <linux/of_device.h> 22#include <linux/of_irq.h> 23#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/machine.h> 25#include <linux/pinctrl/pinctrl.h> 26#include <linux/pinctrl/pinconf-generic.h> 27#include <linux/pinctrl/pinmux.h> 28#include <linux/platform_device.h> 29#include <linux/slab.h> 30 31#include "../core.h" 32#include "../../gpio/gpiolib.h" 33#include "pinctrl-sunxi.h" 34 35static struct irq_chip sunxi_pinctrl_edge_irq_chip; 36static struct irq_chip sunxi_pinctrl_level_irq_chip; 37 38static struct sunxi_pinctrl_group * 39sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 40{ 41 int i; 42 43 for (i = 0; i < pctl->ngroups; i++) { 44 struct sunxi_pinctrl_group *grp = pctl->groups + i; 45 46 if (!strcmp(grp->name, group)) 47 return grp; 48 } 49 50 return NULL; 51} 52 53static struct sunxi_pinctrl_function * 54sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 55 const char *name) 56{ 57 struct sunxi_pinctrl_function *func = pctl->functions; 58 int i; 59 60 for (i = 0; i < pctl->nfunctions; i++) { 61 if (!func[i].name) 62 break; 63 64 if (!strcmp(func[i].name, name)) 65 return func + i; 66 } 67 68 return NULL; 69} 70 71static struct sunxi_desc_function * 72sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 73 const char *pin_name, 74 const char *func_name) 75{ 76 int i; 77 78 for (i = 0; i < pctl->desc->npins; i++) { 79 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 80 81 if (!strcmp(pin->pin.name, pin_name)) { 82 struct sunxi_desc_function *func = pin->functions; 83 84 while (func->name) { 85 if (!strcmp(func->name, func_name)) 86 return func; 87 88 func++; 89 } 90 } 91 } 92 93 return NULL; 94} 95 96static struct sunxi_desc_function * 97sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 98 const u16 pin_num, 99 const char *func_name) 100{ 101 int i; 102 103 for (i = 0; i < pctl->desc->npins; i++) { 104 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 105 106 if (pin->pin.number == pin_num) { 107 struct sunxi_desc_function *func = pin->functions; 108 109 while (func->name) { 110 if (!strcmp(func->name, func_name)) 111 return func; 112 113 func++; 114 } 115 } 116 } 117 118 return NULL; 119} 120 121static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 122{ 123 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 124 125 return pctl->ngroups; 126} 127 128static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 129 unsigned group) 130{ 131 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 132 133 return pctl->groups[group].name; 134} 135 136static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 137 unsigned group, 138 const unsigned **pins, 139 unsigned *num_pins) 140{ 141 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 142 143 *pins = (unsigned *)&pctl->groups[group].pin; 144 *num_pins = 1; 145 146 return 0; 147} 148 149static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 150 struct device_node *node, 151 struct pinctrl_map **map, 152 unsigned *num_maps) 153{ 154 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 155 unsigned long *pinconfig; 156 struct property *prop; 157 const char *function; 158 const char *group; 159 int ret, nmaps, i = 0; 160 u32 val; 161 162 *map = NULL; 163 *num_maps = 0; 164 165 ret = of_property_read_string(node, "allwinner,function", &function); 166 if (ret) { 167 dev_err(pctl->dev, 168 "missing allwinner,function property in node %s\n", 169 node->name); 170 return -EINVAL; 171 } 172 173 nmaps = of_property_count_strings(node, "allwinner,pins") * 2; 174 if (nmaps < 0) { 175 dev_err(pctl->dev, 176 "missing allwinner,pins property in node %s\n", 177 node->name); 178 return -EINVAL; 179 } 180 181 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL); 182 if (!*map) 183 return -ENOMEM; 184 185 of_property_for_each_string(node, "allwinner,pins", prop, group) { 186 struct sunxi_pinctrl_group *grp = 187 sunxi_pinctrl_find_group_by_name(pctl, group); 188 int j = 0, configlen = 0; 189 190 if (!grp) { 191 dev_err(pctl->dev, "unknown pin %s", group); 192 continue; 193 } 194 195 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 196 grp->name, 197 function)) { 198 dev_err(pctl->dev, "unsupported function %s on pin %s", 199 function, group); 200 continue; 201 } 202 203 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 204 (*map)[i].data.mux.group = group; 205 (*map)[i].data.mux.function = function; 206 207 i++; 208 209 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 210 (*map)[i].data.configs.group_or_pin = group; 211 212 if (of_find_property(node, "allwinner,drive", NULL)) 213 configlen++; 214 if (of_find_property(node, "allwinner,pull", NULL)) 215 configlen++; 216 217 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL); 218 if (!pinconfig) { 219 kfree(*map); 220 return -ENOMEM; 221 } 222 223 if (!of_property_read_u32(node, "allwinner,drive", &val)) { 224 u16 strength = (val + 1) * 10; 225 pinconfig[j++] = 226 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 227 strength); 228 } 229 230 if (!of_property_read_u32(node, "allwinner,pull", &val)) { 231 enum pin_config_param pull = PIN_CONFIG_END; 232 if (val == 1) 233 pull = PIN_CONFIG_BIAS_PULL_UP; 234 else if (val == 2) 235 pull = PIN_CONFIG_BIAS_PULL_DOWN; 236 pinconfig[j++] = pinconf_to_config_packed(pull, 0); 237 } 238 239 (*map)[i].data.configs.configs = pinconfig; 240 (*map)[i].data.configs.num_configs = configlen; 241 242 i++; 243 } 244 245 *num_maps = nmaps; 246 247 return 0; 248} 249 250static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 251 struct pinctrl_map *map, 252 unsigned num_maps) 253{ 254 int i; 255 256 for (i = 0; i < num_maps; i++) { 257 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) 258 kfree(map[i].data.configs.configs); 259 } 260 261 kfree(map); 262} 263 264static const struct pinctrl_ops sunxi_pctrl_ops = { 265 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 266 .dt_free_map = sunxi_pctrl_dt_free_map, 267 .get_groups_count = sunxi_pctrl_get_groups_count, 268 .get_group_name = sunxi_pctrl_get_group_name, 269 .get_group_pins = sunxi_pctrl_get_group_pins, 270}; 271 272static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 273 unsigned group, 274 unsigned long *config) 275{ 276 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 277 278 *config = pctl->groups[group].config; 279 280 return 0; 281} 282 283static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, 284 unsigned group, 285 unsigned long *configs, 286 unsigned num_configs) 287{ 288 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 289 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 290 unsigned long flags; 291 unsigned pin = g->pin - pctl->desc->pin_base; 292 u32 val, mask; 293 u16 strength; 294 u8 dlevel; 295 int i; 296 297 spin_lock_irqsave(&pctl->lock, flags); 298 299 for (i = 0; i < num_configs; i++) { 300 switch (pinconf_to_config_param(configs[i])) { 301 case PIN_CONFIG_DRIVE_STRENGTH: 302 strength = pinconf_to_config_argument(configs[i]); 303 if (strength > 40) { 304 spin_unlock_irqrestore(&pctl->lock, flags); 305 return -EINVAL; 306 } 307 /* 308 * We convert from mA to what the register expects: 309 * 0: 10mA 310 * 1: 20mA 311 * 2: 30mA 312 * 3: 40mA 313 */ 314 dlevel = strength / 10 - 1; 315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); 316 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin); 317 writel((val & ~mask) 318 | dlevel << sunxi_dlevel_offset(pin), 319 pctl->membase + sunxi_dlevel_reg(pin)); 320 break; 321 case PIN_CONFIG_BIAS_PULL_UP: 322 val = readl(pctl->membase + sunxi_pull_reg(pin)); 323 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 324 writel((val & ~mask) | 1 << sunxi_pull_offset(pin), 325 pctl->membase + sunxi_pull_reg(pin)); 326 break; 327 case PIN_CONFIG_BIAS_PULL_DOWN: 328 val = readl(pctl->membase + sunxi_pull_reg(pin)); 329 mask = PULL_PINS_MASK << sunxi_pull_offset(pin); 330 writel((val & ~mask) | 2 << sunxi_pull_offset(pin), 331 pctl->membase + sunxi_pull_reg(pin)); 332 break; 333 default: 334 break; 335 } 336 /* cache the config value */ 337 g->config = configs[i]; 338 } /* for each config */ 339 340 spin_unlock_irqrestore(&pctl->lock, flags); 341 342 return 0; 343} 344 345static const struct pinconf_ops sunxi_pconf_ops = { 346 .pin_config_group_get = sunxi_pconf_group_get, 347 .pin_config_group_set = sunxi_pconf_group_set, 348}; 349 350static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 351{ 352 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 353 354 return pctl->nfunctions; 355} 356 357static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 358 unsigned function) 359{ 360 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 361 362 return pctl->functions[function].name; 363} 364 365static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 366 unsigned function, 367 const char * const **groups, 368 unsigned * const num_groups) 369{ 370 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 371 372 *groups = pctl->functions[function].groups; 373 *num_groups = pctl->functions[function].ngroups; 374 375 return 0; 376} 377 378static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 379 unsigned pin, 380 u8 config) 381{ 382 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 383 unsigned long flags; 384 u32 val, mask; 385 386 spin_lock_irqsave(&pctl->lock, flags); 387 388 pin -= pctl->desc->pin_base; 389 val = readl(pctl->membase + sunxi_mux_reg(pin)); 390 mask = MUX_PINS_MASK << sunxi_mux_offset(pin); 391 writel((val & ~mask) | config << sunxi_mux_offset(pin), 392 pctl->membase + sunxi_mux_reg(pin)); 393 394 spin_unlock_irqrestore(&pctl->lock, flags); 395} 396 397static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 398 unsigned function, 399 unsigned group) 400{ 401 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 402 struct sunxi_pinctrl_group *g = pctl->groups + group; 403 struct sunxi_pinctrl_function *func = pctl->functions + function; 404 struct sunxi_desc_function *desc = 405 sunxi_pinctrl_desc_find_function_by_name(pctl, 406 g->name, 407 func->name); 408 409 if (!desc) 410 return -EINVAL; 411 412 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 413 414 return 0; 415} 416 417static int 418sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 419 struct pinctrl_gpio_range *range, 420 unsigned offset, 421 bool input) 422{ 423 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 424 struct sunxi_desc_function *desc; 425 const char *func; 426 427 if (input) 428 func = "gpio_in"; 429 else 430 func = "gpio_out"; 431 432 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 433 if (!desc) 434 return -EINVAL; 435 436 sunxi_pmx_set(pctldev, offset, desc->muxval); 437 438 return 0; 439} 440 441static const struct pinmux_ops sunxi_pmx_ops = { 442 .get_functions_count = sunxi_pmx_get_funcs_cnt, 443 .get_function_name = sunxi_pmx_get_func_name, 444 .get_function_groups = sunxi_pmx_get_func_groups, 445 .set_mux = sunxi_pmx_set_mux, 446 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 447}; 448 449static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset) 450{ 451 return pinctrl_request_gpio(chip->base + offset); 452} 453 454static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset) 455{ 456 pinctrl_free_gpio(chip->base + offset); 457} 458 459static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 460 unsigned offset) 461{ 462 return pinctrl_gpio_direction_input(chip->base + offset); 463} 464 465static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 466{ 467 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 468 u32 reg = sunxi_data_reg(offset); 469 u8 index = sunxi_data_offset(offset); 470 u32 set_mux = pctl->desc->irq_read_needs_mux && 471 test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags); 472 u32 val; 473 474 if (set_mux) 475 sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT); 476 477 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; 478 479 if (set_mux) 480 sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ); 481 482 return val; 483} 484 485static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 486 unsigned offset, int value) 487{ 488 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 489 u32 reg = sunxi_data_reg(offset); 490 u8 index = sunxi_data_offset(offset); 491 unsigned long flags; 492 u32 regval; 493 494 spin_lock_irqsave(&pctl->lock, flags); 495 496 regval = readl(pctl->membase + reg); 497 498 if (value) 499 regval |= BIT(index); 500 else 501 regval &= ~(BIT(index)); 502 503 writel(regval, pctl->membase + reg); 504 505 spin_unlock_irqrestore(&pctl->lock, flags); 506} 507 508static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 509 unsigned offset, int value) 510{ 511 sunxi_pinctrl_gpio_set(chip, offset, value); 512 return pinctrl_gpio_direction_output(chip->base + offset); 513} 514 515static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 516 const struct of_phandle_args *gpiospec, 517 u32 *flags) 518{ 519 int pin, base; 520 521 base = PINS_PER_BANK * gpiospec->args[0]; 522 pin = base + gpiospec->args[1]; 523 524 if (pin > gc->ngpio) 525 return -EINVAL; 526 527 if (flags) 528 *flags = gpiospec->args[2]; 529 530 return pin; 531} 532 533static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 534{ 535 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev); 536 struct sunxi_desc_function *desc; 537 unsigned pinnum = pctl->desc->pin_base + offset; 538 unsigned irqnum; 539 540 if (offset >= chip->ngpio) 541 return -ENXIO; 542 543 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 544 if (!desc) 545 return -EINVAL; 546 547 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 548 549 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 550 chip->label, offset + chip->base, irqnum); 551 552 return irq_find_mapping(pctl->domain, irqnum); 553} 554 555static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 556{ 557 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 558 struct sunxi_desc_function *func; 559 int ret; 560 561 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 562 pctl->irq_array[d->hwirq], "irq"); 563 if (!func) 564 return -EINVAL; 565 566 ret = gpiochip_lock_as_irq(pctl->chip, 567 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 568 if (ret) { 569 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 570 irqd_to_hwirq(d)); 571 return ret; 572 } 573 574 /* Change muxing to INT mode */ 575 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 576 577 return 0; 578} 579 580static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 581{ 582 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 583 584 gpiochip_unlock_as_irq(pctl->chip, 585 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 586} 587 588static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 589{ 590 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 591 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data); 592 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 593 u8 index = sunxi_irq_cfg_offset(d->hwirq); 594 unsigned long flags; 595 u32 regval; 596 u8 mode; 597 598 switch (type) { 599 case IRQ_TYPE_EDGE_RISING: 600 mode = IRQ_EDGE_RISING; 601 break; 602 case IRQ_TYPE_EDGE_FALLING: 603 mode = IRQ_EDGE_FALLING; 604 break; 605 case IRQ_TYPE_EDGE_BOTH: 606 mode = IRQ_EDGE_BOTH; 607 break; 608 case IRQ_TYPE_LEVEL_HIGH: 609 mode = IRQ_LEVEL_HIGH; 610 break; 611 case IRQ_TYPE_LEVEL_LOW: 612 mode = IRQ_LEVEL_LOW; 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 if (type & IRQ_TYPE_LEVEL_MASK) { 619 d->chip = &sunxi_pinctrl_level_irq_chip; 620 desc->handle_irq = handle_fasteoi_irq; 621 } else { 622 d->chip = &sunxi_pinctrl_edge_irq_chip; 623 desc->handle_irq = handle_edge_irq; 624 } 625 626 spin_lock_irqsave(&pctl->lock, flags); 627 628 regval = readl(pctl->membase + reg); 629 regval &= ~(IRQ_CFG_IRQ_MASK << index); 630 writel(regval | (mode << index), pctl->membase + reg); 631 632 spin_unlock_irqrestore(&pctl->lock, flags); 633 634 return 0; 635} 636 637static void sunxi_pinctrl_irq_ack(struct irq_data *d) 638{ 639 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 640 u32 status_reg = sunxi_irq_status_reg(d->hwirq); 641 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 642 643 /* Clear the IRQ */ 644 writel(1 << status_idx, pctl->membase + status_reg); 645} 646 647static void sunxi_pinctrl_irq_mask(struct irq_data *d) 648{ 649 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 650 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 651 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 652 unsigned long flags; 653 u32 val; 654 655 spin_lock_irqsave(&pctl->lock, flags); 656 657 /* Mask the IRQ */ 658 val = readl(pctl->membase + reg); 659 writel(val & ~(1 << idx), pctl->membase + reg); 660 661 spin_unlock_irqrestore(&pctl->lock, flags); 662} 663 664static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 665{ 666 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 667 u32 reg = sunxi_irq_ctrl_reg(d->hwirq); 668 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 669 unsigned long flags; 670 u32 val; 671 672 spin_lock_irqsave(&pctl->lock, flags); 673 674 /* Unmask the IRQ */ 675 val = readl(pctl->membase + reg); 676 writel(val | (1 << idx), pctl->membase + reg); 677 678 spin_unlock_irqrestore(&pctl->lock, flags); 679} 680 681static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 682{ 683 sunxi_pinctrl_irq_ack(d); 684 sunxi_pinctrl_irq_unmask(d); 685} 686 687static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 688 .irq_ack = sunxi_pinctrl_irq_ack, 689 .irq_mask = sunxi_pinctrl_irq_mask, 690 .irq_unmask = sunxi_pinctrl_irq_unmask, 691 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 692 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 693 .irq_set_type = sunxi_pinctrl_irq_set_type, 694 .flags = IRQCHIP_SKIP_SET_WAKE, 695}; 696 697static struct irq_chip sunxi_pinctrl_level_irq_chip = { 698 .irq_eoi = sunxi_pinctrl_irq_ack, 699 .irq_mask = sunxi_pinctrl_irq_mask, 700 .irq_unmask = sunxi_pinctrl_irq_unmask, 701 /* Define irq_enable / disable to avoid spurious irqs for drivers 702 * using these to suppress irqs while they clear the irq source */ 703 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 704 .irq_disable = sunxi_pinctrl_irq_mask, 705 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 706 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 707 .irq_set_type = sunxi_pinctrl_irq_set_type, 708 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED | 709 IRQCHIP_EOI_IF_HANDLED, 710}; 711 712static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 713{ 714 struct irq_chip *chip = irq_get_chip(irq); 715 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 716 unsigned long bank, reg, val; 717 718 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 719 if (irq == pctl->irq[bank]) 720 break; 721 722 if (bank == pctl->desc->irq_banks) 723 return; 724 725 reg = sunxi_irq_status_reg_from_bank(bank); 726 val = readl(pctl->membase + reg); 727 728 if (val) { 729 int irqoffset; 730 731 chained_irq_enter(chip, desc); 732 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) { 733 int pin_irq = irq_find_mapping(pctl->domain, 734 bank * IRQ_PER_BANK + irqoffset); 735 generic_handle_irq(pin_irq); 736 } 737 chained_irq_exit(chip, desc); 738 } 739} 740 741static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 742 const char *name) 743{ 744 struct sunxi_pinctrl_function *func = pctl->functions; 745 746 while (func->name) { 747 /* function already there */ 748 if (strcmp(func->name, name) == 0) { 749 func->ngroups++; 750 return -EEXIST; 751 } 752 func++; 753 } 754 755 func->name = name; 756 func->ngroups = 1; 757 758 pctl->nfunctions++; 759 760 return 0; 761} 762 763static int sunxi_pinctrl_build_state(struct platform_device *pdev) 764{ 765 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 766 int i; 767 768 pctl->ngroups = pctl->desc->npins; 769 770 /* Allocate groups */ 771 pctl->groups = devm_kzalloc(&pdev->dev, 772 pctl->ngroups * sizeof(*pctl->groups), 773 GFP_KERNEL); 774 if (!pctl->groups) 775 return -ENOMEM; 776 777 for (i = 0; i < pctl->desc->npins; i++) { 778 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 779 struct sunxi_pinctrl_group *group = pctl->groups + i; 780 781 group->name = pin->pin.name; 782 group->pin = pin->pin.number; 783 } 784 785 /* 786 * We suppose that we won't have any more functions than pins, 787 * we'll reallocate that later anyway 788 */ 789 pctl->functions = devm_kzalloc(&pdev->dev, 790 pctl->desc->npins * sizeof(*pctl->functions), 791 GFP_KERNEL); 792 if (!pctl->functions) 793 return -ENOMEM; 794 795 /* Count functions and their associated groups */ 796 for (i = 0; i < pctl->desc->npins; i++) { 797 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 798 struct sunxi_desc_function *func = pin->functions; 799 800 while (func->name) { 801 /* Create interrupt mapping while we're at it */ 802 if (!strcmp(func->name, "irq")) { 803 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 804 pctl->irq_array[irqnum] = pin->pin.number; 805 } 806 807 sunxi_pinctrl_add_function(pctl, func->name); 808 func++; 809 } 810 } 811 812 pctl->functions = krealloc(pctl->functions, 813 pctl->nfunctions * sizeof(*pctl->functions), 814 GFP_KERNEL); 815 816 for (i = 0; i < pctl->desc->npins; i++) { 817 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 818 struct sunxi_desc_function *func = pin->functions; 819 820 while (func->name) { 821 struct sunxi_pinctrl_function *func_item; 822 const char **func_grp; 823 824 func_item = sunxi_pinctrl_find_function_by_name(pctl, 825 func->name); 826 if (!func_item) 827 return -EINVAL; 828 829 if (!func_item->groups) { 830 func_item->groups = 831 devm_kzalloc(&pdev->dev, 832 func_item->ngroups * sizeof(*func_item->groups), 833 GFP_KERNEL); 834 if (!func_item->groups) 835 return -ENOMEM; 836 } 837 838 func_grp = func_item->groups; 839 while (*func_grp) 840 func_grp++; 841 842 *func_grp = pin->pin.name; 843 func++; 844 } 845 } 846 847 return 0; 848} 849 850int sunxi_pinctrl_init(struct platform_device *pdev, 851 const struct sunxi_pinctrl_desc *desc) 852{ 853 struct device_node *node = pdev->dev.of_node; 854 struct pinctrl_desc *pctrl_desc; 855 struct pinctrl_pin_desc *pins; 856 struct sunxi_pinctrl *pctl; 857 struct resource *res; 858 int i, ret, last_pin; 859 struct clk *clk; 860 861 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 862 if (!pctl) 863 return -ENOMEM; 864 platform_set_drvdata(pdev, pctl); 865 866 spin_lock_init(&pctl->lock); 867 868 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 869 pctl->membase = devm_ioremap_resource(&pdev->dev, res); 870 if (IS_ERR(pctl->membase)) 871 return PTR_ERR(pctl->membase); 872 873 pctl->dev = &pdev->dev; 874 pctl->desc = desc; 875 876 pctl->irq_array = devm_kcalloc(&pdev->dev, 877 IRQ_PER_BANK * pctl->desc->irq_banks, 878 sizeof(*pctl->irq_array), 879 GFP_KERNEL); 880 if (!pctl->irq_array) 881 return -ENOMEM; 882 883 ret = sunxi_pinctrl_build_state(pdev); 884 if (ret) { 885 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 886 return ret; 887 } 888 889 pins = devm_kzalloc(&pdev->dev, 890 pctl->desc->npins * sizeof(*pins), 891 GFP_KERNEL); 892 if (!pins) 893 return -ENOMEM; 894 895 for (i = 0; i < pctl->desc->npins; i++) 896 pins[i] = pctl->desc->pins[i].pin; 897 898 pctrl_desc = devm_kzalloc(&pdev->dev, 899 sizeof(*pctrl_desc), 900 GFP_KERNEL); 901 if (!pctrl_desc) 902 return -ENOMEM; 903 904 pctrl_desc->name = dev_name(&pdev->dev); 905 pctrl_desc->owner = THIS_MODULE; 906 pctrl_desc->pins = pins; 907 pctrl_desc->npins = pctl->desc->npins; 908 pctrl_desc->confops = &sunxi_pconf_ops; 909 pctrl_desc->pctlops = &sunxi_pctrl_ops; 910 pctrl_desc->pmxops = &sunxi_pmx_ops; 911 912 pctl->pctl_dev = pinctrl_register(pctrl_desc, 913 &pdev->dev, pctl); 914 if (!pctl->pctl_dev) { 915 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 916 return -EINVAL; 917 } 918 919 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 920 if (!pctl->chip) { 921 ret = -ENOMEM; 922 goto pinctrl_error; 923 } 924 925 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 926 pctl->chip->owner = THIS_MODULE; 927 pctl->chip->request = sunxi_pinctrl_gpio_request, 928 pctl->chip->free = sunxi_pinctrl_gpio_free, 929 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, 930 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, 931 pctl->chip->get = sunxi_pinctrl_gpio_get, 932 pctl->chip->set = sunxi_pinctrl_gpio_set, 933 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, 934 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, 935 pctl->chip->of_gpio_n_cells = 3, 936 pctl->chip->can_sleep = false, 937 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 938 pctl->desc->pin_base; 939 pctl->chip->label = dev_name(&pdev->dev); 940 pctl->chip->dev = &pdev->dev; 941 pctl->chip->base = pctl->desc->pin_base; 942 943 ret = gpiochip_add(pctl->chip); 944 if (ret) 945 goto pinctrl_error; 946 947 for (i = 0; i < pctl->desc->npins; i++) { 948 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 949 950 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 951 pin->pin.number - pctl->desc->pin_base, 952 pin->pin.number, 1); 953 if (ret) 954 goto gpiochip_error; 955 } 956 957 clk = devm_clk_get(&pdev->dev, NULL); 958 if (IS_ERR(clk)) { 959 ret = PTR_ERR(clk); 960 goto gpiochip_error; 961 } 962 963 ret = clk_prepare_enable(clk); 964 if (ret) 965 goto gpiochip_error; 966 967 pctl->irq = devm_kcalloc(&pdev->dev, 968 pctl->desc->irq_banks, 969 sizeof(*pctl->irq), 970 GFP_KERNEL); 971 if (!pctl->irq) { 972 ret = -ENOMEM; 973 goto clk_error; 974 } 975 976 for (i = 0; i < pctl->desc->irq_banks; i++) { 977 pctl->irq[i] = platform_get_irq(pdev, i); 978 if (pctl->irq[i] < 0) { 979 ret = pctl->irq[i]; 980 goto clk_error; 981 } 982 } 983 984 pctl->domain = irq_domain_add_linear(node, 985 pctl->desc->irq_banks * IRQ_PER_BANK, 986 &irq_domain_simple_ops, 987 NULL); 988 if (!pctl->domain) { 989 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 990 ret = -ENOMEM; 991 goto clk_error; 992 } 993 994 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 995 int irqno = irq_create_mapping(pctl->domain, i); 996 997 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 998 handle_edge_irq); 999 irq_set_chip_data(irqno, pctl); 1000 }; 1001 1002 for (i = 0; i < pctl->desc->irq_banks; i++) { 1003 /* Mask and clear all IRQs before registering a handler */ 1004 writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i)); 1005 writel(0xffffffff, 1006 pctl->membase + sunxi_irq_status_reg_from_bank(i)); 1007 1008 irq_set_chained_handler(pctl->irq[i], 1009 sunxi_pinctrl_irq_handler); 1010 irq_set_handler_data(pctl->irq[i], pctl); 1011 } 1012 1013 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1014 1015 return 0; 1016 1017clk_error: 1018 clk_disable_unprepare(clk); 1019gpiochip_error: 1020 gpiochip_remove(pctl->chip); 1021pinctrl_error: 1022 pinctrl_unregister(pctl->pctl_dev); 1023 return ret; 1024} 1025