1/* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * * Neither the name of Intel Corporation nor the names of its 40 * contributors may be used to endorse or promote products derived 41 * from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56#include "isci.h" 57#include "host.h" 58#include "phy.h" 59#include "scu_event_codes.h" 60#include "probe_roms.h" 61 62#undef C 63#define C(a) (#a) 64static const char *phy_state_name(enum sci_phy_states state) 65{ 66 static const char * const strings[] = PHY_STATES; 67 68 return strings[state]; 69} 70#undef C 71 72/* Maximum arbitration wait time in micro-seconds */ 73#define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME (700) 74 75enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy) 76{ 77 return iphy->max_negotiated_speed; 78} 79 80static struct isci_host *phy_to_host(struct isci_phy *iphy) 81{ 82 struct isci_phy *table = iphy - iphy->phy_index; 83 struct isci_host *ihost = container_of(table, typeof(*ihost), phys[0]); 84 85 return ihost; 86} 87 88static struct device *sciphy_to_dev(struct isci_phy *iphy) 89{ 90 return &phy_to_host(iphy)->pdev->dev; 91} 92 93static enum sci_status 94sci_phy_transport_layer_initialization(struct isci_phy *iphy, 95 struct scu_transport_layer_registers __iomem *reg) 96{ 97 u32 tl_control; 98 99 iphy->transport_layer_registers = reg; 100 101 writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX, 102 &iphy->transport_layer_registers->stp_rni); 103 104 /* 105 * Hardware team recommends that we enable the STP prefetch for all 106 * transports 107 */ 108 tl_control = readl(&iphy->transport_layer_registers->control); 109 tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH); 110 writel(tl_control, &iphy->transport_layer_registers->control); 111 112 return SCI_SUCCESS; 113} 114 115static enum sci_status 116sci_phy_link_layer_initialization(struct isci_phy *iphy, 117 struct scu_link_layer_registers __iomem *llr) 118{ 119 struct isci_host *ihost = iphy->owning_port->owning_controller; 120 struct sci_phy_user_params *phy_user; 121 struct sci_phy_oem_params *phy_oem; 122 int phy_idx = iphy->phy_index; 123 struct sci_phy_cap phy_cap; 124 u32 phy_configuration; 125 u32 parity_check = 0; 126 u32 parity_count = 0; 127 u32 llctl, link_rate; 128 u32 clksm_value = 0; 129 u32 sp_timeouts = 0; 130 131 phy_user = &ihost->user_parameters.phys[phy_idx]; 132 phy_oem = &ihost->oem_parameters.phys[phy_idx]; 133 iphy->link_layer_registers = llr; 134 135 /* Set our IDENTIFY frame data */ 136 #define SCI_END_DEVICE 0x01 137 138 writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) | 139 SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) | 140 SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) | 141 SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) | 142 SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE), 143 &llr->transmit_identification); 144 145 /* Write the device SAS Address */ 146 writel(0xFEDCBA98, &llr->sas_device_name_high); 147 writel(phy_idx, &llr->sas_device_name_low); 148 149 /* Write the source SAS Address */ 150 writel(phy_oem->sas_address.high, &llr->source_sas_address_high); 151 writel(phy_oem->sas_address.low, &llr->source_sas_address_low); 152 153 /* Clear and Set the PHY Identifier */ 154 writel(0, &llr->identify_frame_phy_id); 155 writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id); 156 157 /* Change the initial state of the phy configuration register */ 158 phy_configuration = readl(&llr->phy_configuration); 159 160 /* Hold OOB state machine in reset */ 161 phy_configuration |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET); 162 writel(phy_configuration, &llr->phy_configuration); 163 164 /* Configure the SNW capabilities */ 165 phy_cap.all = 0; 166 phy_cap.start = 1; 167 phy_cap.gen3_no_ssc = 1; 168 phy_cap.gen2_no_ssc = 1; 169 phy_cap.gen1_no_ssc = 1; 170 if (ihost->oem_parameters.controller.do_enable_ssc) { 171 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe; 172 struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_idx]; 173 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev); 174 bool en_sas = false; 175 bool en_sata = false; 176 u32 sas_type = 0; 177 u32 sata_spread = 0x2; 178 u32 sas_spread = 0x2; 179 180 phy_cap.gen3_ssc = 1; 181 phy_cap.gen2_ssc = 1; 182 phy_cap.gen1_ssc = 1; 183 184 if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1) 185 en_sas = en_sata = true; 186 else { 187 sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level; 188 sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level; 189 190 if (sata_spread) 191 en_sata = true; 192 193 if (sas_spread) { 194 en_sas = true; 195 sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type; 196 } 197 198 } 199 200 if (en_sas) { 201 u32 reg; 202 203 reg = readl(&xcvr->afe_xcvr_control0); 204 reg |= (0x00100000 | (sas_type << 19)); 205 writel(reg, &xcvr->afe_xcvr_control0); 206 207 reg = readl(&xcvr->afe_tx_ssc_control); 208 reg |= sas_spread << 8; 209 writel(reg, &xcvr->afe_tx_ssc_control); 210 } 211 212 if (en_sata) { 213 u32 reg; 214 215 reg = readl(&xcvr->afe_tx_ssc_control); 216 reg |= sata_spread; 217 writel(reg, &xcvr->afe_tx_ssc_control); 218 219 reg = readl(&llr->stp_control); 220 reg |= 1 << 12; 221 writel(reg, &llr->stp_control); 222 } 223 } 224 225 /* The SAS specification indicates that the phy_capabilities that 226 * are transmitted shall have an even parity. Calculate the parity. 227 */ 228 parity_check = phy_cap.all; 229 while (parity_check != 0) { 230 if (parity_check & 0x1) 231 parity_count++; 232 parity_check >>= 1; 233 } 234 235 /* If parity indicates there are an odd number of bits set, then 236 * set the parity bit to 1 in the phy capabilities. 237 */ 238 if ((parity_count % 2) != 0) 239 phy_cap.parity = 1; 240 241 writel(phy_cap.all, &llr->phy_capabilities); 242 243 /* Set the enable spinup period but disable the ability to send 244 * notify enable spinup 245 */ 246 writel(SCU_ENSPINUP_GEN_VAL(COUNT, 247 phy_user->notify_enable_spin_up_insertion_frequency), 248 &llr->notify_enable_spinup_control); 249 250 /* Write the ALIGN Insertion Ferequency for connected phy and 251 * inpendent of connected state 252 */ 253 clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED, 254 phy_user->in_connection_align_insertion_frequency); 255 256 clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL, 257 phy_user->align_insertion_frequency); 258 259 writel(clksm_value, &llr->clock_skew_management); 260 261 if (is_c0(ihost->pdev) || is_c1(ihost->pdev)) { 262 writel(0x04210400, &llr->afe_lookup_table_control); 263 writel(0x020A7C05, &llr->sas_primitive_timeout); 264 } else 265 writel(0x02108421, &llr->afe_lookup_table_control); 266 267 llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT, 268 (u8)ihost->user_parameters.no_outbound_task_timeout); 269 270 switch (phy_user->max_speed_generation) { 271 case SCIC_SDS_PARM_GEN3_SPEED: 272 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3; 273 break; 274 case SCIC_SDS_PARM_GEN2_SPEED: 275 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2; 276 break; 277 default: 278 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1; 279 break; 280 } 281 llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate); 282 writel(llctl, &llr->link_layer_control); 283 284 sp_timeouts = readl(&llr->sas_phy_timeouts); 285 286 /* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */ 287 sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF); 288 289 /* Set RATE_CHANGE timeout value to 0x3B (59us). This ensures SCU can 290 * lock with 3Gb drive when SCU max rate is set to 1.5Gb. 291 */ 292 sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B); 293 294 writel(sp_timeouts, &llr->sas_phy_timeouts); 295 296 if (is_a2(ihost->pdev)) { 297 /* Program the max ARB time for the PHY to 700us so we 298 * inter-operate with the PMC expander which shuts down 299 * PHYs if the expander PHY generates too many breaks. 300 * This time value will guarantee that the initiator PHY 301 * will generate the break. 302 */ 303 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME, 304 &llr->maximum_arbitration_wait_timer_timeout); 305 } 306 307 /* Disable link layer hang detection, rely on the OS timeout for 308 * I/O timeouts. 309 */ 310 writel(0, &llr->link_layer_hang_detection_timeout); 311 312 /* We can exit the initial state to the stopped state */ 313 sci_change_state(&iphy->sm, SCI_PHY_STOPPED); 314 315 return SCI_SUCCESS; 316} 317 318static void phy_sata_timeout(unsigned long data) 319{ 320 struct sci_timer *tmr = (struct sci_timer *)data; 321 struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer); 322 struct isci_host *ihost = iphy->owning_port->owning_controller; 323 unsigned long flags; 324 325 spin_lock_irqsave(&ihost->scic_lock, flags); 326 327 if (tmr->cancel) 328 goto done; 329 330 dev_dbg(sciphy_to_dev(iphy), 331 "%s: SCIC SDS Phy 0x%p did not receive signature fis before " 332 "timeout.\n", 333 __func__, 334 iphy); 335 336 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 337done: 338 spin_unlock_irqrestore(&ihost->scic_lock, flags); 339} 340 341/** 342 * This method returns the port currently containing this phy. If the phy is 343 * currently contained by the dummy port, then the phy is considered to not 344 * be part of a port. 345 * @sci_phy: This parameter specifies the phy for which to retrieve the 346 * containing port. 347 * 348 * This method returns a handle to a port that contains the supplied phy. 349 * NULL This value is returned if the phy is not part of a real 350 * port (i.e. it's contained in the dummy port). !NULL All other 351 * values indicate a handle/pointer to the port containing the phy. 352 */ 353struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy) 354{ 355 struct isci_port *iport = iphy->owning_port; 356 357 if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT) 358 return NULL; 359 360 return iphy->owning_port; 361} 362 363/** 364 * This method will assign a port to the phy object. 365 * @out]: iphy This parameter specifies the phy for which to assign a port 366 * object. 367 * 368 * 369 */ 370void sci_phy_set_port( 371 struct isci_phy *iphy, 372 struct isci_port *iport) 373{ 374 iphy->owning_port = iport; 375 376 if (iphy->bcn_received_while_port_unassigned) { 377 iphy->bcn_received_while_port_unassigned = false; 378 sci_port_broadcast_change_received(iphy->owning_port, iphy); 379 } 380} 381 382enum sci_status sci_phy_initialize(struct isci_phy *iphy, 383 struct scu_transport_layer_registers __iomem *tl, 384 struct scu_link_layer_registers __iomem *ll) 385{ 386 /* Perfrom the initialization of the TL hardware */ 387 sci_phy_transport_layer_initialization(iphy, tl); 388 389 /* Perofrm the initialization of the PE hardware */ 390 sci_phy_link_layer_initialization(iphy, ll); 391 392 /* There is nothing that needs to be done in this state just 393 * transition to the stopped state 394 */ 395 sci_change_state(&iphy->sm, SCI_PHY_STOPPED); 396 397 return SCI_SUCCESS; 398} 399 400/** 401 * This method assigns the direct attached device ID for this phy. 402 * 403 * @iphy The phy for which the direct attached device id is to 404 * be assigned. 405 * @device_id The direct attached device ID to assign to the phy. 406 * This will either be the RNi for the device or an invalid RNi if there 407 * is no current device assigned to the phy. 408 */ 409void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id) 410{ 411 u32 tl_control; 412 413 writel(device_id, &iphy->transport_layer_registers->stp_rni); 414 415 /* 416 * The read should guarantee that the first write gets posted 417 * before the next write 418 */ 419 tl_control = readl(&iphy->transport_layer_registers->control); 420 tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE); 421 writel(tl_control, &iphy->transport_layer_registers->control); 422} 423 424static void sci_phy_suspend(struct isci_phy *iphy) 425{ 426 u32 scu_sas_pcfg_value; 427 428 scu_sas_pcfg_value = 429 readl(&iphy->link_layer_registers->phy_configuration); 430 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE); 431 writel(scu_sas_pcfg_value, 432 &iphy->link_layer_registers->phy_configuration); 433 434 sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX); 435} 436 437void sci_phy_resume(struct isci_phy *iphy) 438{ 439 u32 scu_sas_pcfg_value; 440 441 scu_sas_pcfg_value = 442 readl(&iphy->link_layer_registers->phy_configuration); 443 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE); 444 writel(scu_sas_pcfg_value, 445 &iphy->link_layer_registers->phy_configuration); 446} 447 448void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas) 449{ 450 sas->high = readl(&iphy->link_layer_registers->source_sas_address_high); 451 sas->low = readl(&iphy->link_layer_registers->source_sas_address_low); 452} 453 454void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas) 455{ 456 struct sas_identify_frame *iaf; 457 458 iaf = &iphy->frame_rcvd.iaf; 459 memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE); 460} 461 462void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto) 463{ 464 proto->all = readl(&iphy->link_layer_registers->transmit_identification); 465} 466 467enum sci_status sci_phy_start(struct isci_phy *iphy) 468{ 469 enum sci_phy_states state = iphy->sm.current_state_id; 470 471 if (state != SCI_PHY_STOPPED) { 472 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", 473 __func__, phy_state_name(state)); 474 return SCI_FAILURE_INVALID_STATE; 475 } 476 477 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 478 return SCI_SUCCESS; 479} 480 481enum sci_status sci_phy_stop(struct isci_phy *iphy) 482{ 483 enum sci_phy_states state = iphy->sm.current_state_id; 484 485 switch (state) { 486 case SCI_PHY_SUB_INITIAL: 487 case SCI_PHY_SUB_AWAIT_OSSP_EN: 488 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: 489 case SCI_PHY_SUB_AWAIT_SAS_POWER: 490 case SCI_PHY_SUB_AWAIT_SATA_POWER: 491 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: 492 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: 493 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: 494 case SCI_PHY_SUB_FINAL: 495 case SCI_PHY_READY: 496 break; 497 default: 498 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", 499 __func__, phy_state_name(state)); 500 return SCI_FAILURE_INVALID_STATE; 501 } 502 503 sci_change_state(&iphy->sm, SCI_PHY_STOPPED); 504 return SCI_SUCCESS; 505} 506 507enum sci_status sci_phy_reset(struct isci_phy *iphy) 508{ 509 enum sci_phy_states state = iphy->sm.current_state_id; 510 511 if (state != SCI_PHY_READY) { 512 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", 513 __func__, phy_state_name(state)); 514 return SCI_FAILURE_INVALID_STATE; 515 } 516 517 sci_change_state(&iphy->sm, SCI_PHY_RESETTING); 518 return SCI_SUCCESS; 519} 520 521enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy) 522{ 523 enum sci_phy_states state = iphy->sm.current_state_id; 524 525 switch (state) { 526 case SCI_PHY_SUB_AWAIT_SAS_POWER: { 527 u32 enable_spinup; 528 529 enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control); 530 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE); 531 writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control); 532 533 /* Change state to the final state this substate machine has run to completion */ 534 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL); 535 536 return SCI_SUCCESS; 537 } 538 case SCI_PHY_SUB_AWAIT_SATA_POWER: { 539 u32 scu_sas_pcfg_value; 540 541 /* Release the spinup hold state and reset the OOB state machine */ 542 scu_sas_pcfg_value = 543 readl(&iphy->link_layer_registers->phy_configuration); 544 scu_sas_pcfg_value &= 545 ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE)); 546 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET); 547 writel(scu_sas_pcfg_value, 548 &iphy->link_layer_registers->phy_configuration); 549 550 /* Now restart the OOB operation */ 551 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET); 552 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); 553 writel(scu_sas_pcfg_value, 554 &iphy->link_layer_registers->phy_configuration); 555 556 /* Change state to the final state this substate machine has run to completion */ 557 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN); 558 559 return SCI_SUCCESS; 560 } 561 default: 562 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", 563 __func__, phy_state_name(state)); 564 return SCI_FAILURE_INVALID_STATE; 565 } 566} 567 568static void sci_phy_start_sas_link_training(struct isci_phy *iphy) 569{ 570 /* continue the link training for the phy as if it were a SAS PHY 571 * instead of a SATA PHY. This is done because the completion queue had a SAS 572 * PHY DETECTED event when the state machine was expecting a SATA PHY event. 573 */ 574 u32 phy_control; 575 576 phy_control = readl(&iphy->link_layer_registers->phy_configuration); 577 phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD); 578 writel(phy_control, 579 &iphy->link_layer_registers->phy_configuration); 580 581 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN); 582 583 iphy->protocol = SAS_PROTOCOL_SSP; 584} 585 586static void sci_phy_start_sata_link_training(struct isci_phy *iphy) 587{ 588 /* This method continues the link training for the phy as if it were a SATA PHY 589 * instead of a SAS PHY. This is done because the completion queue had a SATA 590 * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none 591 */ 592 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER); 593 594 iphy->protocol = SAS_PROTOCOL_SATA; 595} 596 597/** 598 * sci_phy_complete_link_training - perform processing common to 599 * all protocols upon completion of link training. 600 * @sci_phy: This parameter specifies the phy object for which link training 601 * has completed. 602 * @max_link_rate: This parameter specifies the maximum link rate to be 603 * associated with this phy. 604 * @next_state: This parameter specifies the next state for the phy's starting 605 * sub-state machine. 606 * 607 */ 608static void sci_phy_complete_link_training(struct isci_phy *iphy, 609 enum sas_linkrate max_link_rate, 610 u32 next_state) 611{ 612 iphy->max_negotiated_speed = max_link_rate; 613 614 sci_change_state(&iphy->sm, next_state); 615} 616 617static const char *phy_event_name(u32 event_code) 618{ 619 switch (scu_get_event_code(event_code)) { 620 case SCU_EVENT_PORT_SELECTOR_DETECTED: 621 return "port selector"; 622 case SCU_EVENT_SENT_PORT_SELECTION: 623 return "port selection"; 624 case SCU_EVENT_HARD_RESET_TRANSMITTED: 625 return "tx hard reset"; 626 case SCU_EVENT_HARD_RESET_RECEIVED: 627 return "rx hard reset"; 628 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT: 629 return "identify timeout"; 630 case SCU_EVENT_LINK_FAILURE: 631 return "link fail"; 632 case SCU_EVENT_SATA_SPINUP_HOLD: 633 return "sata spinup hold"; 634 case SCU_EVENT_SAS_15_SSC: 635 case SCU_EVENT_SAS_15: 636 return "sas 1.5"; 637 case SCU_EVENT_SAS_30_SSC: 638 case SCU_EVENT_SAS_30: 639 return "sas 3.0"; 640 case SCU_EVENT_SAS_60_SSC: 641 case SCU_EVENT_SAS_60: 642 return "sas 6.0"; 643 case SCU_EVENT_SATA_15_SSC: 644 case SCU_EVENT_SATA_15: 645 return "sata 1.5"; 646 case SCU_EVENT_SATA_30_SSC: 647 case SCU_EVENT_SATA_30: 648 return "sata 3.0"; 649 case SCU_EVENT_SATA_60_SSC: 650 case SCU_EVENT_SATA_60: 651 return "sata 6.0"; 652 case SCU_EVENT_SAS_PHY_DETECTED: 653 return "sas detect"; 654 case SCU_EVENT_SATA_PHY_DETECTED: 655 return "sata detect"; 656 default: 657 return "unknown"; 658 } 659} 660 661#define phy_event_dbg(iphy, state, code) \ 662 dev_dbg(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \ 663 phy_to_host(iphy)->id, iphy->phy_index, \ 664 phy_state_name(state), phy_event_name(code), code) 665 666#define phy_event_warn(iphy, state, code) \ 667 dev_warn(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \ 668 phy_to_host(iphy)->id, iphy->phy_index, \ 669 phy_state_name(state), phy_event_name(code), code) 670 671 672void scu_link_layer_set_txcomsas_timeout(struct isci_phy *iphy, u32 timeout) 673{ 674 u32 val; 675 676 /* Extend timeout */ 677 val = readl(&iphy->link_layer_registers->transmit_comsas_signal); 678 val &= ~SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK); 679 val |= SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, timeout); 680 681 writel(val, &iphy->link_layer_registers->transmit_comsas_signal); 682} 683 684enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code) 685{ 686 enum sci_phy_states state = iphy->sm.current_state_id; 687 688 switch (state) { 689 case SCI_PHY_SUB_AWAIT_OSSP_EN: 690 switch (scu_get_event_code(event_code)) { 691 case SCU_EVENT_SAS_PHY_DETECTED: 692 sci_phy_start_sas_link_training(iphy); 693 iphy->is_in_link_training = true; 694 break; 695 case SCU_EVENT_SATA_SPINUP_HOLD: 696 sci_phy_start_sata_link_training(iphy); 697 iphy->is_in_link_training = true; 698 break; 699 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT: 700 /* Extend timeout value */ 701 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED); 702 703 /* Start the oob/sn state machine over again */ 704 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 705 break; 706 default: 707 phy_event_dbg(iphy, state, event_code); 708 return SCI_FAILURE; 709 } 710 return SCI_SUCCESS; 711 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: 712 switch (scu_get_event_code(event_code)) { 713 case SCU_EVENT_SAS_PHY_DETECTED: 714 /* 715 * Why is this being reported again by the controller? 716 * We would re-enter this state so just stay here */ 717 break; 718 case SCU_EVENT_SAS_15: 719 case SCU_EVENT_SAS_15_SSC: 720 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS, 721 SCI_PHY_SUB_AWAIT_IAF_UF); 722 break; 723 case SCU_EVENT_SAS_30: 724 case SCU_EVENT_SAS_30_SSC: 725 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS, 726 SCI_PHY_SUB_AWAIT_IAF_UF); 727 break; 728 case SCU_EVENT_SAS_60: 729 case SCU_EVENT_SAS_60_SSC: 730 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS, 731 SCI_PHY_SUB_AWAIT_IAF_UF); 732 break; 733 case SCU_EVENT_SATA_SPINUP_HOLD: 734 /* 735 * We were doing SAS PHY link training and received a SATA PHY event 736 * continue OOB/SN as if this were a SATA PHY */ 737 sci_phy_start_sata_link_training(iphy); 738 break; 739 case SCU_EVENT_LINK_FAILURE: 740 /* Change the timeout value to default */ 741 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 742 743 /* Link failure change state back to the starting state */ 744 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 745 break; 746 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT: 747 /* Extend the timeout value */ 748 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED); 749 750 /* Start the oob/sn state machine over again */ 751 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 752 break; 753 default: 754 phy_event_warn(iphy, state, event_code); 755 return SCI_FAILURE; 756 break; 757 } 758 return SCI_SUCCESS; 759 case SCI_PHY_SUB_AWAIT_IAF_UF: 760 switch (scu_get_event_code(event_code)) { 761 case SCU_EVENT_SAS_PHY_DETECTED: 762 /* Backup the state machine */ 763 sci_phy_start_sas_link_training(iphy); 764 break; 765 case SCU_EVENT_SATA_SPINUP_HOLD: 766 /* We were doing SAS PHY link training and received a 767 * SATA PHY event continue OOB/SN as if this were a 768 * SATA PHY 769 */ 770 sci_phy_start_sata_link_training(iphy); 771 break; 772 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT: 773 /* Extend the timeout value */ 774 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED); 775 776 /* Start the oob/sn state machine over again */ 777 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 778 break; 779 case SCU_EVENT_LINK_FAILURE: 780 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 781 case SCU_EVENT_HARD_RESET_RECEIVED: 782 /* Start the oob/sn state machine over again */ 783 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 784 break; 785 default: 786 phy_event_warn(iphy, state, event_code); 787 return SCI_FAILURE; 788 } 789 return SCI_SUCCESS; 790 case SCI_PHY_SUB_AWAIT_SAS_POWER: 791 switch (scu_get_event_code(event_code)) { 792 case SCU_EVENT_LINK_FAILURE: 793 /* Change the timeout value to default */ 794 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 795 796 /* Link failure change state back to the starting state */ 797 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 798 break; 799 default: 800 phy_event_warn(iphy, state, event_code); 801 return SCI_FAILURE; 802 } 803 return SCI_SUCCESS; 804 case SCI_PHY_SUB_AWAIT_SATA_POWER: 805 switch (scu_get_event_code(event_code)) { 806 case SCU_EVENT_LINK_FAILURE: 807 /* Change the timeout value to default */ 808 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 809 810 /* Link failure change state back to the starting state */ 811 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 812 break; 813 case SCU_EVENT_SATA_SPINUP_HOLD: 814 /* These events are received every 10ms and are 815 * expected while in this state 816 */ 817 break; 818 819 case SCU_EVENT_SAS_PHY_DETECTED: 820 /* There has been a change in the phy type before OOB/SN for the 821 * SATA finished start down the SAS link traning path. 822 */ 823 sci_phy_start_sas_link_training(iphy); 824 break; 825 826 default: 827 phy_event_warn(iphy, state, event_code); 828 return SCI_FAILURE; 829 } 830 return SCI_SUCCESS; 831 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: 832 switch (scu_get_event_code(event_code)) { 833 case SCU_EVENT_LINK_FAILURE: 834 /* Change the timeout value to default */ 835 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 836 837 /* Link failure change state back to the starting state */ 838 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 839 break; 840 case SCU_EVENT_SATA_SPINUP_HOLD: 841 /* These events might be received since we dont know how many may be in 842 * the completion queue while waiting for power 843 */ 844 break; 845 case SCU_EVENT_SATA_PHY_DETECTED: 846 iphy->protocol = SAS_PROTOCOL_SATA; 847 848 /* We have received the SATA PHY notification change state */ 849 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN); 850 break; 851 case SCU_EVENT_SAS_PHY_DETECTED: 852 /* There has been a change in the phy type before OOB/SN for the 853 * SATA finished start down the SAS link traning path. 854 */ 855 sci_phy_start_sas_link_training(iphy); 856 break; 857 default: 858 phy_event_warn(iphy, state, event_code); 859 return SCI_FAILURE; 860 } 861 return SCI_SUCCESS; 862 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: 863 switch (scu_get_event_code(event_code)) { 864 case SCU_EVENT_SATA_PHY_DETECTED: 865 /* 866 * The hardware reports multiple SATA PHY detected events 867 * ignore the extras */ 868 break; 869 case SCU_EVENT_SATA_15: 870 case SCU_EVENT_SATA_15_SSC: 871 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS, 872 SCI_PHY_SUB_AWAIT_SIG_FIS_UF); 873 break; 874 case SCU_EVENT_SATA_30: 875 case SCU_EVENT_SATA_30_SSC: 876 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS, 877 SCI_PHY_SUB_AWAIT_SIG_FIS_UF); 878 break; 879 case SCU_EVENT_SATA_60: 880 case SCU_EVENT_SATA_60_SSC: 881 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS, 882 SCI_PHY_SUB_AWAIT_SIG_FIS_UF); 883 break; 884 case SCU_EVENT_LINK_FAILURE: 885 /* Change the timeout value to default */ 886 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 887 888 /* Link failure change state back to the starting state */ 889 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 890 break; 891 case SCU_EVENT_SAS_PHY_DETECTED: 892 /* 893 * There has been a change in the phy type before OOB/SN for the 894 * SATA finished start down the SAS link traning path. */ 895 sci_phy_start_sas_link_training(iphy); 896 break; 897 default: 898 phy_event_warn(iphy, state, event_code); 899 return SCI_FAILURE; 900 } 901 902 return SCI_SUCCESS; 903 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: 904 switch (scu_get_event_code(event_code)) { 905 case SCU_EVENT_SATA_PHY_DETECTED: 906 /* Backup the state machine */ 907 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN); 908 break; 909 910 case SCU_EVENT_LINK_FAILURE: 911 /* Change the timeout value to default */ 912 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 913 914 /* Link failure change state back to the starting state */ 915 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 916 break; 917 918 default: 919 phy_event_warn(iphy, state, event_code); 920 return SCI_FAILURE; 921 } 922 return SCI_SUCCESS; 923 case SCI_PHY_READY: 924 switch (scu_get_event_code(event_code)) { 925 case SCU_EVENT_LINK_FAILURE: 926 /* Set default timeout */ 927 scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT); 928 929 /* Link failure change state back to the starting state */ 930 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 931 break; 932 case SCU_EVENT_BROADCAST_CHANGE: 933 case SCU_EVENT_BROADCAST_SES: 934 case SCU_EVENT_BROADCAST_RESERVED0: 935 case SCU_EVENT_BROADCAST_RESERVED1: 936 case SCU_EVENT_BROADCAST_EXPANDER: 937 case SCU_EVENT_BROADCAST_AEN: 938 /* Broadcast change received. Notify the port. */ 939 if (phy_get_non_dummy_port(iphy) != NULL) 940 sci_port_broadcast_change_received(iphy->owning_port, iphy); 941 else 942 iphy->bcn_received_while_port_unassigned = true; 943 break; 944 case SCU_EVENT_BROADCAST_RESERVED3: 945 case SCU_EVENT_BROADCAST_RESERVED4: 946 default: 947 phy_event_warn(iphy, state, event_code); 948 return SCI_FAILURE_INVALID_STATE; 949 } 950 return SCI_SUCCESS; 951 case SCI_PHY_RESETTING: 952 switch (scu_get_event_code(event_code)) { 953 case SCU_EVENT_HARD_RESET_TRANSMITTED: 954 /* Link failure change state back to the starting state */ 955 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 956 break; 957 default: 958 phy_event_warn(iphy, state, event_code); 959 return SCI_FAILURE_INVALID_STATE; 960 break; 961 } 962 return SCI_SUCCESS; 963 default: 964 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", 965 __func__, phy_state_name(state)); 966 return SCI_FAILURE_INVALID_STATE; 967 } 968} 969 970enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index) 971{ 972 enum sci_phy_states state = iphy->sm.current_state_id; 973 struct isci_host *ihost = iphy->owning_port->owning_controller; 974 enum sci_status result; 975 unsigned long flags; 976 977 switch (state) { 978 case SCI_PHY_SUB_AWAIT_IAF_UF: { 979 u32 *frame_words; 980 struct sas_identify_frame iaf; 981 982 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control, 983 frame_index, 984 (void **)&frame_words); 985 986 if (result != SCI_SUCCESS) 987 return result; 988 989 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32)); 990 if (iaf.frame_type == 0) { 991 u32 state; 992 993 spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags); 994 memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf)); 995 spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags); 996 if (iaf.smp_tport) { 997 /* We got the IAF for an expander PHY go to the final 998 * state since there are no power requirements for 999 * expander phys. 1000 */ 1001 state = SCI_PHY_SUB_FINAL; 1002 } else { 1003 /* We got the IAF we can now go to the await spinup 1004 * semaphore state 1005 */ 1006 state = SCI_PHY_SUB_AWAIT_SAS_POWER; 1007 } 1008 sci_change_state(&iphy->sm, state); 1009 result = SCI_SUCCESS; 1010 } else 1011 dev_warn(sciphy_to_dev(iphy), 1012 "%s: PHY starting substate machine received " 1013 "unexpected frame id %x\n", 1014 __func__, frame_index); 1015 1016 sci_controller_release_frame(ihost, frame_index); 1017 return result; 1018 } 1019 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: { 1020 struct dev_to_host_fis *frame_header; 1021 u32 *fis_frame_data; 1022 1023 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control, 1024 frame_index, 1025 (void **)&frame_header); 1026 1027 if (result != SCI_SUCCESS) 1028 return result; 1029 1030 if ((frame_header->fis_type == FIS_REGD2H) && 1031 !(frame_header->status & ATA_BUSY)) { 1032 sci_unsolicited_frame_control_get_buffer(&ihost->uf_control, 1033 frame_index, 1034 (void **)&fis_frame_data); 1035 1036 spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags); 1037 sci_controller_copy_sata_response(&iphy->frame_rcvd.fis, 1038 frame_header, 1039 fis_frame_data); 1040 spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags); 1041 1042 /* got IAF we can now go to the await spinup semaphore state */ 1043 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL); 1044 1045 result = SCI_SUCCESS; 1046 } else 1047 dev_warn(sciphy_to_dev(iphy), 1048 "%s: PHY starting substate machine received " 1049 "unexpected frame id %x\n", 1050 __func__, frame_index); 1051 1052 /* Regardless of the result we are done with this frame with it */ 1053 sci_controller_release_frame(ihost, frame_index); 1054 1055 return result; 1056 } 1057 default: 1058 dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n", 1059 __func__, phy_state_name(state)); 1060 return SCI_FAILURE_INVALID_STATE; 1061 } 1062 1063} 1064 1065static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm) 1066{ 1067 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1068 1069 /* This is just an temporary state go off to the starting state */ 1070 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN); 1071} 1072 1073static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm) 1074{ 1075 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1076 struct isci_host *ihost = iphy->owning_port->owning_controller; 1077 1078 sci_controller_power_control_queue_insert(ihost, iphy); 1079} 1080 1081static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm) 1082{ 1083 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1084 struct isci_host *ihost = iphy->owning_port->owning_controller; 1085 1086 sci_controller_power_control_queue_remove(ihost, iphy); 1087} 1088 1089static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm) 1090{ 1091 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1092 struct isci_host *ihost = iphy->owning_port->owning_controller; 1093 1094 sci_controller_power_control_queue_insert(ihost, iphy); 1095} 1096 1097static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm) 1098{ 1099 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1100 struct isci_host *ihost = iphy->owning_port->owning_controller; 1101 1102 sci_controller_power_control_queue_remove(ihost, iphy); 1103} 1104 1105static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm) 1106{ 1107 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1108 1109 sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT); 1110} 1111 1112static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm) 1113{ 1114 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1115 1116 sci_del_timer(&iphy->sata_timer); 1117} 1118 1119static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm) 1120{ 1121 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1122 1123 sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT); 1124} 1125 1126static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm) 1127{ 1128 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1129 1130 sci_del_timer(&iphy->sata_timer); 1131} 1132 1133static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm) 1134{ 1135 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1136 1137 if (sci_port_link_detected(iphy->owning_port, iphy)) { 1138 1139 /* 1140 * Clear the PE suspend condition so we can actually 1141 * receive SIG FIS 1142 * The hardware will not respond to the XRDY until the PE 1143 * suspend condition is cleared. 1144 */ 1145 sci_phy_resume(iphy); 1146 1147 sci_mod_timer(&iphy->sata_timer, 1148 SCIC_SDS_SIGNATURE_FIS_TIMEOUT); 1149 } else 1150 iphy->is_in_link_training = false; 1151} 1152 1153static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm) 1154{ 1155 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1156 1157 sci_del_timer(&iphy->sata_timer); 1158} 1159 1160static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm) 1161{ 1162 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1163 1164 /* State machine has run to completion so exit out and change 1165 * the base state machine to the ready state 1166 */ 1167 sci_change_state(&iphy->sm, SCI_PHY_READY); 1168} 1169 1170/** 1171 * 1172 * @sci_phy: This is the struct isci_phy object to stop. 1173 * 1174 * This method will stop the struct isci_phy object. This does not reset the 1175 * protocol engine it just suspends it and places it in a state where it will 1176 * not cause the end device to power up. none 1177 */ 1178static void scu_link_layer_stop_protocol_engine( 1179 struct isci_phy *iphy) 1180{ 1181 u32 scu_sas_pcfg_value; 1182 u32 enable_spinup_value; 1183 1184 /* Suspend the protocol engine and place it in a sata spinup hold state */ 1185 scu_sas_pcfg_value = 1186 readl(&iphy->link_layer_registers->phy_configuration); 1187 scu_sas_pcfg_value |= 1188 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) | 1189 SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) | 1190 SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD)); 1191 writel(scu_sas_pcfg_value, 1192 &iphy->link_layer_registers->phy_configuration); 1193 1194 /* Disable the notify enable spinup primitives */ 1195 enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control); 1196 enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE); 1197 writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control); 1198} 1199 1200static void scu_link_layer_start_oob(struct isci_phy *iphy) 1201{ 1202 struct scu_link_layer_registers __iomem *ll = iphy->link_layer_registers; 1203 u32 val; 1204 1205 /** Reset OOB sequence - start */ 1206 val = readl(&ll->phy_configuration); 1207 val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) | 1208 SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE) | 1209 SCU_SAS_PCFG_GEN_BIT(HARD_RESET)); 1210 writel(val, &ll->phy_configuration); 1211 readl(&ll->phy_configuration); /* flush */ 1212 /** Reset OOB sequence - end */ 1213 1214 /** Start OOB sequence - start */ 1215 val = readl(&ll->phy_configuration); 1216 val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); 1217 writel(val, &ll->phy_configuration); 1218 readl(&ll->phy_configuration); /* flush */ 1219 /** Start OOB sequence - end */ 1220} 1221 1222/** 1223 * 1224 * 1225 * This method will transmit a hard reset request on the specified phy. The SCU 1226 * hardware requires that we reset the OOB state machine and set the hard reset 1227 * bit in the phy configuration register. We then must start OOB over with the 1228 * hard reset bit set. 1229 */ 1230static void scu_link_layer_tx_hard_reset( 1231 struct isci_phy *iphy) 1232{ 1233 u32 phy_configuration_value; 1234 1235 /* 1236 * SAS Phys must wait for the HARD_RESET_TX event notification to transition 1237 * to the starting state. */ 1238 phy_configuration_value = 1239 readl(&iphy->link_layer_registers->phy_configuration); 1240 phy_configuration_value &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE)); 1241 phy_configuration_value |= 1242 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) | 1243 SCU_SAS_PCFG_GEN_BIT(OOB_RESET)); 1244 writel(phy_configuration_value, 1245 &iphy->link_layer_registers->phy_configuration); 1246 1247 /* Now take the OOB state machine out of reset */ 1248 phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE); 1249 phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET); 1250 writel(phy_configuration_value, 1251 &iphy->link_layer_registers->phy_configuration); 1252} 1253 1254static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm) 1255{ 1256 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1257 struct isci_port *iport = iphy->owning_port; 1258 struct isci_host *ihost = iport->owning_controller; 1259 1260 /* 1261 * @todo We need to get to the controller to place this PE in a 1262 * reset state 1263 */ 1264 sci_del_timer(&iphy->sata_timer); 1265 1266 scu_link_layer_stop_protocol_engine(iphy); 1267 1268 if (iphy->sm.previous_state_id != SCI_PHY_INITIAL) 1269 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy); 1270} 1271 1272static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm) 1273{ 1274 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1275 struct isci_port *iport = iphy->owning_port; 1276 struct isci_host *ihost = iport->owning_controller; 1277 1278 scu_link_layer_stop_protocol_engine(iphy); 1279 scu_link_layer_start_oob(iphy); 1280 1281 /* We don't know what kind of phy we are going to be just yet */ 1282 iphy->protocol = SAS_PROTOCOL_NONE; 1283 iphy->bcn_received_while_port_unassigned = false; 1284 1285 if (iphy->sm.previous_state_id == SCI_PHY_READY) 1286 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy); 1287 1288 sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL); 1289} 1290 1291static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm) 1292{ 1293 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1294 struct isci_port *iport = iphy->owning_port; 1295 struct isci_host *ihost = iport->owning_controller; 1296 1297 sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy); 1298} 1299 1300static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm) 1301{ 1302 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1303 1304 sci_phy_suspend(iphy); 1305} 1306 1307static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm) 1308{ 1309 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm); 1310 1311 /* The phy is being reset, therefore deactivate it from the port. In 1312 * the resetting state we don't notify the user regarding link up and 1313 * link down notifications 1314 */ 1315 sci_port_deactivate_phy(iphy->owning_port, iphy, false); 1316 1317 if (iphy->protocol == SAS_PROTOCOL_SSP) { 1318 scu_link_layer_tx_hard_reset(iphy); 1319 } else { 1320 /* The SCU does not need to have a discrete reset state so 1321 * just go back to the starting state. 1322 */ 1323 sci_change_state(&iphy->sm, SCI_PHY_STARTING); 1324 } 1325} 1326 1327static const struct sci_base_state sci_phy_state_table[] = { 1328 [SCI_PHY_INITIAL] = { }, 1329 [SCI_PHY_STOPPED] = { 1330 .enter_state = sci_phy_stopped_state_enter, 1331 }, 1332 [SCI_PHY_STARTING] = { 1333 .enter_state = sci_phy_starting_state_enter, 1334 }, 1335 [SCI_PHY_SUB_INITIAL] = { 1336 .enter_state = sci_phy_starting_initial_substate_enter, 1337 }, 1338 [SCI_PHY_SUB_AWAIT_OSSP_EN] = { }, 1339 [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { }, 1340 [SCI_PHY_SUB_AWAIT_IAF_UF] = { }, 1341 [SCI_PHY_SUB_AWAIT_SAS_POWER] = { 1342 .enter_state = sci_phy_starting_await_sas_power_substate_enter, 1343 .exit_state = sci_phy_starting_await_sas_power_substate_exit, 1344 }, 1345 [SCI_PHY_SUB_AWAIT_SATA_POWER] = { 1346 .enter_state = sci_phy_starting_await_sata_power_substate_enter, 1347 .exit_state = sci_phy_starting_await_sata_power_substate_exit 1348 }, 1349 [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = { 1350 .enter_state = sci_phy_starting_await_sata_phy_substate_enter, 1351 .exit_state = sci_phy_starting_await_sata_phy_substate_exit 1352 }, 1353 [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = { 1354 .enter_state = sci_phy_starting_await_sata_speed_substate_enter, 1355 .exit_state = sci_phy_starting_await_sata_speed_substate_exit 1356 }, 1357 [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = { 1358 .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter, 1359 .exit_state = sci_phy_starting_await_sig_fis_uf_substate_exit 1360 }, 1361 [SCI_PHY_SUB_FINAL] = { 1362 .enter_state = sci_phy_starting_final_substate_enter, 1363 }, 1364 [SCI_PHY_READY] = { 1365 .enter_state = sci_phy_ready_state_enter, 1366 .exit_state = sci_phy_ready_state_exit, 1367 }, 1368 [SCI_PHY_RESETTING] = { 1369 .enter_state = sci_phy_resetting_state_enter, 1370 }, 1371 [SCI_PHY_FINAL] = { }, 1372}; 1373 1374void sci_phy_construct(struct isci_phy *iphy, 1375 struct isci_port *iport, u8 phy_index) 1376{ 1377 sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL); 1378 1379 /* Copy the rest of the input data to our locals */ 1380 iphy->owning_port = iport; 1381 iphy->phy_index = phy_index; 1382 iphy->bcn_received_while_port_unassigned = false; 1383 iphy->protocol = SAS_PROTOCOL_NONE; 1384 iphy->link_layer_registers = NULL; 1385 iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN; 1386 1387 /* Create the SIGNATURE FIS Timeout timer for this phy */ 1388 sci_init_timer(&iphy->sata_timer, phy_sata_timeout); 1389} 1390 1391void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index) 1392{ 1393 struct sci_oem_params *oem = &ihost->oem_parameters; 1394 u64 sci_sas_addr; 1395 __be64 sas_addr; 1396 1397 sci_sas_addr = oem->phys[index].sas_address.high; 1398 sci_sas_addr <<= 32; 1399 sci_sas_addr |= oem->phys[index].sas_address.low; 1400 sas_addr = cpu_to_be64(sci_sas_addr); 1401 memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr)); 1402 1403 iphy->sas_phy.enabled = 0; 1404 iphy->sas_phy.id = index; 1405 iphy->sas_phy.sas_addr = &iphy->sas_addr[0]; 1406 iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd; 1407 iphy->sas_phy.ha = &ihost->sas_ha; 1408 iphy->sas_phy.lldd_phy = iphy; 1409 iphy->sas_phy.enabled = 1; 1410 iphy->sas_phy.class = SAS; 1411 iphy->sas_phy.iproto = SAS_PROTOCOL_ALL; 1412 iphy->sas_phy.tproto = 0; 1413 iphy->sas_phy.type = PHY_TYPE_PHYSICAL; 1414 iphy->sas_phy.role = PHY_ROLE_INITIATOR; 1415 iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED; 1416 iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN; 1417 memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd)); 1418} 1419 1420 1421/** 1422 * isci_phy_control() - This function is one of the SAS Domain Template 1423 * functions. This is a phy management function. 1424 * @phy: This parameter specifies the sphy being controlled. 1425 * @func: This parameter specifies the phy control function being invoked. 1426 * @buf: This parameter is specific to the phy function being invoked. 1427 * 1428 * status, zero indicates success. 1429 */ 1430int isci_phy_control(struct asd_sas_phy *sas_phy, 1431 enum phy_func func, 1432 void *buf) 1433{ 1434 int ret = 0; 1435 struct isci_phy *iphy = sas_phy->lldd_phy; 1436 struct asd_sas_port *port = sas_phy->port; 1437 struct isci_host *ihost = sas_phy->ha->lldd_ha; 1438 unsigned long flags; 1439 1440 dev_dbg(&ihost->pdev->dev, 1441 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n", 1442 __func__, sas_phy, func, buf, iphy, port); 1443 1444 switch (func) { 1445 case PHY_FUNC_DISABLE: 1446 spin_lock_irqsave(&ihost->scic_lock, flags); 1447 scu_link_layer_start_oob(iphy); 1448 sci_phy_stop(iphy); 1449 spin_unlock_irqrestore(&ihost->scic_lock, flags); 1450 break; 1451 1452 case PHY_FUNC_LINK_RESET: 1453 spin_lock_irqsave(&ihost->scic_lock, flags); 1454 scu_link_layer_start_oob(iphy); 1455 sci_phy_stop(iphy); 1456 sci_phy_start(iphy); 1457 spin_unlock_irqrestore(&ihost->scic_lock, flags); 1458 break; 1459 1460 case PHY_FUNC_HARD_RESET: 1461 if (!port) 1462 return -ENODEV; 1463 1464 ret = isci_port_perform_hard_reset(ihost, port->lldd_port, iphy); 1465 1466 break; 1467 case PHY_FUNC_GET_EVENTS: { 1468 struct scu_link_layer_registers __iomem *r; 1469 struct sas_phy *phy = sas_phy->phy; 1470 1471 r = iphy->link_layer_registers; 1472 phy->running_disparity_error_count = readl(&r->running_disparity_error_count); 1473 phy->loss_of_dword_sync_count = readl(&r->loss_of_sync_error_count); 1474 phy->phy_reset_problem_count = readl(&r->phy_reset_problem_count); 1475 phy->invalid_dword_count = readl(&r->invalid_dword_counter); 1476 break; 1477 } 1478 1479 default: 1480 dev_dbg(&ihost->pdev->dev, 1481 "%s: phy %p; func %d NOT IMPLEMENTED!\n", 1482 __func__, sas_phy, func); 1483 ret = -ENOSYS; 1484 break; 1485 } 1486 return ret; 1487} 1488