1/* 2 * Copyright (c) 2000-2014 LSI Corporation. 3 * 4 * 5 * Name: mpi2.h 6 * Title: MPI Message independent structures and definitions 7 * including System Interface Register Set and 8 * scatter/gather formats. 9 * Creation Date: June 21, 2006 10 * 11 * mpi2.h Version: 02.00.35 12 * 13 * Version History 14 * --------------- 15 * 16 * Date Version Description 17 * -------- -------- ------------------------------------------------------ 18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 22 * Moved ReplyPostHostIndex register to offset 0x6C of the 23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 25 * Added union of request descriptors. 26 * Added union of reply descriptors. 27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 28 * Added define for MPI2_VERSION_02_00. 29 * Fixed the size of the FunctionDependent5 field in the 30 * MPI2_DEFAULT_REPLY structure. 31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 32 * Removed the MPI-defined Fault Codes and extended the 33 * product specific codes up to 0xEFFF. 34 * Added a sixth key value for the WriteSequence register 35 * and changed the flush value to 0x0. 36 * Added message function codes for Diagnostic Buffer Post 37 * and Diagnsotic Release. 38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 43 * Added #defines for marking a reply descriptor as unused. 44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 46 * Moved LUN field defines from mpi2_init.h. 47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 49 * In all request and reply descriptors, replaced VF_ID 50 * field with MSIxIndex field. 51 * Removed DevHandle field from 52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 53 * bytes reserved. 54 * Added RAID Accelerator functionality. 55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 57 * Added MSI-x index mask and shift for Reply Post Host 58 * Index register. 59 * Added function code for Host Based Discovery Action. 60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 62 * Added defines for product-specific range of message 63 * function codes, 0xF0 to 0xFF. 64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 65 * Added alternative defines for the SGE Direction bit. 66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 75 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 76 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 77 * Added Hard Reset delay timings. 78 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 80 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 81 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 82 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 83 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 84 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 85 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 87 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 88 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 89 * -------------------------------------------------------------------------- 90 */ 91 92#ifndef MPI2_H 93#define MPI2_H 94 95 96/***************************************************************************** 97* 98* MPI Version Definitions 99* 100*****************************************************************************/ 101 102#define MPI2_VERSION_MAJOR (0x02) 103#define MPI2_VERSION_MINOR (0x00) 104#define MPI2_VERSION_MAJOR_MASK (0xFF00) 105#define MPI2_VERSION_MAJOR_SHIFT (8) 106#define MPI2_VERSION_MINOR_MASK (0x00FF) 107#define MPI2_VERSION_MINOR_SHIFT (0) 108#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 109 MPI2_VERSION_MINOR) 110 111#define MPI2_VERSION_02_00 (0x0200) 112 113/* versioning for this MPI header set */ 114#define MPI2_HEADER_VERSION_UNIT (0x23) 115#define MPI2_HEADER_VERSION_DEV (0x00) 116#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 117#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 118#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 119#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 120#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 121 122 123/***************************************************************************** 124* 125* IOC State Definitions 126* 127*****************************************************************************/ 128 129#define MPI2_IOC_STATE_RESET (0x00000000) 130#define MPI2_IOC_STATE_READY (0x10000000) 131#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 132#define MPI2_IOC_STATE_FAULT (0x40000000) 133 134#define MPI2_IOC_STATE_MASK (0xF0000000) 135#define MPI2_IOC_STATE_SHIFT (28) 136 137/* Fault state range for prodcut specific codes */ 138#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 139#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 140 141 142/***************************************************************************** 143* 144* System Interface Register Definitions 145* 146*****************************************************************************/ 147 148typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 149{ 150 U32 Doorbell; /* 0x00 */ 151 U32 WriteSequence; /* 0x04 */ 152 U32 HostDiagnostic; /* 0x08 */ 153 U32 Reserved1; /* 0x0C */ 154 U32 DiagRWData; /* 0x10 */ 155 U32 DiagRWAddressLow; /* 0x14 */ 156 U32 DiagRWAddressHigh; /* 0x18 */ 157 U32 Reserved2[5]; /* 0x1C */ 158 U32 HostInterruptStatus; /* 0x30 */ 159 U32 HostInterruptMask; /* 0x34 */ 160 U32 DCRData; /* 0x38 */ 161 U32 DCRAddress; /* 0x3C */ 162 U32 Reserved3[2]; /* 0x40 */ 163 U32 ReplyFreeHostIndex; /* 0x48 */ 164 U32 Reserved4[8]; /* 0x4C */ 165 U32 ReplyPostHostIndex; /* 0x6C */ 166 U32 Reserved5; /* 0x70 */ 167 U32 HCBSize; /* 0x74 */ 168 U32 HCBAddressLow; /* 0x78 */ 169 U32 HCBAddressHigh; /* 0x7C */ 170 U32 Reserved6[16]; /* 0x80 */ 171 U32 RequestDescriptorPostLow; /* 0xC0 */ 172 U32 RequestDescriptorPostHigh; /* 0xC4 */ 173 U32 Reserved7[14]; /* 0xC8 */ 174} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 175 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 176 177/* 178 * Defines for working with the Doorbell register. 179 */ 180#define MPI2_DOORBELL_OFFSET (0x00000000) 181 182/* IOC --> System values */ 183#define MPI2_DOORBELL_USED (0x08000000) 184#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 185#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 186#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 187#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 188 189/* System --> IOC values */ 190#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 191#define MPI2_DOORBELL_FUNCTION_SHIFT (24) 192#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 193#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 194 195 196/* 197 * Defines for the WriteSequence register 198 */ 199#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 200#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 201#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 202#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 203#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 204#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 205#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 206#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 207#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 208 209/* 210 * Defines for the HostDiagnostic register 211 */ 212#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 213 214#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 215#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 216#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 217 218#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 219#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 220#define MPI2_DIAG_HCB_MODE (0x00000100) 221#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 222#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 223#define MPI2_DIAG_RESET_HISTORY (0x00000020) 224#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 225#define MPI2_DIAG_RESET_ADAPTER (0x00000004) 226#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 227 228/* 229 * Offsets for DiagRWData and address 230 */ 231#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 232#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 233#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 234 235/* 236 * Defines for the HostInterruptStatus register 237 */ 238#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 239#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 240#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 241#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 242#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 243#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 244#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 245 246/* 247 * Defines for the HostInterruptMask register 248 */ 249#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 250#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 251#define MPI2_HIM_REPLY_INT_MASK (0x00000008) 252#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 253#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 254#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 255 256/* 257 * Offsets for DCRData and address 258 */ 259#define MPI2_DCR_DATA_OFFSET (0x00000038) 260#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 261 262/* 263 * Offset for the Reply Free Queue 264 */ 265#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 266 267/* 268 * Defines for the Reply Descriptor Post Queue 269 */ 270#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 271#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 272#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 273#define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 274#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 275 276/* 277 * Defines for the HCBSize and address 278 */ 279#define MPI2_HCB_SIZE_OFFSET (0x00000074) 280#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 281#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 282 283#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 284#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 285 286/* 287 * Offsets for the Request Queue 288 */ 289#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 290#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 291 292 293/* Hard Reset delay timings */ 294#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 295#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 296#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 297 298/***************************************************************************** 299* 300* Message Descriptors 301* 302*****************************************************************************/ 303 304/* Request Descriptors */ 305 306/* Default Request Descriptor */ 307typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 308{ 309 U8 RequestFlags; /* 0x00 */ 310 U8 MSIxIndex; /* 0x01 */ 311 U16 SMID; /* 0x02 */ 312 U16 LMID; /* 0x04 */ 313 U16 DescriptorTypeDependent; /* 0x06 */ 314} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 315 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 316 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 317 318/* defines for the RequestFlags field */ 319#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 320#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 321#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 322#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 323#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 324#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 325 326#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 327 328 329/* High Priority Request Descriptor */ 330typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 331{ 332 U8 RequestFlags; /* 0x00 */ 333 U8 MSIxIndex; /* 0x01 */ 334 U16 SMID; /* 0x02 */ 335 U16 LMID; /* 0x04 */ 336 U16 Reserved1; /* 0x06 */ 337} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 338 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 339 Mpi2HighPriorityRequestDescriptor_t, 340 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 341 342 343/* SCSI IO Request Descriptor */ 344typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 345{ 346 U8 RequestFlags; /* 0x00 */ 347 U8 MSIxIndex; /* 0x01 */ 348 U16 SMID; /* 0x02 */ 349 U16 LMID; /* 0x04 */ 350 U16 DevHandle; /* 0x06 */ 351} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 352 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 353 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 354 355 356/* SCSI Target Request Descriptor */ 357typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 358{ 359 U8 RequestFlags; /* 0x00 */ 360 U8 MSIxIndex; /* 0x01 */ 361 U16 SMID; /* 0x02 */ 362 U16 LMID; /* 0x04 */ 363 U16 IoIndex; /* 0x06 */ 364} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 365 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 366 Mpi2SCSITargetRequestDescriptor_t, 367 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 368 369 370/* RAID Accelerator Request Descriptor */ 371typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 372 U8 RequestFlags; /* 0x00 */ 373 U8 MSIxIndex; /* 0x01 */ 374 U16 SMID; /* 0x02 */ 375 U16 LMID; /* 0x04 */ 376 U16 Reserved; /* 0x06 */ 377} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 378 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 379 Mpi2RAIDAcceleratorRequestDescriptor_t, 380 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 381 382 383/* union of Request Descriptors */ 384typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 385{ 386 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 387 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 388 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 389 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 390 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 391 U64 Words; 392} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 393 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 394 395 396/* Reply Descriptors */ 397 398/* Default Reply Descriptor */ 399typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 400{ 401 U8 ReplyFlags; /* 0x00 */ 402 U8 MSIxIndex; /* 0x01 */ 403 U16 DescriptorTypeDependent1; /* 0x02 */ 404 U32 DescriptorTypeDependent2; /* 0x04 */ 405} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 406 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 407 408/* defines for the ReplyFlags field */ 409#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 410#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 411#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 412#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 413#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 414#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 415#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 416 417/* values for marking a reply descriptor as unused */ 418#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 419#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 420 421/* Address Reply Descriptor */ 422typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 423{ 424 U8 ReplyFlags; /* 0x00 */ 425 U8 MSIxIndex; /* 0x01 */ 426 U16 SMID; /* 0x02 */ 427 U32 ReplyFrameAddress; /* 0x04 */ 428} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 429 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 430 431#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 432 433 434/* SCSI IO Success Reply Descriptor */ 435typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 436{ 437 U8 ReplyFlags; /* 0x00 */ 438 U8 MSIxIndex; /* 0x01 */ 439 U16 SMID; /* 0x02 */ 440 U16 TaskTag; /* 0x04 */ 441 U16 Reserved1; /* 0x06 */ 442} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 443 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 444 Mpi2SCSIIOSuccessReplyDescriptor_t, 445 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 446 447 448/* TargetAssist Success Reply Descriptor */ 449typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 450{ 451 U8 ReplyFlags; /* 0x00 */ 452 U8 MSIxIndex; /* 0x01 */ 453 U16 SMID; /* 0x02 */ 454 U8 SequenceNumber; /* 0x04 */ 455 U8 Reserved1; /* 0x05 */ 456 U16 IoIndex; /* 0x06 */ 457} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 458 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 459 Mpi2TargetAssistSuccessReplyDescriptor_t, 460 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 461 462 463/* Target Command Buffer Reply Descriptor */ 464typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 465{ 466 U8 ReplyFlags; /* 0x00 */ 467 U8 MSIxIndex; /* 0x01 */ 468 U8 VP_ID; /* 0x02 */ 469 U8 Flags; /* 0x03 */ 470 U16 InitiatorDevHandle; /* 0x04 */ 471 U16 IoIndex; /* 0x06 */ 472} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 473 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 474 Mpi2TargetCommandBufferReplyDescriptor_t, 475 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 476 477/* defines for Flags field */ 478#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 479 480 481/* RAID Accelerator Success Reply Descriptor */ 482typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 483 U8 ReplyFlags; /* 0x00 */ 484 U8 MSIxIndex; /* 0x01 */ 485 U16 SMID; /* 0x02 */ 486 U32 Reserved; /* 0x04 */ 487} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 488 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 489 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 490 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 491 492 493/* union of Reply Descriptors */ 494typedef union _MPI2_REPLY_DESCRIPTORS_UNION 495{ 496 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 497 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 498 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 499 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 500 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 501 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 502 U64 Words; 503} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 504Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 505 506 507 508/***************************************************************************** 509* 510* Message Functions 511* 512*****************************************************************************/ 513 514#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 515#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 516#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 517#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 518#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 519#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 520#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 521#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 522#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 523#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 524#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 525#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 526#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 527#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 528#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 529#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 530#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 531#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 532#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 533#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 534#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 535#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 536#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 537#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 538#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 539#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/ 540/* Host Based Discovery Action */ 541#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 542/* Power Management Control */ 543#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 544/* Send Host Message */ 545#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 546/* beginning of product-specific range */ 547#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 548/* end of product-specific range */ 549#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 550 551 552 553 554/* Doorbell functions */ 555#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 556#define MPI2_FUNCTION_HANDSHAKE (0x42) 557 558 559/***************************************************************************** 560* 561* IOC Status Values 562* 563*****************************************************************************/ 564 565/* mask for IOCStatus status value */ 566#define MPI2_IOCSTATUS_MASK (0x7FFF) 567 568/**************************************************************************** 569* Common IOCStatus values for all replies 570****************************************************************************/ 571 572#define MPI2_IOCSTATUS_SUCCESS (0x0000) 573#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 574#define MPI2_IOCSTATUS_BUSY (0x0002) 575#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 576#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 577#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 578#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 579#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 580#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 581#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 582 583/**************************************************************************** 584* Config IOCStatus values 585****************************************************************************/ 586 587#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 588#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 589#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 590#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 591#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 592#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 593 594/**************************************************************************** 595* SCSI IO Reply 596****************************************************************************/ 597 598#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 599#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 600#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 601#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 602#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 603#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 604#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 605#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 606#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 607#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 608#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 609#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 610 611/**************************************************************************** 612* For use by SCSI Initiator and SCSI Target end-to-end data protection 613****************************************************************************/ 614 615#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 616#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 617#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 618 619/**************************************************************************** 620* SCSI Target values 621****************************************************************************/ 622 623#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 624#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 625#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 626#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 627#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 628#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 629#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 630#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 631#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 632#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 633 634/**************************************************************************** 635* Serial Attached SCSI values 636****************************************************************************/ 637 638#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 639#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 640 641/**************************************************************************** 642* Diagnostic Buffer Post / Diagnostic Release values 643****************************************************************************/ 644 645#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 646 647/**************************************************************************** 648* RAID Accelerator values 649****************************************************************************/ 650 651#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 652 653/**************************************************************************** 654* IOCStatus flag to indicate that log info is available 655****************************************************************************/ 656 657#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 658 659/**************************************************************************** 660* IOCLogInfo Types 661****************************************************************************/ 662 663#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 664#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 665#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 666#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 667#define MPI2_IOCLOGINFO_TYPE_FC (0x2) 668#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 669#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 670#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 671 672 673/***************************************************************************** 674* 675* Standard Message Structures 676* 677*****************************************************************************/ 678 679/**************************************************************************** 680* Request Message Header for all request messages 681****************************************************************************/ 682 683typedef struct _MPI2_REQUEST_HEADER 684{ 685 U16 FunctionDependent1; /* 0x00 */ 686 U8 ChainOffset; /* 0x02 */ 687 U8 Function; /* 0x03 */ 688 U16 FunctionDependent2; /* 0x04 */ 689 U8 FunctionDependent3; /* 0x06 */ 690 U8 MsgFlags; /* 0x07 */ 691 U8 VP_ID; /* 0x08 */ 692 U8 VF_ID; /* 0x09 */ 693 U16 Reserved1; /* 0x0A */ 694} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 695 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 696 697 698/**************************************************************************** 699* Default Reply 700****************************************************************************/ 701 702typedef struct _MPI2_DEFAULT_REPLY 703{ 704 U16 FunctionDependent1; /* 0x00 */ 705 U8 MsgLength; /* 0x02 */ 706 U8 Function; /* 0x03 */ 707 U16 FunctionDependent2; /* 0x04 */ 708 U8 FunctionDependent3; /* 0x06 */ 709 U8 MsgFlags; /* 0x07 */ 710 U8 VP_ID; /* 0x08 */ 711 U8 VF_ID; /* 0x09 */ 712 U16 Reserved1; /* 0x0A */ 713 U16 FunctionDependent5; /* 0x0C */ 714 U16 IOCStatus; /* 0x0E */ 715 U32 IOCLogInfo; /* 0x10 */ 716} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 717 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 718 719 720/* common version structure/union used in messages and configuration pages */ 721 722typedef struct _MPI2_VERSION_STRUCT 723{ 724 U8 Dev; /* 0x00 */ 725 U8 Unit; /* 0x01 */ 726 U8 Minor; /* 0x02 */ 727 U8 Major; /* 0x03 */ 728} MPI2_VERSION_STRUCT; 729 730typedef union _MPI2_VERSION_UNION 731{ 732 MPI2_VERSION_STRUCT Struct; 733 U32 Word; 734} MPI2_VERSION_UNION; 735 736 737/* LUN field defines, common to many structures */ 738#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 739#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 740#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 741#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 742#define MPI2_LUN_LEVEL_1_WORD (0xFF00) 743#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 744 745 746/***************************************************************************** 747* 748* Fusion-MPT MPI Scatter Gather Elements 749* 750*****************************************************************************/ 751 752/**************************************************************************** 753* MPI Simple Element structures 754****************************************************************************/ 755 756typedef struct _MPI2_SGE_SIMPLE32 757{ 758 U32 FlagsLength; 759 U32 Address; 760} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 761 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 762 763typedef struct _MPI2_SGE_SIMPLE64 764{ 765 U32 FlagsLength; 766 U64 Address; 767} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 768 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 769 770typedef struct _MPI2_SGE_SIMPLE_UNION 771{ 772 U32 FlagsLength; 773 union 774 { 775 U32 Address32; 776 U64 Address64; 777 } u; 778} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 779 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 780 781 782/**************************************************************************** 783* MPI Chain Element structures 784****************************************************************************/ 785 786typedef struct _MPI2_SGE_CHAIN32 787{ 788 U16 Length; 789 U8 NextChainOffset; 790 U8 Flags; 791 U32 Address; 792} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 793 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 794 795typedef struct _MPI2_SGE_CHAIN64 796{ 797 U16 Length; 798 U8 NextChainOffset; 799 U8 Flags; 800 U64 Address; 801} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 802 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 803 804typedef struct _MPI2_SGE_CHAIN_UNION 805{ 806 U16 Length; 807 U8 NextChainOffset; 808 U8 Flags; 809 union 810 { 811 U32 Address32; 812 U64 Address64; 813 } u; 814} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 815 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 816 817 818/**************************************************************************** 819* MPI Transaction Context Element structures 820****************************************************************************/ 821 822typedef struct _MPI2_SGE_TRANSACTION32 823{ 824 U8 Reserved; 825 U8 ContextSize; 826 U8 DetailsLength; 827 U8 Flags; 828 U32 TransactionContext[1]; 829 U32 TransactionDetails[1]; 830} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 831 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 832 833typedef struct _MPI2_SGE_TRANSACTION64 834{ 835 U8 Reserved; 836 U8 ContextSize; 837 U8 DetailsLength; 838 U8 Flags; 839 U32 TransactionContext[2]; 840 U32 TransactionDetails[1]; 841} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 842 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 843 844typedef struct _MPI2_SGE_TRANSACTION96 845{ 846 U8 Reserved; 847 U8 ContextSize; 848 U8 DetailsLength; 849 U8 Flags; 850 U32 TransactionContext[3]; 851 U32 TransactionDetails[1]; 852} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 853 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 854 855typedef struct _MPI2_SGE_TRANSACTION128 856{ 857 U8 Reserved; 858 U8 ContextSize; 859 U8 DetailsLength; 860 U8 Flags; 861 U32 TransactionContext[4]; 862 U32 TransactionDetails[1]; 863} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 864 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 865 866typedef struct _MPI2_SGE_TRANSACTION_UNION 867{ 868 U8 Reserved; 869 U8 ContextSize; 870 U8 DetailsLength; 871 U8 Flags; 872 union 873 { 874 U32 TransactionContext32[1]; 875 U32 TransactionContext64[2]; 876 U32 TransactionContext96[3]; 877 U32 TransactionContext128[4]; 878 } u; 879 U32 TransactionDetails[1]; 880} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 881 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 882 883 884/**************************************************************************** 885* MPI SGE union for IO SGL's 886****************************************************************************/ 887 888typedef struct _MPI2_MPI_SGE_IO_UNION 889{ 890 union 891 { 892 MPI2_SGE_SIMPLE_UNION Simple; 893 MPI2_SGE_CHAIN_UNION Chain; 894 } u; 895} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 896 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 897 898 899/**************************************************************************** 900* MPI SGE union for SGL's with Simple and Transaction elements 901****************************************************************************/ 902 903typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 904{ 905 union 906 { 907 MPI2_SGE_SIMPLE_UNION Simple; 908 MPI2_SGE_TRANSACTION_UNION Transaction; 909 } u; 910} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 911 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 912 913 914/**************************************************************************** 915* All MPI SGE types union 916****************************************************************************/ 917 918typedef struct _MPI2_MPI_SGE_UNION 919{ 920 union 921 { 922 MPI2_SGE_SIMPLE_UNION Simple; 923 MPI2_SGE_CHAIN_UNION Chain; 924 MPI2_SGE_TRANSACTION_UNION Transaction; 925 } u; 926} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 927 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 928 929 930/**************************************************************************** 931* MPI SGE field definition and masks 932****************************************************************************/ 933 934/* Flags field bit definitions */ 935 936#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 937#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 938#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 939#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 940#define MPI2_SGE_FLAGS_DIRECTION (0x04) 941#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 942#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 943 944#define MPI2_SGE_FLAGS_SHIFT (24) 945 946#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 947#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 948 949/* Element Type */ 950 951#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 952#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 953#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 954#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 955 956/* Address location */ 957 958#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 959 960/* Direction */ 961 962#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 963#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 964 965#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 966#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 967 968/* Address Size */ 969 970#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 971#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 972 973/* Context Size */ 974 975#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 976#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 977#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 978#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 979 980#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 981#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 982 983/**************************************************************************** 984* MPI SGE operation Macros 985****************************************************************************/ 986 987/* SIMPLE FlagsLength manipulations... */ 988#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 989#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 990#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 991#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 992 993#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 994 995#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 996#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 997#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 998 999/* CAUTION - The following are READ-MODIFY-WRITE! */ 1000#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1001#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1002 1003#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1004 1005 1006/***************************************************************************** 1007* 1008* Fusion-MPT IEEE Scatter Gather Elements 1009* 1010*****************************************************************************/ 1011 1012/**************************************************************************** 1013* IEEE Simple Element structures 1014****************************************************************************/ 1015 1016typedef struct _MPI2_IEEE_SGE_SIMPLE32 1017{ 1018 U32 Address; 1019 U32 FlagsLength; 1020} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1021 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1022 1023typedef struct _MPI2_IEEE_SGE_SIMPLE64 1024{ 1025 U64 Address; 1026 U32 Length; 1027 U16 Reserved1; 1028 U8 Reserved2; 1029 U8 Flags; 1030} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1031 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1032 1033typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1034{ 1035 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1036 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1037} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1038 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1039 1040 1041/**************************************************************************** 1042* IEEE Chain Element structures 1043****************************************************************************/ 1044 1045typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1046 1047typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1048 1049typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1050{ 1051 MPI2_IEEE_SGE_CHAIN32 Chain32; 1052 MPI2_IEEE_SGE_CHAIN64 Chain64; 1053} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1054 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1055 1056 1057/**************************************************************************** 1058* All IEEE SGE types union 1059****************************************************************************/ 1060 1061typedef struct _MPI2_IEEE_SGE_UNION 1062{ 1063 union 1064 { 1065 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1066 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1067 } u; 1068} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1069 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1070 1071 1072/**************************************************************************** 1073* IEEE SGE field definitions and masks 1074****************************************************************************/ 1075 1076/* Flags field bit definitions */ 1077 1078#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1079 1080#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1081 1082#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1083 1084/* Element Type */ 1085 1086#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1087#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1088 1089/* Data Location Address Space */ 1090 1091#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1092#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1093 /* IEEE Simple Element only */ 1094#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1095 /* IEEE Simple Element only */ 1096#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1097#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1098 /* IEEE Simple Element only */ 1099#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1100 /* IEEE Chain Element only */ 1101#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1102 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1103 1104/**************************************************************************** 1105* IEEE SGE operation Macros 1106****************************************************************************/ 1107 1108/* SIMPLE FlagsLength manipulations... */ 1109#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1110#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1111#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1112 1113#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1114 1115#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1116#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1117#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1118 1119/* CAUTION - The following are READ-MODIFY-WRITE! */ 1120#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1121#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1122 1123 1124 1125 1126/***************************************************************************** 1127* 1128* Fusion-MPT MPI/IEEE Scatter Gather Unions 1129* 1130*****************************************************************************/ 1131 1132typedef union _MPI2_SIMPLE_SGE_UNION 1133{ 1134 MPI2_SGE_SIMPLE_UNION MpiSimple; 1135 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1136} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1137 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1138 1139 1140typedef union _MPI2_SGE_IO_UNION 1141{ 1142 MPI2_SGE_SIMPLE_UNION MpiSimple; 1143 MPI2_SGE_CHAIN_UNION MpiChain; 1144 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1145 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1146} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1147 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1148 1149 1150/**************************************************************************** 1151* 1152* Values for SGLFlags field, used in many request messages with an SGL 1153* 1154****************************************************************************/ 1155 1156/* values for MPI SGL Data Location Address Space subfield */ 1157#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1158#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1159#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1160#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1161#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1162/* values for SGL Type subfield */ 1163#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1164#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1165#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1166#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1167 1168 1169#endif 1170 1171