1/* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46#include <linux/kernel.h> 47#include <linux/module.h> 48#include <linux/errno.h> 49#include <linux/init.h> 50#include <linux/slab.h> 51#include <linux/types.h> 52#include <linux/pci.h> 53#include <linux/kdev_t.h> 54#include <linux/blkdev.h> 55#include <linux/delay.h> 56#include <linux/interrupt.h> 57#include <linux/dma-mapping.h> 58#include <linux/io.h> 59#include <linux/time.h> 60#include <linux/kthread.h> 61#include <linux/aer.h> 62 63 64#include "mpt3sas_base.h" 65 66static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 67 68 69#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 70 71 /* maximum controller queue depth */ 72#define MAX_HBA_QUEUE_DEPTH 30000 73#define MAX_CHAIN_DEPTH 100000 74static int max_queue_depth = -1; 75module_param(max_queue_depth, int, 0); 76MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 77 78static int max_sgl_entries = -1; 79module_param(max_sgl_entries, int, 0); 80MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 81 82static int msix_disable = -1; 83module_param(msix_disable, int, 0); 84MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 85 86static int max_msix_vectors = 8; 87module_param(max_msix_vectors, int, 0); 88MODULE_PARM_DESC(max_msix_vectors, 89 " max msix vectors - (default=8)"); 90 91static int mpt3sas_fwfault_debug; 92MODULE_PARM_DESC(mpt3sas_fwfault_debug, 93 " enable detection of firmware fault and halt firmware - (default=0)"); 94 95static int 96_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag); 97 98/** 99 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 100 * 101 */ 102static int 103_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp) 104{ 105 int ret = param_set_int(val, kp); 106 struct MPT3SAS_ADAPTER *ioc; 107 108 if (ret) 109 return ret; 110 111 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 112 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 113 ioc->fwfault_debug = mpt3sas_fwfault_debug; 114 return 0; 115} 116module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 117 param_get_int, &mpt3sas_fwfault_debug, 0644); 118 119/** 120 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 121 * @arg: input argument, used to derive ioc 122 * 123 * Return 0 if controller is removed from pci subsystem. 124 * Return -1 for other case. 125 */ 126static int mpt3sas_remove_dead_ioc_func(void *arg) 127{ 128 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 129 struct pci_dev *pdev; 130 131 if ((ioc == NULL)) 132 return -1; 133 134 pdev = ioc->pdev; 135 if ((pdev == NULL)) 136 return -1; 137 pci_stop_and_remove_bus_device_locked(pdev); 138 return 0; 139} 140 141/** 142 * _base_fault_reset_work - workq handling ioc fault conditions 143 * @work: input argument, used to derive ioc 144 * Context: sleep. 145 * 146 * Return nothing. 147 */ 148static void 149_base_fault_reset_work(struct work_struct *work) 150{ 151 struct MPT3SAS_ADAPTER *ioc = 152 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 153 unsigned long flags; 154 u32 doorbell; 155 int rc; 156 struct task_struct *p; 157 158 159 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 160 if (ioc->shost_recovery) 161 goto rearm_timer; 162 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 163 164 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 165 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 166 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", 167 ioc->name); 168 169 /* 170 * Call _scsih_flush_pending_cmds callback so that we flush all 171 * pending commands back to OS. This call is required to aovid 172 * deadlock at block layer. Dead IOC will fail to do diag reset, 173 * and this call is safe since dead ioc will never return any 174 * command back from HW. 175 */ 176 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 177 /* 178 * Set remove_host flag early since kernel thread will 179 * take some time to execute. 180 */ 181 ioc->remove_host = 1; 182 /*Remove the Dead Host */ 183 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 184 "mpt3sas_dead_ioc_%d", ioc->id); 185 if (IS_ERR(p)) 186 pr_err(MPT3SAS_FMT 187 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 188 ioc->name, __func__); 189 else 190 pr_err(MPT3SAS_FMT 191 "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 192 ioc->name, __func__); 193 return; /* don't rearm timer */ 194 } 195 196 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 197 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP, 198 FORCE_BIG_HAMMER); 199 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, 200 __func__, (rc == 0) ? "success" : "failed"); 201 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 202 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 203 mpt3sas_base_fault_info(ioc, doorbell & 204 MPI2_DOORBELL_DATA_MASK); 205 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 206 MPI2_IOC_STATE_OPERATIONAL) 207 return; /* don't rearm timer */ 208 } 209 210 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 211 rearm_timer: 212 if (ioc->fault_reset_work_q) 213 queue_delayed_work(ioc->fault_reset_work_q, 214 &ioc->fault_reset_work, 215 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 216 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 217} 218 219/** 220 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 221 * @ioc: per adapter object 222 * Context: sleep. 223 * 224 * Return nothing. 225 */ 226void 227mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 228{ 229 unsigned long flags; 230 231 if (ioc->fault_reset_work_q) 232 return; 233 234 /* initialize fault polling */ 235 236 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 237 snprintf(ioc->fault_reset_work_q_name, 238 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id); 239 ioc->fault_reset_work_q = 240 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 241 if (!ioc->fault_reset_work_q) { 242 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", 243 ioc->name, __func__, __LINE__); 244 return; 245 } 246 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 247 if (ioc->fault_reset_work_q) 248 queue_delayed_work(ioc->fault_reset_work_q, 249 &ioc->fault_reset_work, 250 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 251 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 252} 253 254/** 255 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 256 * @ioc: per adapter object 257 * Context: sleep. 258 * 259 * Return nothing. 260 */ 261void 262mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 263{ 264 unsigned long flags; 265 struct workqueue_struct *wq; 266 267 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 268 wq = ioc->fault_reset_work_q; 269 ioc->fault_reset_work_q = NULL; 270 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 271 if (wq) { 272 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 273 flush_workqueue(wq); 274 destroy_workqueue(wq); 275 } 276} 277 278/** 279 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 280 * @ioc: per adapter object 281 * @fault_code: fault code 282 * 283 * Return nothing. 284 */ 285void 286mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) 287{ 288 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", 289 ioc->name, fault_code); 290} 291 292/** 293 * mpt3sas_halt_firmware - halt's mpt controller firmware 294 * @ioc: per adapter object 295 * 296 * For debugging timeout related issues. Writing 0xCOFFEE00 297 * to the doorbell register will halt controller firmware. With 298 * the purpose to stop both driver and firmware, the enduser can 299 * obtain a ring buffer from controller UART. 300 */ 301void 302mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 303{ 304 u32 doorbell; 305 306 if (!ioc->fwfault_debug) 307 return; 308 309 dump_stack(); 310 311 doorbell = readl(&ioc->chip->Doorbell); 312 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 313 mpt3sas_base_fault_info(ioc , doorbell); 314 else { 315 writel(0xC0FFEE00, &ioc->chip->Doorbell); 316 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", 317 ioc->name); 318 } 319 320 if (ioc->fwfault_debug == 2) 321 for (;;) 322 ; 323 else 324 panic("panic in %s\n", __func__); 325} 326 327#ifdef CONFIG_SCSI_MPT3SAS_LOGGING 328/** 329 * _base_sas_ioc_info - verbose translation of the ioc status 330 * @ioc: per adapter object 331 * @mpi_reply: reply mf payload returned from firmware 332 * @request_hdr: request mf 333 * 334 * Return nothing. 335 */ 336static void 337_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 338 MPI2RequestHeader_t *request_hdr) 339{ 340 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 341 MPI2_IOCSTATUS_MASK; 342 char *desc = NULL; 343 u16 frame_sz; 344 char *func_str = NULL; 345 346 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 347 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 348 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 349 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 350 return; 351 352 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 353 return; 354 355 switch (ioc_status) { 356 357/**************************************************************************** 358* Common IOCStatus values for all replies 359****************************************************************************/ 360 361 case MPI2_IOCSTATUS_INVALID_FUNCTION: 362 desc = "invalid function"; 363 break; 364 case MPI2_IOCSTATUS_BUSY: 365 desc = "busy"; 366 break; 367 case MPI2_IOCSTATUS_INVALID_SGL: 368 desc = "invalid sgl"; 369 break; 370 case MPI2_IOCSTATUS_INTERNAL_ERROR: 371 desc = "internal error"; 372 break; 373 case MPI2_IOCSTATUS_INVALID_VPID: 374 desc = "invalid vpid"; 375 break; 376 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 377 desc = "insufficient resources"; 378 break; 379 case MPI2_IOCSTATUS_INVALID_FIELD: 380 desc = "invalid field"; 381 break; 382 case MPI2_IOCSTATUS_INVALID_STATE: 383 desc = "invalid state"; 384 break; 385 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 386 desc = "op state not supported"; 387 break; 388 389/**************************************************************************** 390* Config IOCStatus values 391****************************************************************************/ 392 393 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 394 desc = "config invalid action"; 395 break; 396 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 397 desc = "config invalid type"; 398 break; 399 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 400 desc = "config invalid page"; 401 break; 402 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 403 desc = "config invalid data"; 404 break; 405 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 406 desc = "config no defaults"; 407 break; 408 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 409 desc = "config cant commit"; 410 break; 411 412/**************************************************************************** 413* SCSI IO Reply 414****************************************************************************/ 415 416 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 417 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 418 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 419 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 420 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 421 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 422 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 423 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 424 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 425 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 426 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 427 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 428 break; 429 430/**************************************************************************** 431* For use by SCSI Initiator and SCSI Target end-to-end data protection 432****************************************************************************/ 433 434 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 435 desc = "eedp guard error"; 436 break; 437 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 438 desc = "eedp ref tag error"; 439 break; 440 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 441 desc = "eedp app tag error"; 442 break; 443 444/**************************************************************************** 445* SCSI Target values 446****************************************************************************/ 447 448 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 449 desc = "target invalid io index"; 450 break; 451 case MPI2_IOCSTATUS_TARGET_ABORTED: 452 desc = "target aborted"; 453 break; 454 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 455 desc = "target no conn retryable"; 456 break; 457 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 458 desc = "target no connection"; 459 break; 460 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 461 desc = "target xfer count mismatch"; 462 break; 463 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 464 desc = "target data offset error"; 465 break; 466 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 467 desc = "target too much write data"; 468 break; 469 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 470 desc = "target iu too short"; 471 break; 472 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 473 desc = "target ack nak timeout"; 474 break; 475 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 476 desc = "target nak received"; 477 break; 478 479/**************************************************************************** 480* Serial Attached SCSI values 481****************************************************************************/ 482 483 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 484 desc = "smp request failed"; 485 break; 486 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 487 desc = "smp data overrun"; 488 break; 489 490/**************************************************************************** 491* Diagnostic Buffer Post / Diagnostic Release values 492****************************************************************************/ 493 494 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 495 desc = "diagnostic released"; 496 break; 497 default: 498 break; 499 } 500 501 if (!desc) 502 return; 503 504 switch (request_hdr->Function) { 505 case MPI2_FUNCTION_CONFIG: 506 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 507 func_str = "config_page"; 508 break; 509 case MPI2_FUNCTION_SCSI_TASK_MGMT: 510 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 511 func_str = "task_mgmt"; 512 break; 513 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 514 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 515 func_str = "sas_iounit_ctl"; 516 break; 517 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 518 frame_sz = sizeof(Mpi2SepRequest_t); 519 func_str = "enclosure"; 520 break; 521 case MPI2_FUNCTION_IOC_INIT: 522 frame_sz = sizeof(Mpi2IOCInitRequest_t); 523 func_str = "ioc_init"; 524 break; 525 case MPI2_FUNCTION_PORT_ENABLE: 526 frame_sz = sizeof(Mpi2PortEnableRequest_t); 527 func_str = "port_enable"; 528 break; 529 case MPI2_FUNCTION_SMP_PASSTHROUGH: 530 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 531 func_str = "smp_passthru"; 532 break; 533 default: 534 frame_sz = 32; 535 func_str = "unknown"; 536 break; 537 } 538 539 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 540 ioc->name, desc, ioc_status, request_hdr, func_str); 541 542 _debug_dump_mf(request_hdr, frame_sz/4); 543} 544 545/** 546 * _base_display_event_data - verbose translation of firmware asyn events 547 * @ioc: per adapter object 548 * @mpi_reply: reply mf payload returned from firmware 549 * 550 * Return nothing. 551 */ 552static void 553_base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 554 Mpi2EventNotificationReply_t *mpi_reply) 555{ 556 char *desc = NULL; 557 u16 event; 558 559 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 560 return; 561 562 event = le16_to_cpu(mpi_reply->Event); 563 564 switch (event) { 565 case MPI2_EVENT_LOG_DATA: 566 desc = "Log Data"; 567 break; 568 case MPI2_EVENT_STATE_CHANGE: 569 desc = "Status Change"; 570 break; 571 case MPI2_EVENT_HARD_RESET_RECEIVED: 572 desc = "Hard Reset Received"; 573 break; 574 case MPI2_EVENT_EVENT_CHANGE: 575 desc = "Event Change"; 576 break; 577 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 578 desc = "Device Status Change"; 579 break; 580 case MPI2_EVENT_IR_OPERATION_STATUS: 581 desc = "IR Operation Status"; 582 break; 583 case MPI2_EVENT_SAS_DISCOVERY: 584 { 585 Mpi2EventDataSasDiscovery_t *event_data = 586 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 587 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, 588 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? 589 "start" : "stop"); 590 if (event_data->DiscoveryStatus) 591 pr_info("discovery_status(0x%08x)", 592 le32_to_cpu(event_data->DiscoveryStatus)); 593 pr_info("\n"); 594 return; 595 } 596 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 597 desc = "SAS Broadcast Primitive"; 598 break; 599 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 600 desc = "SAS Init Device Status Change"; 601 break; 602 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 603 desc = "SAS Init Table Overflow"; 604 break; 605 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 606 desc = "SAS Topology Change List"; 607 break; 608 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 609 desc = "SAS Enclosure Device Status Change"; 610 break; 611 case MPI2_EVENT_IR_VOLUME: 612 desc = "IR Volume"; 613 break; 614 case MPI2_EVENT_IR_PHYSICAL_DISK: 615 desc = "IR Physical Disk"; 616 break; 617 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 618 desc = "IR Configuration Change List"; 619 break; 620 case MPI2_EVENT_LOG_ENTRY_ADDED: 621 desc = "Log Entry Added"; 622 break; 623 case MPI2_EVENT_TEMP_THRESHOLD: 624 desc = "Temperature Threshold"; 625 break; 626 } 627 628 if (!desc) 629 return; 630 631 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); 632} 633#endif 634 635/** 636 * _base_sas_log_info - verbose translation of firmware log info 637 * @ioc: per adapter object 638 * @log_info: log info 639 * 640 * Return nothing. 641 */ 642static void 643_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) 644{ 645 union loginfo_type { 646 u32 loginfo; 647 struct { 648 u32 subcode:16; 649 u32 code:8; 650 u32 originator:4; 651 u32 bus_type:4; 652 } dw; 653 }; 654 union loginfo_type sas_loginfo; 655 char *originator_str = NULL; 656 657 sas_loginfo.loginfo = log_info; 658 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 659 return; 660 661 /* each nexus loss loginfo */ 662 if (log_info == 0x31170000) 663 return; 664 665 /* eat the loginfos associated with task aborts */ 666 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 667 0x31140000 || log_info == 0x31130000)) 668 return; 669 670 switch (sas_loginfo.dw.originator) { 671 case 0: 672 originator_str = "IOP"; 673 break; 674 case 1: 675 originator_str = "PL"; 676 break; 677 case 2: 678 originator_str = "IR"; 679 break; 680 } 681 682 pr_warn(MPT3SAS_FMT 683 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 684 ioc->name, log_info, 685 originator_str, sas_loginfo.dw.code, 686 sas_loginfo.dw.subcode); 687} 688 689/** 690 * _base_display_reply_info - 691 * @ioc: per adapter object 692 * @smid: system request message index 693 * @msix_index: MSIX table index supplied by the OS 694 * @reply: reply message frame(lower 32bit addr) 695 * 696 * Return nothing. 697 */ 698static void 699_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 700 u32 reply) 701{ 702 MPI2DefaultReply_t *mpi_reply; 703 u16 ioc_status; 704 u32 loginfo = 0; 705 706 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 707 if (unlikely(!mpi_reply)) { 708 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", 709 ioc->name, __FILE__, __LINE__, __func__); 710 return; 711 } 712 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 713#ifdef CONFIG_SCSI_MPT3SAS_LOGGING 714 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 715 (ioc->logging_level & MPT_DEBUG_REPLY)) { 716 _base_sas_ioc_info(ioc , mpi_reply, 717 mpt3sas_base_get_msg_frame(ioc, smid)); 718 } 719#endif 720 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 721 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 722 _base_sas_log_info(ioc, loginfo); 723 } 724 725 if (ioc_status || loginfo) { 726 ioc_status &= MPI2_IOCSTATUS_MASK; 727 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 728 } 729} 730 731/** 732 * mpt3sas_base_done - base internal command completion routine 733 * @ioc: per adapter object 734 * @smid: system request message index 735 * @msix_index: MSIX table index supplied by the OS 736 * @reply: reply message frame(lower 32bit addr) 737 * 738 * Return 1 meaning mf should be freed from _base_interrupt 739 * 0 means the mf is freed from this function. 740 */ 741u8 742mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 743 u32 reply) 744{ 745 MPI2DefaultReply_t *mpi_reply; 746 747 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 748 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 749 return 1; 750 751 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 752 return 1; 753 754 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 755 if (mpi_reply) { 756 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 757 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 758 } 759 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 760 761 complete(&ioc->base_cmds.done); 762 return 1; 763} 764 765/** 766 * _base_async_event - main callback handler for firmware asyn events 767 * @ioc: per adapter object 768 * @msix_index: MSIX table index supplied by the OS 769 * @reply: reply message frame(lower 32bit addr) 770 * 771 * Return 1 meaning mf should be freed from _base_interrupt 772 * 0 means the mf is freed from this function. 773 */ 774static u8 775_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 776{ 777 Mpi2EventNotificationReply_t *mpi_reply; 778 Mpi2EventAckRequest_t *ack_request; 779 u16 smid; 780 781 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 782 if (!mpi_reply) 783 return 1; 784 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 785 return 1; 786#ifdef CONFIG_SCSI_MPT3SAS_LOGGING 787 _base_display_event_data(ioc, mpi_reply); 788#endif 789 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 790 goto out; 791 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 792 if (!smid) { 793 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 794 ioc->name, __func__); 795 goto out; 796 } 797 798 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 799 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 800 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 801 ack_request->Event = mpi_reply->Event; 802 ack_request->EventContext = mpi_reply->EventContext; 803 ack_request->VF_ID = 0; /* TODO */ 804 ack_request->VP_ID = 0; 805 mpt3sas_base_put_smid_default(ioc, smid); 806 807 out: 808 809 /* scsih callback handler */ 810 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 811 812 /* ctl callback handler */ 813 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 814 815 return 1; 816} 817 818/** 819 * _base_get_cb_idx - obtain the callback index 820 * @ioc: per adapter object 821 * @smid: system request message index 822 * 823 * Return callback index. 824 */ 825static u8 826_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 827{ 828 int i; 829 u8 cb_idx; 830 831 if (smid < ioc->hi_priority_smid) { 832 i = smid - 1; 833 cb_idx = ioc->scsi_lookup[i].cb_idx; 834 } else if (smid < ioc->internal_smid) { 835 i = smid - ioc->hi_priority_smid; 836 cb_idx = ioc->hpr_lookup[i].cb_idx; 837 } else if (smid <= ioc->hba_queue_depth) { 838 i = smid - ioc->internal_smid; 839 cb_idx = ioc->internal_lookup[i].cb_idx; 840 } else 841 cb_idx = 0xFF; 842 return cb_idx; 843} 844 845/** 846 * _base_mask_interrupts - disable interrupts 847 * @ioc: per adapter object 848 * 849 * Disabling ResetIRQ, Reply and Doorbell Interrupts 850 * 851 * Return nothing. 852 */ 853static void 854_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 855{ 856 u32 him_register; 857 858 ioc->mask_interrupts = 1; 859 him_register = readl(&ioc->chip->HostInterruptMask); 860 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 861 writel(him_register, &ioc->chip->HostInterruptMask); 862 readl(&ioc->chip->HostInterruptMask); 863} 864 865/** 866 * _base_unmask_interrupts - enable interrupts 867 * @ioc: per adapter object 868 * 869 * Enabling only Reply Interrupts 870 * 871 * Return nothing. 872 */ 873static void 874_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 875{ 876 u32 him_register; 877 878 him_register = readl(&ioc->chip->HostInterruptMask); 879 him_register &= ~MPI2_HIM_RIM; 880 writel(him_register, &ioc->chip->HostInterruptMask); 881 ioc->mask_interrupts = 0; 882} 883 884union reply_descriptor { 885 u64 word; 886 struct { 887 u32 low; 888 u32 high; 889 } u; 890}; 891 892/** 893 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 894 * @irq: irq number (not used) 895 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 896 * @r: pt_regs pointer (not used) 897 * 898 * Return IRQ_HANDLE if processed, else IRQ_NONE. 899 */ 900static irqreturn_t 901_base_interrupt(int irq, void *bus_id) 902{ 903 struct adapter_reply_queue *reply_q = bus_id; 904 union reply_descriptor rd; 905 u32 completed_cmds; 906 u8 request_desript_type; 907 u16 smid; 908 u8 cb_idx; 909 u32 reply; 910 u8 msix_index = reply_q->msix_index; 911 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 912 Mpi2ReplyDescriptorsUnion_t *rpf; 913 u8 rc; 914 915 if (ioc->mask_interrupts) 916 return IRQ_NONE; 917 918 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 919 return IRQ_NONE; 920 921 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 922 request_desript_type = rpf->Default.ReplyFlags 923 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 924 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 925 atomic_dec(&reply_q->busy); 926 return IRQ_NONE; 927 } 928 929 completed_cmds = 0; 930 cb_idx = 0xFF; 931 do { 932 rd.word = le64_to_cpu(rpf->Words); 933 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 934 goto out; 935 reply = 0; 936 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 937 if (request_desript_type == 938 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 939 request_desript_type == 940 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 941 cb_idx = _base_get_cb_idx(ioc, smid); 942 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 943 (likely(mpt_callbacks[cb_idx] != NULL))) { 944 rc = mpt_callbacks[cb_idx](ioc, smid, 945 msix_index, 0); 946 if (rc) 947 mpt3sas_base_free_smid(ioc, smid); 948 } 949 } else if (request_desript_type == 950 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 951 reply = le32_to_cpu( 952 rpf->AddressReply.ReplyFrameAddress); 953 if (reply > ioc->reply_dma_max_address || 954 reply < ioc->reply_dma_min_address) 955 reply = 0; 956 if (smid) { 957 cb_idx = _base_get_cb_idx(ioc, smid); 958 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 959 (likely(mpt_callbacks[cb_idx] != NULL))) { 960 rc = mpt_callbacks[cb_idx](ioc, smid, 961 msix_index, reply); 962 if (reply) 963 _base_display_reply_info(ioc, 964 smid, msix_index, reply); 965 if (rc) 966 mpt3sas_base_free_smid(ioc, 967 smid); 968 } 969 } else { 970 _base_async_event(ioc, msix_index, reply); 971 } 972 973 /* reply free queue handling */ 974 if (reply) { 975 ioc->reply_free_host_index = 976 (ioc->reply_free_host_index == 977 (ioc->reply_free_queue_depth - 1)) ? 978 0 : ioc->reply_free_host_index + 1; 979 ioc->reply_free[ioc->reply_free_host_index] = 980 cpu_to_le32(reply); 981 wmb(); 982 writel(ioc->reply_free_host_index, 983 &ioc->chip->ReplyFreeHostIndex); 984 } 985 } 986 987 rpf->Words = cpu_to_le64(ULLONG_MAX); 988 reply_q->reply_post_host_index = 989 (reply_q->reply_post_host_index == 990 (ioc->reply_post_queue_depth - 1)) ? 0 : 991 reply_q->reply_post_host_index + 1; 992 request_desript_type = 993 reply_q->reply_post_free[reply_q->reply_post_host_index]. 994 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 995 completed_cmds++; 996 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 997 goto out; 998 if (!reply_q->reply_post_host_index) 999 rpf = reply_q->reply_post_free; 1000 else 1001 rpf++; 1002 } while (1); 1003 1004 out: 1005 1006 if (!completed_cmds) { 1007 atomic_dec(&reply_q->busy); 1008 return IRQ_NONE; 1009 } 1010 1011 wmb(); 1012 writel(reply_q->reply_post_host_index | (msix_index << 1013 MPI2_RPHI_MSIX_INDEX_SHIFT), &ioc->chip->ReplyPostHostIndex); 1014 atomic_dec(&reply_q->busy); 1015 return IRQ_HANDLED; 1016} 1017 1018/** 1019 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1020 * @ioc: per adapter object 1021 * 1022 */ 1023static inline int 1024_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1025{ 1026 return (ioc->facts.IOCCapabilities & 1027 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1028} 1029 1030/** 1031 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues 1032 * @ioc: per adapter object 1033 * Context: ISR conext 1034 * 1035 * Called when a Task Management request has completed. We want 1036 * to flush the other reply queues so all the outstanding IO has been 1037 * completed back to OS before we process the TM completetion. 1038 * 1039 * Return nothing. 1040 */ 1041void 1042mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc) 1043{ 1044 struct adapter_reply_queue *reply_q; 1045 1046 /* If MSIX capability is turned off 1047 * then multi-queues are not enabled 1048 */ 1049 if (!_base_is_controller_msix_enabled(ioc)) 1050 return; 1051 1052 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1053 if (ioc->shost_recovery) 1054 return; 1055 /* TMs are on msix_index == 0 */ 1056 if (reply_q->msix_index == 0) 1057 continue; 1058 _base_interrupt(reply_q->vector, (void *)reply_q); 1059 } 1060} 1061 1062/** 1063 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 1064 * @cb_idx: callback index 1065 * 1066 * Return nothing. 1067 */ 1068void 1069mpt3sas_base_release_callback_handler(u8 cb_idx) 1070{ 1071 mpt_callbacks[cb_idx] = NULL; 1072} 1073 1074/** 1075 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 1076 * @cb_func: callback function 1077 * 1078 * Returns cb_func. 1079 */ 1080u8 1081mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 1082{ 1083 u8 cb_idx; 1084 1085 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 1086 if (mpt_callbacks[cb_idx] == NULL) 1087 break; 1088 1089 mpt_callbacks[cb_idx] = cb_func; 1090 return cb_idx; 1091} 1092 1093/** 1094 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 1095 * 1096 * Return nothing. 1097 */ 1098void 1099mpt3sas_base_initialize_callback_handler(void) 1100{ 1101 u8 cb_idx; 1102 1103 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 1104 mpt3sas_base_release_callback_handler(cb_idx); 1105} 1106 1107 1108/** 1109 * _base_build_zero_len_sge - build zero length sg entry 1110 * @ioc: per adapter object 1111 * @paddr: virtual address for SGE 1112 * 1113 * Create a zero length scatter gather entry to insure the IOCs hardware has 1114 * something to use if the target device goes brain dead and tries 1115 * to send data even when none is asked for. 1116 * 1117 * Return nothing. 1118 */ 1119static void 1120_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1121{ 1122 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 1123 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 1124 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 1125 MPI2_SGE_FLAGS_SHIFT); 1126 ioc->base_add_sg_single(paddr, flags_length, -1); 1127} 1128 1129/** 1130 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 1131 * @paddr: virtual address for SGE 1132 * @flags_length: SGE flags and data transfer length 1133 * @dma_addr: Physical address 1134 * 1135 * Return nothing. 1136 */ 1137static void 1138_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1139{ 1140 Mpi2SGESimple32_t *sgel = paddr; 1141 1142 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 1143 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1144 sgel->FlagsLength = cpu_to_le32(flags_length); 1145 sgel->Address = cpu_to_le32(dma_addr); 1146} 1147 1148 1149/** 1150 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 1151 * @paddr: virtual address for SGE 1152 * @flags_length: SGE flags and data transfer length 1153 * @dma_addr: Physical address 1154 * 1155 * Return nothing. 1156 */ 1157static void 1158_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1159{ 1160 Mpi2SGESimple64_t *sgel = paddr; 1161 1162 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 1163 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1164 sgel->FlagsLength = cpu_to_le32(flags_length); 1165 sgel->Address = cpu_to_le64(dma_addr); 1166} 1167 1168/** 1169 * _base_get_chain_buffer_tracker - obtain chain tracker 1170 * @ioc: per adapter object 1171 * @smid: smid associated to an IO request 1172 * 1173 * Returns chain tracker(from ioc->free_chain_list) 1174 */ 1175static struct chain_tracker * 1176_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1177{ 1178 struct chain_tracker *chain_req; 1179 unsigned long flags; 1180 1181 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 1182 if (list_empty(&ioc->free_chain_list)) { 1183 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1184 dfailprintk(ioc, pr_warn(MPT3SAS_FMT 1185 "chain buffers not available\n", ioc->name)); 1186 return NULL; 1187 } 1188 chain_req = list_entry(ioc->free_chain_list.next, 1189 struct chain_tracker, tracker_list); 1190 list_del_init(&chain_req->tracker_list); 1191 list_add_tail(&chain_req->tracker_list, 1192 &ioc->scsi_lookup[smid - 1].chain_list); 1193 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1194 return chain_req; 1195} 1196 1197 1198/** 1199 * _base_build_sg - build generic sg 1200 * @ioc: per adapter object 1201 * @psge: virtual address for SGE 1202 * @data_out_dma: physical address for WRITES 1203 * @data_out_sz: data xfer size for WRITES 1204 * @data_in_dma: physical address for READS 1205 * @data_in_sz: data xfer size for READS 1206 * 1207 * Return nothing. 1208 */ 1209static void 1210_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 1211 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1212 size_t data_in_sz) 1213{ 1214 u32 sgl_flags; 1215 1216 if (!data_out_sz && !data_in_sz) { 1217 _base_build_zero_len_sge(ioc, psge); 1218 return; 1219 } 1220 1221 if (data_out_sz && data_in_sz) { 1222 /* WRITE sgel first */ 1223 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1224 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 1225 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1226 ioc->base_add_sg_single(psge, sgl_flags | 1227 data_out_sz, data_out_dma); 1228 1229 /* incr sgel */ 1230 psge += ioc->sge_size; 1231 1232 /* READ sgel last */ 1233 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1234 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1235 MPI2_SGE_FLAGS_END_OF_LIST); 1236 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1237 ioc->base_add_sg_single(psge, sgl_flags | 1238 data_in_sz, data_in_dma); 1239 } else if (data_out_sz) /* WRITE */ { 1240 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1241 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1242 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 1243 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1244 ioc->base_add_sg_single(psge, sgl_flags | 1245 data_out_sz, data_out_dma); 1246 } else if (data_in_sz) /* READ */ { 1247 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1248 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1249 MPI2_SGE_FLAGS_END_OF_LIST); 1250 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1251 ioc->base_add_sg_single(psge, sgl_flags | 1252 data_in_sz, data_in_dma); 1253 } 1254} 1255 1256/* IEEE format sgls */ 1257 1258/** 1259 * _base_add_sg_single_ieee - add sg element for IEEE format 1260 * @paddr: virtual address for SGE 1261 * @flags: SGE flags 1262 * @chain_offset: number of 128 byte elements from start of segment 1263 * @length: data transfer length 1264 * @dma_addr: Physical address 1265 * 1266 * Return nothing. 1267 */ 1268static void 1269_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 1270 dma_addr_t dma_addr) 1271{ 1272 Mpi25IeeeSgeChain64_t *sgel = paddr; 1273 1274 sgel->Flags = flags; 1275 sgel->NextChainOffset = chain_offset; 1276 sgel->Length = cpu_to_le32(length); 1277 sgel->Address = cpu_to_le64(dma_addr); 1278} 1279 1280/** 1281 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 1282 * @ioc: per adapter object 1283 * @paddr: virtual address for SGE 1284 * 1285 * Create a zero length scatter gather entry to insure the IOCs hardware has 1286 * something to use if the target device goes brain dead and tries 1287 * to send data even when none is asked for. 1288 * 1289 * Return nothing. 1290 */ 1291static void 1292_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1293{ 1294 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1295 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 1296 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 1297 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 1298} 1299 1300/** 1301 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 1302 * @ioc: per adapter object 1303 * @scmd: scsi command 1304 * @smid: system request message index 1305 * Context: none. 1306 * 1307 * The main routine that builds scatter gather table from a given 1308 * scsi request sent via the .queuecommand main handler. 1309 * 1310 * Returns 0 success, anything else error 1311 */ 1312static int 1313_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 1314 struct scsi_cmnd *scmd, u16 smid) 1315{ 1316 Mpi2SCSIIORequest_t *mpi_request; 1317 dma_addr_t chain_dma; 1318 struct scatterlist *sg_scmd; 1319 void *sg_local, *chain; 1320 u32 chain_offset; 1321 u32 chain_length; 1322 int sges_left; 1323 u32 sges_in_segment; 1324 u8 simple_sgl_flags; 1325 u8 simple_sgl_flags_last; 1326 u8 chain_sgl_flags; 1327 struct chain_tracker *chain_req; 1328 1329 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 1330 1331 /* init scatter gather flags */ 1332 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1333 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1334 simple_sgl_flags_last = simple_sgl_flags | 1335 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1336 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 1337 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1338 1339 sg_scmd = scsi_sglist(scmd); 1340 sges_left = scsi_dma_map(scmd); 1341 if (!sges_left) { 1342 sdev_printk(KERN_ERR, scmd->device, 1343 "pci_map_sg failed: request for %d bytes!\n", 1344 scsi_bufflen(scmd)); 1345 return -ENOMEM; 1346 } 1347 1348 sg_local = &mpi_request->SGL; 1349 sges_in_segment = (ioc->request_sz - 1350 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 1351 if (sges_left <= sges_in_segment) 1352 goto fill_in_last_segment; 1353 1354 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 1355 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 1356 1357 /* fill in main message segment when there is a chain following */ 1358 while (sges_in_segment > 1) { 1359 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1360 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1361 sg_scmd = sg_next(sg_scmd); 1362 sg_local += ioc->sge_size_ieee; 1363 sges_left--; 1364 sges_in_segment--; 1365 } 1366 1367 /* initializing the pointers */ 1368 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1369 if (!chain_req) 1370 return -1; 1371 chain = chain_req->chain_buffer; 1372 chain_dma = chain_req->chain_buffer_dma; 1373 do { 1374 sges_in_segment = (sges_left <= 1375 ioc->max_sges_in_chain_message) ? sges_left : 1376 ioc->max_sges_in_chain_message; 1377 chain_offset = (sges_left == sges_in_segment) ? 1378 0 : sges_in_segment; 1379 chain_length = sges_in_segment * ioc->sge_size_ieee; 1380 if (chain_offset) 1381 chain_length += ioc->sge_size_ieee; 1382 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 1383 chain_offset, chain_length, chain_dma); 1384 1385 sg_local = chain; 1386 if (!chain_offset) 1387 goto fill_in_last_segment; 1388 1389 /* fill in chain segments */ 1390 while (sges_in_segment) { 1391 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1392 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1393 sg_scmd = sg_next(sg_scmd); 1394 sg_local += ioc->sge_size_ieee; 1395 sges_left--; 1396 sges_in_segment--; 1397 } 1398 1399 chain_req = _base_get_chain_buffer_tracker(ioc, smid); 1400 if (!chain_req) 1401 return -1; 1402 chain = chain_req->chain_buffer; 1403 chain_dma = chain_req->chain_buffer_dma; 1404 } while (1); 1405 1406 1407 fill_in_last_segment: 1408 1409 /* fill the last segment */ 1410 while (sges_left) { 1411 if (sges_left == 1) 1412 _base_add_sg_single_ieee(sg_local, 1413 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 1414 sg_dma_address(sg_scmd)); 1415 else 1416 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 1417 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 1418 sg_scmd = sg_next(sg_scmd); 1419 sg_local += ioc->sge_size_ieee; 1420 sges_left--; 1421 } 1422 1423 return 0; 1424} 1425 1426/** 1427 * _base_build_sg_ieee - build generic sg for IEEE format 1428 * @ioc: per adapter object 1429 * @psge: virtual address for SGE 1430 * @data_out_dma: physical address for WRITES 1431 * @data_out_sz: data xfer size for WRITES 1432 * @data_in_dma: physical address for READS 1433 * @data_in_sz: data xfer size for READS 1434 * 1435 * Return nothing. 1436 */ 1437static void 1438_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 1439 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1440 size_t data_in_sz) 1441{ 1442 u8 sgl_flags; 1443 1444 if (!data_out_sz && !data_in_sz) { 1445 _base_build_zero_len_sge_ieee(ioc, psge); 1446 return; 1447 } 1448 1449 if (data_out_sz && data_in_sz) { 1450 /* WRITE sgel first */ 1451 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1452 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1453 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1454 data_out_dma); 1455 1456 /* incr sgel */ 1457 psge += ioc->sge_size_ieee; 1458 1459 /* READ sgel last */ 1460 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 1461 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1462 data_in_dma); 1463 } else if (data_out_sz) /* WRITE */ { 1464 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1465 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1466 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1467 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 1468 data_out_dma); 1469 } else if (data_in_sz) /* READ */ { 1470 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 1471 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 1472 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 1473 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 1474 data_in_dma); 1475 } 1476} 1477 1478#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 1479 1480/** 1481 * _base_config_dma_addressing - set dma addressing 1482 * @ioc: per adapter object 1483 * @pdev: PCI device struct 1484 * 1485 * Returns 0 for success, non-zero for failure. 1486 */ 1487static int 1488_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 1489{ 1490 struct sysinfo s; 1491 u64 consistent_dma_mask; 1492 1493 if (ioc->dma_mask) 1494 consistent_dma_mask = DMA_BIT_MASK(64); 1495 else 1496 consistent_dma_mask = DMA_BIT_MASK(32); 1497 1498 if (sizeof(dma_addr_t) > 4) { 1499 const uint64_t required_mask = 1500 dma_get_required_mask(&pdev->dev); 1501 if ((required_mask > DMA_BIT_MASK(32)) && 1502 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && 1503 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { 1504 ioc->base_add_sg_single = &_base_add_sg_single_64; 1505 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 1506 ioc->dma_mask = 64; 1507 goto out; 1508 } 1509 } 1510 1511 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1512 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 1513 ioc->base_add_sg_single = &_base_add_sg_single_32; 1514 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 1515 ioc->dma_mask = 32; 1516 } else 1517 return -ENODEV; 1518 1519 out: 1520 si_meminfo(&s); 1521 pr_info(MPT3SAS_FMT 1522 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 1523 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); 1524 1525 return 0; 1526} 1527 1528static int 1529_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, 1530 struct pci_dev *pdev) 1531{ 1532 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 1533 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 1534 return -ENODEV; 1535 } 1536 return 0; 1537} 1538 1539/** 1540 * _base_check_enable_msix - checks MSIX capabable. 1541 * @ioc: per adapter object 1542 * 1543 * Check to see if card is capable of MSIX, and set number 1544 * of available msix vectors 1545 */ 1546static int 1547_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1548{ 1549 int base; 1550 u16 message_control; 1551 1552 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 1553 if (!base) { 1554 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", 1555 ioc->name)); 1556 return -EINVAL; 1557 } 1558 1559 /* get msix vector count */ 1560 1561 pci_read_config_word(ioc->pdev, base + 2, &message_control); 1562 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 1563 if (ioc->msix_vector_count > 8) 1564 ioc->msix_vector_count = 8; 1565 dinitprintk(ioc, pr_info(MPT3SAS_FMT 1566 "msix is supported, vector_count(%d)\n", 1567 ioc->name, ioc->msix_vector_count)); 1568 return 0; 1569} 1570 1571/** 1572 * _base_free_irq - free irq 1573 * @ioc: per adapter object 1574 * 1575 * Freeing respective reply_queue from the list. 1576 */ 1577static void 1578_base_free_irq(struct MPT3SAS_ADAPTER *ioc) 1579{ 1580 struct adapter_reply_queue *reply_q, *next; 1581 1582 if (list_empty(&ioc->reply_queue_list)) 1583 return; 1584 1585 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 1586 list_del(&reply_q->list); 1587 irq_set_affinity_hint(reply_q->vector, NULL); 1588 free_cpumask_var(reply_q->affinity_hint); 1589 synchronize_irq(reply_q->vector); 1590 free_irq(reply_q->vector, reply_q); 1591 kfree(reply_q); 1592 } 1593} 1594 1595/** 1596 * _base_request_irq - request irq 1597 * @ioc: per adapter object 1598 * @index: msix index into vector table 1599 * @vector: irq vector 1600 * 1601 * Inserting respective reply_queue into the list. 1602 */ 1603static int 1604_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector) 1605{ 1606 struct adapter_reply_queue *reply_q; 1607 int r; 1608 1609 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 1610 if (!reply_q) { 1611 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", 1612 ioc->name, (int)sizeof(struct adapter_reply_queue)); 1613 return -ENOMEM; 1614 } 1615 reply_q->ioc = ioc; 1616 reply_q->msix_index = index; 1617 reply_q->vector = vector; 1618 1619 if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) 1620 return -ENOMEM; 1621 cpumask_clear(reply_q->affinity_hint); 1622 1623 atomic_set(&reply_q->busy, 0); 1624 if (ioc->msix_enable) 1625 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 1626 MPT3SAS_DRIVER_NAME, ioc->id, index); 1627 else 1628 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 1629 MPT3SAS_DRIVER_NAME, ioc->id); 1630 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name, 1631 reply_q); 1632 if (r) { 1633 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", 1634 reply_q->name, vector); 1635 kfree(reply_q); 1636 return -EBUSY; 1637 } 1638 1639 INIT_LIST_HEAD(&reply_q->list); 1640 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 1641 return 0; 1642} 1643 1644/** 1645 * _base_assign_reply_queues - assigning msix index for each cpu 1646 * @ioc: per adapter object 1647 * 1648 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 1649 * 1650 * It would nice if we could call irq_set_affinity, however it is not 1651 * an exported symbol 1652 */ 1653static void 1654_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 1655{ 1656 unsigned int cpu, nr_cpus, nr_msix, index = 0; 1657 struct adapter_reply_queue *reply_q; 1658 1659 if (!_base_is_controller_msix_enabled(ioc)) 1660 return; 1661 1662 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 1663 1664 nr_cpus = num_online_cpus(); 1665 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 1666 ioc->facts.MaxMSIxVectors); 1667 if (!nr_msix) 1668 return; 1669 1670 cpu = cpumask_first(cpu_online_mask); 1671 1672 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1673 1674 unsigned int i, group = nr_cpus / nr_msix; 1675 1676 if (cpu >= nr_cpus) 1677 break; 1678 1679 if (index < nr_cpus % nr_msix) 1680 group++; 1681 1682 for (i = 0 ; i < group ; i++) { 1683 ioc->cpu_msix_table[cpu] = index; 1684 cpumask_or(reply_q->affinity_hint, 1685 reply_q->affinity_hint, get_cpu_mask(cpu)); 1686 cpu = cpumask_next(cpu, cpu_online_mask); 1687 } 1688 1689 if (irq_set_affinity_hint(reply_q->vector, 1690 reply_q->affinity_hint)) 1691 dinitprintk(ioc, pr_info(MPT3SAS_FMT 1692 "error setting affinity hint for irq vector %d\n", 1693 ioc->name, reply_q->vector)); 1694 index++; 1695 } 1696} 1697 1698/** 1699 * _base_disable_msix - disables msix 1700 * @ioc: per adapter object 1701 * 1702 */ 1703static void 1704_base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 1705{ 1706 if (!ioc->msix_enable) 1707 return; 1708 pci_disable_msix(ioc->pdev); 1709 ioc->msix_enable = 0; 1710} 1711 1712/** 1713 * _base_enable_msix - enables msix, failback to io_apic 1714 * @ioc: per adapter object 1715 * 1716 */ 1717static int 1718_base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 1719{ 1720 struct msix_entry *entries, *a; 1721 int r; 1722 int i; 1723 u8 try_msix = 0; 1724 1725 if (msix_disable == -1 || msix_disable == 0) 1726 try_msix = 1; 1727 1728 if (!try_msix) 1729 goto try_ioapic; 1730 1731 if (_base_check_enable_msix(ioc) != 0) 1732 goto try_ioapic; 1733 1734 ioc->reply_queue_count = min_t(int, ioc->cpu_count, 1735 ioc->msix_vector_count); 1736 1737 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" 1738 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, 1739 ioc->cpu_count, max_msix_vectors); 1740 1741 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 1742 max_msix_vectors = 8; 1743 1744 if (max_msix_vectors > 0) { 1745 ioc->reply_queue_count = min_t(int, max_msix_vectors, 1746 ioc->reply_queue_count); 1747 ioc->msix_vector_count = ioc->reply_queue_count; 1748 } else if (max_msix_vectors == 0) 1749 goto try_ioapic; 1750 1751 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry), 1752 GFP_KERNEL); 1753 if (!entries) { 1754 dfailprintk(ioc, pr_info(MPT3SAS_FMT 1755 "kcalloc failed @ at %s:%d/%s() !!!\n", 1756 ioc->name, __FILE__, __LINE__, __func__)); 1757 goto try_ioapic; 1758 } 1759 1760 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) 1761 a->entry = i; 1762 1763 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count); 1764 if (r) { 1765 dfailprintk(ioc, pr_info(MPT3SAS_FMT 1766 "pci_enable_msix_exact failed (r=%d) !!!\n", 1767 ioc->name, r)); 1768 kfree(entries); 1769 goto try_ioapic; 1770 } 1771 1772 ioc->msix_enable = 1; 1773 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) { 1774 r = _base_request_irq(ioc, i, a->vector); 1775 if (r) { 1776 _base_free_irq(ioc); 1777 _base_disable_msix(ioc); 1778 kfree(entries); 1779 goto try_ioapic; 1780 } 1781 } 1782 1783 kfree(entries); 1784 return 0; 1785 1786/* failback to io_apic interrupt routing */ 1787 try_ioapic: 1788 1789 ioc->reply_queue_count = 1; 1790 r = _base_request_irq(ioc, 0, ioc->pdev->irq); 1791 1792 return r; 1793} 1794 1795/** 1796 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 1797 * @ioc: per adapter object 1798 * 1799 * Returns 0 for success, non-zero for failure. 1800 */ 1801int 1802mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 1803{ 1804 struct pci_dev *pdev = ioc->pdev; 1805 u32 memap_sz; 1806 u32 pio_sz; 1807 int i, r = 0; 1808 u64 pio_chip = 0; 1809 u64 chip_phys = 0; 1810 struct adapter_reply_queue *reply_q; 1811 1812 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", 1813 ioc->name, __func__)); 1814 1815 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 1816 if (pci_enable_device_mem(pdev)) { 1817 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", 1818 ioc->name); 1819 ioc->bars = 0; 1820 return -ENODEV; 1821 } 1822 1823 1824 if (pci_request_selected_regions(pdev, ioc->bars, 1825 MPT3SAS_DRIVER_NAME)) { 1826 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", 1827 ioc->name); 1828 ioc->bars = 0; 1829 r = -ENODEV; 1830 goto out_fail; 1831 } 1832 1833/* AER (Advanced Error Reporting) hooks */ 1834 pci_enable_pcie_error_reporting(pdev); 1835 1836 pci_set_master(pdev); 1837 1838 1839 if (_base_config_dma_addressing(ioc, pdev) != 0) { 1840 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", 1841 ioc->name, pci_name(pdev)); 1842 r = -ENODEV; 1843 goto out_fail; 1844 } 1845 1846 for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) { 1847 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 1848 if (pio_sz) 1849 continue; 1850 pio_chip = (u64)pci_resource_start(pdev, i); 1851 pio_sz = pci_resource_len(pdev, i); 1852 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 1853 if (memap_sz) 1854 continue; 1855 ioc->chip_phys = pci_resource_start(pdev, i); 1856 chip_phys = (u64)ioc->chip_phys; 1857 memap_sz = pci_resource_len(pdev, i); 1858 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 1859 if (ioc->chip == NULL) { 1860 pr_err(MPT3SAS_FMT "unable to map adapter memory!\n", 1861 ioc->name); 1862 r = -EINVAL; 1863 goto out_fail; 1864 } 1865 } 1866 } 1867 1868 _base_mask_interrupts(ioc); 1869 1870 r = _base_get_ioc_facts(ioc, CAN_SLEEP); 1871 if (r) 1872 goto out_fail; 1873 1874 if (!ioc->rdpq_array_enable_assigned) { 1875 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 1876 ioc->rdpq_array_enable_assigned = 1; 1877 } 1878 1879 r = _base_enable_msix(ioc); 1880 if (r) 1881 goto out_fail; 1882 1883 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) 1884 pr_info(MPT3SAS_FMT "%s: IRQ %d\n", 1885 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : 1886 "IO-APIC enabled"), reply_q->vector); 1887 1888 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n", 1889 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz); 1890 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", 1891 ioc->name, (unsigned long long)pio_chip, pio_sz); 1892 1893 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 1894 pci_save_state(pdev); 1895 return 0; 1896 1897 out_fail: 1898 if (ioc->chip_phys) 1899 iounmap(ioc->chip); 1900 ioc->chip_phys = 0; 1901 pci_release_selected_regions(ioc->pdev, ioc->bars); 1902 pci_disable_pcie_error_reporting(pdev); 1903 pci_disable_device(pdev); 1904 return r; 1905} 1906 1907/** 1908 * mpt3sas_base_get_msg_frame - obtain request mf pointer 1909 * @ioc: per adapter object 1910 * @smid: system request message index(smid zero is invalid) 1911 * 1912 * Returns virt pointer to message frame. 1913 */ 1914void * 1915mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1916{ 1917 return (void *)(ioc->request + (smid * ioc->request_sz)); 1918} 1919 1920/** 1921 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 1922 * @ioc: per adapter object 1923 * @smid: system request message index 1924 * 1925 * Returns virt pointer to sense buffer. 1926 */ 1927void * 1928mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1929{ 1930 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 1931} 1932 1933/** 1934 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 1935 * @ioc: per adapter object 1936 * @smid: system request message index 1937 * 1938 * Returns phys pointer to the low 32bit address of the sense buffer. 1939 */ 1940__le32 1941mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1942{ 1943 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 1944 SCSI_SENSE_BUFFERSIZE)); 1945} 1946 1947/** 1948 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 1949 * @ioc: per adapter object 1950 * @phys_addr: lower 32 physical addr of the reply 1951 * 1952 * Converts 32bit lower physical addr into a virt address. 1953 */ 1954void * 1955mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 1956{ 1957 if (!phys_addr) 1958 return NULL; 1959 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 1960} 1961 1962/** 1963 * mpt3sas_base_get_smid - obtain a free smid from internal queue 1964 * @ioc: per adapter object 1965 * @cb_idx: callback index 1966 * 1967 * Returns smid (zero is invalid) 1968 */ 1969u16 1970mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 1971{ 1972 unsigned long flags; 1973 struct request_tracker *request; 1974 u16 smid; 1975 1976 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 1977 if (list_empty(&ioc->internal_free_list)) { 1978 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1979 pr_err(MPT3SAS_FMT "%s: smid not available\n", 1980 ioc->name, __func__); 1981 return 0; 1982 } 1983 1984 request = list_entry(ioc->internal_free_list.next, 1985 struct request_tracker, tracker_list); 1986 request->cb_idx = cb_idx; 1987 smid = request->smid; 1988 list_del(&request->tracker_list); 1989 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 1990 return smid; 1991} 1992 1993/** 1994 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 1995 * @ioc: per adapter object 1996 * @cb_idx: callback index 1997 * @scmd: pointer to scsi command object 1998 * 1999 * Returns smid (zero is invalid) 2000 */ 2001u16 2002mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 2003 struct scsi_cmnd *scmd) 2004{ 2005 unsigned long flags; 2006 struct scsiio_tracker *request; 2007 u16 smid; 2008 2009 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2010 if (list_empty(&ioc->free_list)) { 2011 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2012 pr_err(MPT3SAS_FMT "%s: smid not available\n", 2013 ioc->name, __func__); 2014 return 0; 2015 } 2016 2017 request = list_entry(ioc->free_list.next, 2018 struct scsiio_tracker, tracker_list); 2019 request->scmd = scmd; 2020 request->cb_idx = cb_idx; 2021 smid = request->smid; 2022 list_del(&request->tracker_list); 2023 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2024 return smid; 2025} 2026 2027/** 2028 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 2029 * @ioc: per adapter object 2030 * @cb_idx: callback index 2031 * 2032 * Returns smid (zero is invalid) 2033 */ 2034u16 2035mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 2036{ 2037 unsigned long flags; 2038 struct request_tracker *request; 2039 u16 smid; 2040 2041 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2042 if (list_empty(&ioc->hpr_free_list)) { 2043 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2044 return 0; 2045 } 2046 2047 request = list_entry(ioc->hpr_free_list.next, 2048 struct request_tracker, tracker_list); 2049 request->cb_idx = cb_idx; 2050 smid = request->smid; 2051 list_del(&request->tracker_list); 2052 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2053 return smid; 2054} 2055 2056/** 2057 * mpt3sas_base_free_smid - put smid back on free_list 2058 * @ioc: per adapter object 2059 * @smid: system request message index 2060 * 2061 * Return nothing. 2062 */ 2063void 2064mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2065{ 2066 unsigned long flags; 2067 int i; 2068 struct chain_tracker *chain_req, *next; 2069 2070 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 2071 if (smid < ioc->hi_priority_smid) { 2072 /* scsiio queue */ 2073 i = smid - 1; 2074 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) { 2075 list_for_each_entry_safe(chain_req, next, 2076 &ioc->scsi_lookup[i].chain_list, tracker_list) { 2077 list_del_init(&chain_req->tracker_list); 2078 list_add(&chain_req->tracker_list, 2079 &ioc->free_chain_list); 2080 } 2081 } 2082 ioc->scsi_lookup[i].cb_idx = 0xFF; 2083 ioc->scsi_lookup[i].scmd = NULL; 2084 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list); 2085 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2086 2087 /* 2088 * See _wait_for_commands_to_complete() call with regards 2089 * to this code. 2090 */ 2091 if (ioc->shost_recovery && ioc->pending_io_count) { 2092 if (ioc->pending_io_count == 1) 2093 wake_up(&ioc->reset_wq); 2094 ioc->pending_io_count--; 2095 } 2096 return; 2097 } else if (smid < ioc->internal_smid) { 2098 /* hi-priority */ 2099 i = smid - ioc->hi_priority_smid; 2100 ioc->hpr_lookup[i].cb_idx = 0xFF; 2101 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 2102 } else if (smid <= ioc->hba_queue_depth) { 2103 /* internal queue */ 2104 i = smid - ioc->internal_smid; 2105 ioc->internal_lookup[i].cb_idx = 0xFF; 2106 list_add(&ioc->internal_lookup[i].tracker_list, 2107 &ioc->internal_free_list); 2108 } 2109 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 2110} 2111 2112/** 2113 * _base_writeq - 64 bit write to MMIO 2114 * @ioc: per adapter object 2115 * @b: data payload 2116 * @addr: address in MMIO space 2117 * @writeq_lock: spin lock 2118 * 2119 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 2120 * care of 32 bit environment where its not quarenteed to send the entire word 2121 * in one transfer. 2122 */ 2123#if defined(writeq) && defined(CONFIG_64BIT) 2124static inline void 2125_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2126{ 2127 writeq(cpu_to_le64(b), addr); 2128} 2129#else 2130static inline void 2131_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 2132{ 2133 unsigned long flags; 2134 __u64 data_out = cpu_to_le64(b); 2135 2136 spin_lock_irqsave(writeq_lock, flags); 2137 writel((u32)(data_out), addr); 2138 writel((u32)(data_out >> 32), (addr + 4)); 2139 spin_unlock_irqrestore(writeq_lock, flags); 2140} 2141#endif 2142 2143static inline u8 2144_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) 2145{ 2146 return ioc->cpu_msix_table[raw_smp_processor_id()]; 2147} 2148 2149/** 2150 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware 2151 * @ioc: per adapter object 2152 * @smid: system request message index 2153 * @handle: device handle 2154 * 2155 * Return nothing. 2156 */ 2157void 2158mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 2159{ 2160 Mpi2RequestDescriptorUnion_t descriptor; 2161 u64 *request = (u64 *)&descriptor; 2162 2163 2164 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 2165 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2166 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2167 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2168 descriptor.SCSIIO.LMID = 0; 2169 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2170 &ioc->scsi_lookup_lock); 2171} 2172 2173/** 2174 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware 2175 * @ioc: per adapter object 2176 * @smid: system request message index 2177 * @handle: device handle 2178 * 2179 * Return nothing. 2180 */ 2181void 2182mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 2183 u16 handle) 2184{ 2185 Mpi2RequestDescriptorUnion_t descriptor; 2186 u64 *request = (u64 *)&descriptor; 2187 2188 descriptor.SCSIIO.RequestFlags = 2189 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 2190 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 2191 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 2192 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 2193 descriptor.SCSIIO.LMID = 0; 2194 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2195 &ioc->scsi_lookup_lock); 2196} 2197 2198/** 2199 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware 2200 * @ioc: per adapter object 2201 * @smid: system request message index 2202 * 2203 * Return nothing. 2204 */ 2205void 2206mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2207{ 2208 Mpi2RequestDescriptorUnion_t descriptor; 2209 u64 *request = (u64 *)&descriptor; 2210 2211 descriptor.HighPriority.RequestFlags = 2212 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 2213 descriptor.HighPriority.MSIxIndex = 0; 2214 descriptor.HighPriority.SMID = cpu_to_le16(smid); 2215 descriptor.HighPriority.LMID = 0; 2216 descriptor.HighPriority.Reserved1 = 0; 2217 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2218 &ioc->scsi_lookup_lock); 2219} 2220 2221/** 2222 * mpt3sas_base_put_smid_default - Default, primarily used for config pages 2223 * @ioc: per adapter object 2224 * @smid: system request message index 2225 * 2226 * Return nothing. 2227 */ 2228void 2229mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 2230{ 2231 Mpi2RequestDescriptorUnion_t descriptor; 2232 u64 *request = (u64 *)&descriptor; 2233 2234 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2235 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); 2236 descriptor.Default.SMID = cpu_to_le16(smid); 2237 descriptor.Default.LMID = 0; 2238 descriptor.Default.DescriptorTypeDependent = 0; 2239 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 2240 &ioc->scsi_lookup_lock); 2241} 2242 2243/** 2244 * _base_display_intel_branding - Display branding string 2245 * @ioc: per adapter object 2246 * 2247 * Return nothing. 2248 */ 2249static void 2250_base_display_intel_branding(struct MPT3SAS_ADAPTER *ioc) 2251{ 2252 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 2253 return; 2254 2255 switch (ioc->pdev->device) { 2256 case MPI25_MFGPAGE_DEVID_SAS3008: 2257 switch (ioc->pdev->subsystem_device) { 2258 case MPT3SAS_INTEL_RMS3JC080_SSDID: 2259 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2260 MPT3SAS_INTEL_RMS3JC080_BRANDING); 2261 break; 2262 2263 case MPT3SAS_INTEL_RS3GC008_SSDID: 2264 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2265 MPT3SAS_INTEL_RS3GC008_BRANDING); 2266 break; 2267 case MPT3SAS_INTEL_RS3FC044_SSDID: 2268 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2269 MPT3SAS_INTEL_RS3FC044_BRANDING); 2270 break; 2271 case MPT3SAS_INTEL_RS3UC080_SSDID: 2272 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2273 MPT3SAS_INTEL_RS3UC080_BRANDING); 2274 break; 2275 default: 2276 pr_info(MPT3SAS_FMT 2277 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2278 ioc->name, ioc->pdev->subsystem_device); 2279 break; 2280 } 2281 break; 2282 default: 2283 pr_info(MPT3SAS_FMT 2284 "Intel(R) Controller: Subsystem ID: 0x%X\n", 2285 ioc->name, ioc->pdev->subsystem_device); 2286 break; 2287 } 2288} 2289 2290 2291 2292/** 2293 * _base_display_ioc_capabilities - Disply IOC's capabilities. 2294 * @ioc: per adapter object 2295 * 2296 * Return nothing. 2297 */ 2298static void 2299_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 2300{ 2301 int i = 0; 2302 char desc[16]; 2303 u32 iounit_pg1_flags; 2304 u32 bios_version; 2305 2306 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); 2307 strncpy(desc, ioc->manu_pg0.ChipName, 16); 2308 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ 2309 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", 2310 ioc->name, desc, 2311 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 2312 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 2313 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 2314 ioc->facts.FWVersion.Word & 0x000000FF, 2315 ioc->pdev->revision, 2316 (bios_version & 0xFF000000) >> 24, 2317 (bios_version & 0x00FF0000) >> 16, 2318 (bios_version & 0x0000FF00) >> 8, 2319 bios_version & 0x000000FF); 2320 2321 _base_display_intel_branding(ioc); 2322 2323 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); 2324 2325 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 2326 pr_info("Initiator"); 2327 i++; 2328 } 2329 2330 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 2331 pr_info("%sTarget", i ? "," : ""); 2332 i++; 2333 } 2334 2335 i = 0; 2336 pr_info("), "); 2337 pr_info("Capabilities=("); 2338 2339 if (ioc->facts.IOCCapabilities & 2340 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 2341 pr_info("Raid"); 2342 i++; 2343 } 2344 2345 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 2346 pr_info("%sTLR", i ? "," : ""); 2347 i++; 2348 } 2349 2350 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 2351 pr_info("%sMulticast", i ? "," : ""); 2352 i++; 2353 } 2354 2355 if (ioc->facts.IOCCapabilities & 2356 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 2357 pr_info("%sBIDI Target", i ? "," : ""); 2358 i++; 2359 } 2360 2361 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 2362 pr_info("%sEEDP", i ? "," : ""); 2363 i++; 2364 } 2365 2366 if (ioc->facts.IOCCapabilities & 2367 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 2368 pr_info("%sSnapshot Buffer", i ? "," : ""); 2369 i++; 2370 } 2371 2372 if (ioc->facts.IOCCapabilities & 2373 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 2374 pr_info("%sDiag Trace Buffer", i ? "," : ""); 2375 i++; 2376 } 2377 2378 if (ioc->facts.IOCCapabilities & 2379 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 2380 pr_info("%sDiag Extended Buffer", i ? "," : ""); 2381 i++; 2382 } 2383 2384 if (ioc->facts.IOCCapabilities & 2385 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 2386 pr_info("%sTask Set Full", i ? "," : ""); 2387 i++; 2388 } 2389 2390 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 2391 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 2392 pr_info("%sNCQ", i ? "," : ""); 2393 i++; 2394 } 2395 2396 pr_info(")\n"); 2397} 2398 2399/** 2400 * mpt3sas_base_update_missing_delay - change the missing delay timers 2401 * @ioc: per adapter object 2402 * @device_missing_delay: amount of time till device is reported missing 2403 * @io_missing_delay: interval IO is returned when there is a missing device 2404 * 2405 * Return nothing. 2406 * 2407 * Passed on the command line, this function will modify the device missing 2408 * delay, as well as the io missing delay. This should be called at driver 2409 * load time. 2410 */ 2411void 2412mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 2413 u16 device_missing_delay, u8 io_missing_delay) 2414{ 2415 u16 dmd, dmd_new, dmd_orignal; 2416 u8 io_missing_delay_original; 2417 u16 sz; 2418 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 2419 Mpi2ConfigReply_t mpi_reply; 2420 u8 num_phys = 0; 2421 u16 ioc_status; 2422 2423 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 2424 if (!num_phys) 2425 return; 2426 2427 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 2428 sizeof(Mpi2SasIOUnit1PhyData_t)); 2429 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 2430 if (!sas_iounit_pg1) { 2431 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 2432 ioc->name, __FILE__, __LINE__, __func__); 2433 goto out; 2434 } 2435 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 2436 sas_iounit_pg1, sz))) { 2437 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 2438 ioc->name, __FILE__, __LINE__, __func__); 2439 goto out; 2440 } 2441 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 2442 MPI2_IOCSTATUS_MASK; 2443 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 2444 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 2445 ioc->name, __FILE__, __LINE__, __func__); 2446 goto out; 2447 } 2448 2449 /* device missing delay */ 2450 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 2451 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 2452 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 2453 else 2454 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 2455 dmd_orignal = dmd; 2456 if (device_missing_delay > 0x7F) { 2457 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 2458 device_missing_delay; 2459 dmd = dmd / 16; 2460 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 2461 } else 2462 dmd = device_missing_delay; 2463 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 2464 2465 /* io missing delay */ 2466 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 2467 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 2468 2469 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 2470 sz)) { 2471 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 2472 dmd_new = (dmd & 2473 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 2474 else 2475 dmd_new = 2476 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 2477 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", 2478 ioc->name, dmd_orignal, dmd_new); 2479 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", 2480 ioc->name, io_missing_delay_original, 2481 io_missing_delay); 2482 ioc->device_missing_delay = dmd_new; 2483 ioc->io_missing_delay = io_missing_delay; 2484 } 2485 2486out: 2487 kfree(sas_iounit_pg1); 2488} 2489/** 2490 * _base_static_config_pages - static start of day config pages 2491 * @ioc: per adapter object 2492 * 2493 * Return nothing. 2494 */ 2495static void 2496_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 2497{ 2498 Mpi2ConfigReply_t mpi_reply; 2499 u32 iounit_pg1_flags; 2500 2501 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); 2502 if (ioc->ir_firmware) 2503 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 2504 &ioc->manu_pg10); 2505 2506 /* 2507 * Ensure correct T10 PI operation if vendor left EEDPTagMode 2508 * flag unset in NVDATA. 2509 */ 2510 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); 2511 if (ioc->manu_pg11.EEDPTagMode == 0) { 2512 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 2513 ioc->name); 2514 ioc->manu_pg11.EEDPTagMode &= ~0x3; 2515 ioc->manu_pg11.EEDPTagMode |= 0x1; 2516 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 2517 &ioc->manu_pg11); 2518 } 2519 2520 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 2521 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 2522 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 2523 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 2524 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 2525 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 2526 _base_display_ioc_capabilities(ioc); 2527 2528 /* 2529 * Enable task_set_full handling in iounit_pg1 when the 2530 * facts capabilities indicate that its supported. 2531 */ 2532 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 2533 if ((ioc->facts.IOCCapabilities & 2534 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 2535 iounit_pg1_flags &= 2536 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 2537 else 2538 iounit_pg1_flags |= 2539 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 2540 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 2541 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 2542 2543 if (ioc->iounit_pg8.NumSensors) 2544 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 2545} 2546 2547/** 2548 * _base_release_memory_pools - release memory 2549 * @ioc: per adapter object 2550 * 2551 * Free memory allocated from _base_allocate_memory_pools. 2552 * 2553 * Return nothing. 2554 */ 2555static void 2556_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 2557{ 2558 int i = 0; 2559 struct reply_post_struct *rps; 2560 2561 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2562 __func__)); 2563 2564 if (ioc->request) { 2565 pci_free_consistent(ioc->pdev, ioc->request_dma_sz, 2566 ioc->request, ioc->request_dma); 2567 dexitprintk(ioc, pr_info(MPT3SAS_FMT 2568 "request_pool(0x%p): free\n", 2569 ioc->name, ioc->request)); 2570 ioc->request = NULL; 2571 } 2572 2573 if (ioc->sense) { 2574 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 2575 if (ioc->sense_dma_pool) 2576 pci_pool_destroy(ioc->sense_dma_pool); 2577 dexitprintk(ioc, pr_info(MPT3SAS_FMT 2578 "sense_pool(0x%p): free\n", 2579 ioc->name, ioc->sense)); 2580 ioc->sense = NULL; 2581 } 2582 2583 if (ioc->reply) { 2584 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 2585 if (ioc->reply_dma_pool) 2586 pci_pool_destroy(ioc->reply_dma_pool); 2587 dexitprintk(ioc, pr_info(MPT3SAS_FMT 2588 "reply_pool(0x%p): free\n", 2589 ioc->name, ioc->reply)); 2590 ioc->reply = NULL; 2591 } 2592 2593 if (ioc->reply_free) { 2594 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 2595 ioc->reply_free_dma); 2596 if (ioc->reply_free_dma_pool) 2597 pci_pool_destroy(ioc->reply_free_dma_pool); 2598 dexitprintk(ioc, pr_info(MPT3SAS_FMT 2599 "reply_free_pool(0x%p): free\n", 2600 ioc->name, ioc->reply_free)); 2601 ioc->reply_free = NULL; 2602 } 2603 2604 if (ioc->reply_post) { 2605 do { 2606 rps = &ioc->reply_post[i]; 2607 if (rps->reply_post_free) { 2608 pci_pool_free( 2609 ioc->reply_post_free_dma_pool, 2610 rps->reply_post_free, 2611 rps->reply_post_free_dma); 2612 dexitprintk(ioc, pr_info(MPT3SAS_FMT 2613 "reply_post_free_pool(0x%p): free\n", 2614 ioc->name, rps->reply_post_free)); 2615 rps->reply_post_free = NULL; 2616 } 2617 } while (ioc->rdpq_array_enable && 2618 (++i < ioc->reply_queue_count)); 2619 2620 if (ioc->reply_post_free_dma_pool) 2621 pci_pool_destroy(ioc->reply_post_free_dma_pool); 2622 kfree(ioc->reply_post); 2623 } 2624 2625 if (ioc->config_page) { 2626 dexitprintk(ioc, pr_info(MPT3SAS_FMT 2627 "config_page(0x%p): free\n", ioc->name, 2628 ioc->config_page)); 2629 pci_free_consistent(ioc->pdev, ioc->config_page_sz, 2630 ioc->config_page, ioc->config_page_dma); 2631 } 2632 2633 if (ioc->scsi_lookup) { 2634 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages); 2635 ioc->scsi_lookup = NULL; 2636 } 2637 kfree(ioc->hpr_lookup); 2638 kfree(ioc->internal_lookup); 2639 if (ioc->chain_lookup) { 2640 for (i = 0; i < ioc->chain_depth; i++) { 2641 if (ioc->chain_lookup[i].chain_buffer) 2642 pci_pool_free(ioc->chain_dma_pool, 2643 ioc->chain_lookup[i].chain_buffer, 2644 ioc->chain_lookup[i].chain_buffer_dma); 2645 } 2646 if (ioc->chain_dma_pool) 2647 pci_pool_destroy(ioc->chain_dma_pool); 2648 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages); 2649 ioc->chain_lookup = NULL; 2650 } 2651} 2652 2653/** 2654 * _base_allocate_memory_pools - allocate start of day memory pools 2655 * @ioc: per adapter object 2656 * @sleep_flag: CAN_SLEEP or NO_SLEEP 2657 * 2658 * Returns 0 success, anything else error 2659 */ 2660static int 2661_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 2662{ 2663 struct mpt3sas_facts *facts; 2664 u16 max_sge_elements; 2665 u16 chains_needed_per_io; 2666 u32 sz, total_sz, reply_post_free_sz; 2667 u32 retry_sz; 2668 u16 max_request_credit; 2669 unsigned short sg_tablesize; 2670 u16 sge_size; 2671 int i; 2672 2673 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 2674 __func__)); 2675 2676 2677 retry_sz = 0; 2678 facts = &ioc->facts; 2679 2680 /* command line tunables for max sgl entries */ 2681 if (max_sgl_entries != -1) 2682 sg_tablesize = max_sgl_entries; 2683 else 2684 sg_tablesize = MPT3SAS_SG_DEPTH; 2685 2686 if (sg_tablesize < MPT3SAS_MIN_PHYS_SEGMENTS) 2687 sg_tablesize = MPT3SAS_MIN_PHYS_SEGMENTS; 2688 else if (sg_tablesize > MPT3SAS_MAX_PHYS_SEGMENTS) { 2689 sg_tablesize = min_t(unsigned short, sg_tablesize, 2690 SCSI_MAX_SG_CHAIN_SEGMENTS); 2691 pr_warn(MPT3SAS_FMT 2692 "sg_tablesize(%u) is bigger than kernel" 2693 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name, 2694 sg_tablesize, MPT3SAS_MAX_PHYS_SEGMENTS); 2695 } 2696 ioc->shost->sg_tablesize = sg_tablesize; 2697 2698 ioc->hi_priority_depth = facts->HighPriorityCredit; 2699 ioc->internal_depth = ioc->hi_priority_depth + (5); 2700 /* command line tunables for max controller queue depth */ 2701 if (max_queue_depth != -1 && max_queue_depth != 0) { 2702 max_request_credit = min_t(u16, max_queue_depth + 2703 ioc->hi_priority_depth + ioc->internal_depth, 2704 facts->RequestCredit); 2705 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 2706 max_request_credit = MAX_HBA_QUEUE_DEPTH; 2707 } else 2708 max_request_credit = min_t(u16, facts->RequestCredit, 2709 MAX_HBA_QUEUE_DEPTH); 2710 2711 ioc->hba_queue_depth = max_request_credit; 2712 2713 /* request frame size */ 2714 ioc->request_sz = facts->IOCRequestFrameSize * 4; 2715 2716 /* reply frame size */ 2717 ioc->reply_sz = facts->ReplyFrameSize * 4; 2718 2719 /* calculate the max scatter element size */ 2720 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 2721 2722 retry_allocation: 2723 total_sz = 0; 2724 /* calculate number of sg elements left over in the 1st frame */ 2725 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 2726 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 2727 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 2728 2729 /* now do the same for a chain buffer */ 2730 max_sge_elements = ioc->request_sz - sge_size; 2731 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 2732 2733 /* 2734 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 2735 */ 2736 chains_needed_per_io = ((ioc->shost->sg_tablesize - 2737 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 2738 + 1; 2739 if (chains_needed_per_io > facts->MaxChainDepth) { 2740 chains_needed_per_io = facts->MaxChainDepth; 2741 ioc->shost->sg_tablesize = min_t(u16, 2742 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 2743 * chains_needed_per_io), ioc->shost->sg_tablesize); 2744 } 2745 ioc->chains_needed_per_io = chains_needed_per_io; 2746 2747 /* reply free queue sizing - taking into account for 64 FW events */ 2748 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 2749 2750 /* calculate reply descriptor post queue depth */ 2751 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 2752 ioc->reply_free_queue_depth + 1 ; 2753 /* align the reply post queue on the next 16 count boundary */ 2754 if (ioc->reply_post_queue_depth % 16) 2755 ioc->reply_post_queue_depth += 16 - 2756 (ioc->reply_post_queue_depth % 16); 2757 2758 2759 if (ioc->reply_post_queue_depth > 2760 facts->MaxReplyDescriptorPostQueueDepth) { 2761 ioc->reply_post_queue_depth = 2762 facts->MaxReplyDescriptorPostQueueDepth - 2763 (facts->MaxReplyDescriptorPostQueueDepth % 16); 2764 ioc->hba_queue_depth = 2765 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 2766 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 2767 } 2768 2769 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ 2770 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " 2771 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, 2772 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, 2773 ioc->chains_needed_per_io)); 2774 2775 /* reply post queue, 16 byte align */ 2776 reply_post_free_sz = ioc->reply_post_queue_depth * 2777 sizeof(Mpi2DefaultReplyDescriptor_t); 2778 2779 sz = reply_post_free_sz; 2780 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 2781 sz *= ioc->reply_queue_count; 2782 2783 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? 2784 (ioc->reply_queue_count):1, 2785 sizeof(struct reply_post_struct), GFP_KERNEL); 2786 2787 if (!ioc->reply_post) { 2788 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", 2789 ioc->name); 2790 goto out; 2791 } 2792 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool", 2793 ioc->pdev, sz, 16, 0); 2794 if (!ioc->reply_post_free_dma_pool) { 2795 pr_err(MPT3SAS_FMT 2796 "reply_post_free pool: pci_pool_create failed\n", 2797 ioc->name); 2798 goto out; 2799 } 2800 i = 0; 2801 do { 2802 ioc->reply_post[i].reply_post_free = 2803 pci_pool_alloc(ioc->reply_post_free_dma_pool, 2804 GFP_KERNEL, 2805 &ioc->reply_post[i].reply_post_free_dma); 2806 if (!ioc->reply_post[i].reply_post_free) { 2807 pr_err(MPT3SAS_FMT 2808 "reply_post_free pool: pci_pool_alloc failed\n", 2809 ioc->name); 2810 goto out; 2811 } 2812 memset(ioc->reply_post[i].reply_post_free, 0, sz); 2813 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2814 "reply post free pool (0x%p): depth(%d)," 2815 "element_size(%d), pool_size(%d kB)\n", ioc->name, 2816 ioc->reply_post[i].reply_post_free, 2817 ioc->reply_post_queue_depth, 8, sz/1024)); 2818 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2819 "reply_post_free_dma = (0x%llx)\n", ioc->name, 2820 (unsigned long long) 2821 ioc->reply_post[i].reply_post_free_dma)); 2822 total_sz += sz; 2823 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); 2824 2825 if (ioc->dma_mask == 64) { 2826 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { 2827 pr_warn(MPT3SAS_FMT 2828 "no suitable consistent DMA mask for %s\n", 2829 ioc->name, pci_name(ioc->pdev)); 2830 goto out; 2831 } 2832 } 2833 2834 ioc->scsiio_depth = ioc->hba_queue_depth - 2835 ioc->hi_priority_depth - ioc->internal_depth; 2836 2837 /* set the scsi host can_queue depth 2838 * with some internal commands that could be outstanding 2839 */ 2840 ioc->shost->can_queue = ioc->scsiio_depth; 2841 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2842 "scsi host: can_queue depth (%d)\n", 2843 ioc->name, ioc->shost->can_queue)); 2844 2845 2846 /* contiguous pool for request and chains, 16 byte align, one extra " 2847 * "frame for smid=0 2848 */ 2849 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 2850 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 2851 2852 /* hi-priority queue */ 2853 sz += (ioc->hi_priority_depth * ioc->request_sz); 2854 2855 /* internal queue */ 2856 sz += (ioc->internal_depth * ioc->request_sz); 2857 2858 ioc->request_dma_sz = sz; 2859 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); 2860 if (!ioc->request) { 2861 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 2862 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 2863 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, 2864 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 2865 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 2866 goto out; 2867 retry_sz += 64; 2868 ioc->hba_queue_depth = max_request_credit - retry_sz; 2869 goto retry_allocation; 2870 } 2871 2872 if (retry_sz) 2873 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 2874 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 2875 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, 2876 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 2877 2878 /* hi-priority queue */ 2879 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 2880 ioc->request_sz); 2881 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 2882 ioc->request_sz); 2883 2884 /* internal queue */ 2885 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 2886 ioc->request_sz); 2887 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 2888 ioc->request_sz); 2889 2890 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2891 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 2892 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, 2893 (ioc->hba_queue_depth * ioc->request_sz)/1024)); 2894 2895 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", 2896 ioc->name, (unsigned long long) ioc->request_dma)); 2897 total_sz += sz; 2898 2899 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker); 2900 ioc->scsi_lookup_pages = get_order(sz); 2901 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages( 2902 GFP_KERNEL, ioc->scsi_lookup_pages); 2903 if (!ioc->scsi_lookup) { 2904 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n", 2905 ioc->name, (int)sz); 2906 goto out; 2907 } 2908 2909 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", 2910 ioc->name, ioc->request, ioc->scsiio_depth)); 2911 2912 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 2913 sz = ioc->chain_depth * sizeof(struct chain_tracker); 2914 ioc->chain_pages = get_order(sz); 2915 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages( 2916 GFP_KERNEL, ioc->chain_pages); 2917 if (!ioc->chain_lookup) { 2918 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n", 2919 ioc->name); 2920 goto out; 2921 } 2922 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev, 2923 ioc->request_sz, 16, 0); 2924 if (!ioc->chain_dma_pool) { 2925 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n", 2926 ioc->name); 2927 goto out; 2928 } 2929 for (i = 0; i < ioc->chain_depth; i++) { 2930 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc( 2931 ioc->chain_dma_pool , GFP_KERNEL, 2932 &ioc->chain_lookup[i].chain_buffer_dma); 2933 if (!ioc->chain_lookup[i].chain_buffer) { 2934 ioc->chain_depth = i; 2935 goto chain_done; 2936 } 2937 total_sz += ioc->request_sz; 2938 } 2939 chain_done: 2940 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2941 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 2942 ioc->name, ioc->chain_depth, ioc->request_sz, 2943 ((ioc->chain_depth * ioc->request_sz))/1024)); 2944 2945 /* initialize hi-priority queue smid's */ 2946 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 2947 sizeof(struct request_tracker), GFP_KERNEL); 2948 if (!ioc->hpr_lookup) { 2949 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", 2950 ioc->name); 2951 goto out; 2952 } 2953 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 2954 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2955 "hi_priority(0x%p): depth(%d), start smid(%d)\n", 2956 ioc->name, ioc->hi_priority, 2957 ioc->hi_priority_depth, ioc->hi_priority_smid)); 2958 2959 /* initialize internal queue smid's */ 2960 ioc->internal_lookup = kcalloc(ioc->internal_depth, 2961 sizeof(struct request_tracker), GFP_KERNEL); 2962 if (!ioc->internal_lookup) { 2963 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", 2964 ioc->name); 2965 goto out; 2966 } 2967 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 2968 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2969 "internal(0x%p): depth(%d), start smid(%d)\n", 2970 ioc->name, ioc->internal, 2971 ioc->internal_depth, ioc->internal_smid)); 2972 2973 /* sense buffers, 4 byte align */ 2974 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 2975 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4, 2976 0); 2977 if (!ioc->sense_dma_pool) { 2978 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n", 2979 ioc->name); 2980 goto out; 2981 } 2982 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL, 2983 &ioc->sense_dma); 2984 if (!ioc->sense) { 2985 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n", 2986 ioc->name); 2987 goto out; 2988 } 2989 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2990 "sense pool(0x%p): depth(%d), element_size(%d), pool_size" 2991 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, 2992 SCSI_SENSE_BUFFERSIZE, sz/1024)); 2993 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", 2994 ioc->name, (unsigned long long)ioc->sense_dma)); 2995 total_sz += sz; 2996 2997 /* reply pool, 4 byte align */ 2998 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 2999 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4, 3000 0); 3001 if (!ioc->reply_dma_pool) { 3002 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n", 3003 ioc->name); 3004 goto out; 3005 } 3006 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL, 3007 &ioc->reply_dma); 3008 if (!ioc->reply) { 3009 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n", 3010 ioc->name); 3011 goto out; 3012 } 3013 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 3014 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 3015 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3016 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 3017 ioc->name, ioc->reply, 3018 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); 3019 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", 3020 ioc->name, (unsigned long long)ioc->reply_dma)); 3021 total_sz += sz; 3022 3023 /* reply free queue, 16 byte align */ 3024 sz = ioc->reply_free_queue_depth * 4; 3025 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool", 3026 ioc->pdev, sz, 16, 0); 3027 if (!ioc->reply_free_dma_pool) { 3028 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n", 3029 ioc->name); 3030 goto out; 3031 } 3032 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL, 3033 &ioc->reply_free_dma); 3034 if (!ioc->reply_free) { 3035 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n", 3036 ioc->name); 3037 goto out; 3038 } 3039 memset(ioc->reply_free, 0, sz); 3040 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ 3041 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, 3042 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 3043 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3044 "reply_free_dma (0x%llx)\n", 3045 ioc->name, (unsigned long long)ioc->reply_free_dma)); 3046 total_sz += sz; 3047 3048 ioc->config_page_sz = 512; 3049 ioc->config_page = pci_alloc_consistent(ioc->pdev, 3050 ioc->config_page_sz, &ioc->config_page_dma); 3051 if (!ioc->config_page) { 3052 pr_err(MPT3SAS_FMT 3053 "config page: pci_pool_alloc failed\n", 3054 ioc->name); 3055 goto out; 3056 } 3057 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3058 "config page(0x%p): size(%d)\n", 3059 ioc->name, ioc->config_page, ioc->config_page_sz)); 3060 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", 3061 ioc->name, (unsigned long long)ioc->config_page_dma)); 3062 total_sz += ioc->config_page_sz; 3063 3064 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", 3065 ioc->name, total_sz/1024); 3066 pr_info(MPT3SAS_FMT 3067 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 3068 ioc->name, ioc->shost->can_queue, facts->RequestCredit); 3069 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", 3070 ioc->name, ioc->shost->sg_tablesize); 3071 return 0; 3072 3073 out: 3074 return -ENOMEM; 3075} 3076 3077/** 3078 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 3079 * @ioc: Pointer to MPT_ADAPTER structure 3080 * @cooked: Request raw or cooked IOC state 3081 * 3082 * Returns all IOC Doorbell register bits if cooked==0, else just the 3083 * Doorbell bits in MPI_IOC_STATE_MASK. 3084 */ 3085u32 3086mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 3087{ 3088 u32 s, sc; 3089 3090 s = readl(&ioc->chip->Doorbell); 3091 sc = s & MPI2_IOC_STATE_MASK; 3092 return cooked ? sc : s; 3093} 3094 3095/** 3096 * _base_wait_on_iocstate - waiting on a particular ioc state 3097 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 3098 * @timeout: timeout in second 3099 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3100 * 3101 * Returns 0 for success, non-zero for failure. 3102 */ 3103static int 3104_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout, 3105 int sleep_flag) 3106{ 3107 u32 count, cntdn; 3108 u32 current_state; 3109 3110 count = 0; 3111 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3112 do { 3113 current_state = mpt3sas_base_get_iocstate(ioc, 1); 3114 if (current_state == ioc_state) 3115 return 0; 3116 if (count && current_state == MPI2_IOC_STATE_FAULT) 3117 break; 3118 if (sleep_flag == CAN_SLEEP) 3119 usleep_range(1000, 1500); 3120 else 3121 udelay(500); 3122 count++; 3123 } while (--cntdn); 3124 3125 return current_state; 3126} 3127 3128/** 3129 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 3130 * a write to the doorbell) 3131 * @ioc: per adapter object 3132 * @timeout: timeout in second 3133 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3134 * 3135 * Returns 0 for success, non-zero for failure. 3136 * 3137 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 3138 */ 3139static int 3140_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout, 3141 int sleep_flag) 3142{ 3143 u32 cntdn, count; 3144 u32 int_status; 3145 3146 count = 0; 3147 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3148 do { 3149 int_status = readl(&ioc->chip->HostInterruptStatus); 3150 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3151 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3152 "%s: successful count(%d), timeout(%d)\n", 3153 ioc->name, __func__, count, timeout)); 3154 return 0; 3155 } 3156 if (sleep_flag == CAN_SLEEP) 3157 usleep_range(1000, 1500); 3158 else 3159 udelay(500); 3160 count++; 3161 } while (--cntdn); 3162 3163 pr_err(MPT3SAS_FMT 3164 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3165 ioc->name, __func__, count, int_status); 3166 return -EFAULT; 3167} 3168 3169/** 3170 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 3171 * @ioc: per adapter object 3172 * @timeout: timeout in second 3173 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3174 * 3175 * Returns 0 for success, non-zero for failure. 3176 * 3177 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 3178 * doorbell. 3179 */ 3180static int 3181_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout, 3182 int sleep_flag) 3183{ 3184 u32 cntdn, count; 3185 u32 int_status; 3186 u32 doorbell; 3187 3188 count = 0; 3189 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3190 do { 3191 int_status = readl(&ioc->chip->HostInterruptStatus); 3192 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 3193 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3194 "%s: successful count(%d), timeout(%d)\n", 3195 ioc->name, __func__, count, timeout)); 3196 return 0; 3197 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 3198 doorbell = readl(&ioc->chip->Doorbell); 3199 if ((doorbell & MPI2_IOC_STATE_MASK) == 3200 MPI2_IOC_STATE_FAULT) { 3201 mpt3sas_base_fault_info(ioc , doorbell); 3202 return -EFAULT; 3203 } 3204 } else if (int_status == 0xFFFFFFFF) 3205 goto out; 3206 3207 if (sleep_flag == CAN_SLEEP) 3208 usleep_range(1000, 1500); 3209 else 3210 udelay(500); 3211 count++; 3212 } while (--cntdn); 3213 3214 out: 3215 pr_err(MPT3SAS_FMT 3216 "%s: failed due to timeout count(%d), int_status(%x)!\n", 3217 ioc->name, __func__, count, int_status); 3218 return -EFAULT; 3219} 3220 3221/** 3222 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 3223 * @ioc: per adapter object 3224 * @timeout: timeout in second 3225 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3226 * 3227 * Returns 0 for success, non-zero for failure. 3228 * 3229 */ 3230static int 3231_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout, 3232 int sleep_flag) 3233{ 3234 u32 cntdn, count; 3235 u32 doorbell_reg; 3236 3237 count = 0; 3238 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 3239 do { 3240 doorbell_reg = readl(&ioc->chip->Doorbell); 3241 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 3242 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3243 "%s: successful count(%d), timeout(%d)\n", 3244 ioc->name, __func__, count, timeout)); 3245 return 0; 3246 } 3247 if (sleep_flag == CAN_SLEEP) 3248 usleep_range(1000, 1500); 3249 else 3250 udelay(500); 3251 count++; 3252 } while (--cntdn); 3253 3254 pr_err(MPT3SAS_FMT 3255 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 3256 ioc->name, __func__, count, doorbell_reg); 3257 return -EFAULT; 3258} 3259 3260/** 3261 * _base_send_ioc_reset - send doorbell reset 3262 * @ioc: per adapter object 3263 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 3264 * @timeout: timeout in second 3265 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3266 * 3267 * Returns 0 for success, non-zero for failure. 3268 */ 3269static int 3270_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout, 3271 int sleep_flag) 3272{ 3273 u32 ioc_state; 3274 int r = 0; 3275 3276 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 3277 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", 3278 ioc->name, __func__); 3279 return -EFAULT; 3280 } 3281 3282 if (!(ioc->facts.IOCCapabilities & 3283 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 3284 return -EFAULT; 3285 3286 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); 3287 3288 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 3289 &ioc->chip->Doorbell); 3290 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) { 3291 r = -EFAULT; 3292 goto out; 3293 } 3294 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 3295 timeout, sleep_flag); 3296 if (ioc_state) { 3297 pr_err(MPT3SAS_FMT 3298 "%s: failed going to ready state (ioc_state=0x%x)\n", 3299 ioc->name, __func__, ioc_state); 3300 r = -EFAULT; 3301 goto out; 3302 } 3303 out: 3304 pr_info(MPT3SAS_FMT "message unit reset: %s\n", 3305 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); 3306 return r; 3307} 3308 3309/** 3310 * _base_handshake_req_reply_wait - send request thru doorbell interface 3311 * @ioc: per adapter object 3312 * @request_bytes: request length 3313 * @request: pointer having request payload 3314 * @reply_bytes: reply length 3315 * @reply: pointer to reply payload 3316 * @timeout: timeout in second 3317 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3318 * 3319 * Returns 0 for success, non-zero for failure. 3320 */ 3321static int 3322_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 3323 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag) 3324{ 3325 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 3326 int i; 3327 u8 failed; 3328 u16 dummy; 3329 __le32 *mfp; 3330 3331 /* make sure doorbell is not in use */ 3332 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 3333 pr_err(MPT3SAS_FMT 3334 "doorbell is in use (line=%d)\n", 3335 ioc->name, __LINE__); 3336 return -EFAULT; 3337 } 3338 3339 /* clear pending doorbell interrupts from previous state changes */ 3340 if (readl(&ioc->chip->HostInterruptStatus) & 3341 MPI2_HIS_IOC2SYS_DB_STATUS) 3342 writel(0, &ioc->chip->HostInterruptStatus); 3343 3344 /* send message to ioc */ 3345 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 3346 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 3347 &ioc->chip->Doorbell); 3348 3349 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) { 3350 pr_err(MPT3SAS_FMT 3351 "doorbell handshake int failed (line=%d)\n", 3352 ioc->name, __LINE__); 3353 return -EFAULT; 3354 } 3355 writel(0, &ioc->chip->HostInterruptStatus); 3356 3357 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) { 3358 pr_err(MPT3SAS_FMT 3359 "doorbell handshake ack failed (line=%d)\n", 3360 ioc->name, __LINE__); 3361 return -EFAULT; 3362 } 3363 3364 /* send message 32-bits at a time */ 3365 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 3366 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 3367 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) 3368 failed = 1; 3369 } 3370 3371 if (failed) { 3372 pr_err(MPT3SAS_FMT 3373 "doorbell handshake sending request failed (line=%d)\n", 3374 ioc->name, __LINE__); 3375 return -EFAULT; 3376 } 3377 3378 /* now wait for the reply */ 3379 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) { 3380 pr_err(MPT3SAS_FMT 3381 "doorbell handshake int failed (line=%d)\n", 3382 ioc->name, __LINE__); 3383 return -EFAULT; 3384 } 3385 3386 /* read the first two 16-bits, it gives the total length of the reply */ 3387 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) 3388 & MPI2_DOORBELL_DATA_MASK); 3389 writel(0, &ioc->chip->HostInterruptStatus); 3390 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { 3391 pr_err(MPT3SAS_FMT 3392 "doorbell handshake int failed (line=%d)\n", 3393 ioc->name, __LINE__); 3394 return -EFAULT; 3395 } 3396 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) 3397 & MPI2_DOORBELL_DATA_MASK); 3398 writel(0, &ioc->chip->HostInterruptStatus); 3399 3400 for (i = 2; i < default_reply->MsgLength * 2; i++) { 3401 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) { 3402 pr_err(MPT3SAS_FMT 3403 "doorbell handshake int failed (line=%d)\n", 3404 ioc->name, __LINE__); 3405 return -EFAULT; 3406 } 3407 if (i >= reply_bytes/2) /* overflow case */ 3408 dummy = readl(&ioc->chip->Doorbell); 3409 else 3410 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) 3411 & MPI2_DOORBELL_DATA_MASK); 3412 writel(0, &ioc->chip->HostInterruptStatus); 3413 } 3414 3415 _base_wait_for_doorbell_int(ioc, 5, sleep_flag); 3416 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) { 3417 dhsprintk(ioc, pr_info(MPT3SAS_FMT 3418 "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); 3419 } 3420 writel(0, &ioc->chip->HostInterruptStatus); 3421 3422 if (ioc->logging_level & MPT_DEBUG_INIT) { 3423 mfp = (__le32 *)reply; 3424 pr_info("\toffset:data\n"); 3425 for (i = 0; i < reply_bytes/4; i++) 3426 pr_info("\t[0x%02x]:%08x\n", i*4, 3427 le32_to_cpu(mfp[i])); 3428 } 3429 return 0; 3430} 3431 3432/** 3433 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 3434 * @ioc: per adapter object 3435 * @mpi_reply: the reply payload from FW 3436 * @mpi_request: the request payload sent to FW 3437 * 3438 * The SAS IO Unit Control Request message allows the host to perform low-level 3439 * operations, such as resets on the PHYs of the IO Unit, also allows the host 3440 * to obtain the IOC assigned device handles for a device if it has other 3441 * identifying information about the device, in addition allows the host to 3442 * remove IOC resources associated with the device. 3443 * 3444 * Returns 0 for success, non-zero for failure. 3445 */ 3446int 3447mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 3448 Mpi2SasIoUnitControlReply_t *mpi_reply, 3449 Mpi2SasIoUnitControlRequest_t *mpi_request) 3450{ 3451 u16 smid; 3452 u32 ioc_state; 3453 unsigned long timeleft; 3454 bool issue_reset = false; 3455 int rc; 3456 void *request; 3457 u16 wait_state_count; 3458 3459 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3460 __func__)); 3461 3462 mutex_lock(&ioc->base_cmds.mutex); 3463 3464 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 3465 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 3466 ioc->name, __func__); 3467 rc = -EAGAIN; 3468 goto out; 3469 } 3470 3471 wait_state_count = 0; 3472 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 3473 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 3474 if (wait_state_count++ == 10) { 3475 pr_err(MPT3SAS_FMT 3476 "%s: failed due to ioc not operational\n", 3477 ioc->name, __func__); 3478 rc = -EFAULT; 3479 goto out; 3480 } 3481 ssleep(1); 3482 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 3483 pr_info(MPT3SAS_FMT 3484 "%s: waiting for operational state(count=%d)\n", 3485 ioc->name, __func__, wait_state_count); 3486 } 3487 3488 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 3489 if (!smid) { 3490 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 3491 ioc->name, __func__); 3492 rc = -EAGAIN; 3493 goto out; 3494 } 3495 3496 rc = 0; 3497 ioc->base_cmds.status = MPT3_CMD_PENDING; 3498 request = mpt3sas_base_get_msg_frame(ioc, smid); 3499 ioc->base_cmds.smid = smid; 3500 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 3501 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 3502 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 3503 ioc->ioc_link_reset_in_progress = 1; 3504 init_completion(&ioc->base_cmds.done); 3505 mpt3sas_base_put_smid_default(ioc, smid); 3506 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 3507 msecs_to_jiffies(10000)); 3508 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 3509 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 3510 ioc->ioc_link_reset_in_progress) 3511 ioc->ioc_link_reset_in_progress = 0; 3512 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 3513 pr_err(MPT3SAS_FMT "%s: timeout\n", 3514 ioc->name, __func__); 3515 _debug_dump_mf(mpi_request, 3516 sizeof(Mpi2SasIoUnitControlRequest_t)/4); 3517 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 3518 issue_reset = true; 3519 goto issue_host_reset; 3520 } 3521 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 3522 memcpy(mpi_reply, ioc->base_cmds.reply, 3523 sizeof(Mpi2SasIoUnitControlReply_t)); 3524 else 3525 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 3526 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 3527 goto out; 3528 3529 issue_host_reset: 3530 if (issue_reset) 3531 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP, 3532 FORCE_BIG_HAMMER); 3533 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 3534 rc = -EFAULT; 3535 out: 3536 mutex_unlock(&ioc->base_cmds.mutex); 3537 return rc; 3538} 3539 3540/** 3541 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 3542 * @ioc: per adapter object 3543 * @mpi_reply: the reply payload from FW 3544 * @mpi_request: the request payload sent to FW 3545 * 3546 * The SCSI Enclosure Processor request message causes the IOC to 3547 * communicate with SES devices to control LED status signals. 3548 * 3549 * Returns 0 for success, non-zero for failure. 3550 */ 3551int 3552mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 3553 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 3554{ 3555 u16 smid; 3556 u32 ioc_state; 3557 unsigned long timeleft; 3558 bool issue_reset = false; 3559 int rc; 3560 void *request; 3561 u16 wait_state_count; 3562 3563 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3564 __func__)); 3565 3566 mutex_lock(&ioc->base_cmds.mutex); 3567 3568 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 3569 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 3570 ioc->name, __func__); 3571 rc = -EAGAIN; 3572 goto out; 3573 } 3574 3575 wait_state_count = 0; 3576 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 3577 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 3578 if (wait_state_count++ == 10) { 3579 pr_err(MPT3SAS_FMT 3580 "%s: failed due to ioc not operational\n", 3581 ioc->name, __func__); 3582 rc = -EFAULT; 3583 goto out; 3584 } 3585 ssleep(1); 3586 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 3587 pr_info(MPT3SAS_FMT 3588 "%s: waiting for operational state(count=%d)\n", 3589 ioc->name, 3590 __func__, wait_state_count); 3591 } 3592 3593 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 3594 if (!smid) { 3595 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 3596 ioc->name, __func__); 3597 rc = -EAGAIN; 3598 goto out; 3599 } 3600 3601 rc = 0; 3602 ioc->base_cmds.status = MPT3_CMD_PENDING; 3603 request = mpt3sas_base_get_msg_frame(ioc, smid); 3604 ioc->base_cmds.smid = smid; 3605 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 3606 init_completion(&ioc->base_cmds.done); 3607 mpt3sas_base_put_smid_default(ioc, smid); 3608 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 3609 msecs_to_jiffies(10000)); 3610 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 3611 pr_err(MPT3SAS_FMT "%s: timeout\n", 3612 ioc->name, __func__); 3613 _debug_dump_mf(mpi_request, 3614 sizeof(Mpi2SepRequest_t)/4); 3615 if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) 3616 issue_reset = false; 3617 goto issue_host_reset; 3618 } 3619 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 3620 memcpy(mpi_reply, ioc->base_cmds.reply, 3621 sizeof(Mpi2SepReply_t)); 3622 else 3623 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 3624 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 3625 goto out; 3626 3627 issue_host_reset: 3628 if (issue_reset) 3629 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP, 3630 FORCE_BIG_HAMMER); 3631 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 3632 rc = -EFAULT; 3633 out: 3634 mutex_unlock(&ioc->base_cmds.mutex); 3635 return rc; 3636} 3637 3638/** 3639 * _base_get_port_facts - obtain port facts reply and save in ioc 3640 * @ioc: per adapter object 3641 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3642 * 3643 * Returns 0 for success, non-zero for failure. 3644 */ 3645static int 3646_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag) 3647{ 3648 Mpi2PortFactsRequest_t mpi_request; 3649 Mpi2PortFactsReply_t mpi_reply; 3650 struct mpt3sas_port_facts *pfacts; 3651 int mpi_reply_sz, mpi_request_sz, r; 3652 3653 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3654 __func__)); 3655 3656 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 3657 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 3658 memset(&mpi_request, 0, mpi_request_sz); 3659 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 3660 mpi_request.PortNumber = port; 3661 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 3662 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP); 3663 3664 if (r != 0) { 3665 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 3666 ioc->name, __func__, r); 3667 return r; 3668 } 3669 3670 pfacts = &ioc->pfacts[port]; 3671 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 3672 pfacts->PortNumber = mpi_reply.PortNumber; 3673 pfacts->VP_ID = mpi_reply.VP_ID; 3674 pfacts->VF_ID = mpi_reply.VF_ID; 3675 pfacts->MaxPostedCmdBuffers = 3676 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 3677 3678 return 0; 3679} 3680 3681/** 3682 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 3683 * @ioc: per adapter object 3684 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3685 * 3686 * Returns 0 for success, non-zero for failure. 3687 */ 3688static int 3689_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 3690{ 3691 Mpi2IOCFactsRequest_t mpi_request; 3692 Mpi2IOCFactsReply_t mpi_reply; 3693 struct mpt3sas_facts *facts; 3694 int mpi_reply_sz, mpi_request_sz, r; 3695 3696 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3697 __func__)); 3698 3699 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 3700 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 3701 memset(&mpi_request, 0, mpi_request_sz); 3702 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 3703 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 3704 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP); 3705 3706 if (r != 0) { 3707 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 3708 ioc->name, __func__, r); 3709 return r; 3710 } 3711 3712 facts = &ioc->facts; 3713 memset(facts, 0, sizeof(struct mpt3sas_facts)); 3714 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 3715 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 3716 facts->VP_ID = mpi_reply.VP_ID; 3717 facts->VF_ID = mpi_reply.VF_ID; 3718 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 3719 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 3720 facts->WhoInit = mpi_reply.WhoInit; 3721 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 3722 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 3723 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 3724 facts->MaxReplyDescriptorPostQueueDepth = 3725 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 3726 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 3727 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 3728 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 3729 ioc->ir_firmware = 1; 3730 if ((facts->IOCCapabilities & 3731 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE)) 3732 ioc->rdpq_array_capable = 1; 3733 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 3734 facts->IOCRequestFrameSize = 3735 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 3736 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 3737 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 3738 ioc->shost->max_id = -1; 3739 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 3740 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 3741 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 3742 facts->HighPriorityCredit = 3743 le16_to_cpu(mpi_reply.HighPriorityCredit); 3744 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 3745 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 3746 3747 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3748 "hba queue depth(%d), max chains per io(%d)\n", 3749 ioc->name, facts->RequestCredit, 3750 facts->MaxChainDepth)); 3751 dinitprintk(ioc, pr_info(MPT3SAS_FMT 3752 "request frame size(%d), reply frame size(%d)\n", ioc->name, 3753 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); 3754 return 0; 3755} 3756 3757/** 3758 * _base_send_ioc_init - send ioc_init to firmware 3759 * @ioc: per adapter object 3760 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3761 * 3762 * Returns 0 for success, non-zero for failure. 3763 */ 3764static int 3765_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 3766{ 3767 Mpi2IOCInitRequest_t mpi_request; 3768 Mpi2IOCInitReply_t mpi_reply; 3769 int i, r = 0; 3770 struct timeval current_time; 3771 u16 ioc_status; 3772 u32 reply_post_free_array_sz = 0; 3773 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL; 3774 dma_addr_t reply_post_free_array_dma; 3775 3776 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3777 __func__)); 3778 3779 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 3780 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 3781 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 3782 mpi_request.VF_ID = 0; /* TODO */ 3783 mpi_request.VP_ID = 0; 3784 mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION); 3785 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 3786 3787 if (_base_is_controller_msix_enabled(ioc)) 3788 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 3789 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 3790 mpi_request.ReplyDescriptorPostQueueDepth = 3791 cpu_to_le16(ioc->reply_post_queue_depth); 3792 mpi_request.ReplyFreeQueueDepth = 3793 cpu_to_le16(ioc->reply_free_queue_depth); 3794 3795 mpi_request.SenseBufferAddressHigh = 3796 cpu_to_le32((u64)ioc->sense_dma >> 32); 3797 mpi_request.SystemReplyAddressHigh = 3798 cpu_to_le32((u64)ioc->reply_dma >> 32); 3799 mpi_request.SystemRequestFrameBaseAddress = 3800 cpu_to_le64((u64)ioc->request_dma); 3801 mpi_request.ReplyFreeQueueAddress = 3802 cpu_to_le64((u64)ioc->reply_free_dma); 3803 3804 if (ioc->rdpq_array_enable) { 3805 reply_post_free_array_sz = ioc->reply_queue_count * 3806 sizeof(Mpi2IOCInitRDPQArrayEntry); 3807 reply_post_free_array = pci_alloc_consistent(ioc->pdev, 3808 reply_post_free_array_sz, &reply_post_free_array_dma); 3809 if (!reply_post_free_array) { 3810 pr_err(MPT3SAS_FMT 3811 "reply_post_free_array: pci_alloc_consistent failed\n", 3812 ioc->name); 3813 r = -ENOMEM; 3814 goto out; 3815 } 3816 memset(reply_post_free_array, 0, reply_post_free_array_sz); 3817 for (i = 0; i < ioc->reply_queue_count; i++) 3818 reply_post_free_array[i].RDPQBaseAddress = 3819 cpu_to_le64( 3820 (u64)ioc->reply_post[i].reply_post_free_dma); 3821 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 3822 mpi_request.ReplyDescriptorPostQueueAddress = 3823 cpu_to_le64((u64)reply_post_free_array_dma); 3824 } else { 3825 mpi_request.ReplyDescriptorPostQueueAddress = 3826 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 3827 } 3828 3829 /* This time stamp specifies number of milliseconds 3830 * since epoch ~ midnight January 1, 1970. 3831 */ 3832 do_gettimeofday(¤t_time); 3833 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 + 3834 (current_time.tv_usec / 1000)); 3835 3836 if (ioc->logging_level & MPT_DEBUG_INIT) { 3837 __le32 *mfp; 3838 int i; 3839 3840 mfp = (__le32 *)&mpi_request; 3841 pr_info("\toffset:data\n"); 3842 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 3843 pr_info("\t[0x%02x]:%08x\n", i*4, 3844 le32_to_cpu(mfp[i])); 3845 } 3846 3847 r = _base_handshake_req_reply_wait(ioc, 3848 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 3849 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10, 3850 sleep_flag); 3851 3852 if (r != 0) { 3853 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 3854 ioc->name, __func__, r); 3855 goto out; 3856 } 3857 3858 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 3859 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 3860 mpi_reply.IOCLogInfo) { 3861 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); 3862 r = -EIO; 3863 } 3864 3865out: 3866 if (reply_post_free_array) 3867 pci_free_consistent(ioc->pdev, reply_post_free_array_sz, 3868 reply_post_free_array, 3869 reply_post_free_array_dma); 3870 return r; 3871} 3872 3873/** 3874 * mpt3sas_port_enable_done - command completion routine for port enable 3875 * @ioc: per adapter object 3876 * @smid: system request message index 3877 * @msix_index: MSIX table index supplied by the OS 3878 * @reply: reply message frame(lower 32bit addr) 3879 * 3880 * Return 1 meaning mf should be freed from _base_interrupt 3881 * 0 means the mf is freed from this function. 3882 */ 3883u8 3884mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 3885 u32 reply) 3886{ 3887 MPI2DefaultReply_t *mpi_reply; 3888 u16 ioc_status; 3889 3890 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 3891 return 1; 3892 3893 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 3894 if (!mpi_reply) 3895 return 1; 3896 3897 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 3898 return 1; 3899 3900 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 3901 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 3902 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 3903 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 3904 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 3905 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 3906 ioc->port_enable_failed = 1; 3907 3908 if (ioc->is_driver_loading) { 3909 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 3910 mpt3sas_port_enable_complete(ioc); 3911 return 1; 3912 } else { 3913 ioc->start_scan_failed = ioc_status; 3914 ioc->start_scan = 0; 3915 return 1; 3916 } 3917 } 3918 complete(&ioc->port_enable_cmds.done); 3919 return 1; 3920} 3921 3922/** 3923 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 3924 * @ioc: per adapter object 3925 * @sleep_flag: CAN_SLEEP or NO_SLEEP 3926 * 3927 * Returns 0 for success, non-zero for failure. 3928 */ 3929static int 3930_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 3931{ 3932 Mpi2PortEnableRequest_t *mpi_request; 3933 Mpi2PortEnableReply_t *mpi_reply; 3934 unsigned long timeleft; 3935 int r = 0; 3936 u16 smid; 3937 u16 ioc_status; 3938 3939 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 3940 3941 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 3942 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 3943 ioc->name, __func__); 3944 return -EAGAIN; 3945 } 3946 3947 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 3948 if (!smid) { 3949 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 3950 ioc->name, __func__); 3951 return -EAGAIN; 3952 } 3953 3954 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 3955 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 3956 ioc->port_enable_cmds.smid = smid; 3957 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 3958 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 3959 3960 init_completion(&ioc->port_enable_cmds.done); 3961 mpt3sas_base_put_smid_default(ioc, smid); 3962 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done, 3963 300*HZ); 3964 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 3965 pr_err(MPT3SAS_FMT "%s: timeout\n", 3966 ioc->name, __func__); 3967 _debug_dump_mf(mpi_request, 3968 sizeof(Mpi2PortEnableRequest_t)/4); 3969 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 3970 r = -EFAULT; 3971 else 3972 r = -ETIME; 3973 goto out; 3974 } 3975 3976 mpi_reply = ioc->port_enable_cmds.reply; 3977 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 3978 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 3979 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", 3980 ioc->name, __func__, ioc_status); 3981 r = -EFAULT; 3982 goto out; 3983 } 3984 3985 out: 3986 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 3987 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? 3988 "SUCCESS" : "FAILED")); 3989 return r; 3990} 3991 3992/** 3993 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 3994 * @ioc: per adapter object 3995 * 3996 * Returns 0 for success, non-zero for failure. 3997 */ 3998int 3999mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 4000{ 4001 Mpi2PortEnableRequest_t *mpi_request; 4002 u16 smid; 4003 4004 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 4005 4006 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4007 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4008 ioc->name, __func__); 4009 return -EAGAIN; 4010 } 4011 4012 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 4013 if (!smid) { 4014 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4015 ioc->name, __func__); 4016 return -EAGAIN; 4017 } 4018 4019 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 4020 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4021 ioc->port_enable_cmds.smid = smid; 4022 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 4023 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 4024 4025 mpt3sas_base_put_smid_default(ioc, smid); 4026 return 0; 4027} 4028 4029/** 4030 * _base_determine_wait_on_discovery - desposition 4031 * @ioc: per adapter object 4032 * 4033 * Decide whether to wait on discovery to complete. Used to either 4034 * locate boot device, or report volumes ahead of physical devices. 4035 * 4036 * Returns 1 for wait, 0 for don't wait 4037 */ 4038static int 4039_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 4040{ 4041 /* We wait for discovery to complete if IR firmware is loaded. 4042 * The sas topology events arrive before PD events, so we need time to 4043 * turn on the bit in ioc->pd_handles to indicate PD 4044 * Also, it maybe required to report Volumes ahead of physical 4045 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 4046 */ 4047 if (ioc->ir_firmware) 4048 return 1; 4049 4050 /* if no Bios, then we don't need to wait */ 4051 if (!ioc->bios_pg3.BiosVersion) 4052 return 0; 4053 4054 /* Bios is present, then we drop down here. 4055 * 4056 * If there any entries in the Bios Page 2, then we wait 4057 * for discovery to complete. 4058 */ 4059 4060 /* Current Boot Device */ 4061 if ((ioc->bios_pg2.CurrentBootDeviceForm & 4062 MPI2_BIOSPAGE2_FORM_MASK) == 4063 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4064 /* Request Boot Device */ 4065 (ioc->bios_pg2.ReqBootDeviceForm & 4066 MPI2_BIOSPAGE2_FORM_MASK) == 4067 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 4068 /* Alternate Request Boot Device */ 4069 (ioc->bios_pg2.ReqAltBootDeviceForm & 4070 MPI2_BIOSPAGE2_FORM_MASK) == 4071 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 4072 return 0; 4073 4074 return 1; 4075} 4076 4077/** 4078 * _base_unmask_events - turn on notification for this event 4079 * @ioc: per adapter object 4080 * @event: firmware event 4081 * 4082 * The mask is stored in ioc->event_masks. 4083 */ 4084static void 4085_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 4086{ 4087 u32 desired_event; 4088 4089 if (event >= 128) 4090 return; 4091 4092 desired_event = (1 << (event % 32)); 4093 4094 if (event < 32) 4095 ioc->event_masks[0] &= ~desired_event; 4096 else if (event < 64) 4097 ioc->event_masks[1] &= ~desired_event; 4098 else if (event < 96) 4099 ioc->event_masks[2] &= ~desired_event; 4100 else if (event < 128) 4101 ioc->event_masks[3] &= ~desired_event; 4102} 4103 4104/** 4105 * _base_event_notification - send event notification 4106 * @ioc: per adapter object 4107 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4108 * 4109 * Returns 0 for success, non-zero for failure. 4110 */ 4111static int 4112_base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4113{ 4114 Mpi2EventNotificationRequest_t *mpi_request; 4115 unsigned long timeleft; 4116 u16 smid; 4117 int r = 0; 4118 int i; 4119 4120 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4121 __func__)); 4122 4123 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4124 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 4125 ioc->name, __func__); 4126 return -EAGAIN; 4127 } 4128 4129 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 4130 if (!smid) { 4131 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 4132 ioc->name, __func__); 4133 return -EAGAIN; 4134 } 4135 ioc->base_cmds.status = MPT3_CMD_PENDING; 4136 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 4137 ioc->base_cmds.smid = smid; 4138 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 4139 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 4140 mpi_request->VF_ID = 0; /* TODO */ 4141 mpi_request->VP_ID = 0; 4142 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4143 mpi_request->EventMasks[i] = 4144 cpu_to_le32(ioc->event_masks[i]); 4145 init_completion(&ioc->base_cmds.done); 4146 mpt3sas_base_put_smid_default(ioc, smid); 4147 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 4148 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 4149 pr_err(MPT3SAS_FMT "%s: timeout\n", 4150 ioc->name, __func__); 4151 _debug_dump_mf(mpi_request, 4152 sizeof(Mpi2EventNotificationRequest_t)/4); 4153 if (ioc->base_cmds.status & MPT3_CMD_RESET) 4154 r = -EFAULT; 4155 else 4156 r = -ETIME; 4157 } else 4158 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", 4159 ioc->name, __func__)); 4160 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4161 return r; 4162} 4163 4164/** 4165 * mpt3sas_base_validate_event_type - validating event types 4166 * @ioc: per adapter object 4167 * @event: firmware event 4168 * 4169 * This will turn on firmware event notification when application 4170 * ask for that event. We don't mask events that are already enabled. 4171 */ 4172void 4173mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 4174{ 4175 int i, j; 4176 u32 event_mask, desired_event; 4177 u8 send_update_to_fw; 4178 4179 for (i = 0, send_update_to_fw = 0; i < 4180 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 4181 event_mask = ~event_type[i]; 4182 desired_event = 1; 4183 for (j = 0; j < 32; j++) { 4184 if (!(event_mask & desired_event) && 4185 (ioc->event_masks[i] & desired_event)) { 4186 ioc->event_masks[i] &= ~desired_event; 4187 send_update_to_fw = 1; 4188 } 4189 desired_event = (desired_event << 1); 4190 } 4191 } 4192 4193 if (!send_update_to_fw) 4194 return; 4195 4196 mutex_lock(&ioc->base_cmds.mutex); 4197 _base_event_notification(ioc, CAN_SLEEP); 4198 mutex_unlock(&ioc->base_cmds.mutex); 4199} 4200 4201/** 4202 * _base_diag_reset - the "big hammer" start of day reset 4203 * @ioc: per adapter object 4204 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4205 * 4206 * Returns 0 for success, non-zero for failure. 4207 */ 4208static int 4209_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4210{ 4211 u32 host_diagnostic; 4212 u32 ioc_state; 4213 u32 count; 4214 u32 hcb_size; 4215 4216 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); 4217 4218 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", 4219 ioc->name)); 4220 4221 count = 0; 4222 do { 4223 /* Write magic sequence to WriteSequence register 4224 * Loop until in diagnostic mode 4225 */ 4226 drsprintk(ioc, pr_info(MPT3SAS_FMT 4227 "write magic sequence\n", ioc->name)); 4228 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 4229 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 4230 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 4231 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 4232 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 4233 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 4234 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 4235 4236 /* wait 100 msec */ 4237 if (sleep_flag == CAN_SLEEP) 4238 msleep(100); 4239 else 4240 mdelay(100); 4241 4242 if (count++ > 20) 4243 goto out; 4244 4245 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4246 drsprintk(ioc, pr_info(MPT3SAS_FMT 4247 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 4248 ioc->name, count, host_diagnostic)); 4249 4250 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 4251 4252 hcb_size = readl(&ioc->chip->HCBSize); 4253 4254 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", 4255 ioc->name)); 4256 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 4257 &ioc->chip->HostDiagnostic); 4258 4259 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 4260 if (sleep_flag == CAN_SLEEP) 4261 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 4262 else 4263 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 4264 4265 /* Approximately 300 second max wait */ 4266 for (count = 0; count < (300000000 / 4267 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 4268 4269 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 4270 4271 if (host_diagnostic == 0xFFFFFFFF) 4272 goto out; 4273 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 4274 break; 4275 4276 /* Wait to pass the second read delay window */ 4277 if (sleep_flag == CAN_SLEEP) 4278 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC 4279 / 1000); 4280 else 4281 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC 4282 / 1000); 4283 } 4284 4285 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 4286 4287 drsprintk(ioc, pr_info(MPT3SAS_FMT 4288 "restart the adapter assuming the HCB Address points to good F/W\n", 4289 ioc->name)); 4290 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 4291 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 4292 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 4293 4294 drsprintk(ioc, pr_info(MPT3SAS_FMT 4295 "re-enable the HCDW\n", ioc->name)); 4296 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 4297 &ioc->chip->HCBSize); 4298 } 4299 4300 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", 4301 ioc->name)); 4302 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 4303 &ioc->chip->HostDiagnostic); 4304 4305 drsprintk(ioc, pr_info(MPT3SAS_FMT 4306 "disable writes to the diagnostic register\n", ioc->name)); 4307 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 4308 4309 drsprintk(ioc, pr_info(MPT3SAS_FMT 4310 "Wait for FW to go to the READY state\n", ioc->name)); 4311 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20, 4312 sleep_flag); 4313 if (ioc_state) { 4314 pr_err(MPT3SAS_FMT 4315 "%s: failed going to ready state (ioc_state=0x%x)\n", 4316 ioc->name, __func__, ioc_state); 4317 goto out; 4318 } 4319 4320 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); 4321 return 0; 4322 4323 out: 4324 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); 4325 return -EFAULT; 4326} 4327 4328/** 4329 * _base_make_ioc_ready - put controller in READY state 4330 * @ioc: per adapter object 4331 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4332 * @type: FORCE_BIG_HAMMER or SOFT_RESET 4333 * 4334 * Returns 0 for success, non-zero for failure. 4335 */ 4336static int 4337_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag, 4338 enum reset_type type) 4339{ 4340 u32 ioc_state; 4341 int rc; 4342 int count; 4343 4344 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4345 __func__)); 4346 4347 if (ioc->pci_error_recovery) 4348 return 0; 4349 4350 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4351 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 4352 ioc->name, __func__, ioc_state)); 4353 4354 /* if in RESET state, it should move to READY state shortly */ 4355 count = 0; 4356 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 4357 while ((ioc_state & MPI2_IOC_STATE_MASK) != 4358 MPI2_IOC_STATE_READY) { 4359 if (count++ == 10) { 4360 pr_err(MPT3SAS_FMT 4361 "%s: failed going to ready state (ioc_state=0x%x)\n", 4362 ioc->name, __func__, ioc_state); 4363 return -EFAULT; 4364 } 4365 if (sleep_flag == CAN_SLEEP) 4366 ssleep(1); 4367 else 4368 mdelay(1000); 4369 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4370 } 4371 } 4372 4373 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 4374 return 0; 4375 4376 if (ioc_state & MPI2_DOORBELL_USED) { 4377 dhsprintk(ioc, pr_info(MPT3SAS_FMT 4378 "unexpected doorbell active!\n", 4379 ioc->name)); 4380 goto issue_diag_reset; 4381 } 4382 4383 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 4384 mpt3sas_base_fault_info(ioc, ioc_state & 4385 MPI2_DOORBELL_DATA_MASK); 4386 goto issue_diag_reset; 4387 } 4388 4389 if (type == FORCE_BIG_HAMMER) 4390 goto issue_diag_reset; 4391 4392 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 4393 if (!(_base_send_ioc_reset(ioc, 4394 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) { 4395 return 0; 4396 } 4397 4398 issue_diag_reset: 4399 rc = _base_diag_reset(ioc, CAN_SLEEP); 4400 return rc; 4401} 4402 4403/** 4404 * _base_make_ioc_operational - put controller in OPERATIONAL state 4405 * @ioc: per adapter object 4406 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4407 * 4408 * Returns 0 for success, non-zero for failure. 4409 */ 4410static int 4411_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4412{ 4413 int r, i; 4414 unsigned long flags; 4415 u32 reply_address; 4416 u16 smid; 4417 struct _tr_list *delayed_tr, *delayed_tr_next; 4418 struct adapter_reply_queue *reply_q; 4419 long reply_post_free; 4420 u32 reply_post_free_sz, index = 0; 4421 4422 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4423 __func__)); 4424 4425 /* clean the delayed target reset list */ 4426 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 4427 &ioc->delayed_tr_list, list) { 4428 list_del(&delayed_tr->list); 4429 kfree(delayed_tr); 4430 } 4431 4432 4433 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 4434 &ioc->delayed_tr_volume_list, list) { 4435 list_del(&delayed_tr->list); 4436 kfree(delayed_tr); 4437 } 4438 4439 /* initialize the scsi lookup free list */ 4440 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 4441 INIT_LIST_HEAD(&ioc->free_list); 4442 smid = 1; 4443 for (i = 0; i < ioc->scsiio_depth; i++, smid++) { 4444 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list); 4445 ioc->scsi_lookup[i].cb_idx = 0xFF; 4446 ioc->scsi_lookup[i].smid = smid; 4447 ioc->scsi_lookup[i].scmd = NULL; 4448 list_add_tail(&ioc->scsi_lookup[i].tracker_list, 4449 &ioc->free_list); 4450 } 4451 4452 /* hi-priority queue */ 4453 INIT_LIST_HEAD(&ioc->hpr_free_list); 4454 smid = ioc->hi_priority_smid; 4455 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 4456 ioc->hpr_lookup[i].cb_idx = 0xFF; 4457 ioc->hpr_lookup[i].smid = smid; 4458 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 4459 &ioc->hpr_free_list); 4460 } 4461 4462 /* internal queue */ 4463 INIT_LIST_HEAD(&ioc->internal_free_list); 4464 smid = ioc->internal_smid; 4465 for (i = 0; i < ioc->internal_depth; i++, smid++) { 4466 ioc->internal_lookup[i].cb_idx = 0xFF; 4467 ioc->internal_lookup[i].smid = smid; 4468 list_add_tail(&ioc->internal_lookup[i].tracker_list, 4469 &ioc->internal_free_list); 4470 } 4471 4472 /* chain pool */ 4473 INIT_LIST_HEAD(&ioc->free_chain_list); 4474 for (i = 0; i < ioc->chain_depth; i++) 4475 list_add_tail(&ioc->chain_lookup[i].tracker_list, 4476 &ioc->free_chain_list); 4477 4478 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 4479 4480 /* initialize Reply Free Queue */ 4481 for (i = 0, reply_address = (u32)ioc->reply_dma ; 4482 i < ioc->reply_free_queue_depth ; i++, reply_address += 4483 ioc->reply_sz) 4484 ioc->reply_free[i] = cpu_to_le32(reply_address); 4485 4486 /* initialize reply queues */ 4487 if (ioc->is_driver_loading) 4488 _base_assign_reply_queues(ioc); 4489 4490 /* initialize Reply Post Free Queue */ 4491 reply_post_free_sz = ioc->reply_post_queue_depth * 4492 sizeof(Mpi2DefaultReplyDescriptor_t); 4493 reply_post_free = (long)ioc->reply_post[index].reply_post_free; 4494 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 4495 reply_q->reply_post_host_index = 0; 4496 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *) 4497 reply_post_free; 4498 for (i = 0; i < ioc->reply_post_queue_depth; i++) 4499 reply_q->reply_post_free[i].Words = 4500 cpu_to_le64(ULLONG_MAX); 4501 if (!_base_is_controller_msix_enabled(ioc)) 4502 goto skip_init_reply_post_free_queue; 4503 /* 4504 * If RDPQ is enabled, switch to the next allocation. 4505 * Otherwise advance within the contiguous region. 4506 */ 4507 if (ioc->rdpq_array_enable) 4508 reply_post_free = (long) 4509 ioc->reply_post[++index].reply_post_free; 4510 else 4511 reply_post_free += reply_post_free_sz; 4512 } 4513 skip_init_reply_post_free_queue: 4514 4515 r = _base_send_ioc_init(ioc, sleep_flag); 4516 if (r) 4517 return r; 4518 4519 /* initialize reply free host index */ 4520 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 4521 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 4522 4523 /* initialize reply post host index */ 4524 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 4525 writel(reply_q->msix_index << MPI2_RPHI_MSIX_INDEX_SHIFT, 4526 &ioc->chip->ReplyPostHostIndex); 4527 if (!_base_is_controller_msix_enabled(ioc)) 4528 goto skip_init_reply_post_host_index; 4529 } 4530 4531 skip_init_reply_post_host_index: 4532 4533 _base_unmask_interrupts(ioc); 4534 r = _base_event_notification(ioc, sleep_flag); 4535 if (r) 4536 return r; 4537 4538 if (sleep_flag == CAN_SLEEP) 4539 _base_static_config_pages(ioc); 4540 4541 4542 if (ioc->is_driver_loading) { 4543 ioc->wait_for_discovery_to_complete = 4544 _base_determine_wait_on_discovery(ioc); 4545 4546 return r; /* scan_start and scan_finished support */ 4547 } 4548 4549 r = _base_send_port_enable(ioc, sleep_flag); 4550 if (r) 4551 return r; 4552 4553 return r; 4554} 4555 4556/** 4557 * mpt3sas_base_free_resources - free resources controller resources 4558 * @ioc: per adapter object 4559 * 4560 * Return nothing. 4561 */ 4562void 4563mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 4564{ 4565 struct pci_dev *pdev = ioc->pdev; 4566 4567 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4568 __func__)); 4569 4570 if (ioc->chip_phys && ioc->chip) { 4571 _base_mask_interrupts(ioc); 4572 ioc->shost_recovery = 1; 4573 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET); 4574 ioc->shost_recovery = 0; 4575 } 4576 4577 _base_free_irq(ioc); 4578 _base_disable_msix(ioc); 4579 4580 if (ioc->chip_phys && ioc->chip) 4581 iounmap(ioc->chip); 4582 ioc->chip_phys = 0; 4583 4584 if (pci_is_enabled(pdev)) { 4585 pci_release_selected_regions(ioc->pdev, ioc->bars); 4586 pci_disable_pcie_error_reporting(pdev); 4587 pci_disable_device(pdev); 4588 } 4589 return; 4590} 4591 4592/** 4593 * mpt3sas_base_attach - attach controller instance 4594 * @ioc: per adapter object 4595 * 4596 * Returns 0 for success, non-zero for failure. 4597 */ 4598int 4599mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 4600{ 4601 int r, i; 4602 int cpu_id, last_cpu_id = 0; 4603 4604 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4605 __func__)); 4606 4607 /* setup cpu_msix_table */ 4608 ioc->cpu_count = num_online_cpus(); 4609 for_each_online_cpu(cpu_id) 4610 last_cpu_id = cpu_id; 4611 ioc->cpu_msix_table_sz = last_cpu_id + 1; 4612 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 4613 ioc->reply_queue_count = 1; 4614 if (!ioc->cpu_msix_table) { 4615 dfailprintk(ioc, pr_info(MPT3SAS_FMT 4616 "allocation for cpu_msix_table failed!!!\n", 4617 ioc->name)); 4618 r = -ENOMEM; 4619 goto out_free_resources; 4620 } 4621 4622 ioc->rdpq_array_enable_assigned = 0; 4623 ioc->dma_mask = 0; 4624 r = mpt3sas_base_map_resources(ioc); 4625 if (r) 4626 goto out_free_resources; 4627 4628 4629 pci_set_drvdata(ioc->pdev, ioc->shost); 4630 r = _base_get_ioc_facts(ioc, CAN_SLEEP); 4631 if (r) 4632 goto out_free_resources; 4633 4634 /* 4635 * In SAS3.0, 4636 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 4637 * Target Status - all require the IEEE formated scatter gather 4638 * elements. 4639 */ 4640 4641 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 4642 ioc->build_sg = &_base_build_sg_ieee; 4643 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 4644 ioc->mpi25 = 1; 4645 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 4646 4647 /* 4648 * These function pointers for other requests that don't 4649 * the require IEEE scatter gather elements. 4650 * 4651 * For example Configuration Pages and SAS IOUNIT Control don't. 4652 */ 4653 ioc->build_sg_mpi = &_base_build_sg; 4654 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 4655 4656 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET); 4657 if (r) 4658 goto out_free_resources; 4659 4660 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 4661 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 4662 if (!ioc->pfacts) { 4663 r = -ENOMEM; 4664 goto out_free_resources; 4665 } 4666 4667 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 4668 r = _base_get_port_facts(ioc, i, CAN_SLEEP); 4669 if (r) 4670 goto out_free_resources; 4671 } 4672 4673 r = _base_allocate_memory_pools(ioc, CAN_SLEEP); 4674 if (r) 4675 goto out_free_resources; 4676 4677 init_waitqueue_head(&ioc->reset_wq); 4678 4679 /* allocate memory pd handle bitmask list */ 4680 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 4681 if (ioc->facts.MaxDevHandle % 8) 4682 ioc->pd_handles_sz++; 4683 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 4684 GFP_KERNEL); 4685 if (!ioc->pd_handles) { 4686 r = -ENOMEM; 4687 goto out_free_resources; 4688 } 4689 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 4690 GFP_KERNEL); 4691 if (!ioc->blocking_handles) { 4692 r = -ENOMEM; 4693 goto out_free_resources; 4694 } 4695 4696 ioc->fwfault_debug = mpt3sas_fwfault_debug; 4697 4698 /* base internal command bits */ 4699 mutex_init(&ioc->base_cmds.mutex); 4700 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4701 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 4702 4703 /* port_enable command bits */ 4704 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4705 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 4706 4707 /* transport internal command bits */ 4708 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4709 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 4710 mutex_init(&ioc->transport_cmds.mutex); 4711 4712 /* scsih internal command bits */ 4713 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4714 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 4715 mutex_init(&ioc->scsih_cmds.mutex); 4716 4717 /* task management internal command bits */ 4718 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4719 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 4720 mutex_init(&ioc->tm_cmds.mutex); 4721 4722 /* config page internal command bits */ 4723 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4724 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 4725 mutex_init(&ioc->config_cmds.mutex); 4726 4727 /* ctl module internal command bits */ 4728 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 4729 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 4730 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 4731 mutex_init(&ioc->ctl_cmds.mutex); 4732 4733 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply || 4734 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply || 4735 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply || 4736 !ioc->ctl_cmds.sense) { 4737 r = -ENOMEM; 4738 goto out_free_resources; 4739 } 4740 4741 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 4742 ioc->event_masks[i] = -1; 4743 4744 /* here we enable the events we care about */ 4745 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 4746 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 4747 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 4748 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 4749 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 4750 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 4751 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 4752 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 4753 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 4754 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 4755 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 4756 4757 r = _base_make_ioc_operational(ioc, CAN_SLEEP); 4758 if (r) 4759 goto out_free_resources; 4760 4761 return 0; 4762 4763 out_free_resources: 4764 4765 ioc->remove_host = 1; 4766 4767 mpt3sas_base_free_resources(ioc); 4768 _base_release_memory_pools(ioc); 4769 pci_set_drvdata(ioc->pdev, NULL); 4770 kfree(ioc->cpu_msix_table); 4771 kfree(ioc->pd_handles); 4772 kfree(ioc->blocking_handles); 4773 kfree(ioc->tm_cmds.reply); 4774 kfree(ioc->transport_cmds.reply); 4775 kfree(ioc->scsih_cmds.reply); 4776 kfree(ioc->config_cmds.reply); 4777 kfree(ioc->base_cmds.reply); 4778 kfree(ioc->port_enable_cmds.reply); 4779 kfree(ioc->ctl_cmds.reply); 4780 kfree(ioc->ctl_cmds.sense); 4781 kfree(ioc->pfacts); 4782 ioc->ctl_cmds.reply = NULL; 4783 ioc->base_cmds.reply = NULL; 4784 ioc->tm_cmds.reply = NULL; 4785 ioc->scsih_cmds.reply = NULL; 4786 ioc->transport_cmds.reply = NULL; 4787 ioc->config_cmds.reply = NULL; 4788 ioc->pfacts = NULL; 4789 return r; 4790} 4791 4792 4793/** 4794 * mpt3sas_base_detach - remove controller instance 4795 * @ioc: per adapter object 4796 * 4797 * Return nothing. 4798 */ 4799void 4800mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 4801{ 4802 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4803 __func__)); 4804 4805 mpt3sas_base_stop_watchdog(ioc); 4806 mpt3sas_base_free_resources(ioc); 4807 _base_release_memory_pools(ioc); 4808 pci_set_drvdata(ioc->pdev, NULL); 4809 kfree(ioc->cpu_msix_table); 4810 kfree(ioc->pd_handles); 4811 kfree(ioc->blocking_handles); 4812 kfree(ioc->pfacts); 4813 kfree(ioc->ctl_cmds.reply); 4814 kfree(ioc->ctl_cmds.sense); 4815 kfree(ioc->base_cmds.reply); 4816 kfree(ioc->port_enable_cmds.reply); 4817 kfree(ioc->tm_cmds.reply); 4818 kfree(ioc->transport_cmds.reply); 4819 kfree(ioc->scsih_cmds.reply); 4820 kfree(ioc->config_cmds.reply); 4821} 4822 4823/** 4824 * _base_reset_handler - reset callback handler (for base) 4825 * @ioc: per adapter object 4826 * @reset_phase: phase 4827 * 4828 * The handler for doing any required cleanup or initialization. 4829 * 4830 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET, 4831 * MPT3_IOC_DONE_RESET 4832 * 4833 * Return nothing. 4834 */ 4835static void 4836_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase) 4837{ 4838 mpt3sas_scsih_reset_handler(ioc, reset_phase); 4839 mpt3sas_ctl_reset_handler(ioc, reset_phase); 4840 switch (reset_phase) { 4841 case MPT3_IOC_PRE_RESET: 4842 dtmprintk(ioc, pr_info(MPT3SAS_FMT 4843 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); 4844 break; 4845 case MPT3_IOC_AFTER_RESET: 4846 dtmprintk(ioc, pr_info(MPT3SAS_FMT 4847 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); 4848 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 4849 ioc->transport_cmds.status |= MPT3_CMD_RESET; 4850 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 4851 complete(&ioc->transport_cmds.done); 4852 } 4853 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 4854 ioc->base_cmds.status |= MPT3_CMD_RESET; 4855 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 4856 complete(&ioc->base_cmds.done); 4857 } 4858 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 4859 ioc->port_enable_failed = 1; 4860 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 4861 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 4862 if (ioc->is_driver_loading) { 4863 ioc->start_scan_failed = 4864 MPI2_IOCSTATUS_INTERNAL_ERROR; 4865 ioc->start_scan = 0; 4866 ioc->port_enable_cmds.status = 4867 MPT3_CMD_NOT_USED; 4868 } else 4869 complete(&ioc->port_enable_cmds.done); 4870 } 4871 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 4872 ioc->config_cmds.status |= MPT3_CMD_RESET; 4873 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 4874 ioc->config_cmds.smid = USHRT_MAX; 4875 complete(&ioc->config_cmds.done); 4876 } 4877 break; 4878 case MPT3_IOC_DONE_RESET: 4879 dtmprintk(ioc, pr_info(MPT3SAS_FMT 4880 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); 4881 break; 4882 } 4883} 4884 4885/** 4886 * _wait_for_commands_to_complete - reset controller 4887 * @ioc: Pointer to MPT_ADAPTER structure 4888 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4889 * 4890 * This function waiting(3s) for all pending commands to complete 4891 * prior to putting controller in reset. 4892 */ 4893static void 4894_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag) 4895{ 4896 u32 ioc_state; 4897 unsigned long flags; 4898 u16 i; 4899 4900 ioc->pending_io_count = 0; 4901 if (sleep_flag != CAN_SLEEP) 4902 return; 4903 4904 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4905 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 4906 return; 4907 4908 /* pending command count */ 4909 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 4910 for (i = 0; i < ioc->scsiio_depth; i++) 4911 if (ioc->scsi_lookup[i].cb_idx != 0xFF) 4912 ioc->pending_io_count++; 4913 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 4914 4915 if (!ioc->pending_io_count) 4916 return; 4917 4918 /* wait for pending commands to complete */ 4919 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 4920} 4921 4922/** 4923 * mpt3sas_base_hard_reset_handler - reset controller 4924 * @ioc: Pointer to MPT_ADAPTER structure 4925 * @sleep_flag: CAN_SLEEP or NO_SLEEP 4926 * @type: FORCE_BIG_HAMMER or SOFT_RESET 4927 * 4928 * Returns 0 for success, non-zero for failure. 4929 */ 4930int 4931mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag, 4932 enum reset_type type) 4933{ 4934 int r; 4935 unsigned long flags; 4936 u32 ioc_state; 4937 u8 is_fault = 0, is_trigger = 0; 4938 4939 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, 4940 __func__)); 4941 4942 if (ioc->pci_error_recovery) { 4943 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", 4944 ioc->name, __func__); 4945 r = 0; 4946 goto out_unlocked; 4947 } 4948 4949 if (mpt3sas_fwfault_debug) 4950 mpt3sas_halt_firmware(ioc); 4951 4952 /* TODO - What we really should be doing is pulling 4953 * out all the code associated with NO_SLEEP; its never used. 4954 * That is legacy code from mpt fusion driver, ported over. 4955 * I will leave this BUG_ON here for now till its been resolved. 4956 */ 4957 BUG_ON(sleep_flag == NO_SLEEP); 4958 4959 /* wait for an active reset in progress to complete */ 4960 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) { 4961 do { 4962 ssleep(1); 4963 } while (ioc->shost_recovery == 1); 4964 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 4965 __func__)); 4966 return ioc->ioc_reset_in_progress_status; 4967 } 4968 4969 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 4970 ioc->shost_recovery = 1; 4971 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 4972 4973 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 4974 MPT3_DIAG_BUFFER_IS_REGISTERED) && 4975 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 4976 MPT3_DIAG_BUFFER_IS_RELEASED))) { 4977 is_trigger = 1; 4978 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 4979 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 4980 is_fault = 1; 4981 } 4982 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET); 4983 _wait_for_commands_to_complete(ioc, sleep_flag); 4984 _base_mask_interrupts(ioc); 4985 r = _base_make_ioc_ready(ioc, sleep_flag, type); 4986 if (r) 4987 goto out; 4988 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET); 4989 4990 /* If this hard reset is called while port enable is active, then 4991 * there is no reason to call make_ioc_operational 4992 */ 4993 if (ioc->is_driver_loading && ioc->port_enable_failed) { 4994 ioc->remove_host = 1; 4995 r = -EFAULT; 4996 goto out; 4997 } 4998 r = _base_get_ioc_facts(ioc, CAN_SLEEP); 4999 if (r) 5000 goto out; 5001 5002 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 5003 panic("%s: Issue occurred with flashing controller firmware." 5004 "Please reboot the system and ensure that the correct" 5005 " firmware version is running\n", ioc->name); 5006 5007 r = _base_make_ioc_operational(ioc, sleep_flag); 5008 if (!r) 5009 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET); 5010 5011 out: 5012 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", 5013 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); 5014 5015 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 5016 ioc->ioc_reset_in_progress_status = r; 5017 ioc->shost_recovery = 0; 5018 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 5019 ioc->ioc_reset_count++; 5020 mutex_unlock(&ioc->reset_in_progress_mutex); 5021 5022 out_unlocked: 5023 if ((r == 0) && is_trigger) { 5024 if (is_fault) 5025 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 5026 else 5027 mpt3sas_trigger_master(ioc, 5028 MASTER_TRIGGER_ADAPTER_RESET); 5029 } 5030 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 5031 __func__)); 5032 return r; 5033} 5034