1/****************************************************************************** 2** Device driver for the PCI-SCSI NCR538XX controller family. 3** 4** Copyright (C) 1994 Wolfgang Stanglmeier 5** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr> 6** 7** This program is free software; you can redistribute it and/or modify 8** it under the terms of the GNU General Public License as published by 9** the Free Software Foundation; either version 2 of the License, or 10** (at your option) any later version. 11** 12** This program is distributed in the hope that it will be useful, 13** but WITHOUT ANY WARRANTY; without even the implied warranty of 14** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15** GNU General Public License for more details. 16** 17** You should have received a copy of the GNU General Public License 18** along with this program; if not, write to the Free Software 19** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20** 21**----------------------------------------------------------------------------- 22** 23** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver 24** and is currently maintained by 25** 26** Gerard Roudier <groudier@free.fr> 27** 28** Being given that this driver originates from the FreeBSD version, and 29** in order to keep synergy on both, any suggested enhancements and corrections 30** received on Linux are automatically a potential candidate for the FreeBSD 31** version. 32** 33** The original driver has been written for 386bsd and FreeBSD by 34** Wolfgang Stanglmeier <wolf@cologne.de> 35** Stefan Esser <se@mi.Uni-Koeln.de> 36** 37** And has been ported to NetBSD by 38** Charles M. Hannum <mycroft@gnu.ai.mit.edu> 39** 40** NVRAM detection and reading. 41** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 42** 43** Added support for MIPS big endian systems. 44** Carsten Langgaard, carstenl@mips.com 45** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 46** 47** Added support for HP PARISC big endian systems. 48** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 49** 50******************************************************************************* 51*/ 52 53#ifndef NCR53C8XX_H 54#define NCR53C8XX_H 55 56#include <scsi/scsi_host.h> 57 58 59/* 60** If you want a driver as small as possible, donnot define the 61** following options. 62*/ 63#define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT 64#define SCSI_NCR_DEBUG_INFO_SUPPORT 65 66/* 67** To disable integrity checking, do not define the 68** following option. 69*/ 70#ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK 71# define SCSI_NCR_ENABLE_INTEGRITY_CHECK 72#endif 73 74/* --------------------------------------------------------------------- 75** Take into account kernel configured parameters. 76** Most of these options can be overridden at startup by a command line. 77** --------------------------------------------------------------------- 78*/ 79 80/* 81 * For Ultra2 and Ultra3 SCSI support option, use special features. 82 * 83 * Value (default) means: 84 * bit 0 : all features enabled, except: 85 * bit 1 : PCI Write And Invalidate. 86 * bit 2 : Data Phase Mismatch handling from SCRIPTS. 87 * 88 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be 89 * enabled by the driver. 90 */ 91#define SCSI_NCR_SETUP_SPECIAL_FEATURES (3) 92 93#define SCSI_NCR_MAX_SYNC (80) 94 95/* 96 * Allow tags from 2 to 256, default 8 97 */ 98#ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS 99#if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2 100#define SCSI_NCR_MAX_TAGS (2) 101#elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256 102#define SCSI_NCR_MAX_TAGS (256) 103#else 104#define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS 105#endif 106#else 107#define SCSI_NCR_MAX_TAGS (8) 108#endif 109 110/* 111 * Allow tagged command queuing support if configured with default number 112 * of tags set to max (see above). 113 */ 114#ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS 115#define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS 116#elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE 117#define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS 118#else 119#define SCSI_NCR_SETUP_DEFAULT_TAGS (0) 120#endif 121 122/* 123 * Immediate arbitration 124 */ 125#if defined(CONFIG_SCSI_NCR53C8XX_IARB) 126#define SCSI_NCR_IARB_SUPPORT 127#endif 128 129/* 130 * Sync transfer frequency at startup. 131 * Allow from 5Mhz to 80Mhz default 20 Mhz. 132 */ 133#ifndef CONFIG_SCSI_NCR53C8XX_SYNC 134#define CONFIG_SCSI_NCR53C8XX_SYNC (20) 135#elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC 136#undef CONFIG_SCSI_NCR53C8XX_SYNC 137#define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC 138#endif 139 140#if CONFIG_SCSI_NCR53C8XX_SYNC == 0 141#define SCSI_NCR_SETUP_DEFAULT_SYNC (255) 142#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5 143#define SCSI_NCR_SETUP_DEFAULT_SYNC (50) 144#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20 145#define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC)) 146#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33 147#define SCSI_NCR_SETUP_DEFAULT_SYNC (11) 148#elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40 149#define SCSI_NCR_SETUP_DEFAULT_SYNC (10) 150#else 151#define SCSI_NCR_SETUP_DEFAULT_SYNC (9) 152#endif 153 154/* 155 * Disallow disconnections at boot-up 156 */ 157#ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT 158#define SCSI_NCR_SETUP_DISCONNECTION (0) 159#else 160#define SCSI_NCR_SETUP_DISCONNECTION (1) 161#endif 162 163/* 164 * Force synchronous negotiation for all targets 165 */ 166#ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO 167#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1) 168#else 169#define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0) 170#endif 171 172/* 173 * Disable master parity checking (flawed hardwares need that) 174 */ 175#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK 176#define SCSI_NCR_SETUP_MASTER_PARITY (0) 177#else 178#define SCSI_NCR_SETUP_MASTER_PARITY (1) 179#endif 180 181/* 182 * Disable scsi parity checking (flawed devices may need that) 183 */ 184#ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK 185#define SCSI_NCR_SETUP_SCSI_PARITY (0) 186#else 187#define SCSI_NCR_SETUP_SCSI_PARITY (1) 188#endif 189 190/* 191 * Settle time after reset at boot-up 192 */ 193#define SCSI_NCR_SETUP_SETTLE_TIME (2) 194 195/* 196** Bridge quirks work-around option defaulted to 1. 197*/ 198#ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT 199#define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1 200#endif 201 202/* 203** Work-around common bridge misbehaviour. 204** 205** - Do not flush posted writes in the opposite 206** direction on read. 207** - May reorder DMA writes to memory. 208** 209** This option should not affect performances 210** significantly, so it is the default. 211*/ 212#if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1 213#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM 214#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES 215#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS 216 217/* 218** Same as option 1, but also deal with 219** misconfigured interrupts. 220** 221** - Edge triggered instead of level sensitive. 222** - No interrupt line connected. 223** - IRQ number misconfigured. 224** 225** If no interrupt is delivered, the driver will 226** catch the interrupt conditions 10 times per 227** second. No need to say that this option is 228** not recommended. 229*/ 230#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2 231#define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM 232#define SCSI_NCR_PCIQ_MAY_REORDER_WRITES 233#define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS 234#define SCSI_NCR_PCIQ_BROKEN_INTR 235 236/* 237** Some bridge designers decided to flush 238** everything prior to deliver the interrupt. 239** This option tries to deal with such a 240** behaviour. 241*/ 242#elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3 243#define SCSI_NCR_PCIQ_SYNC_ON_INTR 244#endif 245 246/* 247** Other parameters not configurable with "make config" 248** Avoid to change these constants, unless you know what you are doing. 249*/ 250 251#define SCSI_NCR_ALWAYS_SIMPLE_TAG 252#define SCSI_NCR_MAX_SCATTER (127) 253#define SCSI_NCR_MAX_TARGET (16) 254 255/* 256** Compute some desirable value for CAN_QUEUE 257** and CMD_PER_LUN. 258** The driver will use lower values if these 259** ones appear to be too large. 260*/ 261#define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET) 262#define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS) 263 264#define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER) 265#define SCSI_NCR_TIMER_INTERVAL (HZ) 266 267#define SCSI_NCR_MAX_LUN (16) 268 269/* 270 * IO functions definition for big/little endian CPU support. 271 * For now, the NCR is only supported in little endian addressing mode, 272 */ 273 274#ifdef __BIG_ENDIAN 275 276#define inw_l2b inw 277#define inl_l2b inl 278#define outw_b2l outw 279#define outl_b2l outl 280 281#define readb_raw readb 282#define writeb_raw writeb 283 284#if defined(SCSI_NCR_BIG_ENDIAN) 285#define readw_l2b __raw_readw 286#define readl_l2b __raw_readl 287#define writew_b2l __raw_writew 288#define writel_b2l __raw_writel 289#define readw_raw __raw_readw 290#define readl_raw __raw_readl 291#define writew_raw __raw_writew 292#define writel_raw __raw_writel 293#else /* Other big-endian */ 294#define readw_l2b readw 295#define readl_l2b readl 296#define writew_b2l writew 297#define writel_b2l writel 298#define readw_raw readw 299#define readl_raw readl 300#define writew_raw writew 301#define writel_raw writel 302#endif 303 304#else /* little endian */ 305 306#define inw_raw inw 307#define inl_raw inl 308#define outw_raw outw 309#define outl_raw outl 310 311#define readb_raw readb 312#define readw_raw readw 313#define readl_raw readl 314#define writeb_raw writeb 315#define writew_raw writew 316#define writel_raw writel 317 318#endif 319 320#if !defined(__hppa__) && !defined(__mips__) 321#ifdef SCSI_NCR_BIG_ENDIAN 322#error "The NCR in BIG ENDIAN addressing mode is not (yet) supported" 323#endif 324#endif 325 326#define MEMORY_BARRIER() mb() 327 328 329/* 330 * If the NCR uses big endian addressing mode over the 331 * PCI, actual io register addresses for byte and word 332 * accesses must be changed according to lane routing. 333 * Btw, ncr_offb() and ncr_offw() macros only apply to 334 * constants and so donnot generate bloated code. 335 */ 336 337#if defined(SCSI_NCR_BIG_ENDIAN) 338 339#define ncr_offb(o) (((o)&~3)+((~((o)&3))&3)) 340#define ncr_offw(o) (((o)&~3)+((~((o)&3))&2)) 341 342#else 343 344#define ncr_offb(o) (o) 345#define ncr_offw(o) (o) 346 347#endif 348 349/* 350 * If the CPU and the NCR use same endian-ness addressing, 351 * no byte reordering is needed for script patching. 352 * Macro cpu_to_scr() is to be used for script patching. 353 * Macro scr_to_cpu() is to be used for getting a DWORD 354 * from the script. 355 */ 356 357#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) 358 359#define cpu_to_scr(dw) cpu_to_le32(dw) 360#define scr_to_cpu(dw) le32_to_cpu(dw) 361 362#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) 363 364#define cpu_to_scr(dw) cpu_to_be32(dw) 365#define scr_to_cpu(dw) be32_to_cpu(dw) 366 367#else 368 369#define cpu_to_scr(dw) (dw) 370#define scr_to_cpu(dw) (dw) 371 372#endif 373 374/* 375 * Access to the controller chip. 376 * 377 * If the CPU and the NCR use same endian-ness addressing, 378 * no byte reordering is needed for accessing chip io 379 * registers. Functions suffixed by '_raw' are assumed 380 * to access the chip over the PCI without doing byte 381 * reordering. Functions suffixed by '_l2b' are 382 * assumed to perform little-endian to big-endian byte 383 * reordering, those suffixed by '_b2l' blah, blah, 384 * blah, ... 385 */ 386 387/* 388 * MEMORY mapped IO input / output 389 */ 390 391#define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o)) 392#define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o)) 393 394#if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN) 395 396#define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o)) 397#define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o)) 398 399#define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o)) 400#define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o)) 401 402#elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN) 403 404#define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o)) 405#define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o)) 406 407#define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o)) 408#define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o)) 409 410#else 411 412#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS 413/* Only 8 or 32 bit transfers allowed */ 414#define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1)) 415#else 416#define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o)) 417#endif 418#define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o)) 419 420#ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS 421/* Only 8 or 32 bit transfers allowed */ 422#define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0) 423#else 424#define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o)) 425#endif 426#define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o)) 427 428#endif 429 430#define INB(r) INB_OFF (offsetof(struct ncr_reg,r)) 431#define INW(r) INW_OFF (offsetof(struct ncr_reg,r)) 432#define INL(r) INL_OFF (offsetof(struct ncr_reg,r)) 433 434#define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val)) 435#define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val)) 436#define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val)) 437 438/* 439 * Set bit field ON, OFF 440 */ 441 442#define OUTONB(r, m) OUTB(r, INB(r) | (m)) 443#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m)) 444#define OUTONW(r, m) OUTW(r, INW(r) | (m)) 445#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m)) 446#define OUTONL(r, m) OUTL(r, INL(r) | (m)) 447#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m)) 448 449/* 450 * We normally want the chip to have a consistent view 451 * of driver internal data structures when we restart it. 452 * Thus these macros. 453 */ 454#define OUTL_DSP(v) \ 455 do { \ 456 MEMORY_BARRIER(); \ 457 OUTL (nc_dsp, (v)); \ 458 } while (0) 459 460#define OUTONB_STD() \ 461 do { \ 462 MEMORY_BARRIER(); \ 463 OUTONB (nc_dcntl, (STD|NOCOM)); \ 464 } while (0) 465 466 467/* 468** NCR53C8XX devices features table. 469*/ 470struct ncr_chip { 471 unsigned short revision_id; 472 unsigned char burst_max; /* log-base-2 of max burst */ 473 unsigned char offset_max; 474 unsigned char nr_divisor; 475 unsigned int features; 476#define FE_LED0 (1<<0) 477#define FE_WIDE (1<<1) /* Wide data transfers */ 478#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */ 479#define FE_DBLR (1<<4) /* Clock doubler present */ 480#define FE_QUAD (1<<5) /* Clock quadrupler present */ 481#define FE_ERL (1<<6) /* Enable read line */ 482#define FE_CLSE (1<<7) /* Cache line size enable */ 483#define FE_WRIE (1<<8) /* Write & Invalidate enable */ 484#define FE_ERMP (1<<9) /* Enable read multiple */ 485#define FE_BOF (1<<10) /* Burst opcode fetch */ 486#define FE_DFS (1<<11) /* DMA fifo size */ 487#define FE_PFEN (1<<12) /* Prefetch enable */ 488#define FE_LDSTR (1<<13) /* Load/Store supported */ 489#define FE_RAM (1<<14) /* On chip RAM present */ 490#define FE_VARCLK (1<<15) /* SCSI clock may vary */ 491#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */ 492#define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */ 493#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */ 494#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */ 495#define FE_LEDC (1<<20) /* Hardware control of LED */ 496#define FE_DIFF (1<<21) /* Support Differential SCSI */ 497#define FE_66MHZ (1<<23) /* 66MHz PCI Support */ 498#define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */ 499#define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */ 500#define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */ 501#define FE_EHP (1<<27) /* 720: Even host parity */ 502#define FE_MUX (1<<28) /* 720: Multiplexed bus */ 503#define FE_EA (1<<29) /* 720: Enable Ack */ 504 505#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 506#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80) 507#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 508}; 509 510 511/* 512** Driver setup structure. 513** 514** This structure is initialized from linux config options. 515** It can be overridden at boot-up by the boot command line. 516*/ 517#define SCSI_NCR_MAX_EXCLUDES 8 518struct ncr_driver_setup { 519 u8 master_parity; 520 u8 scsi_parity; 521 u8 disconnection; 522 u8 special_features; 523 u8 force_sync_nego; 524 u8 reverse_probe; 525 u8 pci_fix_up; 526 u8 use_nvram; 527 u8 verbose; 528 u8 default_tags; 529 u16 default_sync; 530 u16 debug; 531 u8 burst_max; 532 u8 led_pin; 533 u8 max_wide; 534 u8 settle_delay; 535 u8 diff_support; 536 u8 irqm; 537 u8 bus_check; 538 u8 optimize; 539 u8 recovery; 540 u8 host_id; 541 u16 iarb; 542 u32 excludes[SCSI_NCR_MAX_EXCLUDES]; 543 char tag_ctrl[100]; 544}; 545 546/* 547** Initial setup. 548** Can be overridden at startup by a command line. 549*/ 550#define SCSI_NCR_DRIVER_SETUP \ 551{ \ 552 SCSI_NCR_SETUP_MASTER_PARITY, \ 553 SCSI_NCR_SETUP_SCSI_PARITY, \ 554 SCSI_NCR_SETUP_DISCONNECTION, \ 555 SCSI_NCR_SETUP_SPECIAL_FEATURES, \ 556 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \ 557 0, \ 558 0, \ 559 1, \ 560 0, \ 561 SCSI_NCR_SETUP_DEFAULT_TAGS, \ 562 SCSI_NCR_SETUP_DEFAULT_SYNC, \ 563 0x00, \ 564 7, \ 565 0, \ 566 1, \ 567 SCSI_NCR_SETUP_SETTLE_TIME, \ 568 0, \ 569 0, \ 570 1, \ 571 0, \ 572 0, \ 573 255, \ 574 0x00 \ 575} 576 577/* 578** Boot fail safe setup. 579** Override initial setup from boot command line: 580** ncr53c8xx=safe:y 581*/ 582#define SCSI_NCR_DRIVER_SAFE_SETUP \ 583{ \ 584 0, \ 585 1, \ 586 0, \ 587 0, \ 588 0, \ 589 0, \ 590 0, \ 591 1, \ 592 2, \ 593 0, \ 594 255, \ 595 0x00, \ 596 255, \ 597 0, \ 598 0, \ 599 10, \ 600 1, \ 601 1, \ 602 1, \ 603 0, \ 604 0, \ 605 255 \ 606} 607 608/**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/ 609 610/*----------------------------------------------------------------- 611** 612** The ncr 53c810 register structure. 613** 614**----------------------------------------------------------------- 615*/ 616 617struct ncr_reg { 618/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */ 619 620/*01*/ u8 nc_scntl1; /* no reset */ 621 #define ISCON 0x10 /* connected to scsi */ 622 #define CRST 0x08 /* force reset */ 623 #define IARB 0x02 /* immediate arbitration */ 624 625/*02*/ u8 nc_scntl2; /* no disconnect expected */ 626 #define SDU 0x80 /* cmd: disconnect will raise error */ 627 #define CHM 0x40 /* sta: chained mode */ 628 #define WSS 0x08 /* sta: wide scsi send [W]*/ 629 #define WSR 0x01 /* sta: wide scsi received [W]*/ 630 631/*03*/ u8 nc_scntl3; /* cnf system clock dependent */ 632 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 633 #define ULTRA 0x80 /* cmd: ULTRA enable */ 634 /* bits 0-2, 7 rsvd for C1010 */ 635 636/*04*/ u8 nc_scid; /* cnf host adapter scsi address */ 637 #define RRE 0x40 /* r/w:e enable response to resel. */ 638 #define SRE 0x20 /* r/w:e enable response to select */ 639 640/*05*/ u8 nc_sxfer; /* ### Sync speed and count */ 641 /* bits 6-7 rsvd for C1010 */ 642 643/*06*/ u8 nc_sdid; /* ### Destination-ID */ 644 645/*07*/ u8 nc_gpreg; /* ??? IO-Pins */ 646 647/*08*/ u8 nc_sfbr; /* ### First byte in phase */ 648 649/*09*/ u8 nc_socl; 650 #define CREQ 0x80 /* r/w: SCSI-REQ */ 651 #define CACK 0x40 /* r/w: SCSI-ACK */ 652 #define CBSY 0x20 /* r/w: SCSI-BSY */ 653 #define CSEL 0x10 /* r/w: SCSI-SEL */ 654 #define CATN 0x08 /* r/w: SCSI-ATN */ 655 #define CMSG 0x04 /* r/w: SCSI-MSG */ 656 #define CC_D 0x02 /* r/w: SCSI-C_D */ 657 #define CI_O 0x01 /* r/w: SCSI-I_O */ 658 659/*0a*/ u8 nc_ssid; 660 661/*0b*/ u8 nc_sbcl; 662 663/*0c*/ u8 nc_dstat; 664 #define DFE 0x80 /* sta: dma fifo empty */ 665 #define MDPE 0x40 /* int: master data parity error */ 666 #define BF 0x20 /* int: script: bus fault */ 667 #define ABRT 0x10 /* int: script: command aborted */ 668 #define SSI 0x08 /* int: script: single step */ 669 #define SIR 0x04 /* int: script: interrupt instruct. */ 670 #define IID 0x01 /* int: script: illegal instruct. */ 671 672/*0d*/ u8 nc_sstat0; 673 #define ILF 0x80 /* sta: data in SIDL register lsb */ 674 #define ORF 0x40 /* sta: data in SODR register lsb */ 675 #define OLF 0x20 /* sta: data in SODL register lsb */ 676 #define AIP 0x10 /* sta: arbitration in progress */ 677 #define LOA 0x08 /* sta: arbitration lost */ 678 #define WOA 0x04 /* sta: arbitration won */ 679 #define IRST 0x02 /* sta: scsi reset signal */ 680 #define SDP 0x01 /* sta: scsi parity signal */ 681 682/*0e*/ u8 nc_sstat1; 683 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 684 685/*0f*/ u8 nc_sstat2; 686 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 687 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 688 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 689 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 690 #define LDSC 0x02 /* sta: disconnect & reconnect */ 691 692/*10*/ u8 nc_dsa; /* --> Base page */ 693/*11*/ u8 nc_dsa1; 694/*12*/ u8 nc_dsa2; 695/*13*/ u8 nc_dsa3; 696 697/*14*/ u8 nc_istat; /* --> Main Command and status */ 698 #define CABRT 0x80 /* cmd: abort current operation */ 699 #define SRST 0x40 /* mod: reset chip */ 700 #define SIGP 0x20 /* r/w: message from host to ncr */ 701 #define SEM 0x10 /* r/w: message between host + ncr */ 702 #define CON 0x08 /* sta: connected to scsi */ 703 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 704 #define SIP 0x02 /* sta: scsi-interrupt */ 705 #define DIP 0x01 /* sta: host/script interrupt */ 706 707/*15*/ u8 nc_istat1; /* 896 and later cores only */ 708 #define FLSH 0x04 /* sta: chip is flushing */ 709 #define SRUN 0x02 /* sta: scripts are running */ 710 #define SIRQD 0x01 /* r/w: disable INT pin */ 711 712/*16*/ u8 nc_mbox0; /* 896 and later cores only */ 713/*17*/ u8 nc_mbox1; /* 896 and later cores only */ 714 715/*18*/ u8 nc_ctest0; 716 #define EHP 0x04 /* 720 even host parity */ 717/*19*/ u8 nc_ctest1; 718 719/*1a*/ u8 nc_ctest2; 720 #define CSIGP 0x40 721 /* bits 0-2,7 rsvd for C1010 */ 722 723/*1b*/ u8 nc_ctest3; 724 #define FLF 0x08 /* cmd: flush dma fifo */ 725 #define CLF 0x04 /* cmd: clear dma fifo */ 726 #define FM 0x02 /* mod: fetch pin mode */ 727 #define WRIE 0x01 /* mod: write and invalidate enable */ 728 /* bits 4-7 rsvd for C1010 */ 729 730/*1c*/ u32 nc_temp; /* ### Temporary stack */ 731 732/*20*/ u8 nc_dfifo; 733/*21*/ u8 nc_ctest4; 734 #define MUX 0x80 /* 720 host bus multiplex mode */ 735 #define BDIS 0x80 /* mod: burst disable */ 736 #define MPEE 0x08 /* mod: master parity error enable */ 737 738/*22*/ u8 nc_ctest5; 739 #define DFS 0x20 /* mod: dma fifo size */ 740 /* bits 0-1, 3-7 rsvd for C1010 */ 741/*23*/ u8 nc_ctest6; 742 743/*24*/ u32 nc_dbc; /* ### Byte count and command */ 744/*28*/ u32 nc_dnad; /* ### Next command register */ 745/*2c*/ u32 nc_dsp; /* --> Script Pointer */ 746/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */ 747 748/*34*/ u8 nc_scratcha; /* Temporary register a */ 749/*35*/ u8 nc_scratcha1; 750/*36*/ u8 nc_scratcha2; 751/*37*/ u8 nc_scratcha3; 752 753/*38*/ u8 nc_dmode; 754 #define BL_2 0x80 /* mod: burst length shift value +2 */ 755 #define BL_1 0x40 /* mod: burst length shift value +1 */ 756 #define ERL 0x08 /* mod: enable read line */ 757 #define ERMP 0x04 /* mod: enable read multiple */ 758 #define BOF 0x02 /* mod: burst op code fetch */ 759 760/*39*/ u8 nc_dien; 761/*3a*/ u8 nc_sbr; 762 763/*3b*/ u8 nc_dcntl; /* --> Script execution control */ 764 #define CLSE 0x80 /* mod: cache line size enable */ 765 #define PFF 0x40 /* cmd: pre-fetch flush */ 766 #define PFEN 0x20 /* mod: pre-fetch enable */ 767 #define EA 0x20 /* mod: 720 enable-ack */ 768 #define SSM 0x10 /* mod: single step mode */ 769 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 770 #define STD 0x04 /* cmd: start dma mode */ 771 #define IRQD 0x02 /* mod: irq disable */ 772 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 773 /* bits 0-1 rsvd for C1010 */ 774 775/*3c*/ u32 nc_adder; 776 777/*40*/ u16 nc_sien; /* -->: interrupt enable */ 778/*42*/ u16 nc_sist; /* <--: interrupt status */ 779 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 780 #define STO 0x0400/* sta: timeout (select) */ 781 #define GEN 0x0200/* sta: timeout (general) */ 782 #define HTH 0x0100/* sta: timeout (handshake) */ 783 #define MA 0x80 /* sta: phase mismatch */ 784 #define CMP 0x40 /* sta: arbitration complete */ 785 #define SEL 0x20 /* sta: selected by another device */ 786 #define RSL 0x10 /* sta: reselected by another device*/ 787 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 788 #define UDC 0x04 /* sta: unexpected disconnect */ 789 #define RST 0x02 /* sta: scsi bus reset detected */ 790 #define PAR 0x01 /* sta: scsi parity error */ 791 792/*44*/ u8 nc_slpar; 793/*45*/ u8 nc_swide; 794/*46*/ u8 nc_macntl; 795/*47*/ u8 nc_gpcntl; 796/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/ 797/*49*/ u8 nc_stime1; /* cmd: timeout user defined */ 798/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */ 799 800/*4c*/ u8 nc_stest0; 801 802/*4d*/ u8 nc_stest1; 803 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 804 #define DBLEN 0x08 /* clock doubler running */ 805 #define DBLSEL 0x04 /* clock doubler selected */ 806 807 808/*4e*/ u8 nc_stest2; 809 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 810 #define DIF 0x20 /* 720 SCSI differential mode */ 811 #define EXT 0x02 /* extended filtering */ 812 813/*4f*/ u8 nc_stest3; 814 #define TE 0x80 /* c: tolerAnt enable */ 815 #define HSC 0x20 /* c: Halt SCSI Clock */ 816 #define CSF 0x02 /* c: clear scsi fifo */ 817 818/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */ 819/*52*/ u8 nc_stest4; 820 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 821 #define SMODE_HVD 0x40 /* High Voltage Differential */ 822 #define SMODE_SE 0x80 /* Single Ended */ 823 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 824 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 825 /* bits 0-5 rsvd for C1010 */ 826 827/*53*/ u8 nc_53_; 828/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */ 829/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */ 830 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */ 831 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */ 832 #define ENNDJ 0x20 /* Enable Non Data PM Jump */ 833 #define DISFC 0x10 /* Disable Auto FIFO Clear */ 834 #define DILS 0x02 /* Disable Internal Load/Store */ 835 #define DPR 0x01 /* Disable Pipe Req */ 836 837/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */ 838 #define ZMOD 0x80 /* High Impedance Mode */ 839 #define DIC 0x10 /* Disable Internal Cycles */ 840 #define DDAC 0x08 /* Disable Dual Address Cycle */ 841 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */ 842 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */ 843 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */ 844 845/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */ 846/*5a*/ u16 nc_5a_; 847 848/*5c*/ u8 nc_scr0; /* Working register B */ 849/*5d*/ u8 nc_scr1; /* */ 850/*5e*/ u8 nc_scr2; /* */ 851/*5f*/ u8 nc_scr3; /* */ 852 853/*60*/ u8 nc_scrx[64]; /* Working register C-R */ 854/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */ 855/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */ 856/*a8*/ u32 nc_sfs; /* Script Fetch Selector */ 857/*ac*/ u32 nc_drs; /* DSA Relative Selector */ 858/*b0*/ u32 nc_sbms; /* Static Block Move Selector */ 859/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */ 860/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */ 861/*bc*/ u16 nc_scntl4; /* C1010 only */ 862 #define U3EN 0x80 /* Enable Ultra 3 */ 863 #define AIPEN 0x40 /* Allow check upper byte lanes */ 864 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT 865 transfer edge */ 866 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST 867 transfer edge */ 868 869/*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */ 870/*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */ 871 872/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */ 873/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */ 874/*c8*/ u8 nc_rbc; /* Remaining Byte Count */ 875/*c9*/ u8 nc_rbc1; /* */ 876/*ca*/ u8 nc_rbc2; /* */ 877/*cb*/ u8 nc_rbc3; /* */ 878 879/*cc*/ u8 nc_ua; /* Updated Address */ 880/*cd*/ u8 nc_ua1; /* */ 881/*ce*/ u8 nc_ua2; /* */ 882/*cf*/ u8 nc_ua3; /* */ 883/*d0*/ u32 nc_esa; /* Entry Storage Address */ 884/*d4*/ u8 nc_ia; /* Instruction Address */ 885/*d5*/ u8 nc_ia1; 886/*d6*/ u8 nc_ia2; 887/*d7*/ u8 nc_ia3; 888/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */ 889/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */ 890 891 /* Following for C1010 only */ 892/*e0*/ u16 nc_crcpad; /* CRC Value */ 893/*e2*/ u8 nc_crccntl0; /* CRC control register */ 894 #define SNDCRC 0x10 /* Send CRC Request */ 895/*e3*/ u8 nc_crccntl1; /* CRC control register */ 896/*e4*/ u32 nc_crcdata; /* CRC data register */ 897/*e8*/ u32 nc_e8_; /* rsvd */ 898/*ec*/ u32 nc_ec_; /* rsvd */ 899/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */ 900 901}; 902 903/*----------------------------------------------------------- 904** 905** Utility macros for the script. 906** 907**----------------------------------------------------------- 908*/ 909 910#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r)) 911#define REG(r) REGJ (nc_, r) 912 913typedef u32 ncrcmd; 914 915/*----------------------------------------------------------- 916** 917** SCSI phases 918** 919** DT phases illegal for ncr driver. 920** 921**----------------------------------------------------------- 922*/ 923 924#define SCR_DATA_OUT 0x00000000 925#define SCR_DATA_IN 0x01000000 926#define SCR_COMMAND 0x02000000 927#define SCR_STATUS 0x03000000 928#define SCR_DT_DATA_OUT 0x04000000 929#define SCR_DT_DATA_IN 0x05000000 930#define SCR_MSG_OUT 0x06000000 931#define SCR_MSG_IN 0x07000000 932 933#define SCR_ILG_OUT 0x04000000 934#define SCR_ILG_IN 0x05000000 935 936/*----------------------------------------------------------- 937** 938** Data transfer via SCSI. 939** 940**----------------------------------------------------------- 941** 942** MOVE_ABS (LEN) 943** <<start address>> 944** 945** MOVE_IND (LEN) 946** <<dnad_offset>> 947** 948** MOVE_TBL 949** <<dnad_offset>> 950** 951**----------------------------------------------------------- 952*/ 953 954#define OPC_MOVE 0x08000000 955 956#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 957#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 958#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 959 960#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 961#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 962#define SCR_CHMOV_TBL (0x10000000) 963 964struct scr_tblmove { 965 u32 size; 966 u32 addr; 967}; 968 969/*----------------------------------------------------------- 970** 971** Selection 972** 973**----------------------------------------------------------- 974** 975** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 976** <<alternate_address>> 977** 978** SEL_TBL | << dnad_offset>> [ | REL_JMP] 979** <<alternate_address>> 980** 981**----------------------------------------------------------- 982*/ 983 984#define SCR_SEL_ABS 0x40000000 985#define SCR_SEL_ABS_ATN 0x41000000 986#define SCR_SEL_TBL 0x42000000 987#define SCR_SEL_TBL_ATN 0x43000000 988 989 990#ifdef SCSI_NCR_BIG_ENDIAN 991struct scr_tblsel { 992 u8 sel_scntl3; 993 u8 sel_id; 994 u8 sel_sxfer; 995 u8 sel_scntl4; 996}; 997#else 998struct scr_tblsel { 999 u8 sel_scntl4; 1000 u8 sel_sxfer; 1001 u8 sel_id; 1002 u8 sel_scntl3; 1003}; 1004#endif 1005 1006#define SCR_JMP_REL 0x04000000 1007#define SCR_ID(id) (((u32)(id)) << 16) 1008 1009/*----------------------------------------------------------- 1010** 1011** Waiting for Disconnect or Reselect 1012** 1013**----------------------------------------------------------- 1014** 1015** WAIT_DISC 1016** dummy: <<alternate_address>> 1017** 1018** WAIT_RESEL 1019** <<alternate_address>> 1020** 1021**----------------------------------------------------------- 1022*/ 1023 1024#define SCR_WAIT_DISC 0x48000000 1025#define SCR_WAIT_RESEL 0x50000000 1026 1027/*----------------------------------------------------------- 1028** 1029** Bit Set / Reset 1030** 1031**----------------------------------------------------------- 1032** 1033** SET (flags {|.. }) 1034** 1035** CLR (flags {|.. }) 1036** 1037**----------------------------------------------------------- 1038*/ 1039 1040#define SCR_SET(f) (0x58000000 | (f)) 1041#define SCR_CLR(f) (0x60000000 | (f)) 1042 1043#define SCR_CARRY 0x00000400 1044#define SCR_TRG 0x00000200 1045#define SCR_ACK 0x00000040 1046#define SCR_ATN 0x00000008 1047 1048 1049 1050 1051/*----------------------------------------------------------- 1052** 1053** Memory to memory move 1054** 1055**----------------------------------------------------------- 1056** 1057** COPY (bytecount) 1058** << source_address >> 1059** << destination_address >> 1060** 1061** SCR_COPY sets the NO FLUSH option by default. 1062** SCR_COPY_F does not set this option. 1063** 1064** For chips which do not support this option, 1065** ncr_copy_and_bind() will remove this bit. 1066**----------------------------------------------------------- 1067*/ 1068 1069#define SCR_NO_FLUSH 0x01000000 1070 1071#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 1072#define SCR_COPY_F(n) (0xc0000000 | (n)) 1073 1074/*----------------------------------------------------------- 1075** 1076** Register move and binary operations 1077** 1078**----------------------------------------------------------- 1079** 1080** SFBR_REG (reg, op, data) reg = SFBR op data 1081** << 0 >> 1082** 1083** REG_SFBR (reg, op, data) SFBR = reg op data 1084** << 0 >> 1085** 1086** REG_REG (reg, op, data) reg = reg op data 1087** << 0 >> 1088** 1089**----------------------------------------------------------- 1090** On 810A, 860, 825A, 875, 895 and 896 chips the content 1091** of SFBR register can be used as data (SCR_SFBR_DATA). 1092** The 896 has additional IO registers starting at 1093** offset 0x80. Bit 7 of register offset is stored in 1094** bit 7 of the SCRIPTS instruction first DWORD. 1095**----------------------------------------------------------- 1096*/ 1097 1098#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80)) 1099 1100#define SCR_SFBR_REG(reg,op,data) \ 1101 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 1102 1103#define SCR_REG_SFBR(reg,op,data) \ 1104 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 1105 1106#define SCR_REG_REG(reg,op,data) \ 1107 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 1108 1109 1110#define SCR_LOAD 0x00000000 1111#define SCR_SHL 0x01000000 1112#define SCR_OR 0x02000000 1113#define SCR_XOR 0x03000000 1114#define SCR_AND 0x04000000 1115#define SCR_SHR 0x05000000 1116#define SCR_ADD 0x06000000 1117#define SCR_ADDC 0x07000000 1118 1119#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 1120 1121/*----------------------------------------------------------- 1122** 1123** FROM_REG (reg) SFBR = reg 1124** << 0 >> 1125** 1126** TO_REG (reg) reg = SFBR 1127** << 0 >> 1128** 1129** LOAD_REG (reg, data) reg = <data> 1130** << 0 >> 1131** 1132** LOAD_SFBR(data) SFBR = <data> 1133** << 0 >> 1134** 1135**----------------------------------------------------------- 1136*/ 1137 1138#define SCR_FROM_REG(reg) \ 1139 SCR_REG_SFBR(reg,SCR_OR,0) 1140 1141#define SCR_TO_REG(reg) \ 1142 SCR_SFBR_REG(reg,SCR_OR,0) 1143 1144#define SCR_LOAD_REG(reg,data) \ 1145 SCR_REG_REG(reg,SCR_LOAD,data) 1146 1147#define SCR_LOAD_SFBR(data) \ 1148 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 1149 1150/*----------------------------------------------------------- 1151** 1152** LOAD from memory to register. 1153** STORE from register to memory. 1154** 1155** Only supported by 810A, 860, 825A, 875, 895 and 896. 1156** 1157**----------------------------------------------------------- 1158** 1159** LOAD_ABS (LEN) 1160** <<start address>> 1161** 1162** LOAD_REL (LEN) (DSA relative) 1163** <<dsa_offset>> 1164** 1165**----------------------------------------------------------- 1166*/ 1167 1168#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 1169#define SCR_NO_FLUSH2 0x02000000 1170#define SCR_DSA_REL2 0x10000000 1171 1172#define SCR_LOAD_R(reg, how, n) \ 1173 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 1174 1175#define SCR_STORE_R(reg, how, n) \ 1176 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 1177 1178#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 1179#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 1180#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 1181#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 1182 1183#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 1184#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 1185#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 1186#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 1187 1188 1189/*----------------------------------------------------------- 1190** 1191** Waiting for Disconnect or Reselect 1192** 1193**----------------------------------------------------------- 1194** 1195** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 1196** <<address>> 1197** 1198** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 1199** <<distance>> 1200** 1201** CALL [ | IFTRUE/IFFALSE ( ... ) ] 1202** <<address>> 1203** 1204** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 1205** <<distance>> 1206** 1207** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 1208** <<dummy>> 1209** 1210** INT [ | IFTRUE/IFFALSE ( ... ) ] 1211** <<ident>> 1212** 1213** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 1214** <<ident>> 1215** 1216** Conditions: 1217** WHEN (phase) 1218** IF (phase) 1219** CARRYSET 1220** DATA (data, mask) 1221** 1222**----------------------------------------------------------- 1223*/ 1224 1225#define SCR_NO_OP 0x80000000 1226#define SCR_JUMP 0x80080000 1227#define SCR_JUMP64 0x80480000 1228#define SCR_JUMPR 0x80880000 1229#define SCR_CALL 0x88080000 1230#define SCR_CALLR 0x88880000 1231#define SCR_RETURN 0x90080000 1232#define SCR_INT 0x98080000 1233#define SCR_INT_FLY 0x98180000 1234 1235#define IFFALSE(arg) (0x00080000 | (arg)) 1236#define IFTRUE(arg) (0x00000000 | (arg)) 1237 1238#define WHEN(phase) (0x00030000 | (phase)) 1239#define IF(phase) (0x00020000 | (phase)) 1240 1241#define DATA(D) (0x00040000 | ((D) & 0xff)) 1242#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 1243 1244#define CARRYSET (0x00200000) 1245 1246/*----------------------------------------------------------- 1247** 1248** SCSI constants. 1249** 1250**----------------------------------------------------------- 1251*/ 1252 1253/* 1254** Status 1255*/ 1256 1257#define S_GOOD (0x00) 1258#define S_CHECK_COND (0x02) 1259#define S_COND_MET (0x04) 1260#define S_BUSY (0x08) 1261#define S_INT (0x10) 1262#define S_INT_COND_MET (0x14) 1263#define S_CONFLICT (0x18) 1264#define S_TERMINATED (0x20) 1265#define S_QUEUE_FULL (0x28) 1266#define S_ILLEGAL (0xff) 1267#define S_SENSE (0x80) 1268 1269/* 1270 * End of ncrreg from FreeBSD 1271 */ 1272 1273/* 1274 Build a scatter/gather entry. 1275 see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge() 1276 implementation ;) 1277 */ 1278 1279#define ncr_build_sge(np, data, badd, len) \ 1280do { \ 1281 (data)->addr = cpu_to_scr(badd); \ 1282 (data)->size = cpu_to_scr(len); \ 1283} while (0) 1284 1285/*========================================================== 1286** 1287** Structures used by the detection routine to transmit 1288** device configuration to the attach function. 1289** 1290**========================================================== 1291*/ 1292struct ncr_slot { 1293 u_long base; 1294 u_long base_2; 1295 u_long base_c; 1296 u_long base_2_c; 1297 void __iomem *base_v; 1298 void __iomem *base_2_v; 1299 int irq; 1300/* port and reg fields to use INB, OUTB macros */ 1301 volatile struct ncr_reg __iomem *reg; 1302}; 1303 1304/*========================================================== 1305** 1306** Structure used by detection routine to save data on 1307** each detected board for attach. 1308** 1309**========================================================== 1310*/ 1311struct ncr_device { 1312 struct device *dev; 1313 struct ncr_slot slot; 1314 struct ncr_chip chip; 1315 u_char host_id; 1316 u8 differential; 1317}; 1318 1319extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device); 1320extern void ncr53c8xx_release(struct Scsi_Host *host); 1321irqreturn_t ncr53c8xx_intr(int irq, void *dev_id); 1322extern int ncr53c8xx_init(void); 1323extern void ncr53c8xx_exit(void); 1324 1325#endif /* NCR53C8XX_H */ 1326