1/* 2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40#ifndef _PMC8001_REG_H_ 41#define _PMC8001_REG_H_ 42 43#include <linux/types.h> 44#include <scsi/libsas.h> 45 46 47/* for Request Opcode of IOMB */ 48#define OPC_INB_ECHO 1 /* 0x000 */ 49#define OPC_INB_PHYSTART 4 /* 0x004 */ 50#define OPC_INB_PHYSTOP 5 /* 0x005 */ 51#define OPC_INB_SSPINIIOSTART 6 /* 0x006 */ 52#define OPC_INB_SSPINITMSTART 7 /* 0x007 */ 53#define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */ 54#define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */ 55#define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */ 56#define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */ 57#define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */ 58#define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */ 59#define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */ 60#define OPC_INB_SSP_ABORT 15 /* 0x00F */ 61#define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */ 62#define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */ 63#define OPC_INB_SMP_REQUEST 18 /* 0x012 */ 64/* SMP_RESPONSE is removed */ 65#define OPC_INB_SMP_RESPONSE 19 /* 0x013 */ 66#define OPC_INB_SMP_ABORT 20 /* 0x014 */ 67#define OPC_INB_REG_DEV 22 /* 0x016 */ 68#define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */ 69#define OPC_INB_SATA_ABORT 24 /* 0x018 */ 70#define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */ 71#define OPC_INB_GET_DEV_INFO 26 /* 0x01A */ 72#define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */ 73#define OPC_INB_GPIO 34 /* 0x022 */ 74#define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */ 75#define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */ 76#define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */ 77#define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */ 78#define OPC_INB_PORT_CONTROL 39 /* 0x027 */ 79#define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */ 80#define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */ 81#define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */ 82#define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */ 83#define OPC_INB_SET_DEV_INFO 44 /* 0x02C */ 84#define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */ 85 86/* for Response Opcode of IOMB */ 87#define OPC_OUB_ECHO 1 /* 0x001 */ 88#define OPC_OUB_HW_EVENT 4 /* 0x004 */ 89#define OPC_OUB_SSP_COMP 5 /* 0x005 */ 90#define OPC_OUB_SMP_COMP 6 /* 0x006 */ 91#define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */ 92#define OPC_OUB_DEV_REGIST 10 /* 0x00A */ 93#define OPC_OUB_DEREG_DEV 11 /* 0x00B */ 94#define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */ 95#define OPC_OUB_SATA_COMP 13 /* 0x00D */ 96#define OPC_OUB_SATA_EVENT 14 /* 0x00E */ 97#define OPC_OUB_SSP_EVENT 15 /* 0x00F */ 98#define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */ 99/* SMP_RECEIVED Notification is removed */ 100#define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */ 101#define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */ 102#define OPC_OUB_DEV_INFO 19 /* 0x013 */ 103#define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */ 104#define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */ 105#define OPC_OUB_GPIO_EVENT 23 /* 0x017 */ 106#define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */ 107#define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */ 108#define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */ 109#define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */ 110#define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */ 111#define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */ 112#define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */ 113#define OPC_OUB_PORT_CONTROL 32 /* 0x020 */ 114#define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */ 115#define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */ 116#define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */ 117#define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */ 118#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */ 119#define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */ 120#define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */ 121#define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */ 122#define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */ 123 124/* for phy start*/ 125#define SPINHOLD_DISABLE (0x00 << 14) 126#define SPINHOLD_ENABLE (0x01 << 14) 127#define LINKMODE_SAS (0x01 << 12) 128#define LINKMODE_DSATA (0x02 << 12) 129#define LINKMODE_AUTO (0x03 << 12) 130#define LINKRATE_15 (0x01 << 8) 131#define LINKRATE_30 (0x02 << 8) 132#define LINKRATE_60 (0x04 << 8) 133 134/* for phy state */ 135 136#define PHY_STATE_LINK_UP_SPC 0x1 137 138/* for new SPC controllers MEMBASE III is shared between BIOS and DATA */ 139#define GSM_SM_BASE 0x4F0000 140struct mpi_msg_hdr{ 141 __le32 header; /* Bits [11:0] - Message operation code */ 142 /* Bits [15:12] - Message Category */ 143 /* Bits [21:16] - Outboundqueue ID for the 144 operation completion message */ 145 /* Bits [23:22] - Reserved */ 146 /* Bits [28:24] - Buffer Count, indicates how 147 many buffer are allocated for the massage */ 148 /* Bits [30:29] - Reserved */ 149 /* Bits [31] - Message Valid bit */ 150} __attribute__((packed, aligned(4))); 151 152 153/* 154 * brief the data structure of PHY Start Command 155 * use to describe enable the phy (64 bytes) 156 */ 157struct phy_start_req { 158 __le32 tag; 159 __le32 ase_sh_lm_slr_phyid; 160 struct sas_identify_frame sas_identify; 161 u32 reserved[5]; 162} __attribute__((packed, aligned(4))); 163 164 165/* 166 * brief the data structure of PHY Start Command 167 * use to disable the phy (64 bytes) 168 */ 169struct phy_stop_req { 170 __le32 tag; 171 __le32 phy_id; 172 u32 reserved[13]; 173} __attribute__((packed, aligned(4))); 174 175 176/* set device bits fis - device to host */ 177struct set_dev_bits_fis { 178 u8 fis_type; /* 0xA1*/ 179 u8 n_i_pmport; 180 /* b7 : n Bit. Notification bit. If set device needs attention. */ 181 /* b6 : i Bit. Interrupt Bit */ 182 /* b5-b4: reserved2 */ 183 /* b3-b0: PM Port */ 184 u8 status; 185 u8 error; 186 u32 _r_a; 187} __attribute__ ((packed)); 188/* PIO setup FIS - device to host */ 189struct pio_setup_fis { 190 u8 fis_type; /* 0x5f */ 191 u8 i_d_pmPort; 192 /* b7 : reserved */ 193 /* b6 : i bit. Interrupt bit */ 194 /* b5 : d bit. data transfer direction. set to 1 for device to host 195 xfer */ 196 /* b4 : reserved */ 197 /* b3-b0: PM Port */ 198 u8 status; 199 u8 error; 200 u8 lbal; 201 u8 lbam; 202 u8 lbah; 203 u8 device; 204 u8 lbal_exp; 205 u8 lbam_exp; 206 u8 lbah_exp; 207 u8 _r_a; 208 u8 sector_count; 209 u8 sector_count_exp; 210 u8 _r_b; 211 u8 e_status; 212 u8 _r_c[2]; 213 u8 transfer_count; 214} __attribute__ ((packed)); 215 216/* 217 * brief the data structure of SATA Completion Response 218 * use to describe the sata task response (64 bytes) 219 */ 220struct sata_completion_resp { 221 __le32 tag; 222 __le32 status; 223 __le32 param; 224 u32 sata_resp[12]; 225} __attribute__((packed, aligned(4))); 226 227 228/* 229 * brief the data structure of SAS HW Event Notification 230 * use to alert the host about the hardware event(64 bytes) 231 */ 232struct hw_event_resp { 233 __le32 lr_evt_status_phyid_portid; 234 __le32 evt_param; 235 __le32 npip_portstate; 236 struct sas_identify_frame sas_identify; 237 struct dev_to_host_fis sata_fis; 238} __attribute__((packed, aligned(4))); 239 240 241/* 242 * brief the data structure of REGISTER DEVICE Command 243 * use to describe MPI REGISTER DEVICE Command (64 bytes) 244 */ 245 246struct reg_dev_req { 247 __le32 tag; 248 __le32 phyid_portid; 249 __le32 dtype_dlr_retry; 250 __le32 firstburstsize_ITNexustimeout; 251 u8 sas_addr[SAS_ADDR_SIZE]; 252 __le32 upper_device_id; 253 u32 reserved[8]; 254} __attribute__((packed, aligned(4))); 255 256 257/* 258 * brief the data structure of DEREGISTER DEVICE Command 259 * use to request spc to remove all internal resources associated 260 * with the device id (64 bytes) 261 */ 262 263struct dereg_dev_req { 264 __le32 tag; 265 __le32 device_id; 266 u32 reserved[13]; 267} __attribute__((packed, aligned(4))); 268 269 270/* 271 * brief the data structure of DEVICE_REGISTRATION Response 272 * use to notify the completion of the device registration (64 bytes) 273 */ 274 275struct dev_reg_resp { 276 __le32 tag; 277 __le32 status; 278 __le32 device_id; 279 u32 reserved[12]; 280} __attribute__((packed, aligned(4))); 281 282 283/* 284 * brief the data structure of Local PHY Control Command 285 * use to issue PHY CONTROL to local phy (64 bytes) 286 */ 287struct local_phy_ctl_req { 288 __le32 tag; 289 __le32 phyop_phyid; 290 u32 reserved1[13]; 291} __attribute__((packed, aligned(4))); 292 293 294/** 295 * brief the data structure of Local Phy Control Response 296 * use to describe MPI Local Phy Control Response (64 bytes) 297 */ 298struct local_phy_ctl_resp { 299 __le32 tag; 300 __le32 phyop_phyid; 301 __le32 status; 302 u32 reserved[12]; 303} __attribute__((packed, aligned(4))); 304 305 306#define OP_BITS 0x0000FF00 307#define ID_BITS 0x000000FF 308 309/* 310 * brief the data structure of PORT Control Command 311 * use to control port properties (64 bytes) 312 */ 313 314struct port_ctl_req { 315 __le32 tag; 316 __le32 portop_portid; 317 __le32 param0; 318 __le32 param1; 319 u32 reserved1[11]; 320} __attribute__((packed, aligned(4))); 321 322 323/* 324 * brief the data structure of HW Event Ack Command 325 * use to acknowledge receive HW event (64 bytes) 326 */ 327 328struct hw_event_ack_req { 329 __le32 tag; 330 __le32 sea_phyid_portid; 331 __le32 param0; 332 __le32 param1; 333 u32 reserved1[11]; 334} __attribute__((packed, aligned(4))); 335 336 337/* 338 * brief the data structure of SSP Completion Response 339 * use to indicate a SSP Completion (n bytes) 340 */ 341struct ssp_completion_resp { 342 __le32 tag; 343 __le32 status; 344 __le32 param; 345 __le32 ssptag_rescv_rescpad; 346 struct ssp_response_iu ssp_resp_iu; 347 __le32 residual_count; 348} __attribute__((packed, aligned(4))); 349 350 351#define SSP_RESCV_BIT 0x00010000 352 353/* 354 * brief the data structure of SATA EVNET esponse 355 * use to indicate a SATA Completion (64 bytes) 356 */ 357 358struct sata_event_resp { 359 __le32 tag; 360 __le32 event; 361 __le32 port_id; 362 __le32 device_id; 363 u32 reserved[11]; 364} __attribute__((packed, aligned(4))); 365 366/* 367 * brief the data structure of SSP EVNET esponse 368 * use to indicate a SSP Completion (64 bytes) 369 */ 370 371struct ssp_event_resp { 372 __le32 tag; 373 __le32 event; 374 __le32 port_id; 375 __le32 device_id; 376 u32 reserved[11]; 377} __attribute__((packed, aligned(4))); 378 379/** 380 * brief the data structure of General Event Notification Response 381 * use to describe MPI General Event Notification Response (64 bytes) 382 */ 383struct general_event_resp { 384 __le32 status; 385 __le32 inb_IOMB_payload[14]; 386} __attribute__((packed, aligned(4))); 387 388 389#define GENERAL_EVENT_PAYLOAD 14 390#define OPCODE_BITS 0x00000fff 391 392/* 393 * brief the data structure of SMP Request Command 394 * use to describe MPI SMP REQUEST Command (64 bytes) 395 */ 396struct smp_req { 397 __le32 tag; 398 __le32 device_id; 399 __le32 len_ip_ir; 400 /* Bits [0] - Indirect response */ 401 /* Bits [1] - Indirect Payload */ 402 /* Bits [15:2] - Reserved */ 403 /* Bits [23:16] - direct payload Len */ 404 /* Bits [31:24] - Reserved */ 405 u8 smp_req16[16]; 406 union { 407 u8 smp_req[32]; 408 struct { 409 __le64 long_req_addr;/* sg dma address, LE */ 410 __le32 long_req_size;/* LE */ 411 u32 _r_a; 412 __le64 long_resp_addr;/* sg dma address, LE */ 413 __le32 long_resp_size;/* LE */ 414 u32 _r_b; 415 } long_smp_req;/* sequencer extension */ 416 }; 417} __attribute__((packed, aligned(4))); 418/* 419 * brief the data structure of SMP Completion Response 420 * use to describe MPI SMP Completion Response (64 bytes) 421 */ 422struct smp_completion_resp { 423 __le32 tag; 424 __le32 status; 425 __le32 param; 426 __le32 _r_a[12]; 427} __attribute__((packed, aligned(4))); 428 429/* 430 *brief the data structure of SSP SMP SATA Abort Command 431 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes) 432 */ 433struct task_abort_req { 434 __le32 tag; 435 __le32 device_id; 436 __le32 tag_to_abort; 437 __le32 abort_all; 438 u32 reserved[11]; 439} __attribute__((packed, aligned(4))); 440 441/* These flags used for SSP SMP & SATA Abort */ 442#define ABORT_MASK 0x3 443#define ABORT_SINGLE 0x0 444#define ABORT_ALL 0x1 445 446/** 447 * brief the data structure of SSP SATA SMP Abort Response 448 * use to describe SSP SMP & SATA Abort Response ( 64 bytes) 449 */ 450struct task_abort_resp { 451 __le32 tag; 452 __le32 status; 453 __le32 scp; 454 u32 reserved[12]; 455} __attribute__((packed, aligned(4))); 456 457 458/** 459 * brief the data structure of SAS Diagnostic Start/End Command 460 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) 461 */ 462struct sas_diag_start_end_req { 463 __le32 tag; 464 __le32 operation_phyid; 465 u32 reserved[13]; 466} __attribute__((packed, aligned(4))); 467 468 469/** 470 * brief the data structure of SAS Diagnostic Execute Command 471 * use to describe MPI SAS Diagnostic Execute Command (64 bytes) 472 */ 473struct sas_diag_execute_req{ 474 __le32 tag; 475 __le32 cmdtype_cmddesc_phyid; 476 __le32 pat1_pat2; 477 __le32 threshold; 478 __le32 codepat_errmsk; 479 __le32 pmon; 480 __le32 pERF1CTL; 481 u32 reserved[8]; 482} __attribute__((packed, aligned(4))); 483 484 485#define SAS_DIAG_PARAM_BYTES 24 486 487/* 488 * brief the data structure of Set Device State Command 489 * use to describe MPI Set Device State Command (64 bytes) 490 */ 491struct set_dev_state_req { 492 __le32 tag; 493 __le32 device_id; 494 __le32 nds; 495 u32 reserved[12]; 496} __attribute__((packed, aligned(4))); 497 498/* 499 * brief the data structure of sas_re_initialization 500 */ 501struct sas_re_initialization_req { 502 503 __le32 tag; 504 __le32 SSAHOLT;/* bit29-set max port; 505 ** bit28-set open reject cmd retries. 506 ** bit27-set open reject data retries. 507 ** bit26-set open reject option, remap:1 or not:0. 508 ** bit25-set sata head of line time out. 509 */ 510 __le32 reserved_maxPorts; 511 __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16; 512 * data retries: bit15-bit0. 513 */ 514 __le32 sata_hol_tmo; 515 u32 reserved1[10]; 516} __attribute__((packed, aligned(4))); 517 518/* 519 * brief the data structure of SATA Start Command 520 * use to describe MPI SATA IO Start Command (64 bytes) 521 */ 522 523struct sata_start_req { 524 __le32 tag; 525 __le32 device_id; 526 __le32 data_len; 527 __le32 ncqtag_atap_dir_m; 528 struct host_to_dev_fis sata_fis; 529 u32 reserved1; 530 u32 reserved2; 531 u32 addr_low; 532 u32 addr_high; 533 __le32 len; 534 __le32 esgl; 535} __attribute__((packed, aligned(4))); 536 537/** 538 * brief the data structure of SSP INI TM Start Command 539 * use to describe MPI SSP INI TM Start Command (64 bytes) 540 */ 541struct ssp_ini_tm_start_req { 542 __le32 tag; 543 __le32 device_id; 544 __le32 relate_tag; 545 __le32 tmf; 546 u8 lun[8]; 547 __le32 ds_ads_m; 548 u32 reserved[8]; 549} __attribute__((packed, aligned(4))); 550 551 552struct ssp_info_unit { 553 u8 lun[8];/* SCSI Logical Unit Number */ 554 u8 reserved1;/* reserved */ 555 u8 efb_prio_attr; 556 /* B7 : enabledFirstBurst */ 557 /* B6-3 : taskPriority */ 558 /* B2-0 : taskAttribute */ 559 u8 reserved2; /* reserved */ 560 u8 additional_cdb_len; 561 /* B7-2 : additional_cdb_len */ 562 /* B1-0 : reserved */ 563 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */ 564} __attribute__((packed, aligned(4))); 565 566 567/** 568 * brief the data structure of SSP INI IO Start Command 569 * use to describe MPI SSP INI IO Start Command (64 bytes) 570 */ 571struct ssp_ini_io_start_req { 572 __le32 tag; 573 __le32 device_id; 574 __le32 data_len; 575 __le32 dir_m_tlr; 576 struct ssp_info_unit ssp_iu; 577 __le32 addr_low; 578 __le32 addr_high; 579 __le32 len; 580 __le32 esgl; 581} __attribute__((packed, aligned(4))); 582 583 584/** 585 * brief the data structure of Firmware download 586 * use to describe MPI FW DOWNLOAD Command (64 bytes) 587 */ 588struct fw_flash_Update_req { 589 __le32 tag; 590 __le32 cur_image_offset; 591 __le32 cur_image_len; 592 __le32 total_image_len; 593 u32 reserved0[7]; 594 __le32 sgl_addr_lo; 595 __le32 sgl_addr_hi; 596 __le32 len; 597 __le32 ext_reserved; 598} __attribute__((packed, aligned(4))); 599 600 601#define FWFLASH_IOMB_RESERVED_LEN 0x07 602/** 603 * brief the data structure of FW_FLASH_UPDATE Response 604 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) 605 * 606 */ 607struct fw_flash_Update_resp { 608 __le32 tag; 609 __le32 status; 610 u32 reserved[13]; 611} __attribute__((packed, aligned(4))); 612 613 614/** 615 * brief the data structure of Get NVM Data Command 616 * use to get data from NVM in HBA(64 bytes) 617 */ 618struct get_nvm_data_req { 619 __le32 tag; 620 __le32 len_ir_vpdd; 621 __le32 vpd_offset; 622 u32 reserved[8]; 623 __le32 resp_addr_lo; 624 __le32 resp_addr_hi; 625 __le32 resp_len; 626 u32 reserved1; 627} __attribute__((packed, aligned(4))); 628 629 630struct set_nvm_data_req { 631 __le32 tag; 632 __le32 len_ir_vpdd; 633 __le32 vpd_offset; 634 __le32 reserved[8]; 635 __le32 resp_addr_lo; 636 __le32 resp_addr_hi; 637 __le32 resp_len; 638 u32 reserved1; 639} __attribute__((packed, aligned(4))); 640 641 642#define TWI_DEVICE 0x0 643#define C_SEEPROM 0x1 644#define VPD_FLASH 0x4 645#define AAP1_RDUMP 0x5 646#define IOP_RDUMP 0x6 647#define EXPAN_ROM 0x7 648 649#define IPMode 0x80000000 650#define NVMD_TYPE 0x0000000F 651#define NVMD_STAT 0x0000FFFF 652#define NVMD_LEN 0xFF000000 653/** 654 * brief the data structure of Get NVMD Data Response 655 * use to describe MPI Get NVMD Data Response (64 bytes) 656 */ 657struct get_nvm_data_resp { 658 __le32 tag; 659 __le32 ir_tda_bn_dps_das_nvm; 660 __le32 dlen_status; 661 __le32 nvm_data[12]; 662} __attribute__((packed, aligned(4))); 663 664 665/** 666 * brief the data structure of SAS Diagnostic Start/End Response 667 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) 668 * 669 */ 670struct sas_diag_start_end_resp { 671 __le32 tag; 672 __le32 status; 673 u32 reserved[13]; 674} __attribute__((packed, aligned(4))); 675 676 677/** 678 * brief the data structure of SAS Diagnostic Execute Response 679 * use to describe MPI SAS Diagnostic Execute Response (64 bytes) 680 * 681 */ 682struct sas_diag_execute_resp { 683 __le32 tag; 684 __le32 cmdtype_cmddesc_phyid; 685 __le32 Status; 686 __le32 ReportData; 687 u32 reserved[11]; 688} __attribute__((packed, aligned(4))); 689 690 691/** 692 * brief the data structure of Set Device State Response 693 * use to describe MPI Set Device State Response (64 bytes) 694 * 695 */ 696struct set_dev_state_resp { 697 __le32 tag; 698 __le32 status; 699 __le32 device_id; 700 __le32 pds_nds; 701 u32 reserved[11]; 702} __attribute__((packed, aligned(4))); 703 704 705#define NDS_BITS 0x0F 706#define PDS_BITS 0xF0 707 708/* 709 * HW Events type 710 */ 711 712#define HW_EVENT_RESET_START 0x01 713#define HW_EVENT_CHIP_RESET_COMPLETE 0x02 714#define HW_EVENT_PHY_STOP_STATUS 0x03 715#define HW_EVENT_SAS_PHY_UP 0x04 716#define HW_EVENT_SATA_PHY_UP 0x05 717#define HW_EVENT_SATA_SPINUP_HOLD 0x06 718#define HW_EVENT_PHY_DOWN 0x07 719#define HW_EVENT_PORT_INVALID 0x08 720#define HW_EVENT_BROADCAST_CHANGE 0x09 721#define HW_EVENT_PHY_ERROR 0x0A 722#define HW_EVENT_BROADCAST_SES 0x0B 723#define HW_EVENT_INBOUND_CRC_ERROR 0x0C 724#define HW_EVENT_HARD_RESET_RECEIVED 0x0D 725#define HW_EVENT_MALFUNCTION 0x0E 726#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F 727#define HW_EVENT_BROADCAST_EXP 0x10 728#define HW_EVENT_PHY_START_STATUS 0x11 729#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12 730#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13 731#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14 732#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15 733#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16 734#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 735#define HW_EVENT_PORT_RECOVER 0x18 736#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19 737#define HW_EVENT_PORT_RESET_COMPLETE 0x20 738#define EVENT_BROADCAST_ASYNCH_EVENT 0x21 739 740/* port state */ 741#define PORT_NOT_ESTABLISHED 0x00 742#define PORT_VALID 0x01 743#define PORT_LOSTCOMM 0x02 744#define PORT_IN_RESET 0x04 745#define PORT_INVALID 0x08 746 747/* 748 * SSP/SMP/SATA IO Completion Status values 749 */ 750 751#define IO_SUCCESS 0x00 752#define IO_ABORTED 0x01 753#define IO_OVERFLOW 0x02 754#define IO_UNDERFLOW 0x03 755#define IO_FAILED 0x04 756#define IO_ABORT_RESET 0x05 757#define IO_NOT_VALID 0x06 758#define IO_NO_DEVICE 0x07 759#define IO_ILLEGAL_PARAMETER 0x08 760#define IO_LINK_FAILURE 0x09 761#define IO_PROG_ERROR 0x0A 762#define IO_EDC_IN_ERROR 0x0B 763#define IO_EDC_OUT_ERROR 0x0C 764#define IO_ERROR_HW_TIMEOUT 0x0D 765#define IO_XFER_ERROR_BREAK 0x0E 766#define IO_XFER_ERROR_PHY_NOT_READY 0x0F 767#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10 768#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11 769#define IO_OPEN_CNX_ERROR_BREAK 0x12 770#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13 771#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14 772#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15 773#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16 774#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17 775#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18 776#define IO_XFER_ERROR_NAK_RECEIVED 0x19 777#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A 778#define IO_XFER_ERROR_PEER_ABORTED 0x1B 779#define IO_XFER_ERROR_RX_FRAME 0x1C 780#define IO_XFER_ERROR_DMA 0x1D 781#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E 782#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F 783#define IO_XFER_ERROR_SATA 0x20 784#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22 785#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21 786#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23 787#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24 788#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25 789#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26 790#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27 791#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28 792 793#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30 794#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31 795#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32 796 797#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34 798#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35 799#define IO_XFER_CMD_FRAME_ISSUED 0x36 800#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37 801#define IO_PORT_IN_RESET 0x38 802#define IO_DS_NON_OPERATIONAL 0x39 803#define IO_DS_IN_RECOVERY 0x3A 804#define IO_TM_TAG_NOT_FOUND 0x3B 805#define IO_XFER_PIO_SETUP_ERROR 0x3C 806#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D 807#define IO_DS_IN_ERROR 0x3E 808#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F 809#define IO_ABORT_IN_PROGRESS 0x40 810#define IO_ABORT_DELAYED 0x41 811#define IO_INVALID_LENGTH 0x42 812 813/* WARNING: This error code must always be the last number. 814 * If you add error code, modify this code also 815 * It is used as an index 816 */ 817#define IO_ERROR_UNKNOWN_GENERIC 0x43 818 819/* MSGU CONFIGURATION TABLE*/ 820 821#define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */ 822#define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */ 823#define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */ 824#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */ 825#define MSGU_IBDB_SET 0x04 826#define MSGU_HOST_INT_STATUS 0x08 827#define MSGU_HOST_INT_MASK 0x0C 828#define MSGU_IOPIB_INT_STATUS 0x18 829#define MSGU_IOPIB_INT_MASK 0x1C 830#define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */ 831#define MSGU_MSGU_CONTROL 0x24 832#define MSGU_ODR 0x3C/* RevB */ 833#define MSGU_ODCR 0x40/* RevB */ 834#define MSGU_SCRATCH_PAD_0 0x44 835#define MSGU_SCRATCH_PAD_1 0x48 836#define MSGU_SCRATCH_PAD_2 0x4C 837#define MSGU_SCRATCH_PAD_3 0x50 838#define MSGU_HOST_SCRATCH_PAD_0 0x54 839#define MSGU_HOST_SCRATCH_PAD_1 0x58 840#define MSGU_HOST_SCRATCH_PAD_2 0x5C 841#define MSGU_HOST_SCRATCH_PAD_3 0x60 842#define MSGU_HOST_SCRATCH_PAD_4 0x64 843#define MSGU_HOST_SCRATCH_PAD_5 0x68 844#define MSGU_HOST_SCRATCH_PAD_6 0x6C 845#define MSGU_HOST_SCRATCH_PAD_7 0x70 846#define MSGU_ODMR 0x74/* RevB */ 847 848/* bit definition for ODMR register */ 849#define ODMR_MASK_ALL 0xFFFFFFFF/* mask all 850 interrupt vector */ 851#define ODMR_CLEAR_ALL 0/* clear all 852 interrupt vector */ 853/* bit definition for ODCR register */ 854#define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all 855 interrupt vector*/ 856/* MSIX Interupts */ 857#define MSIX_TABLE_OFFSET 0x2000 858#define MSIX_TABLE_ELEMENT_SIZE 0x10 859#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC 860#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET) 861#define MSIX_INTERRUPT_DISABLE 0x1 862#define MSIX_INTERRUPT_ENABLE 0x0 863 864 865/* state definition for Scratch Pad1 register */ 866#define SCRATCH_PAD1_POR 0x00 /* power on reset state */ 867#define SCRATCH_PAD1_SFR 0x01 /* soft reset state */ 868#define SCRATCH_PAD1_ERR 0x02 /* error state */ 869#define SCRATCH_PAD1_RDY 0x03 /* ready state */ 870#define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */ 871#define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */ 872#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 873 Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */ 874#define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1 875 Reserved bit 3 to 9 */ 876 877 /* state definition for Scratch Pad2 register */ 878#define SCRATCH_PAD2_POR 0x00 /* power on state */ 879#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */ 880#define SCRATCH_PAD2_ERR 0x02 /* error state */ 881#define SCRATCH_PAD2_RDY 0x03 /* ready state */ 882#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/ 883#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */ 884#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2 885 Mask, bit1-0 State */ 886#define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1 887 Reserved bit 2 to 9 */ 888 889#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */ 890#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */ 891 892/* main configuration offset - byte offset */ 893#define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */ 894#define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */ 895#define MAIN_FW_REVISION 0x08/* DWORD 0x02 */ 896#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */ 897#define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */ 898#define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */ 899#define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */ 900#define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */ 901#define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */ 902#define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */ 903#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */ 904#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */ 905#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */ 906#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */ 907#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */ 908#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */ 909#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */ 910#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */ 911#define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */ 912#define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */ 913#define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */ 914#define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */ 915#define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */ 916#define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */ 917#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */ 918#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */ 919#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */ 920#define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */ 921#define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */ 922#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */ 923#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */ 924#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */ 925#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */ 926#define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */ 927#define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */ 928 929/* Gereral Status Table offset - byte offset */ 930#define GST_GSTLEN_MPIS_OFFSET 0x00 931#define GST_IQ_FREEZE_STATE0_OFFSET 0x04 932#define GST_IQ_FREEZE_STATE1_OFFSET 0x08 933#define GST_MSGUTCNT_OFFSET 0x0C 934#define GST_IOPTCNT_OFFSET 0x10 935#define GST_PHYSTATE_OFFSET 0x18 936#define GST_PHYSTATE0_OFFSET 0x18 937#define GST_PHYSTATE1_OFFSET 0x1C 938#define GST_PHYSTATE2_OFFSET 0x20 939#define GST_PHYSTATE3_OFFSET 0x24 940#define GST_PHYSTATE4_OFFSET 0x28 941#define GST_PHYSTATE5_OFFSET 0x2C 942#define GST_PHYSTATE6_OFFSET 0x30 943#define GST_PHYSTATE7_OFFSET 0x34 944#define GST_RERRINFO_OFFSET 0x44 945 946/* General Status Table - MPI state */ 947#define GST_MPI_STATE_UNINIT 0x00 948#define GST_MPI_STATE_INIT 0x01 949#define GST_MPI_STATE_TERMINATION 0x02 950#define GST_MPI_STATE_ERROR 0x03 951#define GST_MPI_STATE_MASK 0x07 952 953#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418 954#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418 955/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */ 956#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040 957#define PCIE_EVENT_INTERRUPT 0x003044 958#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048 959#define PCIE_ERROR_INTERRUPT 0x00304C 960/* signature definition for host scratch pad0 register */ 961#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd 962/* Signature for Soft Reset */ 963 964/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */ 965#define SPC_REG_RESET 0x000000/* reset register */ 966 967/* bit difination for SPC_RESET register */ 968#define SPC_REG_RESET_OSSP 0x00000001 969#define SPC_REG_RESET_RAAE 0x00000002 970#define SPC_REG_RESET_PCS_SPBC 0x00000004 971#define SPC_REG_RESET_PCS_IOP_SS 0x00000008 972#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010 973#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020 974#define SPC_REG_RESET_PCS_LM 0x00000040 975#define SPC_REG_RESET_PCS 0x00000080 976#define SPC_REG_RESET_GSM 0x00000100 977#define SPC_REG_RESET_DDR2 0x00010000 978#define SPC_REG_RESET_BDMA_CORE 0x00020000 979#define SPC_REG_RESET_BDMA_SXCBI 0x00040000 980#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000 981#define SPC_REG_RESET_PCIE_PWR 0x00100000 982#define SPC_REG_RESET_PCIE_SFT 0x00200000 983#define SPC_REG_RESET_PCS_SXCBI 0x00400000 984#define SPC_REG_RESET_LMS_SXCBI 0x00800000 985#define SPC_REG_RESET_PMIC_SXCBI 0x01000000 986#define SPC_REG_RESET_PMIC_CORE 0x02000000 987#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000 988#define SPC_REG_RESET_DEVICE 0x80000000 989 990/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */ 991#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258 992 993#define MBIC_AAP1_ADDR_BASE 0x060000 994#define MBIC_IOP_ADDR_BASE 0x070000 995#define GSM_ADDR_BASE 0x0700000 996/* Dynamic map through Bar4 - 0x00700000 */ 997#define GSM_CONFIG_RESET 0x00000000 998#define RAM_ECC_DB_ERR 0x00000018 999#define GSM_READ_ADDR_PARITY_INDIC 0x00000058 1000#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060 1001#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068 1002#define GSM_READ_ADDR_PARITY_CHECK 0x00000038 1003#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040 1004#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048 1005 1006#define RB6_ACCESS_REG 0x6A0000 1007#define HDAC_EXEC_CMD 0x0002 1008#define HDA_C_PA 0xcb 1009#define HDA_SEQ_ID_BITS 0x00ff0000 1010#define HDA_GSM_OFFSET_BITS 0x00FFFFFF 1011#define MBIC_AAP1_ADDR_BASE 0x060000 1012#define MBIC_IOP_ADDR_BASE 0x070000 1013#define GSM_ADDR_BASE 0x0700000 1014#define SPC_TOP_LEVEL_ADDR_BASE 0x000000 1015#define GSM_CONFIG_RESET_VALUE 0x00003b00 1016#define GPIO_ADDR_BASE 0x00090000 1017#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c 1018 1019/* RB6 offset */ 1020#define SPC_RB6_OFFSET 0x80C0 1021/* Magic number of soft reset for RB6 */ 1022#define RB6_MAGIC_NUMBER_RST 0x1234 1023 1024/* Device Register status */ 1025#define DEVREG_SUCCESS 0x00 1026#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01 1027#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 1028#define DEVREG_FAILURE_INVALID_PHY_ID 0x03 1029#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 1030#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 1031#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06 1032#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 1033 1034#define GSM_BASE 0x4F0000 1035#define SHIFT_REG_64K_MASK 0xffff0000 1036#define SHIFT_REG_BIT_SHIFT 8 1037#endif 1038 1039