1/*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/highmem.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spi/spi.h>
23#include <linux/gpio.h>
24
25#include "spi-dw.h"
26
27#ifdef CONFIG_DEBUG_FS
28#include <linux/debugfs.h>
29#endif
30
31/* Slave spi_dev related */
32struct chip_data {
33	u16 cr0;
34	u8 cs;			/* chip select pin */
35	u8 n_bytes;		/* current is a 1/2/4 byte op */
36	u8 tmode;		/* TR/TO/RO/EEPROM */
37	u8 type;		/* SPI/SSP/MicroWire */
38
39	u8 poll_mode;		/* 1 means use poll mode */
40
41	u32 dma_width;
42	u32 rx_threshold;
43	u32 tx_threshold;
44	u8 enable_dma;
45	u8 bits_per_word;
46	u16 clk_div;		/* baud rate divider */
47	u32 speed_hz;		/* baud rate */
48	void (*cs_control)(u32 command);
49};
50
51#ifdef CONFIG_DEBUG_FS
52#define SPI_REGS_BUFSIZE	1024
53static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
54		size_t count, loff_t *ppos)
55{
56	struct dw_spi *dws = file->private_data;
57	char *buf;
58	u32 len = 0;
59	ssize_t ret;
60
61	buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
62	if (!buf)
63		return 0;
64
65	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
66			"%s registers:\n", dev_name(&dws->master->dev));
67	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
68			"=================================\n");
69	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
70			"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
71	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
72			"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
73	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
74			"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
75	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
76			"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
77	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
78			"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
79	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
80			"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
81	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82			"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
83	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84			"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
85	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86			"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
87	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88			"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
89	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90			"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
91	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92			"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
93	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94			"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
95	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96			"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
97	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98			"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
99	len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100			"=================================\n");
101
102	ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
103	kfree(buf);
104	return ret;
105}
106
107static const struct file_operations dw_spi_regs_ops = {
108	.owner		= THIS_MODULE,
109	.open		= simple_open,
110	.read		= dw_spi_show_regs,
111	.llseek		= default_llseek,
112};
113
114static int dw_spi_debugfs_init(struct dw_spi *dws)
115{
116	dws->debugfs = debugfs_create_dir("dw_spi", NULL);
117	if (!dws->debugfs)
118		return -ENOMEM;
119
120	debugfs_create_file("registers", S_IFREG | S_IRUGO,
121		dws->debugfs, (void *)dws, &dw_spi_regs_ops);
122	return 0;
123}
124
125static void dw_spi_debugfs_remove(struct dw_spi *dws)
126{
127	debugfs_remove_recursive(dws->debugfs);
128}
129
130#else
131static inline int dw_spi_debugfs_init(struct dw_spi *dws)
132{
133	return 0;
134}
135
136static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
137{
138}
139#endif /* CONFIG_DEBUG_FS */
140
141static void dw_spi_set_cs(struct spi_device *spi, bool enable)
142{
143	struct dw_spi *dws = spi_master_get_devdata(spi->master);
144	struct chip_data *chip = spi_get_ctldata(spi);
145
146	/* Chip select logic is inverted from spi_set_cs() */
147	if (chip && chip->cs_control)
148		chip->cs_control(!enable);
149
150	if (!enable)
151		dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
152}
153
154/* Return the max entries we can fill into tx fifo */
155static inline u32 tx_max(struct dw_spi *dws)
156{
157	u32 tx_left, tx_room, rxtx_gap;
158
159	tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
160	tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
161
162	/*
163	 * Another concern is about the tx/rx mismatch, we
164	 * though to use (dws->fifo_len - rxflr - txflr) as
165	 * one maximum value for tx, but it doesn't cover the
166	 * data which is out of tx/rx fifo and inside the
167	 * shift registers. So a control from sw point of
168	 * view is taken.
169	 */
170	rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
171			/ dws->n_bytes;
172
173	return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
174}
175
176/* Return the max entries we should read out of rx fifo */
177static inline u32 rx_max(struct dw_spi *dws)
178{
179	u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
180
181	return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
182}
183
184static void dw_writer(struct dw_spi *dws)
185{
186	u32 max = tx_max(dws);
187	u16 txw = 0;
188
189	while (max--) {
190		/* Set the tx word if the transfer's original "tx" is not null */
191		if (dws->tx_end - dws->len) {
192			if (dws->n_bytes == 1)
193				txw = *(u8 *)(dws->tx);
194			else
195				txw = *(u16 *)(dws->tx);
196		}
197		dw_write_io_reg(dws, DW_SPI_DR, txw);
198		dws->tx += dws->n_bytes;
199	}
200}
201
202static void dw_reader(struct dw_spi *dws)
203{
204	u32 max = rx_max(dws);
205	u16 rxw;
206
207	while (max--) {
208		rxw = dw_read_io_reg(dws, DW_SPI_DR);
209		/* Care rx only if the transfer's original "rx" is not null */
210		if (dws->rx_end - dws->len) {
211			if (dws->n_bytes == 1)
212				*(u8 *)(dws->rx) = rxw;
213			else
214				*(u16 *)(dws->rx) = rxw;
215		}
216		dws->rx += dws->n_bytes;
217	}
218}
219
220static void int_error_stop(struct dw_spi *dws, const char *msg)
221{
222	spi_reset_chip(dws);
223
224	dev_err(&dws->master->dev, "%s\n", msg);
225	dws->master->cur_msg->status = -EIO;
226	spi_finalize_current_transfer(dws->master);
227}
228
229static irqreturn_t interrupt_transfer(struct dw_spi *dws)
230{
231	u16 irq_status = dw_readl(dws, DW_SPI_ISR);
232
233	/* Error handling */
234	if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
235		dw_readl(dws, DW_SPI_ICR);
236		int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
237		return IRQ_HANDLED;
238	}
239
240	dw_reader(dws);
241	if (dws->rx_end == dws->rx) {
242		spi_mask_intr(dws, SPI_INT_TXEI);
243		spi_finalize_current_transfer(dws->master);
244		return IRQ_HANDLED;
245	}
246	if (irq_status & SPI_INT_TXEI) {
247		spi_mask_intr(dws, SPI_INT_TXEI);
248		dw_writer(dws);
249		/* Enable TX irq always, it will be disabled when RX finished */
250		spi_umask_intr(dws, SPI_INT_TXEI);
251	}
252
253	return IRQ_HANDLED;
254}
255
256static irqreturn_t dw_spi_irq(int irq, void *dev_id)
257{
258	struct spi_master *master = dev_id;
259	struct dw_spi *dws = spi_master_get_devdata(master);
260	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
261
262	if (!irq_status)
263		return IRQ_NONE;
264
265	if (!master->cur_msg) {
266		spi_mask_intr(dws, SPI_INT_TXEI);
267		return IRQ_HANDLED;
268	}
269
270	return dws->transfer_handler(dws);
271}
272
273/* Must be called inside pump_transfers() */
274static int poll_transfer(struct dw_spi *dws)
275{
276	do {
277		dw_writer(dws);
278		dw_reader(dws);
279		cpu_relax();
280	} while (dws->rx_end > dws->rx);
281
282	return 0;
283}
284
285static int dw_spi_transfer_one(struct spi_master *master,
286		struct spi_device *spi, struct spi_transfer *transfer)
287{
288	struct dw_spi *dws = spi_master_get_devdata(master);
289	struct chip_data *chip = spi_get_ctldata(spi);
290	u8 imask = 0;
291	u16 txlevel = 0;
292	u16 clk_div = 0;
293	u32 speed = 0;
294	u32 cr0 = 0;
295	int ret;
296
297	dws->dma_mapped = 0;
298	dws->n_bytes = chip->n_bytes;
299	dws->dma_width = chip->dma_width;
300
301	dws->tx = (void *)transfer->tx_buf;
302	dws->tx_end = dws->tx + transfer->len;
303	dws->rx = transfer->rx_buf;
304	dws->rx_end = dws->rx + transfer->len;
305	dws->len = transfer->len;
306
307	spi_enable_chip(dws, 0);
308
309	cr0 = chip->cr0;
310
311	/* Handle per transfer options for bpw and speed */
312	if (transfer->speed_hz) {
313		speed = chip->speed_hz;
314
315		if ((transfer->speed_hz != speed) || !chip->clk_div) {
316			speed = transfer->speed_hz;
317
318			/* clk_div doesn't support odd number */
319			clk_div = (dws->max_freq / speed + 1) & 0xfffe;
320
321			chip->speed_hz = speed;
322			chip->clk_div = clk_div;
323
324			spi_set_clk(dws, chip->clk_div);
325		}
326	}
327	if (transfer->bits_per_word) {
328		if (transfer->bits_per_word == 8) {
329			dws->n_bytes = 1;
330			dws->dma_width = 1;
331		} else if (transfer->bits_per_word == 16) {
332			dws->n_bytes = 2;
333			dws->dma_width = 2;
334		}
335		cr0 = (transfer->bits_per_word - 1)
336			| (chip->type << SPI_FRF_OFFSET)
337			| (spi->mode << SPI_MODE_OFFSET)
338			| (chip->tmode << SPI_TMOD_OFFSET);
339	}
340
341	/*
342	 * Adjust transfer mode if necessary. Requires platform dependent
343	 * chipselect mechanism.
344	 */
345	if (chip->cs_control) {
346		if (dws->rx && dws->tx)
347			chip->tmode = SPI_TMOD_TR;
348		else if (dws->rx)
349			chip->tmode = SPI_TMOD_RO;
350		else
351			chip->tmode = SPI_TMOD_TO;
352
353		cr0 &= ~SPI_TMOD_MASK;
354		cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
355	}
356
357	dw_writel(dws, DW_SPI_CTRL0, cr0);
358
359	/* Check if current transfer is a DMA transaction */
360	if (master->can_dma && master->can_dma(master, spi, transfer))
361		dws->dma_mapped = master->cur_msg_mapped;
362
363	/* For poll mode just disable all interrupts */
364	spi_mask_intr(dws, 0xff);
365
366	/*
367	 * Interrupt mode
368	 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
369	 */
370	if (dws->dma_mapped) {
371		ret = dws->dma_ops->dma_setup(dws, transfer);
372		if (ret < 0) {
373			spi_enable_chip(dws, 1);
374			return ret;
375		}
376	} else if (!chip->poll_mode) {
377		txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
378		dw_writel(dws, DW_SPI_TXFLTR, txlevel);
379
380		/* Set the interrupt mask */
381		imask |= SPI_INT_TXEI | SPI_INT_TXOI |
382			 SPI_INT_RXUI | SPI_INT_RXOI;
383		spi_umask_intr(dws, imask);
384
385		dws->transfer_handler = interrupt_transfer;
386	}
387
388	spi_enable_chip(dws, 1);
389
390	if (dws->dma_mapped) {
391		ret = dws->dma_ops->dma_transfer(dws, transfer);
392		if (ret < 0)
393			return ret;
394	}
395
396	if (chip->poll_mode)
397		return poll_transfer(dws);
398
399	return 1;
400}
401
402static void dw_spi_handle_err(struct spi_master *master,
403		struct spi_message *msg)
404{
405	struct dw_spi *dws = spi_master_get_devdata(master);
406
407	if (dws->dma_mapped)
408		dws->dma_ops->dma_stop(dws);
409
410	spi_reset_chip(dws);
411}
412
413/* This may be called twice for each spi dev */
414static int dw_spi_setup(struct spi_device *spi)
415{
416	struct dw_spi_chip *chip_info = NULL;
417	struct chip_data *chip;
418	int ret;
419
420	/* Only alloc on first setup */
421	chip = spi_get_ctldata(spi);
422	if (!chip) {
423		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
424		if (!chip)
425			return -ENOMEM;
426		spi_set_ctldata(spi, chip);
427	}
428
429	/*
430	 * Protocol drivers may change the chip settings, so...
431	 * if chip_info exists, use it
432	 */
433	chip_info = spi->controller_data;
434
435	/* chip_info doesn't always exist */
436	if (chip_info) {
437		if (chip_info->cs_control)
438			chip->cs_control = chip_info->cs_control;
439
440		chip->poll_mode = chip_info->poll_mode;
441		chip->type = chip_info->type;
442
443		chip->rx_threshold = 0;
444		chip->tx_threshold = 0;
445	}
446
447	if (spi->bits_per_word == 8) {
448		chip->n_bytes = 1;
449		chip->dma_width = 1;
450	} else if (spi->bits_per_word == 16) {
451		chip->n_bytes = 2;
452		chip->dma_width = 2;
453	}
454	chip->bits_per_word = spi->bits_per_word;
455
456	if (!spi->max_speed_hz) {
457		dev_err(&spi->dev, "No max speed HZ parameter\n");
458		return -EINVAL;
459	}
460
461	chip->tmode = 0; /* Tx & Rx */
462	/* Default SPI mode is SCPOL = 0, SCPH = 0 */
463	chip->cr0 = (chip->bits_per_word - 1)
464			| (chip->type << SPI_FRF_OFFSET)
465			| (spi->mode  << SPI_MODE_OFFSET)
466			| (chip->tmode << SPI_TMOD_OFFSET);
467
468	if (spi->mode & SPI_LOOP)
469		chip->cr0 |= 1 << SPI_SRL_OFFSET;
470
471	if (gpio_is_valid(spi->cs_gpio)) {
472		ret = gpio_direction_output(spi->cs_gpio,
473				!(spi->mode & SPI_CS_HIGH));
474		if (ret)
475			return ret;
476	}
477
478	return 0;
479}
480
481static void dw_spi_cleanup(struct spi_device *spi)
482{
483	struct chip_data *chip = spi_get_ctldata(spi);
484
485	kfree(chip);
486	spi_set_ctldata(spi, NULL);
487}
488
489/* Restart the controller, disable all interrupts, clean rx fifo */
490static void spi_hw_init(struct device *dev, struct dw_spi *dws)
491{
492	spi_reset_chip(dws);
493
494	/*
495	 * Try to detect the FIFO depth if not set by interface driver,
496	 * the depth could be from 2 to 256 from HW spec
497	 */
498	if (!dws->fifo_len) {
499		u32 fifo;
500
501		for (fifo = 1; fifo < 256; fifo++) {
502			dw_writel(dws, DW_SPI_TXFLTR, fifo);
503			if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
504				break;
505		}
506		dw_writel(dws, DW_SPI_TXFLTR, 0);
507
508		dws->fifo_len = (fifo == 1) ? 0 : fifo;
509		dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
510	}
511}
512
513int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
514{
515	struct spi_master *master;
516	int ret;
517
518	BUG_ON(dws == NULL);
519
520	master = spi_alloc_master(dev, 0);
521	if (!master)
522		return -ENOMEM;
523
524	dws->master = master;
525	dws->type = SSI_MOTO_SPI;
526	dws->dma_inited = 0;
527	dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
528	snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
529
530	ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
531			dws->name, master);
532	if (ret < 0) {
533		dev_err(&master->dev, "can not get IRQ\n");
534		goto err_free_master;
535	}
536
537	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
538	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
539	master->bus_num = dws->bus_num;
540	master->num_chipselect = dws->num_cs;
541	master->setup = dw_spi_setup;
542	master->cleanup = dw_spi_cleanup;
543	master->set_cs = dw_spi_set_cs;
544	master->transfer_one = dw_spi_transfer_one;
545	master->handle_err = dw_spi_handle_err;
546	master->max_speed_hz = dws->max_freq;
547	master->dev.of_node = dev->of_node;
548
549	/* Basic HW init */
550	spi_hw_init(dev, dws);
551
552	if (dws->dma_ops && dws->dma_ops->dma_init) {
553		ret = dws->dma_ops->dma_init(dws);
554		if (ret) {
555			dev_warn(dev, "DMA init failed\n");
556			dws->dma_inited = 0;
557		} else {
558			master->can_dma = dws->dma_ops->can_dma;
559		}
560	}
561
562	spi_master_set_devdata(master, dws);
563	ret = devm_spi_register_master(dev, master);
564	if (ret) {
565		dev_err(&master->dev, "problem registering spi master\n");
566		goto err_dma_exit;
567	}
568
569	dw_spi_debugfs_init(dws);
570	return 0;
571
572err_dma_exit:
573	if (dws->dma_ops && dws->dma_ops->dma_exit)
574		dws->dma_ops->dma_exit(dws);
575	spi_enable_chip(dws, 0);
576err_free_master:
577	spi_master_put(master);
578	return ret;
579}
580EXPORT_SYMBOL_GPL(dw_spi_add_host);
581
582void dw_spi_remove_host(struct dw_spi *dws)
583{
584	if (!dws)
585		return;
586	dw_spi_debugfs_remove(dws);
587
588	if (dws->dma_ops && dws->dma_ops->dma_exit)
589		dws->dma_ops->dma_exit(dws);
590	spi_enable_chip(dws, 0);
591	/* Disable clk */
592	spi_set_clk(dws, 0);
593}
594EXPORT_SYMBOL_GPL(dw_spi_remove_host);
595
596int dw_spi_suspend_host(struct dw_spi *dws)
597{
598	int ret = 0;
599
600	ret = spi_master_suspend(dws->master);
601	if (ret)
602		return ret;
603	spi_enable_chip(dws, 0);
604	spi_set_clk(dws, 0);
605	return ret;
606}
607EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
608
609int dw_spi_resume_host(struct dw_spi *dws)
610{
611	int ret;
612
613	spi_hw_init(&dws->master->dev, dws);
614	ret = spi_master_resume(dws->master);
615	if (ret)
616		dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
617	return ret;
618}
619EXPORT_SYMBOL_GPL(dw_spi_resume_host);
620
621MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
622MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
623MODULE_LICENSE("GPL v2");
624