1/*
2 * Freescale SPI/eSPI controller driver library.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright 2010 Freescale Semiconductor, Inc.
7 * Copyright (C) 2006 Polycom, Inc.
8 *
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009  MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
12 *
13 * This program is free software; you can redistribute  it and/or modify it
14 * under  the terms of  the GNU General  Public License as published by the
15 * Free Software Foundation;  either version 2 of the  License, or (at your
16 * option) any later version.
17 */
18#ifndef __SPI_FSL_LIB_H__
19#define __SPI_FSL_LIB_H__
20
21#include <asm/io.h>
22
23/* SPI/eSPI Controller driver's private data. */
24struct mpc8xxx_spi {
25	struct device *dev;
26	void *reg_base;
27
28	/* rx & tx bufs from the spi_transfer */
29	const void *tx;
30	void *rx;
31#if IS_ENABLED(CONFIG_SPI_FSL_ESPI)
32	int len;
33#endif
34
35	int subblock;
36	struct spi_pram __iomem *pram;
37#ifdef CONFIG_FSL_SOC
38	struct cpm_buf_desc __iomem *tx_bd;
39	struct cpm_buf_desc __iomem *rx_bd;
40#endif
41
42	struct spi_transfer *xfer_in_progress;
43
44	/* dma addresses for CPM transfers */
45	dma_addr_t tx_dma;
46	dma_addr_t rx_dma;
47	bool map_tx_dma;
48	bool map_rx_dma;
49
50	dma_addr_t dma_dummy_tx;
51	dma_addr_t dma_dummy_rx;
52
53	/* functions to deal with different sized buffers */
54	void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
55	u32(*get_tx) (struct mpc8xxx_spi *);
56
57	/* hooks for different controller driver */
58	void (*spi_remove) (struct mpc8xxx_spi *mspi);
59
60	unsigned int count;
61	unsigned int irq;
62
63	unsigned nsecs;		/* (clock cycle time)/2 */
64
65	u32 spibrg;		/* SPIBRG input clock */
66	u32 rx_shift;		/* RX data reg shift when in qe mode */
67	u32 tx_shift;		/* TX data reg shift when in qe mode */
68
69	unsigned int flags;
70
71#if IS_ENABLED(CONFIG_SPI_FSL_SPI)
72	int type;
73	int native_chipselects;
74	u8 max_bits_per_word;
75
76	void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
77			   int bits_per_word, int msb_first);
78#endif
79
80	struct completion done;
81};
82
83struct spi_mpc8xxx_cs {
84	/* functions to deal with different sized buffers */
85	void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
86	u32 (*get_tx) (struct mpc8xxx_spi *);
87	u32 rx_shift;		/* RX data reg shift when in qe mode */
88	u32 tx_shift;		/* TX data reg shift when in qe mode */
89	u32 hw_mode;		/* Holds HW mode register settings */
90};
91
92static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
93{
94	iowrite32be(val, reg);
95}
96
97static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
98{
99	return ioread32be(reg);
100}
101
102struct mpc8xxx_spi_probe_info {
103	struct fsl_spi_platform_data pdata;
104	int *gpios;
105	bool *alow_flags;
106};
107
108extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
109extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
110extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
111extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
112extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
113extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
114
115extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
116		struct fsl_spi_platform_data *pdata);
117extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
118		struct spi_transfer *t, unsigned int len);
119extern const char *mpc8xxx_spi_strmode(unsigned int flags);
120extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
121		unsigned int irq);
122extern int mpc8xxx_spi_remove(struct device *dev);
123extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
124
125#endif /* __SPI_FSL_LIB_H__ */
126