1/* 2 * Copyright 2003 Digi International (www.digi.com) 3 * Scott H Kilau <Scott_Kilau at digi dot com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 13 * PURPOSE. See the GNU General Public License for more details. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/sched.h> /* For jiffies, task states */ 18#include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */ 19#include <linux/delay.h> /* For udelay */ 20#include <linux/io.h> /* For read[bwl]/write[bwl] */ 21#include <linux/serial.h> /* For struct async_serial */ 22#include <linux/serial_reg.h> /* For the various UART offsets */ 23#include <linux/pci.h> 24 25#include "dgnc_driver.h" /* Driver main header file */ 26#include "dgnc_cls.h" 27#include "dgnc_tty.h" 28 29static inline void cls_parse_isr(struct dgnc_board *brd, uint port); 30static inline void cls_clear_break(struct channel_t *ch, int force); 31static inline void cls_set_cts_flow_control(struct channel_t *ch); 32static inline void cls_set_rts_flow_control(struct channel_t *ch); 33static inline void cls_set_ixon_flow_control(struct channel_t *ch); 34static inline void cls_set_ixoff_flow_control(struct channel_t *ch); 35static inline void cls_set_no_output_flow_control(struct channel_t *ch); 36static inline void cls_set_no_input_flow_control(struct channel_t *ch); 37static void cls_parse_modem(struct channel_t *ch, unsigned char signals); 38static void cls_tasklet(unsigned long data); 39static void cls_vpd(struct dgnc_board *brd); 40static void cls_uart_init(struct channel_t *ch); 41static void cls_uart_off(struct channel_t *ch); 42static int cls_drain(struct tty_struct *tty, uint seconds); 43static void cls_param(struct tty_struct *tty); 44static void cls_assert_modem_signals(struct channel_t *ch); 45static void cls_flush_uart_write(struct channel_t *ch); 46static void cls_flush_uart_read(struct channel_t *ch); 47static void cls_disable_receiver(struct channel_t *ch); 48static void cls_enable_receiver(struct channel_t *ch); 49static void cls_send_break(struct channel_t *ch, int msecs); 50static void cls_send_start_character(struct channel_t *ch); 51static void cls_send_stop_character(struct channel_t *ch); 52static void cls_copy_data_from_uart_to_queue(struct channel_t *ch); 53static void cls_copy_data_from_queue_to_uart(struct channel_t *ch); 54static uint cls_get_uart_bytes_left(struct channel_t *ch); 55static void cls_send_immediate_char(struct channel_t *ch, unsigned char); 56static irqreturn_t cls_intr(int irq, void *voidbrd); 57 58struct board_ops dgnc_cls_ops = { 59 .tasklet = cls_tasklet, 60 .intr = cls_intr, 61 .uart_init = cls_uart_init, 62 .uart_off = cls_uart_off, 63 .drain = cls_drain, 64 .param = cls_param, 65 .vpd = cls_vpd, 66 .assert_modem_signals = cls_assert_modem_signals, 67 .flush_uart_write = cls_flush_uart_write, 68 .flush_uart_read = cls_flush_uart_read, 69 .disable_receiver = cls_disable_receiver, 70 .enable_receiver = cls_enable_receiver, 71 .send_break = cls_send_break, 72 .send_start_character = cls_send_start_character, 73 .send_stop_character = cls_send_stop_character, 74 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart, 75 .get_uart_bytes_left = cls_get_uart_bytes_left, 76 .send_immediate_char = cls_send_immediate_char 77}; 78 79static inline void cls_set_cts_flow_control(struct channel_t *ch) 80{ 81 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 82 unsigned char ier = readb(&ch->ch_cls_uart->ier); 83 unsigned char isr_fcr = 0; 84 85 /* 86 * The Enhanced Register Set may only be accessed when 87 * the Line Control Register is set to 0xBFh. 88 */ 89 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 90 91 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 92 93 /* Turn on CTS flow control, turn off IXON flow control */ 94 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR); 95 isr_fcr &= ~(UART_EXAR654_EFR_IXON); 96 97 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 98 99 /* Write old LCR value back out, which turns enhanced access off */ 100 writeb(lcrb, &ch->ch_cls_uart->lcr); 101 102 /* 103 * Enable interrupts for CTS flow, turn off interrupts for 104 * received XOFF chars 105 */ 106 ier |= (UART_EXAR654_IER_CTSDSR); 107 ier &= ~(UART_EXAR654_IER_XOFF); 108 writeb(ier, &ch->ch_cls_uart->ier); 109 110 /* Set the usual FIFO values */ 111 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 112 113 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | 114 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 115 &ch->ch_cls_uart->isr_fcr); 116 117 ch->ch_t_tlevel = 16; 118 119} 120 121static inline void cls_set_ixon_flow_control(struct channel_t *ch) 122{ 123 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 124 unsigned char ier = readb(&ch->ch_cls_uart->ier); 125 unsigned char isr_fcr = 0; 126 127 /* 128 * The Enhanced Register Set may only be accessed when 129 * the Line Control Register is set to 0xBFh. 130 */ 131 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 132 133 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 134 135 /* Turn on IXON flow control, turn off CTS flow control */ 136 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON); 137 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR); 138 139 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 140 141 /* Now set our current start/stop chars while in enhanced mode */ 142 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); 143 writeb(0, &ch->ch_cls_uart->lsr); 144 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); 145 writeb(0, &ch->ch_cls_uart->spr); 146 147 /* Write old LCR value back out, which turns enhanced access off */ 148 writeb(lcrb, &ch->ch_cls_uart->lcr); 149 150 /* 151 * Disable interrupts for CTS flow, turn on interrupts for 152 * received XOFF chars 153 */ 154 ier &= ~(UART_EXAR654_IER_CTSDSR); 155 ier |= (UART_EXAR654_IER_XOFF); 156 writeb(ier, &ch->ch_cls_uart->ier); 157 158 /* Set the usual FIFO values */ 159 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 160 161 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 162 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 163 &ch->ch_cls_uart->isr_fcr); 164 165} 166 167static inline void cls_set_no_output_flow_control(struct channel_t *ch) 168{ 169 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 170 unsigned char ier = readb(&ch->ch_cls_uart->ier); 171 unsigned char isr_fcr = 0; 172 173 /* 174 * The Enhanced Register Set may only be accessed when 175 * the Line Control Register is set to 0xBFh. 176 */ 177 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 178 179 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 180 181 /* Turn off IXON flow control, turn off CTS flow control */ 182 isr_fcr |= (UART_EXAR654_EFR_ECB); 183 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON); 184 185 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 186 187 /* Write old LCR value back out, which turns enhanced access off */ 188 writeb(lcrb, &ch->ch_cls_uart->lcr); 189 190 /* 191 * Disable interrupts for CTS flow, turn off interrupts for 192 * received XOFF chars 193 */ 194 ier &= ~(UART_EXAR654_IER_CTSDSR); 195 ier &= ~(UART_EXAR654_IER_XOFF); 196 writeb(ier, &ch->ch_cls_uart->ier); 197 198 /* Set the usual FIFO values */ 199 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 200 201 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 202 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 203 &ch->ch_cls_uart->isr_fcr); 204 205 ch->ch_r_watermark = 0; 206 ch->ch_t_tlevel = 16; 207 ch->ch_r_tlevel = 16; 208 209} 210 211static inline void cls_set_rts_flow_control(struct channel_t *ch) 212{ 213 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 214 unsigned char ier = readb(&ch->ch_cls_uart->ier); 215 unsigned char isr_fcr = 0; 216 217 /* 218 * The Enhanced Register Set may only be accessed when 219 * the Line Control Register is set to 0xBFh. 220 */ 221 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 222 223 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 224 225 /* Turn on RTS flow control, turn off IXOFF flow control */ 226 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR); 227 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF); 228 229 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 230 231 /* Write old LCR value back out, which turns enhanced access off */ 232 writeb(lcrb, &ch->ch_cls_uart->lcr); 233 234 /* Enable interrupts for RTS flow */ 235 ier |= (UART_EXAR654_IER_RTSDTR); 236 writeb(ier, &ch->ch_cls_uart->ier); 237 238 /* Set the usual FIFO values */ 239 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 240 241 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | 242 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 243 &ch->ch_cls_uart->isr_fcr); 244 245 ch->ch_r_watermark = 4; 246 ch->ch_r_tlevel = 8; 247 248} 249 250static inline void cls_set_ixoff_flow_control(struct channel_t *ch) 251{ 252 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 253 unsigned char ier = readb(&ch->ch_cls_uart->ier); 254 unsigned char isr_fcr = 0; 255 256 /* 257 * The Enhanced Register Set may only be accessed when 258 * the Line Control Register is set to 0xBFh. 259 */ 260 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 261 262 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 263 264 /* Turn on IXOFF flow control, turn off RTS flow control */ 265 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF); 266 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR); 267 268 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 269 270 /* Now set our current start/stop chars while in enhanced mode */ 271 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); 272 writeb(0, &ch->ch_cls_uart->lsr); 273 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); 274 writeb(0, &ch->ch_cls_uart->spr); 275 276 /* Write old LCR value back out, which turns enhanced access off */ 277 writeb(lcrb, &ch->ch_cls_uart->lcr); 278 279 /* Disable interrupts for RTS flow */ 280 ier &= ~(UART_EXAR654_IER_RTSDTR); 281 writeb(ier, &ch->ch_cls_uart->ier); 282 283 /* Set the usual FIFO values */ 284 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 285 286 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 287 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 288 &ch->ch_cls_uart->isr_fcr); 289 290} 291 292static inline void cls_set_no_input_flow_control(struct channel_t *ch) 293{ 294 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 295 unsigned char ier = readb(&ch->ch_cls_uart->ier); 296 unsigned char isr_fcr = 0; 297 298 /* 299 * The Enhanced Register Set may only be accessed when 300 * the Line Control Register is set to 0xBFh. 301 */ 302 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 303 304 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 305 306 /* Turn off IXOFF flow control, turn off RTS flow control */ 307 isr_fcr |= (UART_EXAR654_EFR_ECB); 308 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF); 309 310 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 311 312 /* Write old LCR value back out, which turns enhanced access off */ 313 writeb(lcrb, &ch->ch_cls_uart->lcr); 314 315 /* Disable interrupts for RTS flow */ 316 ier &= ~(UART_EXAR654_IER_RTSDTR); 317 writeb(ier, &ch->ch_cls_uart->ier); 318 319 /* Set the usual FIFO values */ 320 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); 321 322 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | 323 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), 324 &ch->ch_cls_uart->isr_fcr); 325 326 ch->ch_t_tlevel = 16; 327 ch->ch_r_tlevel = 16; 328 329} 330 331/* 332 * cls_clear_break. 333 * Determines whether its time to shut off break condition. 334 * 335 * No locks are assumed to be held when calling this function. 336 * channel lock is held and released in this function. 337 */ 338static inline void cls_clear_break(struct channel_t *ch, int force) 339{ 340 unsigned long flags; 341 342 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 343 return; 344 345 spin_lock_irqsave(&ch->ch_lock, flags); 346 347 /* Bail if we aren't currently sending a break. */ 348 if (!ch->ch_stop_sending_break) { 349 spin_unlock_irqrestore(&ch->ch_lock, flags); 350 return; 351 } 352 353 /* Turn break off, and unset some variables */ 354 if (ch->ch_flags & CH_BREAK_SENDING) { 355 if (time_after(jiffies, ch->ch_stop_sending_break) || force) { 356 unsigned char temp = readb(&ch->ch_cls_uart->lcr); 357 358 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); 359 ch->ch_flags &= ~(CH_BREAK_SENDING); 360 ch->ch_stop_sending_break = 0; 361 } 362 } 363 spin_unlock_irqrestore(&ch->ch_lock, flags); 364} 365 366/* Parse the ISR register for the specific port */ 367static inline void cls_parse_isr(struct dgnc_board *brd, uint port) 368{ 369 struct channel_t *ch; 370 unsigned char isr = 0; 371 unsigned long flags; 372 373 /* 374 * No need to verify board pointer, it was already 375 * verified in the interrupt routine. 376 */ 377 378 if (port >= brd->nasync) 379 return; 380 381 ch = brd->channels[port]; 382 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 383 return; 384 385 /* Here we try to figure out what caused the interrupt to happen */ 386 while (1) { 387 388 isr = readb(&ch->ch_cls_uart->isr_fcr); 389 390 /* Bail if no pending interrupt on port */ 391 if (isr & UART_IIR_NO_INT) 392 break; 393 394 /* Receive Interrupt pending */ 395 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) { 396 /* Read data from uart -> queue */ 397 brd->intr_rx++; 398 ch->ch_intr_rx++; 399 cls_copy_data_from_uart_to_queue(ch); 400 dgnc_check_queue_flow_control(ch); 401 } 402 403 /* Transmit Hold register empty pending */ 404 if (isr & UART_IIR_THRI) { 405 /* Transfer data (if any) from Write Queue -> UART. */ 406 spin_lock_irqsave(&ch->ch_lock, flags); 407 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 408 brd->intr_tx++; 409 ch->ch_intr_tx++; 410 spin_unlock_irqrestore(&ch->ch_lock, flags); 411 cls_copy_data_from_queue_to_uart(ch); 412 } 413 414 /* CTS/RTS change of state */ 415 if (isr & UART_IIR_CTSRTS) { 416 brd->intr_modem++; 417 ch->ch_intr_modem++; 418 /* 419 * Don't need to do anything, the cls_parse_modem 420 * below will grab the updated modem signals. 421 */ 422 } 423 424 /* Parse any modem signal changes */ 425 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); 426 } 427} 428 429/* 430 * cls_param() 431 * Send any/all changes to the line to the UART. 432 */ 433static void cls_param(struct tty_struct *tty) 434{ 435 unsigned char lcr = 0; 436 unsigned char uart_lcr = 0; 437 unsigned char ier = 0; 438 unsigned char uart_ier = 0; 439 uint baud = 9600; 440 int quot = 0; 441 struct dgnc_board *bd; 442 struct channel_t *ch; 443 struct un_t *un; 444 445 if (!tty || tty->magic != TTY_MAGIC) 446 return; 447 448 un = (struct un_t *) tty->driver_data; 449 if (!un || un->magic != DGNC_UNIT_MAGIC) 450 return; 451 452 ch = un->un_ch; 453 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 454 return; 455 456 bd = ch->ch_bd; 457 if (!bd || bd->magic != DGNC_BOARD_MAGIC) 458 return; 459 460 /* 461 * If baud rate is zero, flush queues, and set mval to drop DTR. 462 */ 463 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 464 ch->ch_r_head = 0; 465 ch->ch_r_tail = 0; 466 ch->ch_e_head = 0; 467 ch->ch_e_tail = 0; 468 ch->ch_w_head = 0; 469 ch->ch_w_tail = 0; 470 471 cls_flush_uart_write(ch); 472 cls_flush_uart_read(ch); 473 474 /* The baudrate is B0 so all modem lines are to be dropped. */ 475 ch->ch_flags |= (CH_BAUD0); 476 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 477 cls_assert_modem_signals(ch); 478 ch->ch_old_baud = 0; 479 return; 480 } else if (ch->ch_custom_speed) { 481 482 baud = ch->ch_custom_speed; 483 /* Handle transition from B0 */ 484 if (ch->ch_flags & CH_BAUD0) { 485 ch->ch_flags &= ~(CH_BAUD0); 486 487 /* 488 * Bring back up RTS and DTR... 489 * Also handle RTS or DTR toggle if set. 490 */ 491 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) 492 ch->ch_mostat |= (UART_MCR_RTS); 493 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) 494 ch->ch_mostat |= (UART_MCR_DTR); 495 } 496 497 } else { 498 int iindex = 0; 499 int jindex = 0; 500 501 ulong bauds[4][16] = { 502 { /* slowbaud */ 503 0, 50, 75, 110, 504 134, 150, 200, 300, 505 600, 1200, 1800, 2400, 506 4800, 9600, 19200, 38400 }, 507 { /* slowbaud & CBAUDEX */ 508 0, 57600, 115200, 230400, 509 460800, 150, 200, 921600, 510 600, 1200, 1800, 2400, 511 4800, 9600, 19200, 38400 }, 512 { /* fastbaud */ 513 0, 57600, 76800, 115200, 514 131657, 153600, 230400, 460800, 515 921600, 1200, 1800, 2400, 516 4800, 9600, 19200, 38400 }, 517 { /* fastbaud & CBAUDEX */ 518 0, 57600, 115200, 230400, 519 460800, 150, 200, 921600, 520 600, 1200, 1800, 2400, 521 4800, 9600, 19200, 38400 } 522 }; 523 524 /* 525 * Only use the TXPrint baud rate if the terminal 526 * unit is NOT open 527 */ 528 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && 529 (un->un_type == DGNC_PRINT)) 530 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff; 531 else 532 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff; 533 534 if (ch->ch_c_cflag & CBAUDEX) 535 iindex = 1; 536 537 if (ch->ch_digi.digi_flags & DIGI_FAST) 538 iindex += 2; 539 540 jindex = baud; 541 542 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && 543 (jindex < 16)) { 544 baud = bauds[iindex][jindex]; 545 } else { 546 baud = 0; 547 } 548 549 if (baud == 0) 550 baud = 9600; 551 552 /* Handle transition from B0 */ 553 if (ch->ch_flags & CH_BAUD0) { 554 ch->ch_flags &= ~(CH_BAUD0); 555 556 /* 557 * Bring back up RTS and DTR... 558 * Also handle RTS or DTR toggle if set. 559 */ 560 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) 561 ch->ch_mostat |= (UART_MCR_RTS); 562 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) 563 ch->ch_mostat |= (UART_MCR_DTR); 564 } 565 } 566 567 if (ch->ch_c_cflag & PARENB) 568 lcr |= UART_LCR_PARITY; 569 570 if (!(ch->ch_c_cflag & PARODD)) 571 lcr |= UART_LCR_EPAR; 572 573 /* 574 * Not all platforms support mark/space parity, 575 * so this will hide behind an ifdef. 576 */ 577#ifdef CMSPAR 578 if (ch->ch_c_cflag & CMSPAR) 579 lcr |= UART_LCR_SPAR; 580#endif 581 582 if (ch->ch_c_cflag & CSTOPB) 583 lcr |= UART_LCR_STOP; 584 585 switch (ch->ch_c_cflag & CSIZE) { 586 case CS5: 587 lcr |= UART_LCR_WLEN5; 588 break; 589 case CS6: 590 lcr |= UART_LCR_WLEN6; 591 break; 592 case CS7: 593 lcr |= UART_LCR_WLEN7; 594 break; 595 case CS8: 596 default: 597 lcr |= UART_LCR_WLEN8; 598 break; 599 } 600 601 uart_ier = readb(&ch->ch_cls_uart->ier); 602 ier = uart_ier; 603 uart_lcr = readb(&ch->ch_cls_uart->lcr); 604 605 if (baud == 0) 606 baud = 9600; 607 608 quot = ch->ch_bd->bd_dividend / baud; 609 610 if (quot != 0 && ch->ch_old_baud != baud) { 611 ch->ch_old_baud = baud; 612 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); 613 writeb((quot & 0xff), &ch->ch_cls_uart->txrx); 614 writeb((quot >> 8), &ch->ch_cls_uart->ier); 615 writeb(lcr, &ch->ch_cls_uart->lcr); 616 } 617 618 if (uart_lcr != lcr) 619 writeb(lcr, &ch->ch_cls_uart->lcr); 620 621 if (ch->ch_c_cflag & CREAD) 622 ier |= (UART_IER_RDI | UART_IER_RLSI); 623 else 624 ier &= ~(UART_IER_RDI | UART_IER_RLSI); 625 626 /* 627 * Have the UART interrupt on modem signal changes ONLY when 628 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set. 629 */ 630 if ((ch->ch_digi.digi_flags & CTSPACE) || 631 (ch->ch_digi.digi_flags & RTSPACE) || 632 (ch->ch_c_cflag & CRTSCTS) || 633 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) || 634 !(ch->ch_c_cflag & CLOCAL)) 635 ier |= UART_IER_MSI; 636 else 637 ier &= ~UART_IER_MSI; 638 639 ier |= UART_IER_THRI; 640 641 if (ier != uart_ier) 642 writeb(ier, &ch->ch_cls_uart->ier); 643 644 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) { 645 cls_set_cts_flow_control(ch); 646 } else if (ch->ch_c_iflag & IXON) { 647 /* 648 * If start/stop is set to disable, then we should 649 * disable flow control 650 */ 651 if ((ch->ch_startc == _POSIX_VDISABLE) || 652 (ch->ch_stopc == _POSIX_VDISABLE)) 653 cls_set_no_output_flow_control(ch); 654 else 655 cls_set_ixon_flow_control(ch); 656 } else { 657 cls_set_no_output_flow_control(ch); 658 } 659 660 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) { 661 cls_set_rts_flow_control(ch); 662 } else if (ch->ch_c_iflag & IXOFF) { 663 /* 664 * If start/stop is set to disable, then we should disable 665 * flow control 666 */ 667 if ((ch->ch_startc == _POSIX_VDISABLE) || 668 (ch->ch_stopc == _POSIX_VDISABLE)) 669 cls_set_no_input_flow_control(ch); 670 else 671 cls_set_ixoff_flow_control(ch); 672 } else { 673 cls_set_no_input_flow_control(ch); 674 } 675 676 cls_assert_modem_signals(ch); 677 678 /* Get current status of the modem signals now */ 679 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); 680} 681 682/* 683 * Our board poller function. 684 */ 685static void cls_tasklet(unsigned long data) 686{ 687 struct dgnc_board *bd = (struct dgnc_board *) data; 688 struct channel_t *ch; 689 unsigned long flags; 690 int i; 691 int state = 0; 692 int ports = 0; 693 694 if (!bd || bd->magic != DGNC_BOARD_MAGIC) 695 return; 696 697 /* Cache a couple board values */ 698 spin_lock_irqsave(&bd->bd_lock, flags); 699 state = bd->state; 700 ports = bd->nasync; 701 spin_unlock_irqrestore(&bd->bd_lock, flags); 702 703 /* 704 * Do NOT allow the interrupt routine to read the intr registers 705 * Until we release this lock. 706 */ 707 spin_lock_irqsave(&bd->bd_intr_lock, flags); 708 709 /* 710 * If board is ready, parse deeper to see if there is anything to do. 711 */ 712 if ((state == BOARD_READY) && (ports > 0)) { 713 714 /* Loop on each port */ 715 for (i = 0; i < ports; i++) { 716 ch = bd->channels[i]; 717 if (!ch) 718 continue; 719 720 /* 721 * NOTE: Remember you CANNOT hold any channel 722 * locks when calling input. 723 * During input processing, its possible we 724 * will call ld, which might do callbacks back 725 * into us. 726 */ 727 dgnc_input(ch); 728 729 /* 730 * Channel lock is grabbed and then released 731 * inside this routine. 732 */ 733 cls_copy_data_from_queue_to_uart(ch); 734 dgnc_wakeup_writes(ch); 735 736 /* 737 * Check carrier function. 738 */ 739 dgnc_carrier(ch); 740 741 /* 742 * The timing check of turning off the break is done 743 * inside clear_break() 744 */ 745 if (ch->ch_stop_sending_break) 746 cls_clear_break(ch, 0); 747 } 748 } 749 750 spin_unlock_irqrestore(&bd->bd_intr_lock, flags); 751 752} 753 754/* 755 * cls_intr() 756 * 757 * Classic specific interrupt handler. 758 */ 759static irqreturn_t cls_intr(int irq, void *voidbrd) 760{ 761 struct dgnc_board *brd = voidbrd; 762 uint i = 0; 763 unsigned char poll_reg; 764 unsigned long flags; 765 766 /* 767 * Check to make sure it didn't receive interrupt with a null board 768 * associated or a board pointer that wasn't ours. 769 */ 770 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 771 return IRQ_NONE; 772 773 spin_lock_irqsave(&brd->bd_intr_lock, flags); 774 775 brd->intr_count++; 776 777 /* 778 * Check the board's global interrupt offset to see if we 779 * we actually do have an interrupt pending for us. 780 */ 781 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET); 782 783 /* If 0, no interrupts pending */ 784 if (!poll_reg) { 785 spin_unlock_irqrestore(&brd->bd_intr_lock, flags); 786 return IRQ_NONE; 787 } 788 789 /* Parse each port to find out what caused the interrupt */ 790 for (i = 0; i < brd->nasync; i++) 791 cls_parse_isr(brd, i); 792 793 /* 794 * Schedule tasklet to more in-depth servicing at a better time. 795 */ 796 tasklet_schedule(&brd->helper_tasklet); 797 798 spin_unlock_irqrestore(&brd->bd_intr_lock, flags); 799 800 return IRQ_HANDLED; 801} 802 803static void cls_disable_receiver(struct channel_t *ch) 804{ 805 unsigned char tmp = readb(&ch->ch_cls_uart->ier); 806 807 tmp &= ~(UART_IER_RDI); 808 writeb(tmp, &ch->ch_cls_uart->ier); 809} 810 811static void cls_enable_receiver(struct channel_t *ch) 812{ 813 unsigned char tmp = readb(&ch->ch_cls_uart->ier); 814 815 tmp |= (UART_IER_RDI); 816 writeb(tmp, &ch->ch_cls_uart->ier); 817} 818 819static void cls_copy_data_from_uart_to_queue(struct channel_t *ch) 820{ 821 int qleft = 0; 822 unsigned char linestatus = 0; 823 unsigned char error_mask = 0; 824 ushort head; 825 ushort tail; 826 unsigned long flags; 827 828 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 829 return; 830 831 spin_lock_irqsave(&ch->ch_lock, flags); 832 833 /* cache head and tail of queue */ 834 head = ch->ch_r_head; 835 tail = ch->ch_r_tail; 836 837 /* Store how much space we have left in the queue */ 838 qleft = (tail - head - 1); 839 if (qleft < 0) 840 qleft += RQUEUEMASK + 1; 841 842 /* 843 * Create a mask to determine whether we should 844 * insert the character (if any) into our queue. 845 */ 846 if (ch->ch_c_iflag & IGNBRK) 847 error_mask |= UART_LSR_BI; 848 849 while (1) { 850 linestatus = readb(&ch->ch_cls_uart->lsr); 851 852 if (!(linestatus & (UART_LSR_DR))) 853 break; 854 855 /* 856 * Discard character if we are ignoring the error mask. 857 */ 858 if (linestatus & error_mask) { 859 unsigned char discard; 860 861 linestatus = 0; 862 discard = readb(&ch->ch_cls_uart->txrx); 863 continue; 864 } 865 866 /* 867 * If our queue is full, we have no choice but to drop some 868 * data. The assumption is that HWFLOW or SWFLOW should have 869 * stopped things way way before we got to this point. 870 * 871 * I decided that I wanted to ditch the oldest data first, 872 * I hope thats okay with everyone? Yes? Good. 873 */ 874 while (qleft < 1) { 875 tail = (tail + 1) & RQUEUEMASK; 876 ch->ch_r_tail = tail; 877 ch->ch_err_overrun++; 878 qleft++; 879 } 880 881 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE 882 | UART_LSR_FE); 883 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); 884 885 qleft--; 886 887 if (ch->ch_equeue[head] & UART_LSR_PE) 888 ch->ch_err_parity++; 889 if (ch->ch_equeue[head] & UART_LSR_BI) 890 ch->ch_err_break++; 891 if (ch->ch_equeue[head] & UART_LSR_FE) 892 ch->ch_err_frame++; 893 894 /* Add to, and flip head if needed */ 895 head = (head + 1) & RQUEUEMASK; 896 ch->ch_rxcount++; 897 } 898 899 /* 900 * Write new final heads to channel structure. 901 */ 902 ch->ch_r_head = head & RQUEUEMASK; 903 ch->ch_e_head = head & EQUEUEMASK; 904 905 spin_unlock_irqrestore(&ch->ch_lock, flags); 906} 907 908/* 909 * This function basically goes to sleep for secs, or until 910 * it gets signalled that the port has fully drained. 911 */ 912static int cls_drain(struct tty_struct *tty, uint seconds) 913{ 914 unsigned long flags; 915 struct channel_t *ch; 916 struct un_t *un; 917 918 if (!tty || tty->magic != TTY_MAGIC) 919 return -ENXIO; 920 921 un = (struct un_t *) tty->driver_data; 922 if (!un || un->magic != DGNC_UNIT_MAGIC) 923 return -ENXIO; 924 925 ch = un->un_ch; 926 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 927 return -ENXIO; 928 929 spin_lock_irqsave(&ch->ch_lock, flags); 930 un->un_flags |= UN_EMPTY; 931 spin_unlock_irqrestore(&ch->ch_lock, flags); 932 933 /* 934 * NOTE: Do something with time passed in. 935 */ 936 937 /* If ret is non-zero, user ctrl-c'ed us */ 938 939 return wait_event_interruptible(un->un_flags_wait, 940 ((un->un_flags & UN_EMPTY) == 0)); 941} 942 943/* Channel lock MUST be held before calling this function! */ 944static void cls_flush_uart_write(struct channel_t *ch) 945{ 946 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 947 return; 948 949 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), 950 &ch->ch_cls_uart->isr_fcr); 951 udelay(10); 952 953 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 954} 955 956/* Channel lock MUST be held before calling this function! */ 957static void cls_flush_uart_read(struct channel_t *ch) 958{ 959 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 960 return; 961 962 /* 963 * For complete POSIX compatibility, we should be purging the 964 * read FIFO in the UART here. 965 * 966 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also 967 * incorrectly flushes write data as well as just basically trashing the 968 * FIFO. 969 * 970 * Presumably, this is a bug in this UART. 971 */ 972 973 udelay(10); 974} 975 976static void cls_copy_data_from_queue_to_uart(struct channel_t *ch) 977{ 978 ushort head; 979 ushort tail; 980 int n; 981 int qlen; 982 uint len_written = 0; 983 unsigned long flags; 984 985 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 986 return; 987 988 spin_lock_irqsave(&ch->ch_lock, flags); 989 990 /* No data to write to the UART */ 991 if (ch->ch_w_tail == ch->ch_w_head) 992 goto exit_unlock; 993 994 /* If port is "stopped", don't send any data to the UART */ 995 if ((ch->ch_flags & CH_FORCED_STOP) || 996 (ch->ch_flags & CH_BREAK_SENDING)) 997 goto exit_unlock; 998 999 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 1000 goto exit_unlock; 1001 1002 n = 32; 1003 1004 /* cache head and tail of queue */ 1005 head = ch->ch_w_head & WQUEUEMASK; 1006 tail = ch->ch_w_tail & WQUEUEMASK; 1007 qlen = (head - tail) & WQUEUEMASK; 1008 1009 /* Find minimum of the FIFO space, versus queue length */ 1010 n = min(n, qlen); 1011 1012 while (n > 0) { 1013 1014 /* 1015 * If RTS Toggle mode is on, turn on RTS now if not already set, 1016 * and make sure we get an event when the data transfer has 1017 * completed. 1018 */ 1019 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) { 1020 if (!(ch->ch_mostat & UART_MCR_RTS)) { 1021 ch->ch_mostat |= (UART_MCR_RTS); 1022 cls_assert_modem_signals(ch); 1023 } 1024 ch->ch_tun.un_flags |= (UN_EMPTY); 1025 } 1026 1027 /* 1028 * If DTR Toggle mode is on, turn on DTR now if not already set, 1029 * and make sure we get an event when the data transfer has 1030 * completed. 1031 */ 1032 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) { 1033 if (!(ch->ch_mostat & UART_MCR_DTR)) { 1034 ch->ch_mostat |= (UART_MCR_DTR); 1035 cls_assert_modem_signals(ch); 1036 } 1037 ch->ch_tun.un_flags |= (UN_EMPTY); 1038 } 1039 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx); 1040 ch->ch_w_tail++; 1041 ch->ch_w_tail &= WQUEUEMASK; 1042 ch->ch_txcount++; 1043 len_written++; 1044 n--; 1045 } 1046 1047 if (len_written > 0) 1048 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1049 1050exit_unlock: 1051 spin_unlock_irqrestore(&ch->ch_lock, flags); 1052} 1053 1054static void cls_parse_modem(struct channel_t *ch, unsigned char signals) 1055{ 1056 unsigned char msignals = signals; 1057 unsigned long flags; 1058 1059 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1060 return; 1061 1062 /* 1063 * Do altpin switching. Altpin switches DCD and DSR. 1064 * This prolly breaks DSRPACE, so we should be more clever here. 1065 */ 1066 spin_lock_irqsave(&ch->ch_lock, flags); 1067 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) { 1068 unsigned char mswap = signals; 1069 1070 if (mswap & UART_MSR_DDCD) { 1071 msignals &= ~UART_MSR_DDCD; 1072 msignals |= UART_MSR_DDSR; 1073 } 1074 if (mswap & UART_MSR_DDSR) { 1075 msignals &= ~UART_MSR_DDSR; 1076 msignals |= UART_MSR_DDCD; 1077 } 1078 if (mswap & UART_MSR_DCD) { 1079 msignals &= ~UART_MSR_DCD; 1080 msignals |= UART_MSR_DSR; 1081 } 1082 if (mswap & UART_MSR_DSR) { 1083 msignals &= ~UART_MSR_DSR; 1084 msignals |= UART_MSR_DCD; 1085 } 1086 } 1087 spin_unlock_irqrestore(&ch->ch_lock, flags); 1088 1089 /* 1090 * Scrub off lower bits. They signify delta's, which I don't 1091 * care about 1092 */ 1093 signals &= 0xf0; 1094 1095 spin_lock_irqsave(&ch->ch_lock, flags); 1096 if (msignals & UART_MSR_DCD) 1097 ch->ch_mistat |= UART_MSR_DCD; 1098 else 1099 ch->ch_mistat &= ~UART_MSR_DCD; 1100 1101 if (msignals & UART_MSR_DSR) 1102 ch->ch_mistat |= UART_MSR_DSR; 1103 else 1104 ch->ch_mistat &= ~UART_MSR_DSR; 1105 1106 if (msignals & UART_MSR_RI) 1107 ch->ch_mistat |= UART_MSR_RI; 1108 else 1109 ch->ch_mistat &= ~UART_MSR_RI; 1110 1111 if (msignals & UART_MSR_CTS) 1112 ch->ch_mistat |= UART_MSR_CTS; 1113 else 1114 ch->ch_mistat &= ~UART_MSR_CTS; 1115 spin_unlock_irqrestore(&ch->ch_lock, flags); 1116} 1117 1118/* Make the UART raise any of the output signals we want up */ 1119static void cls_assert_modem_signals(struct channel_t *ch) 1120{ 1121 unsigned char out; 1122 1123 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1124 return; 1125 1126 out = ch->ch_mostat; 1127 1128 if (ch->ch_flags & CH_LOOPBACK) 1129 out |= UART_MCR_LOOP; 1130 1131 writeb(out, &ch->ch_cls_uart->mcr); 1132 1133 /* Give time for the UART to actually drop the signals */ 1134 udelay(10); 1135} 1136 1137static void cls_send_start_character(struct channel_t *ch) 1138{ 1139 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1140 return; 1141 1142 if (ch->ch_startc != _POSIX_VDISABLE) { 1143 ch->ch_xon_sends++; 1144 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); 1145 } 1146} 1147 1148static void cls_send_stop_character(struct channel_t *ch) 1149{ 1150 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1151 return; 1152 1153 if (ch->ch_stopc != _POSIX_VDISABLE) { 1154 ch->ch_xoff_sends++; 1155 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); 1156 } 1157} 1158 1159/* Inits UART */ 1160static void cls_uart_init(struct channel_t *ch) 1161{ 1162 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); 1163 unsigned char isr_fcr = 0; 1164 1165 writeb(0, &ch->ch_cls_uart->ier); 1166 1167 /* 1168 * The Enhanced Register Set may only be accessed when 1169 * the Line Control Register is set to 0xBFh. 1170 */ 1171 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); 1172 1173 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); 1174 1175 /* Turn on Enhanced/Extended controls */ 1176 isr_fcr |= (UART_EXAR654_EFR_ECB); 1177 1178 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); 1179 1180 /* Write old LCR value back out, which turns enhanced access off */ 1181 writeb(lcrb, &ch->ch_cls_uart->lcr); 1182 1183 /* Clear out UART and FIFO */ 1184 readb(&ch->ch_cls_uart->txrx); 1185 1186 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), 1187 &ch->ch_cls_uart->isr_fcr); 1188 udelay(10); 1189 1190 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1191 1192 readb(&ch->ch_cls_uart->lsr); 1193 readb(&ch->ch_cls_uart->msr); 1194} 1195 1196/* 1197 * Turns off UART. 1198 */ 1199static void cls_uart_off(struct channel_t *ch) 1200{ 1201 writeb(0, &ch->ch_cls_uart->ier); 1202} 1203 1204/* 1205 * cls_get_uarts_bytes_left. 1206 * Returns 0 is nothing left in the FIFO, returns 1 otherwise. 1207 * 1208 * The channel lock MUST be held by the calling function. 1209 */ 1210static uint cls_get_uart_bytes_left(struct channel_t *ch) 1211{ 1212 unsigned char left = 0; 1213 unsigned char lsr = 0; 1214 1215 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1216 return 0; 1217 1218 lsr = readb(&ch->ch_cls_uart->lsr); 1219 1220 /* Determine whether the Transmitter is empty or not */ 1221 if (!(lsr & UART_LSR_TEMT)) { 1222 if (ch->ch_flags & CH_TX_FIFO_EMPTY) 1223 tasklet_schedule(&ch->ch_bd->helper_tasklet); 1224 left = 1; 1225 } else { 1226 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1227 left = 0; 1228 } 1229 1230 return left; 1231} 1232 1233/* 1234 * cls_send_break. 1235 * Starts sending a break thru the UART. 1236 * 1237 * The channel lock MUST be held by the calling function. 1238 */ 1239static void cls_send_break(struct channel_t *ch, int msecs) 1240{ 1241 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1242 return; 1243 1244 /* 1245 * If we receive a time of 0, this means turn off the break. 1246 */ 1247 if (msecs == 0) { 1248 /* Turn break off, and unset some variables */ 1249 if (ch->ch_flags & CH_BREAK_SENDING) { 1250 unsigned char temp = readb(&ch->ch_cls_uart->lcr); 1251 1252 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); 1253 ch->ch_flags &= ~(CH_BREAK_SENDING); 1254 ch->ch_stop_sending_break = 0; 1255 } 1256 return; 1257 } 1258 1259 /* 1260 * Set the time we should stop sending the break. 1261 * If we are already sending a break, toss away the existing 1262 * time to stop, and use this new value instead. 1263 */ 1264 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs); 1265 1266 /* Tell the UART to start sending the break */ 1267 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1268 unsigned char temp = readb(&ch->ch_cls_uart->lcr); 1269 1270 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); 1271 ch->ch_flags |= (CH_BREAK_SENDING); 1272 } 1273} 1274 1275/* 1276 * cls_send_immediate_char. 1277 * Sends a specific character as soon as possible to the UART, 1278 * jumping over any bytes that might be in the write queue. 1279 * 1280 * The channel lock MUST be held by the calling function. 1281 */ 1282static void cls_send_immediate_char(struct channel_t *ch, unsigned char c) 1283{ 1284 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1285 return; 1286 1287 writeb(c, &ch->ch_cls_uart->txrx); 1288} 1289 1290static void cls_vpd(struct dgnc_board *brd) 1291{ 1292 ulong vpdbase; /* Start of io base of the card */ 1293 u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */ 1294 int i = 0; 1295 1296 vpdbase = pci_resource_start(brd->pdev, 3); 1297 1298 /* No VPD */ 1299 if (!vpdbase) 1300 return; 1301 1302 re_map_vpdbase = ioremap(vpdbase, 0x400); 1303 1304 if (!re_map_vpdbase) 1305 return; 1306 1307 /* Store the VPD into our buffer */ 1308 for (i = 0; i < 0x40; i++) { 1309 brd->vpd[i] = readb(re_map_vpdbase + i); 1310 pr_info("%x ", brd->vpd[i]); 1311 } 1312 pr_info("\n"); 1313 1314 if (re_map_vpdbase) 1315 iounmap(re_map_vpdbase); 1316} 1317