1/* 2 * FB driver for the ILI9320 LCD Controller 3 * 4 * Copyright (C) 2013 Noralf Tronnes 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21#include <linux/module.h> 22#include <linux/kernel.h> 23#include <linux/init.h> 24#include <linux/gpio.h> 25#include <linux/spi/spi.h> 26#include <linux/delay.h> 27 28#include "fbtft.h" 29 30#define DRVNAME "fb_ili9320" 31#define WIDTH 240 32#define HEIGHT 320 33#define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \ 34 "07 08 4 7 5 1 2 0 7 7" 35 36 37static unsigned read_devicecode(struct fbtft_par *par) 38{ 39 int ret; 40 u8 rxbuf[8] = {0, }; 41 42 write_reg(par, 0x0000); 43 ret = par->fbtftops.read(par, rxbuf, 4); 44 return (rxbuf[2] << 8) | rxbuf[3]; 45} 46 47static int init_display(struct fbtft_par *par) 48{ 49 unsigned devcode; 50 51 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); 52 53 par->fbtftops.reset(par); 54 55 devcode = read_devicecode(par); 56 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n", 57 devcode); 58 if ((devcode != 0x0000) && (devcode != 0x9320)) 59 dev_warn(par->info->device, 60 "Unrecognized Device code: 0x%04X (expected 0x9320)\n", 61 devcode); 62 63 /* Initialization sequence from ILI9320 Application Notes */ 64 65 /* *********** Start Initial Sequence ********* */ 66 write_reg(par, 0x00E5, 0x8000); /* Set the Vcore voltage and this setting is must. */ 67 write_reg(par, 0x0000, 0x0001); /* Start internal OSC. */ 68 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ 69 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ 70 write_reg(par, 0x0004, 0x0000); /* Resize register */ 71 write_reg(par, 0x0008, 0x0202); /* set the back and front porch */ 72 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ 73 write_reg(par, 0x000A, 0x0000); /* FMARK function */ 74 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ 75 write_reg(par, 0x000D, 0x0000); /* Frame marker Position */ 76 write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */ 77 78 /* ***********Power On sequence *************** */ 79 write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ 80 write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ 81 write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */ 82 write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ 83 mdelay(200); /* Dis-charge capacitor power voltage */ 84 write_reg(par, 0x0010, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ 85 write_reg(par, 0x0011, 0x0031); /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */ 86 mdelay(50); 87 write_reg(par, 0x0012, 0x0138); /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */ 88 mdelay(50); 89 write_reg(par, 0x0013, 0x1800); /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */ 90 write_reg(par, 0x0029, 0x0008); /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */ 91 mdelay(50); 92 write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */ 93 write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */ 94 95 /* ------------------ Set GRAM area --------------- */ 96 write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ 97 write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */ 98 write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ 99 write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ 100 write_reg(par, 0x0060, 0x2700); /* Gate Scan Line */ 101 write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */ 102 write_reg(par, 0x006A, 0x0000); /* set scrolling line */ 103 104 /* -------------- Partial Display Control --------- */ 105 write_reg(par, 0x0080, 0x0000); 106 write_reg(par, 0x0081, 0x0000); 107 write_reg(par, 0x0082, 0x0000); 108 write_reg(par, 0x0083, 0x0000); 109 write_reg(par, 0x0084, 0x0000); 110 write_reg(par, 0x0085, 0x0000); 111 112 /* -------------- Panel Control ------------------- */ 113 write_reg(par, 0x0090, 0x0010); 114 write_reg(par, 0x0092, 0x0000); 115 write_reg(par, 0x0093, 0x0003); 116 write_reg(par, 0x0095, 0x0110); 117 write_reg(par, 0x0097, 0x0000); 118 write_reg(par, 0x0098, 0x0000); 119 write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */ 120 121 return 0; 122} 123 124static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 125{ 126 fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, 127 "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye); 128 129 switch (par->info->var.rotate) { 130 /* R20h = Horizontal GRAM Start Address */ 131 /* R21h = Vertical GRAM Start Address */ 132 case 0: 133 write_reg(par, 0x0020, xs); 134 write_reg(par, 0x0021, ys); 135 break; 136 case 180: 137 write_reg(par, 0x0020, WIDTH - 1 - xs); 138 write_reg(par, 0x0021, HEIGHT - 1 - ys); 139 break; 140 case 270: 141 write_reg(par, 0x0020, WIDTH - 1 - ys); 142 write_reg(par, 0x0021, xs); 143 break; 144 case 90: 145 write_reg(par, 0x0020, ys); 146 write_reg(par, 0x0021, HEIGHT - 1 - xs); 147 break; 148 } 149 write_reg(par, 0x0022); /* Write Data to GRAM */ 150} 151 152static int set_var(struct fbtft_par *par) 153{ 154 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); 155 156 switch (par->info->var.rotate) { 157 case 0: 158 write_reg(par, 0x3, (par->bgr << 12) | 0x30); 159 break; 160 case 270: 161 write_reg(par, 0x3, (par->bgr << 12) | 0x28); 162 break; 163 case 180: 164 write_reg(par, 0x3, (par->bgr << 12) | 0x00); 165 break; 166 case 90: 167 write_reg(par, 0x3, (par->bgr << 12) | 0x18); 168 break; 169 } 170 return 0; 171} 172 173/* 174 Gamma string format: 175 VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5 176 VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5 177*/ 178#define CURVE(num, idx) curves[num*par->gamma.num_values + idx] 179static int set_gamma(struct fbtft_par *par, unsigned long *curves) 180{ 181 unsigned long mask[] = { 182 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 183 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 184 }; 185 int i, j; 186 187 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); 188 189 /* apply mask */ 190 for (i = 0; i < 2; i++) 191 for (j = 0; j < 10; j++) 192 CURVE(i, j) &= mask[i*par->gamma.num_values + j]; 193 194 write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); 195 write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); 196 write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8)); 197 write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2)); 198 write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0)); 199 200 write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4)); 201 write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6)); 202 write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8)); 203 write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2)); 204 write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0)); 205 206 return 0; 207} 208#undef CURVE 209 210 211static struct fbtft_display display = { 212 .regwidth = 16, 213 .width = WIDTH, 214 .height = HEIGHT, 215 .gamma_num = 2, 216 .gamma_len = 10, 217 .gamma = DEFAULT_GAMMA, 218 .fbtftops = { 219 .init_display = init_display, 220 .set_addr_win = set_addr_win, 221 .set_var = set_var, 222 .set_gamma = set_gamma, 223 }, 224}; 225FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display); 226 227MODULE_ALIAS("spi:" DRVNAME); 228MODULE_ALIAS("platform:" DRVNAME); 229MODULE_ALIAS("spi:ili9320"); 230MODULE_ALIAS("platform:ili9320"); 231 232MODULE_DESCRIPTION("FB driver for the ILI9320 LCD Controller"); 233MODULE_AUTHOR("Noralf Tronnes"); 234MODULE_LICENSE("GPL"); 235