1/* 2 * AD7280A Lithium Ion Battery Monitoring System 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9#include <linux/device.h> 10#include <linux/kernel.h> 11#include <linux/slab.h> 12#include <linux/sysfs.h> 13#include <linux/spi/spi.h> 14#include <linux/err.h> 15#include <linux/delay.h> 16#include <linux/interrupt.h> 17#include <linux/module.h> 18 19#include <linux/iio/iio.h> 20#include <linux/iio/sysfs.h> 21#include <linux/iio/events.h> 22 23#include "ad7280a.h" 24 25/* Registers */ 26#define AD7280A_CELL_VOLTAGE_1 0x0 /* D11 to D0, Read only */ 27#define AD7280A_CELL_VOLTAGE_2 0x1 /* D11 to D0, Read only */ 28#define AD7280A_CELL_VOLTAGE_3 0x2 /* D11 to D0, Read only */ 29#define AD7280A_CELL_VOLTAGE_4 0x3 /* D11 to D0, Read only */ 30#define AD7280A_CELL_VOLTAGE_5 0x4 /* D11 to D0, Read only */ 31#define AD7280A_CELL_VOLTAGE_6 0x5 /* D11 to D0, Read only */ 32#define AD7280A_AUX_ADC_1 0x6 /* D11 to D0, Read only */ 33#define AD7280A_AUX_ADC_2 0x7 /* D11 to D0, Read only */ 34#define AD7280A_AUX_ADC_3 0x8 /* D11 to D0, Read only */ 35#define AD7280A_AUX_ADC_4 0x9 /* D11 to D0, Read only */ 36#define AD7280A_AUX_ADC_5 0xA /* D11 to D0, Read only */ 37#define AD7280A_AUX_ADC_6 0xB /* D11 to D0, Read only */ 38#define AD7280A_SELF_TEST 0xC /* D11 to D0, Read only */ 39#define AD7280A_CONTROL_HB 0xD /* D15 to D8, Read/write */ 40#define AD7280A_CONTROL_LB 0xE /* D7 to D0, Read/write */ 41#define AD7280A_CELL_OVERVOLTAGE 0xF /* D7 to D0, Read/write */ 42#define AD7280A_CELL_UNDERVOLTAGE 0x10 /* D7 to D0, Read/write */ 43#define AD7280A_AUX_ADC_OVERVOLTAGE 0x11 /* D7 to D0, Read/write */ 44#define AD7280A_AUX_ADC_UNDERVOLTAGE 0x12 /* D7 to D0, Read/write */ 45#define AD7280A_ALERT 0x13 /* D7 to D0, Read/write */ 46#define AD7280A_CELL_BALANCE 0x14 /* D7 to D0, Read/write */ 47#define AD7280A_CB1_TIMER 0x15 /* D7 to D0, Read/write */ 48#define AD7280A_CB2_TIMER 0x16 /* D7 to D0, Read/write */ 49#define AD7280A_CB3_TIMER 0x17 /* D7 to D0, Read/write */ 50#define AD7280A_CB4_TIMER 0x18 /* D7 to D0, Read/write */ 51#define AD7280A_CB5_TIMER 0x19 /* D7 to D0, Read/write */ 52#define AD7280A_CB6_TIMER 0x1A /* D7 to D0, Read/write */ 53#define AD7280A_PD_TIMER 0x1B /* D7 to D0, Read/write */ 54#define AD7280A_READ 0x1C /* D7 to D0, Read/write */ 55#define AD7280A_CNVST_CONTROL 0x1D /* D7 to D0, Read/write */ 56 57/* Bits and Masks */ 58#define AD7280A_CTRL_HB_CONV_INPUT_ALL 0 59#define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4 BIT(6) 60#define AD7280A_CTRL_HB_CONV_INPUT_6CELL BIT(7) 61#define AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST (BIT(7) | BIT(6)) 62#define AD7280A_CTRL_HB_CONV_RES_READ_ALL 0 63#define AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4 BIT(4) 64#define AD7280A_CTRL_HB_CONV_RES_READ_6CELL BIT(5) 65#define AD7280A_CTRL_HB_CONV_RES_READ_NO (BIT(5) | BIT(4)) 66#define AD7280A_CTRL_HB_CONV_START_CNVST 0 67#define AD7280A_CTRL_HB_CONV_START_CS BIT(3) 68#define AD7280A_CTRL_HB_CONV_AVG_DIS 0 69#define AD7280A_CTRL_HB_CONV_AVG_2 BIT(1) 70#define AD7280A_CTRL_HB_CONV_AVG_4 BIT(2) 71#define AD7280A_CTRL_HB_CONV_AVG_8 (BIT(2) | BIT(1)) 72#define AD7280A_CTRL_HB_CONV_AVG(x) ((x) << 1) 73#define AD7280A_CTRL_HB_PWRDN_SW BIT(0) 74 75#define AD7280A_CTRL_LB_SWRST BIT(7) 76#define AD7280A_CTRL_LB_ACQ_TIME_400ns 0 77#define AD7280A_CTRL_LB_ACQ_TIME_800ns BIT(5) 78#define AD7280A_CTRL_LB_ACQ_TIME_1200ns BIT(6) 79#define AD7280A_CTRL_LB_ACQ_TIME_1600ns (BIT(6) | BIT(5)) 80#define AD7280A_CTRL_LB_ACQ_TIME(x) ((x) << 5) 81#define AD7280A_CTRL_LB_MUST_SET BIT(4) 82#define AD7280A_CTRL_LB_THERMISTOR_EN BIT(3) 83#define AD7280A_CTRL_LB_LOCK_DEV_ADDR BIT(2) 84#define AD7280A_CTRL_LB_INC_DEV_ADDR BIT(1) 85#define AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN BIT(0) 86 87#define AD7280A_ALERT_GEN_STATIC_HIGH BIT(6) 88#define AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN (BIT(7) | BIT(6)) 89 90#define AD7280A_ALL_CELLS (0xAD << 16) 91 92#define AD7280A_MAX_SPI_CLK_Hz 700000 /* < 1MHz */ 93#define AD7280A_MAX_CHAIN 8 94#define AD7280A_CELLS_PER_DEV 6 95#define AD7280A_BITS 12 96#define AD7280A_NUM_CH (AD7280A_AUX_ADC_6 - \ 97 AD7280A_CELL_VOLTAGE_1 + 1) 98 99#define AD7280A_DEVADDR_MASTER 0 100#define AD7280A_DEVADDR_ALL 0x1F 101/* 5-bit device address is sent LSB first */ 102#define AD7280A_DEVADDR(addr) (((addr & 0x1) << 4) | ((addr & 0x2) << 3) | \ 103 (addr & 0x4) | ((addr & 0x8) >> 3) | \ 104 ((addr & 0x10) >> 4)) 105 106/* During a read a valid write is mandatory. 107 * So writing to the highest available address (Address 0x1F) 108 * and setting the address all parts bit to 0 is recommended 109 * So the TXVAL is AD7280A_DEVADDR_ALL + CRC 110 */ 111#define AD7280A_READ_TXVAL 0xF800030A 112 113/* 114 * AD7280 CRC 115 * 116 * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F 117 */ 118#define POLYNOM 0x2F 119#define POLYNOM_ORDER 8 120#define HIGHBIT (1 << (POLYNOM_ORDER - 1)) 121 122struct ad7280_state { 123 struct spi_device *spi; 124 struct iio_chan_spec *channels; 125 struct iio_dev_attr *iio_attr; 126 int slave_num; 127 int scan_cnt; 128 int readback_delay_us; 129 unsigned char crc_tab[256]; 130 unsigned char ctrl_hb; 131 unsigned char ctrl_lb; 132 unsigned char cell_threshhigh; 133 unsigned char cell_threshlow; 134 unsigned char aux_threshhigh; 135 unsigned char aux_threshlow; 136 unsigned char cb_mask[AD7280A_MAX_CHAIN]; 137 138 __be32 buf[2] ____cacheline_aligned; 139}; 140 141static void ad7280_crc8_build_table(unsigned char *crc_tab) 142{ 143 unsigned char bit, crc; 144 int cnt, i; 145 146 for (cnt = 0; cnt < 256; cnt++) { 147 crc = cnt; 148 for (i = 0; i < 8; i++) { 149 bit = crc & HIGHBIT; 150 crc <<= 1; 151 if (bit) 152 crc ^= POLYNOM; 153 } 154 crc_tab[cnt] = crc; 155 } 156} 157 158static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned val) 159{ 160 unsigned char crc; 161 162 crc = crc_tab[val >> 16 & 0xFF]; 163 crc = crc_tab[crc ^ (val >> 8 & 0xFF)]; 164 165 return crc ^ (val & 0xFF); 166} 167 168static int ad7280_check_crc(struct ad7280_state *st, unsigned val) 169{ 170 unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10); 171 172 if (crc != ((val >> 2) & 0xFF)) 173 return -EIO; 174 175 return 0; 176} 177 178/* After initiating a conversion sequence we need to wait until the 179 * conversion is done. The delay is typically in the range of 15..30 us 180 * however depending an the number of devices in the daisy chain and the 181 * number of averages taken, conversion delays and acquisition time options 182 * it may take up to 250us, in this case we better sleep instead of busy 183 * wait. 184 */ 185 186static void ad7280_delay(struct ad7280_state *st) 187{ 188 if (st->readback_delay_us < 50) 189 udelay(st->readback_delay_us); 190 else 191 usleep_range(250, 500); 192} 193 194static int __ad7280_read32(struct ad7280_state *st, unsigned *val) 195{ 196 int ret; 197 struct spi_transfer t = { 198 .tx_buf = &st->buf[0], 199 .rx_buf = &st->buf[1], 200 .len = 4, 201 }; 202 203 st->buf[0] = cpu_to_be32(AD7280A_READ_TXVAL); 204 205 ret = spi_sync_transfer(st->spi, &t, 1); 206 if (ret) 207 return ret; 208 209 *val = be32_to_cpu(st->buf[1]); 210 211 return 0; 212} 213 214static int ad7280_write(struct ad7280_state *st, unsigned devaddr, 215 unsigned addr, bool all, unsigned val) 216{ 217 unsigned reg = (devaddr << 27 | addr << 21 | 218 (val & 0xFF) << 13 | all << 12); 219 220 reg |= ad7280_calc_crc8(st->crc_tab, reg >> 11) << 3 | 0x2; 221 st->buf[0] = cpu_to_be32(reg); 222 223 return spi_write(st->spi, &st->buf[0], 4); 224} 225 226static int ad7280_read(struct ad7280_state *st, unsigned devaddr, 227 unsigned addr) 228{ 229 int ret; 230 unsigned tmp; 231 232 /* turns off the read operation on all parts */ 233 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 234 AD7280A_CTRL_HB_CONV_INPUT_ALL | 235 AD7280A_CTRL_HB_CONV_RES_READ_NO | 236 st->ctrl_hb); 237 if (ret) 238 return ret; 239 240 /* turns on the read operation on the addressed part */ 241 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0, 242 AD7280A_CTRL_HB_CONV_INPUT_ALL | 243 AD7280A_CTRL_HB_CONV_RES_READ_ALL | 244 st->ctrl_hb); 245 if (ret) 246 return ret; 247 248 /* Set register address on the part to be read from */ 249 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2); 250 if (ret) 251 return ret; 252 253 __ad7280_read32(st, &tmp); 254 255 if (ad7280_check_crc(st, tmp)) 256 return -EIO; 257 258 if (((tmp >> 27) != devaddr) || (((tmp >> 21) & 0x3F) != addr)) 259 return -EFAULT; 260 261 return (tmp >> 13) & 0xFF; 262} 263 264static int ad7280_read_channel(struct ad7280_state *st, unsigned devaddr, 265 unsigned addr) 266{ 267 int ret; 268 unsigned tmp; 269 270 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2); 271 if (ret) 272 return ret; 273 274 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 275 AD7280A_CTRL_HB_CONV_INPUT_ALL | 276 AD7280A_CTRL_HB_CONV_RES_READ_NO | 277 st->ctrl_hb); 278 if (ret) 279 return ret; 280 281 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0, 282 AD7280A_CTRL_HB_CONV_INPUT_ALL | 283 AD7280A_CTRL_HB_CONV_RES_READ_ALL | 284 AD7280A_CTRL_HB_CONV_START_CS | 285 st->ctrl_hb); 286 if (ret) 287 return ret; 288 289 ad7280_delay(st); 290 291 __ad7280_read32(st, &tmp); 292 293 if (ad7280_check_crc(st, tmp)) 294 return -EIO; 295 296 if (((tmp >> 27) != devaddr) || (((tmp >> 23) & 0xF) != addr)) 297 return -EFAULT; 298 299 return (tmp >> 11) & 0xFFF; 300} 301 302static int ad7280_read_all_channels(struct ad7280_state *st, unsigned cnt, 303 unsigned *array) 304{ 305 int i, ret; 306 unsigned tmp, sum = 0; 307 308 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1, 309 AD7280A_CELL_VOLTAGE_1 << 2); 310 if (ret) 311 return ret; 312 313 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 314 AD7280A_CTRL_HB_CONV_INPUT_ALL | 315 AD7280A_CTRL_HB_CONV_RES_READ_ALL | 316 AD7280A_CTRL_HB_CONV_START_CS | 317 st->ctrl_hb); 318 if (ret) 319 return ret; 320 321 ad7280_delay(st); 322 323 for (i = 0; i < cnt; i++) { 324 __ad7280_read32(st, &tmp); 325 326 if (ad7280_check_crc(st, tmp)) 327 return -EIO; 328 329 if (array) 330 array[i] = tmp; 331 /* only sum cell voltages */ 332 if (((tmp >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) 333 sum += ((tmp >> 11) & 0xFFF); 334 } 335 336 return sum; 337} 338 339static int ad7280_chain_setup(struct ad7280_state *st) 340{ 341 unsigned val, n; 342 int ret; 343 344 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1, 345 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN | 346 AD7280A_CTRL_LB_LOCK_DEV_ADDR | 347 AD7280A_CTRL_LB_MUST_SET | 348 AD7280A_CTRL_LB_SWRST | 349 st->ctrl_lb); 350 if (ret) 351 return ret; 352 353 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1, 354 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN | 355 AD7280A_CTRL_LB_LOCK_DEV_ADDR | 356 AD7280A_CTRL_LB_MUST_SET | 357 st->ctrl_lb); 358 if (ret) 359 return ret; 360 361 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1, 362 AD7280A_CONTROL_LB << 2); 363 if (ret) 364 return ret; 365 366 for (n = 0; n <= AD7280A_MAX_CHAIN; n++) { 367 __ad7280_read32(st, &val); 368 if (val == 0) 369 return n - 1; 370 371 if (ad7280_check_crc(st, val)) 372 return -EIO; 373 374 if (n != AD7280A_DEVADDR(val >> 27)) 375 return -EIO; 376 } 377 378 return -EFAULT; 379} 380 381static ssize_t ad7280_show_balance_sw(struct device *dev, 382 struct device_attribute *attr, 383 char *buf) 384{ 385 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 386 struct ad7280_state *st = iio_priv(indio_dev); 387 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 388 389 return sprintf(buf, "%d\n", 390 !!(st->cb_mask[this_attr->address >> 8] & 391 (1 << ((this_attr->address & 0xFF) + 2)))); 392} 393 394static ssize_t ad7280_store_balance_sw(struct device *dev, 395 struct device_attribute *attr, 396 const char *buf, 397 size_t len) 398{ 399 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 400 struct ad7280_state *st = iio_priv(indio_dev); 401 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 402 bool readin; 403 int ret; 404 unsigned devaddr, ch; 405 406 ret = strtobool(buf, &readin); 407 if (ret) 408 return ret; 409 410 devaddr = this_attr->address >> 8; 411 ch = this_attr->address & 0xFF; 412 413 mutex_lock(&indio_dev->mlock); 414 if (readin) 415 st->cb_mask[devaddr] |= 1 << (ch + 2); 416 else 417 st->cb_mask[devaddr] &= ~(1 << (ch + 2)); 418 419 ret = ad7280_write(st, devaddr, AD7280A_CELL_BALANCE, 420 0, st->cb_mask[devaddr]); 421 mutex_unlock(&indio_dev->mlock); 422 423 return ret ? ret : len; 424} 425 426static ssize_t ad7280_show_balance_timer(struct device *dev, 427 struct device_attribute *attr, 428 char *buf) 429{ 430 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 431 struct ad7280_state *st = iio_priv(indio_dev); 432 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 433 int ret; 434 unsigned msecs; 435 436 mutex_lock(&indio_dev->mlock); 437 ret = ad7280_read(st, this_attr->address >> 8, 438 this_attr->address & 0xFF); 439 mutex_unlock(&indio_dev->mlock); 440 441 if (ret < 0) 442 return ret; 443 444 msecs = (ret >> 3) * 71500; 445 446 return sprintf(buf, "%u\n", msecs); 447} 448 449static ssize_t ad7280_store_balance_timer(struct device *dev, 450 struct device_attribute *attr, 451 const char *buf, 452 size_t len) 453{ 454 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 455 struct ad7280_state *st = iio_priv(indio_dev); 456 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 457 unsigned long val; 458 int ret; 459 460 ret = kstrtoul(buf, 10, &val); 461 if (ret) 462 return ret; 463 464 val /= 71500; 465 466 if (val > 31) 467 return -EINVAL; 468 469 mutex_lock(&indio_dev->mlock); 470 ret = ad7280_write(st, this_attr->address >> 8, 471 this_attr->address & 0xFF, 472 0, (val & 0x1F) << 3); 473 mutex_unlock(&indio_dev->mlock); 474 475 return ret ? ret : len; 476} 477 478static struct attribute *ad7280_attributes[AD7280A_MAX_CHAIN * 479 AD7280A_CELLS_PER_DEV * 2 + 1]; 480 481static struct attribute_group ad7280_attrs_group = { 482 .attrs = ad7280_attributes, 483}; 484 485static int ad7280_channel_init(struct ad7280_state *st) 486{ 487 int dev, ch, cnt; 488 489 st->channels = kcalloc((st->slave_num + 1) * 12 + 2, 490 sizeof(*st->channels), GFP_KERNEL); 491 if (st->channels == NULL) 492 return -ENOMEM; 493 494 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++) 495 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_AUX_ADC_6; ch++, 496 cnt++) { 497 if (ch < AD7280A_AUX_ADC_1) { 498 st->channels[cnt].type = IIO_VOLTAGE; 499 st->channels[cnt].differential = 1; 500 st->channels[cnt].channel = (dev * 6) + ch; 501 st->channels[cnt].channel2 = 502 st->channels[cnt].channel + 1; 503 } else { 504 st->channels[cnt].type = IIO_TEMP; 505 st->channels[cnt].channel = (dev * 6) + ch - 6; 506 } 507 st->channels[cnt].indexed = 1; 508 st->channels[cnt].info_mask_separate = 509 BIT(IIO_CHAN_INFO_RAW); 510 st->channels[cnt].info_mask_shared_by_type = 511 BIT(IIO_CHAN_INFO_SCALE); 512 st->channels[cnt].address = 513 AD7280A_DEVADDR(dev) << 8 | ch; 514 st->channels[cnt].scan_index = cnt; 515 st->channels[cnt].scan_type.sign = 'u'; 516 st->channels[cnt].scan_type.realbits = 12; 517 st->channels[cnt].scan_type.storagebits = 32; 518 st->channels[cnt].scan_type.shift = 0; 519 } 520 521 st->channels[cnt].type = IIO_VOLTAGE; 522 st->channels[cnt].differential = 1; 523 st->channels[cnt].channel = 0; 524 st->channels[cnt].channel2 = dev * 6; 525 st->channels[cnt].address = AD7280A_ALL_CELLS; 526 st->channels[cnt].indexed = 1; 527 st->channels[cnt].info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 528 st->channels[cnt].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 529 st->channels[cnt].scan_index = cnt; 530 st->channels[cnt].scan_type.sign = 'u'; 531 st->channels[cnt].scan_type.realbits = 32; 532 st->channels[cnt].scan_type.storagebits = 32; 533 st->channels[cnt].scan_type.shift = 0; 534 cnt++; 535 st->channels[cnt].type = IIO_TIMESTAMP; 536 st->channels[cnt].channel = -1; 537 st->channels[cnt].scan_index = cnt; 538 st->channels[cnt].scan_type.sign = 's'; 539 st->channels[cnt].scan_type.realbits = 64; 540 st->channels[cnt].scan_type.storagebits = 64; 541 st->channels[cnt].scan_type.shift = 0; 542 543 return cnt + 1; 544} 545 546static int ad7280_attr_init(struct ad7280_state *st) 547{ 548 int dev, ch, cnt; 549 550 st->iio_attr = kcalloc(2, sizeof(*st->iio_attr) * 551 (st->slave_num + 1) * AD7280A_CELLS_PER_DEV, 552 GFP_KERNEL); 553 if (st->iio_attr == NULL) 554 return -ENOMEM; 555 556 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++) 557 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_CELL_VOLTAGE_6; 558 ch++, cnt++) { 559 st->iio_attr[cnt].address = 560 AD7280A_DEVADDR(dev) << 8 | ch; 561 st->iio_attr[cnt].dev_attr.attr.mode = 562 S_IWUSR | S_IRUGO; 563 st->iio_attr[cnt].dev_attr.show = 564 ad7280_show_balance_sw; 565 st->iio_attr[cnt].dev_attr.store = 566 ad7280_store_balance_sw; 567 st->iio_attr[cnt].dev_attr.attr.name = 568 kasprintf(GFP_KERNEL, 569 "in%d-in%d_balance_switch_en", 570 (dev * AD7280A_CELLS_PER_DEV) + ch, 571 (dev * AD7280A_CELLS_PER_DEV) + ch + 1); 572 ad7280_attributes[cnt] = 573 &st->iio_attr[cnt].dev_attr.attr; 574 cnt++; 575 st->iio_attr[cnt].address = 576 AD7280A_DEVADDR(dev) << 8 | 577 (AD7280A_CB1_TIMER + ch); 578 st->iio_attr[cnt].dev_attr.attr.mode = 579 S_IWUSR | S_IRUGO; 580 st->iio_attr[cnt].dev_attr.show = 581 ad7280_show_balance_timer; 582 st->iio_attr[cnt].dev_attr.store = 583 ad7280_store_balance_timer; 584 st->iio_attr[cnt].dev_attr.attr.name = 585 kasprintf(GFP_KERNEL, "in%d-in%d_balance_timer", 586 (dev * AD7280A_CELLS_PER_DEV) + ch, 587 (dev * AD7280A_CELLS_PER_DEV) + ch + 1); 588 ad7280_attributes[cnt] = 589 &st->iio_attr[cnt].dev_attr.attr; 590 } 591 592 ad7280_attributes[cnt] = NULL; 593 594 return 0; 595} 596 597static ssize_t ad7280_read_channel_config(struct device *dev, 598 struct device_attribute *attr, 599 char *buf) 600{ 601 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 602 struct ad7280_state *st = iio_priv(indio_dev); 603 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 604 unsigned val; 605 606 switch ((u32) this_attr->address) { 607 case AD7280A_CELL_OVERVOLTAGE: 608 val = 1000 + (st->cell_threshhigh * 1568) / 100; 609 break; 610 case AD7280A_CELL_UNDERVOLTAGE: 611 val = 1000 + (st->cell_threshlow * 1568) / 100; 612 break; 613 case AD7280A_AUX_ADC_OVERVOLTAGE: 614 val = (st->aux_threshhigh * 196) / 10; 615 break; 616 case AD7280A_AUX_ADC_UNDERVOLTAGE: 617 val = (st->aux_threshlow * 196) / 10; 618 break; 619 default: 620 return -EINVAL; 621 } 622 623 return sprintf(buf, "%u\n", val); 624} 625 626static ssize_t ad7280_write_channel_config(struct device *dev, 627 struct device_attribute *attr, 628 const char *buf, 629 size_t len) 630{ 631 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 632 struct ad7280_state *st = iio_priv(indio_dev); 633 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 634 635 long val; 636 int ret; 637 638 ret = kstrtol(buf, 10, &val); 639 if (ret) 640 return ret; 641 642 switch ((u32) this_attr->address) { 643 case AD7280A_CELL_OVERVOLTAGE: 644 case AD7280A_CELL_UNDERVOLTAGE: 645 val = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */ 646 break; 647 case AD7280A_AUX_ADC_OVERVOLTAGE: 648 case AD7280A_AUX_ADC_UNDERVOLTAGE: 649 val = (val * 10) / 196; /* LSB 19.6mV */ 650 break; 651 default: 652 return -EFAULT; 653 } 654 655 val = clamp(val, 0L, 0xFFL); 656 657 mutex_lock(&indio_dev->mlock); 658 switch ((u32) this_attr->address) { 659 case AD7280A_CELL_OVERVOLTAGE: 660 st->cell_threshhigh = val; 661 break; 662 case AD7280A_CELL_UNDERVOLTAGE: 663 st->cell_threshlow = val; 664 break; 665 case AD7280A_AUX_ADC_OVERVOLTAGE: 666 st->aux_threshhigh = val; 667 break; 668 case AD7280A_AUX_ADC_UNDERVOLTAGE: 669 st->aux_threshlow = val; 670 break; 671 } 672 673 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, 674 this_attr->address, 1, val); 675 676 mutex_unlock(&indio_dev->mlock); 677 678 return ret ? ret : len; 679} 680 681static irqreturn_t ad7280_event_handler(int irq, void *private) 682{ 683 struct iio_dev *indio_dev = private; 684 struct ad7280_state *st = iio_priv(indio_dev); 685 unsigned *channels; 686 int i, ret; 687 688 channels = kcalloc(st->scan_cnt, sizeof(*channels), GFP_KERNEL); 689 if (channels == NULL) 690 return IRQ_HANDLED; 691 692 ret = ad7280_read_all_channels(st, st->scan_cnt, channels); 693 if (ret < 0) 694 goto out; 695 696 for (i = 0; i < st->scan_cnt; i++) { 697 if (((channels[i] >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) { 698 if (((channels[i] >> 11) & 0xFFF) >= 699 st->cell_threshhigh) 700 iio_push_event(indio_dev, 701 IIO_EVENT_CODE(IIO_VOLTAGE, 702 1, 703 0, 704 IIO_EV_DIR_RISING, 705 IIO_EV_TYPE_THRESH, 706 0, 0, 0), 707 iio_get_time_ns()); 708 else if (((channels[i] >> 11) & 0xFFF) <= 709 st->cell_threshlow) 710 iio_push_event(indio_dev, 711 IIO_EVENT_CODE(IIO_VOLTAGE, 712 1, 713 0, 714 IIO_EV_DIR_FALLING, 715 IIO_EV_TYPE_THRESH, 716 0, 0, 0), 717 iio_get_time_ns()); 718 } else { 719 if (((channels[i] >> 11) & 0xFFF) >= st->aux_threshhigh) 720 iio_push_event(indio_dev, 721 IIO_UNMOD_EVENT_CODE(IIO_TEMP, 722 0, 723 IIO_EV_TYPE_THRESH, 724 IIO_EV_DIR_RISING), 725 iio_get_time_ns()); 726 else if (((channels[i] >> 11) & 0xFFF) <= 727 st->aux_threshlow) 728 iio_push_event(indio_dev, 729 IIO_UNMOD_EVENT_CODE(IIO_TEMP, 730 0, 731 IIO_EV_TYPE_THRESH, 732 IIO_EV_DIR_FALLING), 733 iio_get_time_ns()); 734 } 735 } 736 737out: 738 kfree(channels); 739 740 return IRQ_HANDLED; 741} 742 743static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value, 744 in_voltage-voltage_thresh_low_value, 745 S_IRUGO | S_IWUSR, 746 ad7280_read_channel_config, 747 ad7280_write_channel_config, 748 AD7280A_CELL_UNDERVOLTAGE); 749 750static IIO_DEVICE_ATTR_NAMED(in_thresh_high_value, 751 in_voltage-voltage_thresh_high_value, 752 S_IRUGO | S_IWUSR, 753 ad7280_read_channel_config, 754 ad7280_write_channel_config, 755 AD7280A_CELL_OVERVOLTAGE); 756 757static IIO_DEVICE_ATTR(in_temp_thresh_low_value, 758 S_IRUGO | S_IWUSR, 759 ad7280_read_channel_config, 760 ad7280_write_channel_config, 761 AD7280A_AUX_ADC_UNDERVOLTAGE); 762 763static IIO_DEVICE_ATTR(in_temp_thresh_high_value, 764 S_IRUGO | S_IWUSR, 765 ad7280_read_channel_config, 766 ad7280_write_channel_config, 767 AD7280A_AUX_ADC_OVERVOLTAGE); 768 769 770static struct attribute *ad7280_event_attributes[] = { 771 &iio_dev_attr_in_thresh_low_value.dev_attr.attr, 772 &iio_dev_attr_in_thresh_high_value.dev_attr.attr, 773 &iio_dev_attr_in_temp_thresh_low_value.dev_attr.attr, 774 &iio_dev_attr_in_temp_thresh_high_value.dev_attr.attr, 775 NULL, 776}; 777 778static struct attribute_group ad7280_event_attrs_group = { 779 .attrs = ad7280_event_attributes, 780}; 781 782static int ad7280_read_raw(struct iio_dev *indio_dev, 783 struct iio_chan_spec const *chan, 784 int *val, 785 int *val2, 786 long m) 787{ 788 struct ad7280_state *st = iio_priv(indio_dev); 789 int ret; 790 791 switch (m) { 792 case IIO_CHAN_INFO_RAW: 793 mutex_lock(&indio_dev->mlock); 794 if (chan->address == AD7280A_ALL_CELLS) 795 ret = ad7280_read_all_channels(st, st->scan_cnt, NULL); 796 else 797 ret = ad7280_read_channel(st, chan->address >> 8, 798 chan->address & 0xFF); 799 mutex_unlock(&indio_dev->mlock); 800 801 if (ret < 0) 802 return ret; 803 804 *val = ret; 805 806 return IIO_VAL_INT; 807 case IIO_CHAN_INFO_SCALE: 808 if ((chan->address & 0xFF) <= AD7280A_CELL_VOLTAGE_6) 809 *val = 4000; 810 else 811 *val = 5000; 812 813 *val2 = AD7280A_BITS; 814 return IIO_VAL_FRACTIONAL_LOG2; 815 } 816 return -EINVAL; 817} 818 819static const struct iio_info ad7280_info = { 820 .read_raw = &ad7280_read_raw, 821 .event_attrs = &ad7280_event_attrs_group, 822 .attrs = &ad7280_attrs_group, 823 .driver_module = THIS_MODULE, 824}; 825 826static const struct ad7280_platform_data ad7793_default_pdata = { 827 .acquisition_time = AD7280A_ACQ_TIME_400ns, 828 .conversion_averaging = AD7280A_CONV_AVG_DIS, 829 .thermistor_term_en = true, 830}; 831 832static int ad7280_probe(struct spi_device *spi) 833{ 834 const struct ad7280_platform_data *pdata = spi->dev.platform_data; 835 struct ad7280_state *st; 836 int ret; 837 const unsigned short tACQ_ns[4] = {465, 1010, 1460, 1890}; 838 const unsigned short nAVG[4] = {1, 2, 4, 8}; 839 struct iio_dev *indio_dev; 840 841 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 842 if (indio_dev == NULL) 843 return -ENOMEM; 844 845 st = iio_priv(indio_dev); 846 spi_set_drvdata(spi, indio_dev); 847 st->spi = spi; 848 849 if (!pdata) 850 pdata = &ad7793_default_pdata; 851 852 ad7280_crc8_build_table(st->crc_tab); 853 854 st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_Hz; 855 st->spi->mode = SPI_MODE_1; 856 spi_setup(st->spi); 857 858 st->ctrl_lb = AD7280A_CTRL_LB_ACQ_TIME(pdata->acquisition_time & 0x3); 859 st->ctrl_hb = AD7280A_CTRL_HB_CONV_AVG(pdata->conversion_averaging 860 & 0x3) | (pdata->thermistor_term_en ? 861 AD7280A_CTRL_LB_THERMISTOR_EN : 0); 862 863 ret = ad7280_chain_setup(st); 864 if (ret < 0) 865 return ret; 866 867 st->slave_num = ret; 868 st->scan_cnt = (st->slave_num + 1) * AD7280A_NUM_CH; 869 st->cell_threshhigh = 0xFF; 870 st->aux_threshhigh = 0xFF; 871 872 /* 873 * Total Conversion Time = ((tACQ + tCONV) * 874 * (Number of Conversions per Part)) − 875 * tACQ + ((N - 1) * tDELAY) 876 * 877 * Readback Delay = Total Conversion Time + tWAIT 878 */ 879 880 st->readback_delay_us = 881 ((tACQ_ns[pdata->acquisition_time & 0x3] + 695) * 882 (AD7280A_NUM_CH * nAVG[pdata->conversion_averaging & 0x3])) 883 - tACQ_ns[pdata->acquisition_time & 0x3] + 884 st->slave_num * 250; 885 886 /* Convert to usecs */ 887 st->readback_delay_us = DIV_ROUND_UP(st->readback_delay_us, 1000); 888 st->readback_delay_us += 5; /* Add tWAIT */ 889 890 indio_dev->name = spi_get_device_id(spi)->name; 891 indio_dev->dev.parent = &spi->dev; 892 indio_dev->modes = INDIO_DIRECT_MODE; 893 894 ret = ad7280_channel_init(st); 895 if (ret < 0) 896 return ret; 897 898 indio_dev->num_channels = ret; 899 indio_dev->channels = st->channels; 900 indio_dev->info = &ad7280_info; 901 902 ret = ad7280_attr_init(st); 903 if (ret < 0) 904 goto error_free_channels; 905 906 ret = iio_device_register(indio_dev); 907 if (ret) 908 goto error_free_attr; 909 910 if (spi->irq > 0) { 911 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, 912 AD7280A_ALERT, 1, 913 AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN); 914 if (ret) 915 goto error_unregister; 916 917 ret = ad7280_write(st, AD7280A_DEVADDR(st->slave_num), 918 AD7280A_ALERT, 0, 919 AD7280A_ALERT_GEN_STATIC_HIGH | 920 (pdata->chain_last_alert_ignore & 0xF)); 921 if (ret) 922 goto error_unregister; 923 924 ret = request_threaded_irq(spi->irq, 925 NULL, 926 ad7280_event_handler, 927 IRQF_TRIGGER_FALLING | 928 IRQF_ONESHOT, 929 indio_dev->name, 930 indio_dev); 931 if (ret) 932 goto error_unregister; 933 } 934 935 return 0; 936error_unregister: 937 iio_device_unregister(indio_dev); 938 939error_free_attr: 940 kfree(st->iio_attr); 941 942error_free_channels: 943 kfree(st->channels); 944 945 return ret; 946} 947 948static int ad7280_remove(struct spi_device *spi) 949{ 950 struct iio_dev *indio_dev = spi_get_drvdata(spi); 951 struct ad7280_state *st = iio_priv(indio_dev); 952 953 if (spi->irq > 0) 954 free_irq(spi->irq, indio_dev); 955 iio_device_unregister(indio_dev); 956 957 ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1, 958 AD7280A_CTRL_HB_PWRDN_SW | st->ctrl_hb); 959 960 kfree(st->channels); 961 kfree(st->iio_attr); 962 963 return 0; 964} 965 966static const struct spi_device_id ad7280_id[] = { 967 {"ad7280a", 0}, 968 {} 969}; 970MODULE_DEVICE_TABLE(spi, ad7280_id); 971 972static struct spi_driver ad7280_driver = { 973 .driver = { 974 .name = "ad7280", 975 .owner = THIS_MODULE, 976 }, 977 .probe = ad7280_probe, 978 .remove = ad7280_remove, 979 .id_table = ad7280_id, 980}; 981module_spi_driver(ad7280_driver); 982 983MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 984MODULE_DESCRIPTION("Analog Devices AD7280A"); 985MODULE_LICENSE("GPL v2"); 986