1/* 2 * Copyright (c) 2003-2012 Broadcom Corporation 3 * All Rights Reserved 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the Broadcom 9 * license below: 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34#include <linux/phy.h> 35#include <linux/delay.h> 36#include <linux/netdevice.h> 37#include <linux/smp.h> 38#include <linux/ethtool.h> 39#include <linux/module.h> 40#include <linux/etherdevice.h> 41#include <linux/skbuff.h> 42#include <linux/jiffies.h> 43#include <linux/interrupt.h> 44#include <linux/platform_device.h> 45 46#include <asm/mipsregs.h> 47/* 48 * fmn.h - For FMN credit configuration and registering fmn_handler. 49 * FMN is communication mechanism that allows processing agents within 50 * XLR/XLS to communicate each other. 51 */ 52#include <asm/netlogic/xlr/fmn.h> 53 54#include "platform_net.h" 55#include "xlr_net.h" 56 57/* 58 * The readl/writel implementation byteswaps on XLR/XLS, so 59 * we need to use __raw_ IO to read the NAE registers 60 * because they are in the big-endian MMIO area on the SoC. 61 */ 62static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val) 63{ 64 __raw_writel(val, base + reg); 65} 66 67static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg) 68{ 69 return __raw_readl(base + reg); 70} 71 72static inline void xlr_reg_update(u32 *base_addr, 73 u32 off, u32 val, u32 mask) 74{ 75 u32 tmp; 76 77 tmp = xlr_nae_rdreg(base_addr, off); 78 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask)); 79} 80 81#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES 82 83static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr) 84{ 85 struct nlm_fmn_msg msg; 86 int ret = 0, num_try = 0, stnid; 87 unsigned long paddr, mflags; 88 89 paddr = virt_to_bus(addr); 90 msg.msg0 = (u64)paddr & 0xffffffffe0ULL; 91 msg.msg1 = 0; 92 msg.msg2 = 0; 93 msg.msg3 = 0; 94 stnid = priv->nd->rfr_station; 95 do { 96 mflags = nlm_cop2_enable_irqsave(); 97 ret = nlm_fmn_send(1, 0, stnid, &msg); 98 nlm_cop2_disable_irqrestore(mflags); 99 if (ret == 0) 100 return 0; 101 } while (++num_try < 10000); 102 103 pr_err("Send to RFR failed in RX path\n"); 104 return ret; 105} 106 107static inline unsigned char *xlr_alloc_skb(void) 108{ 109 struct sk_buff *skb; 110 int buf_len = sizeof(struct sk_buff *); 111 unsigned char *skb_data; 112 113 /* skb->data is cache aligned */ 114 skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC); 115 if (!skb) 116 return NULL; 117 skb_data = skb->data; 118 skb_put(skb, MAC_SKB_BACK_PTR_SIZE); 119 skb_pull(skb, MAC_SKB_BACK_PTR_SIZE); 120 memcpy(skb_data, &skb, buf_len); 121 122 return skb->data; 123} 124 125static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, 126 int code, struct nlm_fmn_msg *msg, void *arg) 127{ 128 struct sk_buff *skb; 129 void *skb_data = NULL; 130 struct net_device *ndev; 131 struct xlr_net_priv *priv; 132 u32 port, length; 133 unsigned char *addr; 134 struct xlr_adapter *adapter = (struct xlr_adapter *) arg; 135 136 length = (msg->msg0 >> 40) & 0x3fff; 137 if (length == 0) { 138 addr = bus_to_virt(msg->msg0 & 0xffffffffffULL); 139 addr = addr - MAC_SKB_BACK_PTR_SIZE; 140 skb = (struct sk_buff *) *(unsigned long *)addr; 141 dev_kfree_skb_any((struct sk_buff *)addr); 142 } else { 143 addr = (unsigned char *) 144 bus_to_virt(msg->msg0 & 0xffffffffe0ULL); 145 length = length - BYTE_OFFSET - MAC_CRC_LEN; 146 port = ((int)msg->msg0) & 0x0f; 147 addr = addr - MAC_SKB_BACK_PTR_SIZE; 148 skb = (struct sk_buff *) *(unsigned long *)addr; 149 skb->dev = adapter->netdev[port]; 150 if (skb->dev == NULL) 151 return; 152 ndev = skb->dev; 153 priv = netdev_priv(ndev); 154 155 /* 16 byte IP header align */ 156 skb_reserve(skb, BYTE_OFFSET); 157 skb_put(skb, length); 158 skb->protocol = eth_type_trans(skb, skb->dev); 159 skb->dev->last_rx = jiffies; 160 netif_rx(skb); 161 /* Fill rx ring */ 162 skb_data = xlr_alloc_skb(); 163 if (skb_data) 164 send_to_rfr_fifo(priv, skb_data); 165 } 166} 167 168/* 169 * Ethtool operation 170 */ 171static int xlr_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 172{ 173 struct xlr_net_priv *priv = netdev_priv(ndev); 174 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 175 176 if (!phydev) 177 return -ENODEV; 178 return phy_ethtool_gset(phydev, ecmd); 179} 180 181static int xlr_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 182{ 183 struct xlr_net_priv *priv = netdev_priv(ndev); 184 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 185 186 if (!phydev) 187 return -ENODEV; 188 return phy_ethtool_sset(phydev, ecmd); 189} 190 191static struct ethtool_ops xlr_ethtool_ops = { 192 .get_settings = xlr_get_settings, 193 .set_settings = xlr_set_settings, 194}; 195 196/* 197 * Net operations 198 */ 199static int xlr_net_fill_rx_ring(struct net_device *ndev) 200{ 201 void *skb_data; 202 struct xlr_net_priv *priv = netdev_priv(ndev); 203 int i; 204 205 for (i = 0; i < MAX_FRIN_SPILL/4; i++) { 206 skb_data = xlr_alloc_skb(); 207 if (!skb_data) { 208 pr_err("SKB allocation failed\n"); 209 return -ENOMEM; 210 } 211 send_to_rfr_fifo(priv, skb_data); 212 } 213 pr_info("Rx ring setup done\n"); 214 return 0; 215} 216 217static int xlr_net_open(struct net_device *ndev) 218{ 219 u32 err; 220 struct xlr_net_priv *priv = netdev_priv(ndev); 221 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 222 223 /* schedule a link state check */ 224 phy_start(phydev); 225 226 err = phy_start_aneg(phydev); 227 if (err) { 228 pr_err("Autoneg failed\n"); 229 return err; 230 } 231 /* Setup the speed from PHY to internal reg*/ 232 xlr_set_gmac_speed(priv); 233 234 netif_tx_start_all_queues(ndev); 235 236 return 0; 237} 238 239static int xlr_net_stop(struct net_device *ndev) 240{ 241 struct xlr_net_priv *priv = netdev_priv(ndev); 242 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 243 244 phy_stop(phydev); 245 netif_tx_stop_all_queues(ndev); 246 return 0; 247} 248 249static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr, 250 struct sk_buff *skb) 251{ 252 unsigned long physkb = virt_to_phys(skb); 253 int cpu_core = nlm_core_id(); 254 int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */ 255 256 msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */ 257 ((u64)127 << 54) | /* No Free back */ 258 (u64)skb->len << 40 | /* Length of data */ 259 ((u64)addr)); 260 msg->msg1 = (((u64)1 << 63) | 261 ((u64)fr_stn_id << 54) | /* Free back id */ 262 (u64)0 << 40 | /* Set len to 0 */ 263 ((u64)physkb & 0xffffffff)); /* 32bit address */ 264 msg->msg2 = msg->msg3 = 0; 265} 266 267static void __maybe_unused xlr_wakeup_queue(unsigned long dev) 268{ 269 struct net_device *ndev = (struct net_device *) dev; 270 struct xlr_net_priv *priv = netdev_priv(ndev); 271 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 272 273 if (phydev->link) 274 netif_tx_wake_queue(netdev_get_tx_queue(ndev, priv->wakeup_q)); 275} 276 277static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb, 278 struct net_device *ndev) 279{ 280 struct nlm_fmn_msg msg; 281 struct xlr_net_priv *priv = netdev_priv(ndev); 282 int ret; 283 u32 flags; 284 285 xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb); 286 flags = nlm_cop2_enable_irqsave(); 287 ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg); 288 nlm_cop2_disable_irqrestore(flags); 289 if (ret) 290 dev_kfree_skb_any(skb); 291 return NETDEV_TX_OK; 292} 293 294static u16 xlr_net_select_queue(struct net_device *ndev, struct sk_buff *skb, 295 void *accel_priv, 296 select_queue_fallback_t fallback) 297{ 298 return (u16)smp_processor_id(); 299} 300 301static void xlr_hw_set_mac_addr(struct net_device *ndev) 302{ 303 struct xlr_net_priv *priv = netdev_priv(ndev); 304 305 /* set mac station address */ 306 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0, 307 ((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) | 308 (ndev->dev_addr[3] << 8) | (ndev->dev_addr[2]))); 309 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1, 310 ((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16))); 311 312 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff); 313 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff); 314 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff); 315 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff); 316 317 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, 318 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | 319 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) | 320 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID)); 321 322 if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII || 323 priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII) 324 xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f); 325} 326 327static int xlr_net_set_mac_addr(struct net_device *ndev, void *data) 328{ 329 int err; 330 331 err = eth_mac_addr(ndev, data); 332 if (err) 333 return err; 334 xlr_hw_set_mac_addr(ndev); 335 return 0; 336} 337 338static void xlr_set_rx_mode(struct net_device *ndev) 339{ 340 struct xlr_net_priv *priv = netdev_priv(ndev); 341 u32 regval; 342 343 regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG); 344 345 if (ndev->flags & IFF_PROMISC) { 346 regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | 347 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | 348 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) | 349 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN); 350 } else { 351 regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | 352 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN)); 353 } 354 355 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval); 356} 357 358static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats) 359{ 360 struct xlr_net_priv *priv = netdev_priv(ndev); 361 362 stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER); 363 stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER); 364 stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER); 365 stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER); 366 stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER); 367 stats->rx_dropped = xlr_nae_rdreg(priv->base_addr, 368 RX_DROP_PACKET_COUNTER); 369 stats->tx_dropped = xlr_nae_rdreg(priv->base_addr, 370 TX_DROP_FRAME_COUNTER); 371 372 stats->multicast = xlr_nae_rdreg(priv->base_addr, 373 RX_MULTICAST_PACKET_COUNTER); 374 stats->collisions = xlr_nae_rdreg(priv->base_addr, 375 TX_TOTAL_COLLISION_COUNTER); 376 377 stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr, 378 RX_FRAME_LENGTH_ERROR_COUNTER); 379 stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr, 380 RX_DROP_PACKET_COUNTER); 381 stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr, 382 RX_FCS_ERROR_COUNTER); 383 stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr, 384 RX_ALIGNMENT_ERROR_COUNTER); 385 386 stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr, 387 RX_DROP_PACKET_COUNTER); 388 stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr, 389 RX_CARRIER_SENSE_ERROR_COUNTER); 390 391 stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors + 392 stats->rx_frame_errors + stats->rx_fifo_errors + 393 stats->rx_missed_errors); 394 395 stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr, 396 TX_EXCESSIVE_COLLISION_PACKET_COUNTER); 397 stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr, 398 TX_DROP_FRAME_COUNTER); 399 stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr, 400 TX_DROP_FRAME_COUNTER); 401} 402 403static struct rtnl_link_stats64 *xlr_get_stats64(struct net_device *ndev, 404 struct rtnl_link_stats64 *stats) 405{ 406 xlr_stats(ndev, stats); 407 return stats; 408} 409 410static struct net_device_ops xlr_netdev_ops = { 411 .ndo_open = xlr_net_open, 412 .ndo_stop = xlr_net_stop, 413 .ndo_start_xmit = xlr_net_start_xmit, 414 .ndo_select_queue = xlr_net_select_queue, 415 .ndo_set_mac_address = xlr_net_set_mac_addr, 416 .ndo_set_rx_mode = xlr_set_rx_mode, 417 .ndo_get_stats64 = xlr_get_stats64, 418}; 419 420/* 421 * Gmac init 422 */ 423static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0, 424 int reg_start_1, int reg_size, int size) 425{ 426 void *spill; 427 u32 *base; 428 unsigned long phys_addr; 429 u32 spill_size; 430 431 base = priv->base_addr; 432 spill_size = size; 433 spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_ATOMIC); 434 if (!spill) 435 pr_err("Unable to allocate memory for spill area!\n"); 436 437 spill = PTR_ALIGN(spill, SMP_CACHE_BYTES); 438 phys_addr = virt_to_phys(spill); 439 dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n", 440 size, phys_addr); 441 xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff); 442 xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07); 443 xlr_nae_wreg(base, reg_size, spill_size); 444 445 return spill; 446} 447 448/* 449 * Configure the 6 FIFO's that are used by the network accelarator to 450 * communicate with the rest of the XLx device. 4 of the FIFO's are for 451 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding 452 * the NA with free descriptors. 453 */ 454static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv) 455{ 456 priv->frin_spill = xlr_config_spill(priv, 457 R_REG_FRIN_SPILL_MEM_START_0, 458 R_REG_FRIN_SPILL_MEM_START_1, 459 R_REG_FRIN_SPILL_MEM_SIZE, 460 MAX_FRIN_SPILL * 461 sizeof(u64)); 462 priv->frout_spill = xlr_config_spill(priv, 463 R_FROUT_SPILL_MEM_START_0, 464 R_FROUT_SPILL_MEM_START_1, 465 R_FROUT_SPILL_MEM_SIZE, 466 MAX_FROUT_SPILL * 467 sizeof(u64)); 468 priv->class_0_spill = xlr_config_spill(priv, 469 R_CLASS0_SPILL_MEM_START_0, 470 R_CLASS0_SPILL_MEM_START_1, 471 R_CLASS0_SPILL_MEM_SIZE, 472 MAX_CLASS_0_SPILL * 473 sizeof(u64)); 474 priv->class_1_spill = xlr_config_spill(priv, 475 R_CLASS1_SPILL_MEM_START_0, 476 R_CLASS1_SPILL_MEM_START_1, 477 R_CLASS1_SPILL_MEM_SIZE, 478 MAX_CLASS_1_SPILL * 479 sizeof(u64)); 480 priv->class_2_spill = xlr_config_spill(priv, 481 R_CLASS2_SPILL_MEM_START_0, 482 R_CLASS2_SPILL_MEM_START_1, 483 R_CLASS2_SPILL_MEM_SIZE, 484 MAX_CLASS_2_SPILL * 485 sizeof(u64)); 486 priv->class_3_spill = xlr_config_spill(priv, 487 R_CLASS3_SPILL_MEM_START_0, 488 R_CLASS3_SPILL_MEM_START_1, 489 R_CLASS3_SPILL_MEM_SIZE, 490 MAX_CLASS_3_SPILL * 491 sizeof(u64)); 492} 493 494/* 495 * Configure PDE to Round-Robin distribution of packets to the 496 * available cpu 497 */ 498static void xlr_config_pde(struct xlr_net_priv *priv) 499{ 500 int i = 0; 501 u64 bkt_map = 0; 502 503 /* Each core has 8 buckets(station) */ 504 for (i = 0; i < hweight32(priv->nd->cpu_mask); i++) 505 bkt_map |= (0xff << (i * 8)); 506 507 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff)); 508 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1, 509 ((bkt_map >> 32) & 0xffffffff)); 510 511 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff)); 512 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1, 513 ((bkt_map >> 32) & 0xffffffff)); 514 515 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff)); 516 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1, 517 ((bkt_map >> 32) & 0xffffffff)); 518 519 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff)); 520 xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1, 521 ((bkt_map >> 32) & 0xffffffff)); 522} 523 524/* 525 * Setup the Message ring credits, bucket size and other 526 * common configuration 527 */ 528static int xlr_config_common(struct xlr_net_priv *priv) 529{ 530 struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info; 531 int start_stn_id = gmac->start_stn_id; 532 int end_stn_id = gmac->end_stn_id; 533 int *bucket_size = priv->nd->bucket_size; 534 int i, j, err; 535 536 /* Setting non-core MsgBktSize(0x321 - 0x325) */ 537 for (i = start_stn_id; i <= end_stn_id; i++) { 538 xlr_nae_wreg(priv->base_addr, 539 R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id, 540 bucket_size[i]); 541 } 542 543 /* 544 * Setting non-core Credit counter register 545 * Distributing Gmac's credit to CPU's 546 */ 547 for (i = 0; i < 8; i++) { 548 for (j = 0; j < 8; j++) 549 xlr_nae_wreg(priv->base_addr, 550 (R_CC_CPU0_0 + (i * 8)) + j, 551 gmac->credit_config[(i * 8) + j]); 552 } 553 554 xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3); 555 xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff); 556 xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff); 557 xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff); 558 xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff); 559 xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0); 560 561 err = xlr_net_fill_rx_ring(priv->ndev); 562 if (err) 563 return err; 564 nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler, 565 priv->adapter); 566 return 0; 567} 568 569static void xlr_config_translate_table(struct xlr_net_priv *priv) 570{ 571 u32 cpu_mask; 572 u32 val; 573 int bkts[32]; /* one bucket is assumed for each cpu */ 574 int b1, b2, c1, c2, i, j, k; 575 int use_bkt; 576 577 use_bkt = 0; 578 cpu_mask = priv->nd->cpu_mask; 579 580 pr_info("Using %s-based distribution\n", 581 (use_bkt) ? "bucket" : "class"); 582 j = 0; 583 for (i = 0; i < 32; i++) { 584 if ((1 << i) & cpu_mask) { 585 /* for each cpu, mark the 4+threadid bucket */ 586 bkts[j] = ((i / 4) * 8) + (i % 4); 587 j++; 588 } 589 } 590 591 /*configure the 128 * 9 Translation table to send to available buckets*/ 592 k = 0; 593 c1 = 3; 594 c2 = 0; 595 for (i = 0; i < 64; i++) { 596 /* 597 * On use_bkt set the b0, b1 are used, else 598 * the 4 classes are used, here implemented 599 * a logic to distribute the packets to the 600 * buckets equally or based on the class 601 */ 602 c1 = (c1 + 1) & 3; 603 c2 = (c1 + 1) & 3; 604 b1 = bkts[k]; 605 k = (k + 1) % j; 606 b2 = bkts[k]; 607 k = (k + 1) % j; 608 609 val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) | 610 (c2 << 7) | (b2 << 1) | (use_bkt << 0)); 611 dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n", 612 i, b1, b2, c1, c2); 613 xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val); 614 c1 = c2; 615 } 616} 617 618static void xlr_config_parser(struct xlr_net_priv *priv) 619{ 620 u32 val; 621 622 /* Mark it as ETHERNET type */ 623 xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01); 624 625 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/ 626 xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG, 627 ((0x7f << 8) | (1 << 1))); 628 629 /* configure the parser : L2 Type is configured in the bootloader */ 630 /* extract IP: src, dest protocol */ 631 xlr_nae_wreg(priv->base_addr, R_L3CTABLE, 632 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) | 633 (0x0800 << 0)); 634 xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1, 635 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) | 636 (16 << 4) | 4); 637 638 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */ 639 xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6); 640 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17); 641 val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7)); 642 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val); 643 xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val); 644 645 xlr_config_translate_table(priv); 646} 647 648static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val) 649{ 650 unsigned long timeout, stoptime, checktime; 651 int timedout; 652 653 /* 100ms timeout*/ 654 timeout = msecs_to_jiffies(100); 655 stoptime = jiffies + timeout; 656 timedout = 0; 657 658 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum); 659 660 /* Write the data which starts the write cycle */ 661 xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32) val); 662 663 /* poll for the read cycle to complete */ 664 while (!timedout) { 665 checktime = jiffies; 666 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0) 667 break; 668 timedout = time_after(checktime, stoptime); 669 } 670 if (timedout) { 671 pr_info("Phy device write err: device busy"); 672 return -EBUSY; 673 } 674 675 return 0; 676} 677 678static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum) 679{ 680 unsigned long timeout, stoptime, checktime; 681 int timedout; 682 683 /* 100ms timeout*/ 684 timeout = msecs_to_jiffies(100); 685 stoptime = jiffies + timeout; 686 timedout = 0; 687 688 /* setup the phy reg to be used */ 689 xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, 690 (phy_addr << 8) | (regnum << 0)); 691 692 /* Issue the read command */ 693 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 694 (1 << O_MII_MGMT_COMMAND__rstat)); 695 696 /* poll for the read cycle to complete */ 697 while (!timedout) { 698 checktime = jiffies; 699 if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0) 700 break; 701 timedout = time_after(checktime, stoptime); 702 } 703 if (timedout) { 704 pr_info("Phy device read err: device busy"); 705 return -EBUSY; 706 } 707 708 /* clear the read cycle */ 709 xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0); 710 711 /* Read the data */ 712 return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS); 713} 714 715static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val) 716{ 717 struct xlr_net_priv *priv = bus->priv; 718 int ret; 719 720 ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val); 721 dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n", 722 phy_addr, regnum, val, ret); 723 return ret; 724} 725 726static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum) 727{ 728 struct xlr_net_priv *priv = bus->priv; 729 int ret; 730 731 ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum); 732 dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n", 733 phy_addr, regnum, ret); 734 return ret; 735} 736 737/* 738 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0, 739 * which can be configured either SGMII or RGMII, considered SGMII 740 * by default, if board setup to RGMII the port_type need to set 741 * accordingly.Serdes and PCS layer need to configured for SGMII 742 */ 743static void xlr_sgmii_init(struct xlr_net_priv *priv) 744{ 745 int phy; 746 747 xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0); 748 xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF); 749 xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0); 750 xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF); 751 xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000); 752 xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000); 753 xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005); 754 xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001); 755 xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000); 756 xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000); 757 xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000); 758 759 /* program GPIO values for serdes init parameters */ 760 xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802); 761 xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104); 762 763 xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802); 764 xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104); 765 766 /* enable autoneg - more magic */ 767 phy = priv->phy_addr % 4 + 27; 768 xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000); 769 xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200); 770} 771 772void xlr_set_gmac_speed(struct xlr_net_priv *priv) 773{ 774 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 775 int speed; 776 777 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) 778 xlr_sgmii_init(priv); 779 780 if (phydev->speed != priv->phy_speed) { 781 speed = phydev->speed; 782 if (speed == SPEED_1000) { 783 /* Set interface to Byte mode */ 784 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217); 785 priv->phy_speed = speed; 786 } else if (speed == SPEED_100 || speed == SPEED_10) { 787 /* Set interface to Nibble mode */ 788 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117); 789 priv->phy_speed = speed; 790 } 791 /* Set SGMII speed in Interface control reg */ 792 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 793 if (speed == SPEED_10) 794 xlr_nae_wreg(priv->base_addr, 795 R_INTERFACE_CONTROL, SGMII_SPEED_10); 796 if (speed == SPEED_100) 797 xlr_nae_wreg(priv->base_addr, 798 R_INTERFACE_CONTROL, SGMII_SPEED_100); 799 if (speed == SPEED_1000) 800 xlr_nae_wreg(priv->base_addr, 801 R_INTERFACE_CONTROL, SGMII_SPEED_1000); 802 } 803 if (speed == SPEED_10) 804 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2); 805 if (speed == SPEED_100) 806 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1); 807 if (speed == SPEED_1000) 808 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0); 809 } 810 pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed); 811} 812 813static void xlr_gmac_link_adjust(struct net_device *ndev) 814{ 815 struct xlr_net_priv *priv = netdev_priv(ndev); 816 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 817 u32 intreg; 818 819 intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG); 820 if (phydev->link) { 821 if (phydev->speed != priv->phy_speed) { 822 xlr_set_gmac_speed(priv); 823 pr_info("gmac%d : Link up\n", priv->port_id); 824 } 825 } else { 826 xlr_set_gmac_speed(priv); 827 pr_info("gmac%d : Link down\n", priv->port_id); 828 } 829} 830 831static int xlr_mii_probe(struct xlr_net_priv *priv) 832{ 833 struct phy_device *phydev = priv->mii_bus->phy_map[priv->phy_addr]; 834 835 if (!phydev) { 836 pr_err("no PHY found on phy_addr %d\n", priv->phy_addr); 837 return -ENODEV; 838 } 839 840 /* Attach MAC to PHY */ 841 phydev = phy_connect(priv->ndev, dev_name(&phydev->dev), 842 &xlr_gmac_link_adjust, priv->nd->phy_interface); 843 844 if (IS_ERR(phydev)) { 845 pr_err("could not attach PHY\n"); 846 return PTR_ERR(phydev); 847 } 848 phydev->supported &= (ADVERTISED_10baseT_Full 849 | ADVERTISED_10baseT_Half 850 | ADVERTISED_100baseT_Full 851 | ADVERTISED_100baseT_Half 852 | ADVERTISED_1000baseT_Full 853 | ADVERTISED_Autoneg 854 | ADVERTISED_MII); 855 856 phydev->advertising = phydev->supported; 857 pr_info("attached PHY driver [%s] (mii_bus:phy_addr=%s\n", 858 phydev->drv->name, dev_name(&phydev->dev)); 859 return 0; 860} 861 862static int xlr_setup_mdio(struct xlr_net_priv *priv, 863 struct platform_device *pdev) 864{ 865 int err; 866 867 priv->mii_bus = mdiobus_alloc(); 868 if (!priv->mii_bus) { 869 pr_err("mdiobus alloc failed\n"); 870 return -ENOMEM; 871 } 872 873 priv->mii_bus->priv = priv; 874 priv->mii_bus->name = "xlr-mdio"; 875 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d", 876 priv->mii_bus->name, priv->port_id); 877 priv->mii_bus->read = xlr_mii_read; 878 priv->mii_bus->write = xlr_mii_write; 879 priv->mii_bus->parent = &pdev->dev; 880 priv->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 881 if (priv->mii_bus->irq == NULL) { 882 pr_err("irq alloc failed\n"); 883 mdiobus_free(priv->mii_bus); 884 return -ENOMEM; 885 } 886 887 priv->mii_bus->irq[priv->phy_addr] = priv->ndev->irq; 888 889 /* Scan only the enabled address */ 890 priv->mii_bus->phy_mask = ~(1 << priv->phy_addr); 891 892 /* setting clock divisor to 54 */ 893 xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7); 894 895 err = mdiobus_register(priv->mii_bus); 896 if (err) { 897 mdiobus_free(priv->mii_bus); 898 pr_err("mdio bus registration failed\n"); 899 return err; 900 } 901 902 pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id); 903 err = xlr_mii_probe(priv); 904 if (err) { 905 mdiobus_free(priv->mii_bus); 906 return err; 907 } 908 return 0; 909} 910 911static void xlr_port_enable(struct xlr_net_priv *priv) 912{ 913 u32 prid = (read_c0_prid() & 0xf000); 914 915 /* Setup MAC_CONFIG reg if (xls & rgmii) */ 916 if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) && 917 priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII) 918 xlr_reg_update(priv->base_addr, R_RX_CONTROL, 919 (1 << O_RX_CONTROL__RGMII), (1 << O_RX_CONTROL__RGMII)); 920 921 /* Rx Tx enable */ 922 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1, 923 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) | 924 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)), 925 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) | 926 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc))); 927 928 /* Setup tx control reg */ 929 xlr_reg_update(priv->base_addr, R_TX_CONTROL, 930 ((1 << O_TX_CONTROL__TxEnable) | 931 (512 << O_TX_CONTROL__TxThreshold)), 0x3fff); 932 933 /* Setup rx control reg */ 934 xlr_reg_update(priv->base_addr, R_RX_CONTROL, 935 1 << O_RX_CONTROL__RxEnable, 1 << O_RX_CONTROL__RxEnable); 936} 937 938static void xlr_port_disable(struct xlr_net_priv *priv) 939{ 940 /* Setup MAC_CONFIG reg */ 941 /* Rx Tx disable*/ 942 xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1, 943 ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen) | 944 (1 << O_MAC_CONFIG_1__rxfc) | (1 << O_MAC_CONFIG_1__txfc)), 945 0x0); 946 947 /* Setup tx control reg */ 948 xlr_reg_update(priv->base_addr, R_TX_CONTROL, 949 ((1 << O_TX_CONTROL__TxEnable) | 950 (512 << O_TX_CONTROL__TxThreshold)), 0); 951 952 /* Setup rx control reg */ 953 xlr_reg_update(priv->base_addr, R_RX_CONTROL, 954 1 << O_RX_CONTROL__RxEnable, 0); 955} 956 957/* 958 * Initialization of gmac 959 */ 960static int xlr_gmac_init(struct xlr_net_priv *priv, 961 struct platform_device *pdev) 962{ 963 int ret; 964 965 pr_info("Initializing the gmac%d\n", priv->port_id); 966 967 xlr_port_disable(priv); 968 969 xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL, 970 (1 << O_DESC_PACK_CTRL__MaxEntry) 971 | (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset) 972 | (1600 << O_DESC_PACK_CTRL__RegularSize)); 973 974 ret = xlr_setup_mdio(priv, pdev); 975 if (ret) 976 return ret; 977 xlr_port_enable(priv); 978 979 /* Enable Full-duplex/1000Mbps/CRC */ 980 xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217); 981 /* speed 2.5Mhz */ 982 xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02); 983 /* Setup Interrupt mask reg */ 984 xlr_nae_wreg(priv->base_addr, R_INTMASK, 985 (1 << O_INTMASK__TxIllegal) | 986 (1 << O_INTMASK__MDInt) | 987 (1 << O_INTMASK__TxFetchError) | 988 (1 << O_INTMASK__P2PSpillEcc) | 989 (1 << O_INTMASK__TagFull) | 990 (1 << O_INTMASK__Underrun) | 991 (1 << O_INTMASK__Abort) 992 ); 993 994 /* Clear all stats */ 995 xlr_reg_update(priv->base_addr, R_STATCTRL, 996 0, 1 << O_STATCTRL__ClrCnt); 997 xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 998 1 << 2); 999 return 0; 1000} 1001 1002static int xlr_net_probe(struct platform_device *pdev) 1003{ 1004 struct xlr_net_priv *priv = NULL; 1005 struct net_device *ndev; 1006 struct resource *res; 1007 struct xlr_adapter *adapter; 1008 int err, port; 1009 1010 pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id); 1011 /* 1012 * Allocate our adapter data structure and attach it to the device. 1013 */ 1014 adapter = (struct xlr_adapter *) 1015 devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL); 1016 if (!adapter) { 1017 err = -ENOMEM; 1018 return err; 1019 } 1020 1021 /* 1022 * XLR and XLS have 1 and 2 NAE controller respectively 1023 * Each controller has 4 gmac ports, mapping each controller 1024 * under one parent device, 4 gmac ports under one device. 1025 */ 1026 for (port = 0; port < pdev->num_resources/2; port++) { 1027 ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32); 1028 if (!ndev) { 1029 pr_err("Allocation of Ethernet device failed\n"); 1030 return -ENOMEM; 1031 } 1032 1033 priv = netdev_priv(ndev); 1034 priv->pdev = pdev; 1035 priv->ndev = ndev; 1036 priv->port_id = (pdev->id * 4) + port; 1037 priv->nd = (struct xlr_net_data *)pdev->dev.platform_data; 1038 res = platform_get_resource(pdev, IORESOURCE_MEM, port); 1039 1040 if (res == NULL) { 1041 pr_err("No memory resource for MAC %d\n", 1042 priv->port_id); 1043 err = -ENODEV; 1044 goto err_gmac; 1045 } 1046 priv->base_addr = devm_ioremap_resource(&pdev->dev, res); 1047 if (IS_ERR(priv->base_addr)) { 1048 err = PTR_ERR(priv->base_addr); 1049 goto err_gmac; 1050 } 1051 priv->adapter = adapter; 1052 adapter->netdev[port] = ndev; 1053 1054 res = platform_get_resource(pdev, IORESOURCE_IRQ, port); 1055 if (res == NULL) { 1056 pr_err("No irq resource for MAC %d\n", priv->port_id); 1057 err = -ENODEV; 1058 goto err_gmac; 1059 } 1060 1061 ndev->irq = res->start; 1062 1063 priv->phy_addr = priv->nd->phy_addr[port]; 1064 priv->tx_stnid = priv->nd->tx_stnid[port]; 1065 priv->mii_addr = priv->nd->mii_addr; 1066 priv->serdes_addr = priv->nd->serdes_addr; 1067 priv->pcs_addr = priv->nd->pcs_addr; 1068 priv->gpio_addr = priv->nd->gpio_addr; 1069 1070 ndev->netdev_ops = &xlr_netdev_ops; 1071 ndev->watchdog_timeo = HZ; 1072 1073 /* Setup Mac address and Rx mode */ 1074 eth_hw_addr_random(ndev); 1075 xlr_hw_set_mac_addr(ndev); 1076 xlr_set_rx_mode(ndev); 1077 1078 priv->num_rx_desc += MAX_NUM_DESC_SPILL; 1079 ndev->ethtool_ops = &xlr_ethtool_ops; 1080 SET_NETDEV_DEV(ndev, &pdev->dev); 1081 1082 xlr_config_fifo_spill_area(priv); 1083 /* Configure PDE to Round-Robin pkt distribution */ 1084 xlr_config_pde(priv); 1085 xlr_config_parser(priv); 1086 1087 /* Call init with respect to port */ 1088 if (strcmp(res->name, "gmac") == 0) { 1089 err = xlr_gmac_init(priv, pdev); 1090 if (err) { 1091 pr_err("gmac%d init failed\n", priv->port_id); 1092 goto err_gmac; 1093 } 1094 } 1095 1096 if (priv->port_id == 0 || priv->port_id == 4) { 1097 err = xlr_config_common(priv); 1098 if (err) 1099 goto err_netdev; 1100 } 1101 1102 err = register_netdev(ndev); 1103 if (err) { 1104 pr_err("Registering netdev failed for gmac%d\n", 1105 priv->port_id); 1106 goto err_netdev; 1107 } 1108 platform_set_drvdata(pdev, priv); 1109 } 1110 1111 return 0; 1112 1113err_netdev: 1114 mdiobus_free(priv->mii_bus); 1115err_gmac: 1116 free_netdev(ndev); 1117 return err; 1118} 1119 1120static int xlr_net_remove(struct platform_device *pdev) 1121{ 1122 struct xlr_net_priv *priv = platform_get_drvdata(pdev); 1123 1124 unregister_netdev(priv->ndev); 1125 mdiobus_unregister(priv->mii_bus); 1126 mdiobus_free(priv->mii_bus); 1127 free_netdev(priv->ndev); 1128 return 0; 1129} 1130 1131static struct platform_driver xlr_net_driver = { 1132 .probe = xlr_net_probe, 1133 .remove = xlr_net_remove, 1134 .driver = { 1135 .name = "xlr-net", 1136 }, 1137}; 1138 1139module_platform_driver(xlr_net_driver); 1140 1141MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); 1142MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS"); 1143MODULE_LICENSE("Dual BSD/GPL"); 1144MODULE_ALIAS("platform:xlr-net"); 1145