1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *
15 ******************************************************************************/
16#ifndef __INC_HAL8723PHYCFG_H__
17#define __INC_HAL8723PHYCFG_H__
18
19/*------------------------------Define structure----------------------------*/
20enum RF_RADIO_PATH {
21	RF_PATH_A = 0,			/* Radio Path A */
22	RF_PATH_B = 1,			/* Radio Path B */
23	RF_PATH_MAX			/* Max RF number 90 support */
24};
25
26#define CHANNEL_MAX_NUMBER		14	/*  14 is the max channel number */
27
28enum WIRELESS_MODE {
29	WIRELESS_MODE_UNKNOWN	= 0x00,
30	WIRELESS_MODE_A		= BIT(2),
31	WIRELESS_MODE_B		= BIT(0),
32	WIRELESS_MODE_G		= BIT(1),
33	WIRELESS_MODE_AUTO	= BIT(5),
34	WIRELESS_MODE_N_24G	= BIT(3),
35	WIRELESS_MODE_N_5G	= BIT(4),
36	WIRELESS_MODE_AC	= BIT(6)
37};
38
39struct bb_reg_define {
40	u32 rfintfs;		/*  set software control: */
41				/*		0x870~0x877[8 bytes] */
42	u32 rfintfi;		/*  readback data: */
43				/*		0x8e0~0x8e7[8 bytes] */
44	u32 rfintfo;		/*  output data: */
45				/*		0x860~0x86f [16 bytes] */
46	u32 rfintfe;		/*  output enable: */
47				/*		0x860~0x86f [16 bytes] */
48	u32 rf3wireOffset;	/*  LSSI data: */
49				/*		0x840~0x84f [16 bytes] */
50	u32 rfLSSI_Select;	/*  BB Band Select: */
51				/*		0x878~0x87f [8 bytes] */
52	u32 rfTxGainStage;	/*  Tx gain stage: */
53				/*		0x80c~0x80f [4 bytes] */
54	u32 rfHSSIPara1;	/*  wire parameter control1 : */
55				/*		0x820~0x823, 0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
56	u32 rfHSSIPara2;	/*  wire parameter control2 : */
57				/*		0x824~0x827, 0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
58	u32 rfSwitchControl; /* Tx Rx antenna control : */
59				/*		0x858~0x85f [16 bytes] */
60	u32 rfAGCControl1;	/* AGC parameter control1 : */
61				/*	0xc50~0xc53, 0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
62	u32 rfAGCControl2;	/* AGC parameter control2 : */
63				/*		0xc54~0xc57, 0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
64	u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
65				/*		0xc14~0xc17, 0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
66	u32 rfRxAFE;		/* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
67				/*	0xc10~0xc13, 0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
68	u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
69				/*	0xc80~0xc83, 0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
70	u32 rfTxAFE;		/* Tx IQ DC Offset and Tx DFIR type */
71				/*	0xc84~0xc87, 0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
72	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */
73				/*	0x8a0~0x8af [16 bytes] */
74	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
75};
76
77struct r_antenna_sel_ofdm {
78	u32			r_tx_antenna:4;
79	u32			r_ant_l:4;
80	u32			r_ant_non_ht:4;
81	u32			r_ant_ht1:4;
82	u32			r_ant_ht2:4;
83	u32			r_ant_ht_s1:4;
84	u32			r_ant_non_ht_s1:4;
85	u32			OFDM_TXSC:2;
86	u32			Reserved:2;
87};
88
89struct r_antenna_sel_cck {
90	u8			r_cckrx_enable_2:2;
91	u8			r_cckrx_enable:2;
92	u8			r_ccktx_enable:4;
93};
94
95/*------------------------------Define structure----------------------------*/
96
97
98/*------------------------Export global variable----------------------------*/
99/*------------------------Export global variable----------------------------*/
100
101
102/*------------------------Export Macro Definition---------------------------*/
103/*------------------------Export Macro Definition---------------------------*/
104
105
106/*--------------------------Exported Function prototype---------------------*/
107/*  */
108/*  BB and RF register read/write */
109/*  */
110u32	PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
111		       u32 BitMask);
112void	PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
113		     u32 BitMask, u32 Data);
114u32	PHY_QueryRFReg(struct rtw_adapter *Adapter,
115		       enum RF_RADIO_PATH	eRFPath, u32 RegAddr,
116		       u32 BitMask);
117void	PHY_SetRFReg(struct rtw_adapter *Adapter,
118		     enum RF_RADIO_PATH eRFPath, u32 RegAddr,
119		     u32 BitMask,  u32	Data);
120
121/*  */
122/*  BB TX Power R/W */
123/*  */
124void PHY_SetTxPowerLevel8723A(struct rtw_adapter *Adapter, u8 channel);
125
126/*  */
127/*  Switch bandwidth for 8723A */
128/*  */
129void	PHY_SetBWMode23a8723A(struct rtw_adapter *pAdapter,
130			   enum ht_channel_width ChnlWidth,
131			   unsigned char Offset);
132
133/*  */
134/*  channel switch related funciton */
135/*  */
136void	PHY_SwChnl8723A(struct rtw_adapter *pAdapter, u8 channel);
137				/*  Call after initialization */
138void ChkFwCmdIoDone(struct rtw_adapter *Adapter);
139
140/*  */
141/*  Modify the value of the hw register when beacon interval be changed. */
142/*  */
143void
144rtl8192c_PHY_SetBeaconHwReg(struct rtw_adapter *Adapter, u16 BeaconInterval);
145
146
147void PHY_SwitchEphyParameter(struct rtw_adapter *Adapter);
148
149void PHY_EnableHostClkReq(struct rtw_adapter *Adapter);
150
151bool
152SetAntennaConfig92C(struct rtw_adapter *Adapter, u8 DefaultAnt);
153
154/*--------------------------Exported Function prototype---------------------*/
155
156#define PHY_SetMacReg	PHY_SetBBReg
157
158/* MAC/BB/RF HAL config */
159int PHY_BBConfig8723A(struct rtw_adapter *Adapter);
160s32 PHY_MACConfig8723A(struct rtw_adapter *padapter);
161
162#endif
163