1/* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23#include <linux/blkdev.h> 24#include <linux/kthread.h> 25#include <linux/sched.h> 26#include <linux/vmalloc.h> 27 28#include "rtsx.h" 29#include "ms.h" 30 31static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code) 32{ 33 struct ms_info *ms_card = &(chip->ms_card); 34 35 ms_card->err_code = err_code; 36} 37 38static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code) 39{ 40 struct ms_info *ms_card = &(chip->ms_card); 41 42 return (ms_card->err_code == err_code); 43} 44 45static int ms_parse_err_code(struct rtsx_chip *chip) 46{ 47 rtsx_trace(chip); 48 return STATUS_FAIL; 49} 50 51static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, 52 u8 tpc, u8 cnt, u8 cfg) 53{ 54 struct ms_info *ms_card = &(chip->ms_card); 55 int retval; 56 u8 *ptr; 57 58 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc); 59 60 rtsx_init_cmd(chip); 61 62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 66 0x01, PINGPONG_BUFFER); 67 68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 69 0xFF, MS_TRANSFER_START | trans_mode); 70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 71 MS_TRANSFER_END, MS_TRANSFER_END); 72 73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 74 75 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 76 if (retval < 0) { 77 rtsx_clear_ms_error(chip); 78 ms_set_err_code(chip, MS_TO_ERROR); 79 rtsx_trace(chip); 80 return ms_parse_err_code(chip); 81 } 82 83 ptr = rtsx_get_cmd_data(chip) + 1; 84 85 if (!(tpc & 0x08)) { /* Read Packet */ 86 if (*ptr & MS_CRC16_ERR) { 87 ms_set_err_code(chip, MS_CRC16_ERROR); 88 rtsx_trace(chip); 89 return ms_parse_err_code(chip); 90 } 91 } else { /* Write Packet */ 92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) { 93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) { 94 ms_set_err_code(chip, MS_CMD_NK); 95 rtsx_trace(chip); 96 return ms_parse_err_code(chip); 97 } 98 } 99 } 100 101 if (*ptr & MS_RDY_TIMEOUT) { 102 rtsx_clear_ms_error(chip); 103 ms_set_err_code(chip, MS_TO_ERROR); 104 rtsx_trace(chip); 105 return ms_parse_err_code(chip); 106 } 107 108 return STATUS_SUCCESS; 109} 110 111static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 112 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, 113 int use_sg, void *buf, int buf_len) 114{ 115 int retval; 116 u8 val, err_code = 0; 117 enum dma_data_direction dir; 118 119 if (!buf || !buf_len) { 120 rtsx_trace(chip); 121 return STATUS_FAIL; 122 } 123 124 if (trans_mode == MS_TM_AUTO_READ) { 125 dir = DMA_FROM_DEVICE; 126 err_code = MS_FLASH_READ_ERROR; 127 } else if (trans_mode == MS_TM_AUTO_WRITE) { 128 dir = DMA_TO_DEVICE; 129 err_code = MS_FLASH_WRITE_ERROR; 130 } else { 131 rtsx_trace(chip); 132 return STATUS_FAIL; 133 } 134 135 rtsx_init_cmd(chip); 136 137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 138 rtsx_add_cmd(chip, WRITE_REG_CMD, 139 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); 140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 142 143 if (mode_2k) { 144 rtsx_add_cmd(chip, WRITE_REG_CMD, 145 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE); 146 } else { 147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0); 148 } 149 150 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); 151 152 rtsx_add_cmd(chip, WRITE_REG_CMD, 153 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); 154 rtsx_add_cmd(chip, CHECK_REG_CMD, 155 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 156 157 rtsx_send_cmd_no_wait(chip); 158 159 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, 160 use_sg, dir, chip->mspro_timeout); 161 if (retval < 0) { 162 ms_set_err_code(chip, err_code); 163 if (retval == -ETIMEDOUT) 164 retval = STATUS_TIMEDOUT; 165 else 166 retval = STATUS_FAIL; 167 168 rtsx_trace(chip); 169 return retval; 170 } 171 172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 173 if (retval) { 174 rtsx_trace(chip); 175 return retval; 176 } 177 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 178 rtsx_trace(chip); 179 return STATUS_FAIL; 180 } 181 182 return STATUS_SUCCESS; 183} 184 185static int ms_write_bytes(struct rtsx_chip *chip, 186 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 187{ 188 struct ms_info *ms_card = &(chip->ms_card); 189 int retval, i; 190 191 if (!data || (data_len < cnt)) { 192 rtsx_trace(chip); 193 return STATUS_ERROR; 194 } 195 196 rtsx_init_cmd(chip); 197 198 for (i = 0; i < cnt; i++) { 199 rtsx_add_cmd(chip, WRITE_REG_CMD, 200 PPBUF_BASE2 + i, 0xFF, data[i]); 201 } 202 if (cnt % 2) 203 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); 204 205 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 206 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 207 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 208 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 209 0x01, PINGPONG_BUFFER); 210 211 rtsx_add_cmd(chip, WRITE_REG_CMD, 212 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES); 213 rtsx_add_cmd(chip, CHECK_REG_CMD, 214 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 215 216 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 217 if (retval < 0) { 218 u8 val = 0; 219 220 rtsx_read_register(chip, MS_TRANS_CFG, &val); 221 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); 222 223 rtsx_clear_ms_error(chip); 224 225 if (!(tpc & 0x08)) { 226 if (val & MS_CRC16_ERR) { 227 ms_set_err_code(chip, MS_CRC16_ERROR); 228 rtsx_trace(chip); 229 return ms_parse_err_code(chip); 230 } 231 } else { 232 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 233 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 234 ms_set_err_code(chip, MS_CMD_NK); 235 rtsx_trace(chip); 236 return ms_parse_err_code(chip); 237 } 238 } 239 } 240 241 if (val & MS_RDY_TIMEOUT) { 242 ms_set_err_code(chip, MS_TO_ERROR); 243 rtsx_trace(chip); 244 return ms_parse_err_code(chip); 245 } 246 247 ms_set_err_code(chip, MS_TO_ERROR); 248 rtsx_trace(chip); 249 return ms_parse_err_code(chip); 250 } 251 252 return STATUS_SUCCESS; 253} 254 255static int ms_read_bytes(struct rtsx_chip *chip, 256 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 257{ 258 struct ms_info *ms_card = &(chip->ms_card); 259 int retval, i; 260 u8 *ptr; 261 262 if (!data) { 263 rtsx_trace(chip); 264 return STATUS_ERROR; 265 } 266 267 rtsx_init_cmd(chip); 268 269 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 270 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 271 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 272 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 273 0x01, PINGPONG_BUFFER); 274 275 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 276 MS_TRANSFER_START | MS_TM_READ_BYTES); 277 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 278 MS_TRANSFER_END, MS_TRANSFER_END); 279 280 for (i = 0; i < data_len - 1; i++) 281 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); 282 283 if (data_len % 2) 284 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); 285 else 286 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 287 0, 0); 288 289 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 290 if (retval < 0) { 291 u8 val = 0; 292 293 rtsx_read_register(chip, MS_TRANS_CFG, &val); 294 rtsx_clear_ms_error(chip); 295 296 if (!(tpc & 0x08)) { 297 if (val & MS_CRC16_ERR) { 298 ms_set_err_code(chip, MS_CRC16_ERROR); 299 rtsx_trace(chip); 300 return ms_parse_err_code(chip); 301 } 302 } else { 303 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 304 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 305 ms_set_err_code(chip, MS_CMD_NK); 306 rtsx_trace(chip); 307 return ms_parse_err_code(chip); 308 } 309 } 310 } 311 312 if (val & MS_RDY_TIMEOUT) { 313 ms_set_err_code(chip, MS_TO_ERROR); 314 rtsx_trace(chip); 315 return ms_parse_err_code(chip); 316 } 317 318 ms_set_err_code(chip, MS_TO_ERROR); 319 rtsx_trace(chip); 320 return ms_parse_err_code(chip); 321 } 322 323 ptr = rtsx_get_cmd_data(chip) + 1; 324 325 for (i = 0; i < data_len; i++) 326 data[i] = ptr[i]; 327 328 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) { 329 dev_dbg(rtsx_dev(chip), "Read format progress:\n"); 330 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr, 331 cnt); 332 } 333 334 return STATUS_SUCCESS; 335} 336 337static int ms_set_rw_reg_addr(struct rtsx_chip *chip, 338 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt) 339{ 340 int retval, i; 341 u8 data[4]; 342 343 data[0] = read_start; 344 data[1] = read_cnt; 345 data[2] = write_start; 346 data[3] = write_cnt; 347 348 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 349 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, 350 NO_WAIT_INT, data, 4); 351 if (retval == STATUS_SUCCESS) 352 return STATUS_SUCCESS; 353 rtsx_clear_ms_error(chip); 354 } 355 356 rtsx_trace(chip); 357 return STATUS_FAIL; 358} 359 360static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg) 361{ 362 u8 data[2]; 363 364 data[0] = cmd; 365 data[1] = 0; 366 367 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1); 368} 369 370static int ms_set_init_para(struct rtsx_chip *chip) 371{ 372 struct ms_info *ms_card = &(chip->ms_card); 373 int retval; 374 375 if (CHK_HG8BIT(ms_card)) { 376 if (chip->asic_code) 377 ms_card->ms_clock = chip->asic_ms_hg_clk; 378 else 379 ms_card->ms_clock = chip->fpga_ms_hg_clk; 380 381 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) { 382 if (chip->asic_code) 383 ms_card->ms_clock = chip->asic_ms_4bit_clk; 384 else 385 ms_card->ms_clock = chip->fpga_ms_4bit_clk; 386 387 } else { 388 if (chip->asic_code) 389 ms_card->ms_clock = chip->asic_ms_1bit_clk; 390 else 391 ms_card->ms_clock = chip->fpga_ms_1bit_clk; 392 } 393 394 retval = switch_clock(chip, ms_card->ms_clock); 395 if (retval != STATUS_SUCCESS) { 396 rtsx_trace(chip); 397 return STATUS_FAIL; 398 } 399 400 retval = select_card(chip, MS_CARD); 401 if (retval != STATUS_SUCCESS) { 402 rtsx_trace(chip); 403 return STATUS_FAIL; 404 } 405 406 return STATUS_SUCCESS; 407} 408 409static int ms_switch_clock(struct rtsx_chip *chip) 410{ 411 struct ms_info *ms_card = &(chip->ms_card); 412 int retval; 413 414 retval = select_card(chip, MS_CARD); 415 if (retval != STATUS_SUCCESS) { 416 rtsx_trace(chip); 417 return STATUS_FAIL; 418 } 419 420 retval = switch_clock(chip, ms_card->ms_clock); 421 if (retval != STATUS_SUCCESS) { 422 rtsx_trace(chip); 423 return STATUS_FAIL; 424 } 425 426 return STATUS_SUCCESS; 427} 428 429static int ms_pull_ctl_disable(struct rtsx_chip *chip) 430{ 431 int retval; 432 433 if (CHECK_PID(chip, 0x5208)) { 434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 435 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD); 436 if (retval) { 437 rtsx_trace(chip); 438 return retval; 439 } 440 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 441 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD); 442 if (retval) { 443 rtsx_trace(chip); 444 return retval; 445 } 446 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 447 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 448 if (retval) { 449 rtsx_trace(chip); 450 return retval; 451 } 452 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 453 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 454 if (retval) { 455 rtsx_trace(chip); 456 return retval; 457 } 458 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 459 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 460 if (retval) { 461 rtsx_trace(chip); 462 return retval; 463 } 464 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 465 MS_D5_PD | MS_D4_PD); 466 if (retval) { 467 rtsx_trace(chip); 468 return retval; 469 } 470 } else if (CHECK_PID(chip, 0x5288)) { 471 if (CHECK_BARO_PKG(chip, QFN)) { 472 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 473 0xFF, 0x55); 474 if (retval) { 475 rtsx_trace(chip); 476 return retval; 477 } 478 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 479 0xFF, 0x55); 480 if (retval) { 481 rtsx_trace(chip); 482 return retval; 483 } 484 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 485 0xFF, 0x4B); 486 if (retval) { 487 rtsx_trace(chip); 488 return retval; 489 } 490 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 491 0xFF, 0x69); 492 if (retval) { 493 rtsx_trace(chip); 494 return retval; 495 } 496 } 497 } 498 499 return STATUS_SUCCESS; 500} 501 502static int ms_pull_ctl_enable(struct rtsx_chip *chip) 503{ 504 int retval; 505 506 rtsx_init_cmd(chip); 507 508 if (CHECK_PID(chip, 0x5208)) { 509 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 510 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD); 511 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 512 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD); 513 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 514 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 515 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 516 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 517 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 518 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 519 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 520 MS_D5_PD | MS_D4_PD); 521 } else if (CHECK_PID(chip, 0x5288)) { 522 if (CHECK_BARO_PKG(chip, QFN)) { 523 rtsx_add_cmd(chip, WRITE_REG_CMD, 524 CARD_PULL_CTL1, 0xFF, 0x55); 525 rtsx_add_cmd(chip, WRITE_REG_CMD, 526 CARD_PULL_CTL2, 0xFF, 0x45); 527 rtsx_add_cmd(chip, WRITE_REG_CMD, 528 CARD_PULL_CTL3, 0xFF, 0x4B); 529 rtsx_add_cmd(chip, WRITE_REG_CMD, 530 CARD_PULL_CTL4, 0xFF, 0x29); 531 } 532 } 533 534 retval = rtsx_send_cmd(chip, MS_CARD, 100); 535 if (retval < 0) { 536 rtsx_trace(chip); 537 return STATUS_FAIL; 538 } 539 540 return STATUS_SUCCESS; 541} 542 543static int ms_prepare_reset(struct rtsx_chip *chip) 544{ 545 struct ms_info *ms_card = &(chip->ms_card); 546 int retval; 547 u8 oc_mask = 0; 548 549 ms_card->ms_type = 0; 550 ms_card->check_ms_flow = 0; 551 ms_card->switch_8bit_fail = 0; 552 ms_card->delay_write.delay_write_flag = 0; 553 554 ms_card->pro_under_formatting = 0; 555 556 retval = ms_power_off_card3v3(chip); 557 if (retval != STATUS_SUCCESS) { 558 rtsx_trace(chip); 559 return STATUS_FAIL; 560 } 561 562 if (!chip->ft2_fast_mode) 563 wait_timeout(250); 564 565 retval = enable_card_clock(chip, MS_CARD); 566 if (retval != STATUS_SUCCESS) { 567 rtsx_trace(chip); 568 return STATUS_FAIL; 569 } 570 571 if (chip->asic_code) { 572 retval = ms_pull_ctl_enable(chip); 573 if (retval != STATUS_SUCCESS) { 574 rtsx_trace(chip); 575 return STATUS_FAIL; 576 } 577 } else { 578 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 579 FPGA_MS_PULL_CTL_BIT | 0x20, 0); 580 if (retval) { 581 rtsx_trace(chip); 582 return retval; 583 } 584 } 585 586 if (!chip->ft2_fast_mode) { 587 retval = card_power_on(chip, MS_CARD); 588 if (retval != STATUS_SUCCESS) { 589 rtsx_trace(chip); 590 return STATUS_FAIL; 591 } 592 593 wait_timeout(150); 594 595#ifdef SUPPORT_OCP 596 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 597 oc_mask = MS_OC_NOW | MS_OC_EVER; 598 else 599 oc_mask = SD_OC_NOW | SD_OC_EVER; 600 601 if (chip->ocp_stat & oc_mask) { 602 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 603 chip->ocp_stat); 604 rtsx_trace(chip); 605 return STATUS_FAIL; 606 } 607#endif 608 } 609 610 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 611 MS_OUTPUT_EN); 612 if (retval) { 613 rtsx_trace(chip); 614 return retval; 615 } 616 617 if (chip->asic_code) { 618 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 619 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); 620 if (retval) { 621 rtsx_trace(chip); 622 return retval; 623 } 624 } else { 625 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 626 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); 627 if (retval) { 628 rtsx_trace(chip); 629 return retval; 630 } 631 } 632 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, 633 NO_WAIT_INT | NO_AUTO_READ_INT_REG); 634 if (retval) { 635 rtsx_trace(chip); 636 return retval; 637 } 638 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 639 MS_STOP | MS_CLR_ERR); 640 if (retval) { 641 rtsx_trace(chip); 642 return retval; 643 } 644 645 retval = ms_set_init_para(chip); 646 if (retval != STATUS_SUCCESS) { 647 rtsx_trace(chip); 648 return STATUS_FAIL; 649 } 650 651 return STATUS_SUCCESS; 652} 653 654static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 655{ 656 struct ms_info *ms_card = &(chip->ms_card); 657 int retval, i; 658 u8 val; 659 660 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1); 661 if (retval != STATUS_SUCCESS) { 662 rtsx_trace(chip); 663 return STATUS_FAIL; 664 } 665 666 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 667 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 668 6, NO_WAIT_INT); 669 if (retval == STATUS_SUCCESS) 670 break; 671 } 672 if (i == MS_MAX_RETRY_COUNT) { 673 rtsx_trace(chip); 674 return STATUS_FAIL; 675 } 676 677 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); 678 if (retval) { 679 rtsx_trace(chip); 680 return retval; 681 } 682 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); 683 if (val != 0x01) { 684 if (val != 0x02) 685 ms_card->check_ms_flow = 1; 686 687 rtsx_trace(chip); 688 return STATUS_FAIL; 689 } 690 691 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); 692 if (retval) { 693 rtsx_trace(chip); 694 return retval; 695 } 696 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); 697 if (val != 0) { 698 ms_card->check_ms_flow = 1; 699 rtsx_trace(chip); 700 return STATUS_FAIL; 701 } 702 703 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); 704 if (retval) { 705 rtsx_trace(chip); 706 return retval; 707 } 708 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); 709 if (val == 0) { 710 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 711 if (retval) { 712 rtsx_trace(chip); 713 return retval; 714 } 715 if (val & WRT_PRTCT) 716 chip->card_wp |= MS_CARD; 717 else 718 chip->card_wp &= ~MS_CARD; 719 720 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { 721 chip->card_wp |= MS_CARD; 722 } else { 723 ms_card->check_ms_flow = 1; 724 rtsx_trace(chip); 725 return STATUS_FAIL; 726 } 727 728 ms_card->ms_type |= TYPE_MSPRO; 729 730 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); 731 if (retval) { 732 rtsx_trace(chip); 733 return retval; 734 } 735 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); 736 if (val == 0) { 737 ms_card->ms_type &= 0x0F; 738 } else if (val == 7) { 739 if (switch_8bit_bus) 740 ms_card->ms_type |= MS_HG; 741 else 742 ms_card->ms_type &= 0x0F; 743 744 } else { 745 rtsx_trace(chip); 746 return STATUS_FAIL; 747 } 748 749 return STATUS_SUCCESS; 750} 751 752static int ms_confirm_cpu_startup(struct rtsx_chip *chip) 753{ 754 int retval, i, k; 755 u8 val; 756 757 /* Confirm CPU StartUp */ 758 k = 0; 759 do { 760 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 761 ms_set_err_code(chip, MS_NO_CARD); 762 rtsx_trace(chip); 763 return STATUS_FAIL; 764 } 765 766 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 767 retval = ms_read_bytes(chip, GET_INT, 1, 768 NO_WAIT_INT, &val, 1); 769 if (retval == STATUS_SUCCESS) 770 break; 771 } 772 if (i == MS_MAX_RETRY_COUNT) { 773 rtsx_trace(chip); 774 return STATUS_FAIL; 775 } 776 777 if (k > 100) { 778 rtsx_trace(chip); 779 return STATUS_FAIL; 780 } 781 782 k++; 783 wait_timeout(100); 784 } while (!(val & INT_REG_CED)); 785 786 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 787 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 788 if (retval == STATUS_SUCCESS) 789 break; 790 } 791 if (i == MS_MAX_RETRY_COUNT) { 792 rtsx_trace(chip); 793 return STATUS_FAIL; 794 } 795 796 if (val & INT_REG_ERR) { 797 if (val & INT_REG_CMDNK) 798 chip->card_wp |= (MS_CARD); 799 else { 800 rtsx_trace(chip); 801 return STATUS_FAIL; 802 } 803 } 804 /* -- end confirm CPU startup */ 805 806 return STATUS_SUCCESS; 807} 808 809static int ms_switch_parallel_bus(struct rtsx_chip *chip) 810{ 811 int retval, i; 812 u8 data[2]; 813 814 data[0] = PARALLEL_4BIT_IF; 815 data[1] = 0; 816 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 817 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, 818 data, 2); 819 if (retval == STATUS_SUCCESS) 820 break; 821 } 822 if (retval != STATUS_SUCCESS) { 823 rtsx_trace(chip); 824 return STATUS_FAIL; 825 } 826 827 return STATUS_SUCCESS; 828} 829 830static int ms_switch_8bit_bus(struct rtsx_chip *chip) 831{ 832 struct ms_info *ms_card = &(chip->ms_card); 833 int retval, i; 834 u8 data[2]; 835 836 data[0] = PARALLEL_8BIT_IF; 837 data[1] = 0; 838 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 839 retval = ms_write_bytes(chip, WRITE_REG, 1, 840 NO_WAIT_INT, data, 2); 841 if (retval == STATUS_SUCCESS) 842 break; 843 } 844 if (retval != STATUS_SUCCESS) { 845 rtsx_trace(chip); 846 return STATUS_FAIL; 847 } 848 849 retval = rtsx_write_register(chip, MS_CFG, 0x98, 850 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); 851 if (retval) { 852 rtsx_trace(chip); 853 return retval; 854 } 855 ms_card->ms_type |= MS_8BIT; 856 retval = ms_set_init_para(chip); 857 if (retval != STATUS_SUCCESS) { 858 rtsx_trace(chip); 859 return STATUS_FAIL; 860 } 861 862 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 863 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 864 1, NO_WAIT_INT); 865 if (retval != STATUS_SUCCESS) { 866 rtsx_trace(chip); 867 return STATUS_FAIL; 868 } 869 } 870 871 return STATUS_SUCCESS; 872} 873 874static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 875{ 876 struct ms_info *ms_card = &(chip->ms_card); 877 int retval, i; 878 879 for (i = 0; i < 3; i++) { 880 retval = ms_prepare_reset(chip); 881 if (retval != STATUS_SUCCESS) { 882 rtsx_trace(chip); 883 return STATUS_FAIL; 884 } 885 886 retval = ms_identify_media_type(chip, switch_8bit_bus); 887 if (retval != STATUS_SUCCESS) { 888 rtsx_trace(chip); 889 return STATUS_FAIL; 890 } 891 892 retval = ms_confirm_cpu_startup(chip); 893 if (retval != STATUS_SUCCESS) { 894 rtsx_trace(chip); 895 return STATUS_FAIL; 896 } 897 898 retval = ms_switch_parallel_bus(chip); 899 if (retval != STATUS_SUCCESS) { 900 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 901 ms_set_err_code(chip, MS_NO_CARD); 902 rtsx_trace(chip); 903 return STATUS_FAIL; 904 } 905 continue; 906 } else { 907 break; 908 } 909 } 910 911 if (retval != STATUS_SUCCESS) { 912 rtsx_trace(chip); 913 return STATUS_FAIL; 914 } 915 916 /* Switch MS-PRO into Parallel mode */ 917 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); 918 if (retval) { 919 rtsx_trace(chip); 920 return retval; 921 } 922 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, 923 PUSH_TIME_ODD); 924 if (retval) { 925 rtsx_trace(chip); 926 return retval; 927 } 928 929 retval = ms_set_init_para(chip); 930 if (retval != STATUS_SUCCESS) { 931 rtsx_trace(chip); 932 return STATUS_FAIL; 933 } 934 935 /* If MSPro HG Card, We shall try to switch to 8-bit bus */ 936 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) { 937 retval = ms_switch_8bit_bus(chip); 938 if (retval != STATUS_SUCCESS) { 939 ms_card->switch_8bit_fail = 1; 940 rtsx_trace(chip); 941 return STATUS_FAIL; 942 } 943 } 944 945 return STATUS_SUCCESS; 946} 947 948#ifdef XC_POWERCLASS 949static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 950{ 951 int retval; 952 u8 buf[6]; 953 954 ms_cleanup_work(chip); 955 956 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 957 if (retval != STATUS_SUCCESS) { 958 rtsx_trace(chip); 959 return STATUS_FAIL; 960 } 961 962 buf[0] = 0; 963 buf[1] = mode; 964 buf[2] = 0; 965 buf[3] = 0; 966 buf[4] = 0; 967 buf[5] = 0; 968 969 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6); 970 if (retval != STATUS_SUCCESS) { 971 rtsx_trace(chip); 972 return STATUS_FAIL; 973 } 974 975 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT); 976 if (retval != STATUS_SUCCESS) { 977 rtsx_trace(chip); 978 return STATUS_FAIL; 979 } 980 981 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); 982 if (retval) { 983 rtsx_trace(chip); 984 return retval; 985 } 986 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) { 987 rtsx_trace(chip); 988 return STATUS_FAIL; 989 } 990 991 return STATUS_SUCCESS; 992} 993#endif 994 995static int ms_read_attribute_info(struct rtsx_chip *chip) 996{ 997 struct ms_info *ms_card = &(chip->ms_card); 998 int retval, i; 999 u8 val, *buf, class_code, device_type, sub_class, data[16]; 1000 u16 total_blk = 0, blk_size = 0; 1001#ifdef SUPPORT_MSXC 1002 u32 xc_total_blk = 0, xc_blk_size = 0; 1003#endif 1004 u32 sys_info_addr = 0, sys_info_size; 1005#ifdef SUPPORT_PCGL_1P18 1006 u32 model_name_addr = 0, model_name_size; 1007 int found_sys_info = 0, found_model_name = 0; 1008#endif 1009 1010 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7); 1011 if (retval != STATUS_SUCCESS) { 1012 rtsx_trace(chip); 1013 return STATUS_FAIL; 1014 } 1015 1016 if (CHK_MS8BIT(ms_card)) 1017 data[0] = PARALLEL_8BIT_IF; 1018 else 1019 data[0] = PARALLEL_4BIT_IF; 1020 1021 data[1] = 0; 1022 1023 data[2] = 0x40; 1024 data[3] = 0; 1025 data[4] = 0; 1026 data[5] = 0; 1027 data[6] = 0; 1028 data[7] = 0; 1029 1030 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1031 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, 1032 data, 8); 1033 if (retval == STATUS_SUCCESS) 1034 break; 1035 } 1036 if (retval != STATUS_SUCCESS) { 1037 rtsx_trace(chip); 1038 return STATUS_FAIL; 1039 } 1040 1041 buf = kmalloc(64 * 512, GFP_KERNEL); 1042 if (buf == NULL) { 1043 rtsx_trace(chip); 1044 return STATUS_ERROR; 1045 } 1046 1047 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1048 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT); 1049 if (retval != STATUS_SUCCESS) 1050 continue; 1051 1052 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1053 if (retval != STATUS_SUCCESS) { 1054 kfree(buf); 1055 rtsx_trace(chip); 1056 return STATUS_FAIL; 1057 } 1058 if (!(val & MS_INT_BREQ)) { 1059 kfree(buf); 1060 rtsx_trace(chip); 1061 return STATUS_FAIL; 1062 } 1063 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, 1064 PRO_READ_LONG_DATA, 0x40, WAIT_INT, 1065 0, 0, buf, 64 * 512); 1066 if (retval == STATUS_SUCCESS) 1067 break; 1068 1069 rtsx_clear_ms_error(chip); 1070 } 1071 if (retval != STATUS_SUCCESS) { 1072 kfree(buf); 1073 rtsx_trace(chip); 1074 return STATUS_FAIL; 1075 } 1076 1077 i = 0; 1078 do { 1079 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1080 if (retval != STATUS_SUCCESS) { 1081 kfree(buf); 1082 rtsx_trace(chip); 1083 return STATUS_FAIL; 1084 } 1085 1086 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) 1087 break; 1088 1089 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, 1090 PRO_READ_LONG_DATA, 0, WAIT_INT); 1091 if (retval != STATUS_SUCCESS) { 1092 kfree(buf); 1093 rtsx_trace(chip); 1094 return STATUS_FAIL; 1095 } 1096 1097 i++; 1098 } while (i < 1024); 1099 1100 if (retval != STATUS_SUCCESS) { 1101 kfree(buf); 1102 rtsx_trace(chip); 1103 return STATUS_FAIL; 1104 } 1105 1106 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) { 1107 /* Signature code is wrong */ 1108 kfree(buf); 1109 rtsx_trace(chip); 1110 return STATUS_FAIL; 1111 } 1112 1113 if ((buf[4] < 1) || (buf[4] > 12)) { 1114 kfree(buf); 1115 rtsx_trace(chip); 1116 return STATUS_FAIL; 1117 } 1118 1119 for (i = 0; i < buf[4]; i++) { 1120 int cur_addr_off = 16 + i * 12; 1121 1122#ifdef SUPPORT_MSXC 1123 if ((buf[cur_addr_off + 8] == 0x10) || 1124 (buf[cur_addr_off + 8] == 0x13)) 1125#else 1126 if (buf[cur_addr_off + 8] == 0x10) 1127#endif 1128 { 1129 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1130 ((u32)buf[cur_addr_off + 1] << 16) | 1131 ((u32)buf[cur_addr_off + 2] << 8) | 1132 buf[cur_addr_off + 3]; 1133 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) | 1134 ((u32)buf[cur_addr_off + 5] << 16) | 1135 ((u32)buf[cur_addr_off + 6] << 8) | 1136 buf[cur_addr_off + 7]; 1137 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n", 1138 sys_info_addr, sys_info_size); 1139 if (sys_info_size != 96) { 1140 kfree(buf); 1141 rtsx_trace(chip); 1142 return STATUS_FAIL; 1143 } 1144 if (sys_info_addr < 0x1A0) { 1145 kfree(buf); 1146 rtsx_trace(chip); 1147 return STATUS_FAIL; 1148 } 1149 if ((sys_info_size + sys_info_addr) > 0x8000) { 1150 kfree(buf); 1151 rtsx_trace(chip); 1152 return STATUS_FAIL; 1153 } 1154 1155#ifdef SUPPORT_MSXC 1156 if (buf[cur_addr_off + 8] == 0x13) 1157 ms_card->ms_type |= MS_XC; 1158#endif 1159#ifdef SUPPORT_PCGL_1P18 1160 found_sys_info = 1; 1161#else 1162 break; 1163#endif 1164 } 1165#ifdef SUPPORT_PCGL_1P18 1166 if (buf[cur_addr_off + 8] == 0x15) { 1167 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1168 ((u32)buf[cur_addr_off + 1] << 16) | 1169 ((u32)buf[cur_addr_off + 2] << 8) | 1170 buf[cur_addr_off + 3]; 1171 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) | 1172 ((u32)buf[cur_addr_off + 5] << 16) | 1173 ((u32)buf[cur_addr_off + 6] << 8) | 1174 buf[cur_addr_off + 7]; 1175 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n", 1176 model_name_addr, model_name_size); 1177 if (model_name_size != 48) { 1178 kfree(buf); 1179 rtsx_trace(chip); 1180 return STATUS_FAIL; 1181 } 1182 if (model_name_addr < 0x1A0) { 1183 kfree(buf); 1184 rtsx_trace(chip); 1185 return STATUS_FAIL; 1186 } 1187 if ((model_name_size + model_name_addr) > 0x8000) { 1188 kfree(buf); 1189 rtsx_trace(chip); 1190 return STATUS_FAIL; 1191 } 1192 1193 found_model_name = 1; 1194 } 1195 1196 if (found_sys_info && found_model_name) 1197 break; 1198#endif 1199 } 1200 1201 if (i == buf[4]) { 1202 kfree(buf); 1203 rtsx_trace(chip); 1204 return STATUS_FAIL; 1205 } 1206 1207 class_code = buf[sys_info_addr + 0]; 1208 device_type = buf[sys_info_addr + 56]; 1209 sub_class = buf[sys_info_addr + 46]; 1210#ifdef SUPPORT_MSXC 1211 if (CHK_MSXC(ms_card)) { 1212 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) | 1213 ((u32)buf[sys_info_addr + 7] << 16) | 1214 ((u32)buf[sys_info_addr + 8] << 8) | 1215 buf[sys_info_addr + 9]; 1216 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) | 1217 ((u32)buf[sys_info_addr + 33] << 16) | 1218 ((u32)buf[sys_info_addr + 34] << 8) | 1219 buf[sys_info_addr + 35]; 1220 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", 1221 xc_total_blk, xc_blk_size); 1222 } else { 1223 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | 1224 buf[sys_info_addr + 7]; 1225 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | 1226 buf[sys_info_addr + 3]; 1227 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1228 total_blk, blk_size); 1229 } 1230#else 1231 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7]; 1232 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3]; 1233 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1234 total_blk, blk_size); 1235#endif 1236 1237 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n", 1238 class_code, device_type, sub_class); 1239 1240 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96); 1241#ifdef SUPPORT_PCGL_1P18 1242 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48); 1243#endif 1244 1245 kfree(buf); 1246 1247#ifdef SUPPORT_MSXC 1248 if (CHK_MSXC(ms_card)) { 1249 if (class_code != 0x03) { 1250 rtsx_trace(chip); 1251 return STATUS_FAIL; 1252 } 1253 } else { 1254 if (class_code != 0x02) { 1255 rtsx_trace(chip); 1256 return STATUS_FAIL; 1257 } 1258 } 1259#else 1260 if (class_code != 0x02) { 1261 rtsx_trace(chip); 1262 return STATUS_FAIL; 1263 } 1264#endif 1265 1266 if (device_type != 0x00) { 1267 if ((device_type == 0x01) || (device_type == 0x02) || 1268 (device_type == 0x03)) { 1269 chip->card_wp |= MS_CARD; 1270 } else { 1271 rtsx_trace(chip); 1272 return STATUS_FAIL; 1273 } 1274 } 1275 1276 if (sub_class & 0xC0) { 1277 rtsx_trace(chip); 1278 return STATUS_FAIL; 1279 } 1280 1281 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n", 1282 class_code, device_type, sub_class); 1283 1284#ifdef SUPPORT_MSXC 1285 if (CHK_MSXC(ms_card)) { 1286 chip->capacity[chip->card2lun[MS_CARD]] = 1287 ms_card->capacity = xc_total_blk * xc_blk_size; 1288 } else { 1289 chip->capacity[chip->card2lun[MS_CARD]] = 1290 ms_card->capacity = total_blk * blk_size; 1291 } 1292#else 1293 ms_card->capacity = total_blk * blk_size; 1294 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 1295#endif 1296 1297 return STATUS_SUCCESS; 1298} 1299 1300#ifdef SUPPORT_MAGIC_GATE 1301static int mg_set_tpc_para_sub(struct rtsx_chip *chip, 1302 int type, u8 mg_entry_num); 1303#endif 1304 1305static int reset_ms_pro(struct rtsx_chip *chip) 1306{ 1307 struct ms_info *ms_card = &(chip->ms_card); 1308 int retval; 1309#ifdef XC_POWERCLASS 1310 u8 change_power_class; 1311 1312 if (chip->ms_power_class_en & 0x02) 1313 change_power_class = 2; 1314 else if (chip->ms_power_class_en & 0x01) 1315 change_power_class = 1; 1316 else 1317 change_power_class = 0; 1318#endif 1319 1320#ifdef XC_POWERCLASS 1321Retry: 1322#endif 1323 retval = ms_pro_reset_flow(chip, 1); 1324 if (retval != STATUS_SUCCESS) { 1325 if (ms_card->switch_8bit_fail) { 1326 retval = ms_pro_reset_flow(chip, 0); 1327 if (retval != STATUS_SUCCESS) { 1328 rtsx_trace(chip); 1329 return STATUS_FAIL; 1330 } 1331 } else { 1332 rtsx_trace(chip); 1333 return STATUS_FAIL; 1334 } 1335 } 1336 1337 retval = ms_read_attribute_info(chip); 1338 if (retval != STATUS_SUCCESS) { 1339 rtsx_trace(chip); 1340 return STATUS_FAIL; 1341 } 1342 1343#ifdef XC_POWERCLASS 1344 if (CHK_HG8BIT(ms_card)) 1345 change_power_class = 0; 1346 1347 if (change_power_class && CHK_MSXC(ms_card)) { 1348 u8 power_class_en = chip->ms_power_class_en; 1349 1350 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n", 1351 power_class_en); 1352 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n", 1353 change_power_class); 1354 1355 if (change_power_class) 1356 power_class_en &= (1 << (change_power_class - 1)); 1357 else 1358 power_class_en = 0; 1359 1360 if (power_class_en) { 1361 u8 power_class_mode = 1362 (ms_card->raw_sys_info[46] & 0x18) >> 3; 1363 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x", 1364 power_class_mode); 1365 if (change_power_class > power_class_mode) 1366 change_power_class = power_class_mode; 1367 if (change_power_class) { 1368 retval = msxc_change_power(chip, 1369 change_power_class); 1370 if (retval != STATUS_SUCCESS) { 1371 change_power_class--; 1372 goto Retry; 1373 } 1374 } 1375 } 1376 } 1377#endif 1378 1379#ifdef SUPPORT_MAGIC_GATE 1380 retval = mg_set_tpc_para_sub(chip, 0, 0); 1381 if (retval != STATUS_SUCCESS) { 1382 rtsx_trace(chip); 1383 return STATUS_FAIL; 1384 } 1385#endif 1386 1387 if (CHK_HG8BIT(ms_card)) 1388 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8; 1389 else 1390 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 1391 1392 return STATUS_SUCCESS; 1393} 1394 1395static int ms_read_status_reg(struct rtsx_chip *chip) 1396{ 1397 int retval; 1398 u8 val[2]; 1399 1400 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0); 1401 if (retval != STATUS_SUCCESS) { 1402 rtsx_trace(chip); 1403 return STATUS_FAIL; 1404 } 1405 1406 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); 1407 if (retval != STATUS_SUCCESS) { 1408 rtsx_trace(chip); 1409 return STATUS_FAIL; 1410 } 1411 1412 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { 1413 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1414 rtsx_trace(chip); 1415 return STATUS_FAIL; 1416 } 1417 1418 return STATUS_SUCCESS; 1419} 1420 1421 1422static int ms_read_extra_data(struct rtsx_chip *chip, 1423 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1424{ 1425 struct ms_info *ms_card = &(chip->ms_card); 1426 int retval, i; 1427 u8 val, data[10]; 1428 1429 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1430 SystemParm, 6); 1431 if (retval != STATUS_SUCCESS) { 1432 rtsx_trace(chip); 1433 return STATUS_FAIL; 1434 } 1435 1436 if (CHK_MS4BIT(ms_card)) { 1437 /* Parallel interface */ 1438 data[0] = 0x88; 1439 } else { 1440 /* Serial interface */ 1441 data[0] = 0x80; 1442 } 1443 data[1] = 0; 1444 data[2] = (u8)(block_addr >> 8); 1445 data[3] = (u8)block_addr; 1446 data[4] = 0x40; 1447 data[5] = page_num; 1448 1449 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1450 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1451 data, 6); 1452 if (retval == STATUS_SUCCESS) 1453 break; 1454 } 1455 if (i == MS_MAX_RETRY_COUNT) { 1456 rtsx_trace(chip); 1457 return STATUS_FAIL; 1458 } 1459 1460 ms_set_err_code(chip, MS_NO_ERROR); 1461 1462 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1463 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1464 if (retval == STATUS_SUCCESS) 1465 break; 1466 } 1467 if (i == MS_MAX_RETRY_COUNT) { 1468 rtsx_trace(chip); 1469 return STATUS_FAIL; 1470 } 1471 1472 ms_set_err_code(chip, MS_NO_ERROR); 1473 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1474 if (retval != STATUS_SUCCESS) { 1475 rtsx_trace(chip); 1476 return STATUS_FAIL; 1477 } 1478 1479 if (val & INT_REG_CMDNK) { 1480 ms_set_err_code(chip, MS_CMD_NK); 1481 rtsx_trace(chip); 1482 return STATUS_FAIL; 1483 } 1484 if (val & INT_REG_CED) { 1485 if (val & INT_REG_ERR) { 1486 retval = ms_read_status_reg(chip); 1487 if (retval != STATUS_SUCCESS) { 1488 rtsx_trace(chip); 1489 return STATUS_FAIL; 1490 } 1491 1492 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1493 MS_EXTRA_SIZE, SystemParm, 6); 1494 if (retval != STATUS_SUCCESS) { 1495 rtsx_trace(chip); 1496 return STATUS_FAIL; 1497 } 1498 } 1499 } 1500 1501 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, 1502 data, MS_EXTRA_SIZE); 1503 if (retval != STATUS_SUCCESS) { 1504 rtsx_trace(chip); 1505 return STATUS_FAIL; 1506 } 1507 1508 if (buf && buf_len) { 1509 if (buf_len > MS_EXTRA_SIZE) 1510 buf_len = MS_EXTRA_SIZE; 1511 memcpy(buf, data, buf_len); 1512 } 1513 1514 return STATUS_SUCCESS; 1515} 1516 1517static int ms_write_extra_data(struct rtsx_chip *chip, 1518 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1519{ 1520 struct ms_info *ms_card = &(chip->ms_card); 1521 int retval, i; 1522 u8 val, data[16]; 1523 1524 if (!buf || (buf_len < MS_EXTRA_SIZE)) { 1525 rtsx_trace(chip); 1526 return STATUS_FAIL; 1527 } 1528 1529 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1530 SystemParm, 6 + MS_EXTRA_SIZE); 1531 if (retval != STATUS_SUCCESS) { 1532 rtsx_trace(chip); 1533 return STATUS_FAIL; 1534 } 1535 1536 if (CHK_MS4BIT(ms_card)) 1537 data[0] = 0x88; 1538 else 1539 data[0] = 0x80; 1540 1541 data[1] = 0; 1542 data[2] = (u8)(block_addr >> 8); 1543 data[3] = (u8)block_addr; 1544 data[4] = 0x40; 1545 data[5] = page_num; 1546 1547 for (i = 6; i < MS_EXTRA_SIZE + 6; i++) 1548 data[i] = buf[i - 6]; 1549 1550 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1551 NO_WAIT_INT, data, 16); 1552 if (retval != STATUS_SUCCESS) { 1553 rtsx_trace(chip); 1554 return STATUS_FAIL; 1555 } 1556 1557 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1558 if (retval != STATUS_SUCCESS) { 1559 rtsx_trace(chip); 1560 return STATUS_FAIL; 1561 } 1562 1563 ms_set_err_code(chip, MS_NO_ERROR); 1564 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1565 if (retval != STATUS_SUCCESS) { 1566 rtsx_trace(chip); 1567 return STATUS_FAIL; 1568 } 1569 1570 if (val & INT_REG_CMDNK) { 1571 ms_set_err_code(chip, MS_CMD_NK); 1572 rtsx_trace(chip); 1573 return STATUS_FAIL; 1574 } 1575 if (val & INT_REG_CED) { 1576 if (val & INT_REG_ERR) { 1577 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1578 rtsx_trace(chip); 1579 return STATUS_FAIL; 1580 } 1581 } 1582 1583 return STATUS_SUCCESS; 1584} 1585 1586 1587static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num) 1588{ 1589 struct ms_info *ms_card = &(chip->ms_card); 1590 int retval; 1591 u8 val, data[6]; 1592 1593 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1594 SystemParm, 6); 1595 if (retval != STATUS_SUCCESS) { 1596 rtsx_trace(chip); 1597 return STATUS_FAIL; 1598 } 1599 1600 if (CHK_MS4BIT(ms_card)) 1601 data[0] = 0x88; 1602 else 1603 data[0] = 0x80; 1604 1605 data[1] = 0; 1606 data[2] = (u8)(block_addr >> 8); 1607 data[3] = (u8)block_addr; 1608 data[4] = 0x20; 1609 data[5] = page_num; 1610 1611 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1612 if (retval != STATUS_SUCCESS) { 1613 rtsx_trace(chip); 1614 return STATUS_FAIL; 1615 } 1616 1617 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1618 if (retval != STATUS_SUCCESS) { 1619 rtsx_trace(chip); 1620 return STATUS_FAIL; 1621 } 1622 1623 ms_set_err_code(chip, MS_NO_ERROR); 1624 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1625 if (retval != STATUS_SUCCESS) { 1626 rtsx_trace(chip); 1627 return STATUS_FAIL; 1628 } 1629 1630 if (val & INT_REG_CMDNK) { 1631 ms_set_err_code(chip, MS_CMD_NK); 1632 rtsx_trace(chip); 1633 return STATUS_FAIL; 1634 } 1635 1636 if (val & INT_REG_CED) { 1637 if (val & INT_REG_ERR) { 1638 if (!(val & INT_REG_BREQ)) { 1639 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1640 rtsx_trace(chip); 1641 return STATUS_FAIL; 1642 } 1643 retval = ms_read_status_reg(chip); 1644 if (retval != STATUS_SUCCESS) 1645 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1646 1647 } else { 1648 if (!(val & INT_REG_BREQ)) { 1649 ms_set_err_code(chip, MS_BREQ_ERROR); 1650 rtsx_trace(chip); 1651 return STATUS_FAIL; 1652 } 1653 } 1654 } 1655 1656 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 1657 0, NO_WAIT_INT); 1658 if (retval != STATUS_SUCCESS) { 1659 rtsx_trace(chip); 1660 return STATUS_FAIL; 1661 } 1662 1663 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 1664 rtsx_trace(chip); 1665 return STATUS_FAIL; 1666 } 1667 1668 return STATUS_SUCCESS; 1669} 1670 1671 1672static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk) 1673{ 1674 struct ms_info *ms_card = &(chip->ms_card); 1675 int retval; 1676 u8 val, data[8], extra[MS_EXTRA_SIZE]; 1677 1678 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE); 1679 if (retval != STATUS_SUCCESS) { 1680 rtsx_trace(chip); 1681 return STATUS_FAIL; 1682 } 1683 1684 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1685 SystemParm, 7); 1686 if (retval != STATUS_SUCCESS) { 1687 rtsx_trace(chip); 1688 return STATUS_FAIL; 1689 } 1690 1691 ms_set_err_code(chip, MS_NO_ERROR); 1692 1693 if (CHK_MS4BIT(ms_card)) 1694 data[0] = 0x88; 1695 else 1696 data[0] = 0x80; 1697 1698 data[1] = 0; 1699 data[2] = (u8)(phy_blk >> 8); 1700 data[3] = (u8)phy_blk; 1701 data[4] = 0x80; 1702 data[5] = 0; 1703 data[6] = extra[0] & 0x7F; 1704 data[7] = 0xFF; 1705 1706 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7); 1707 if (retval != STATUS_SUCCESS) { 1708 rtsx_trace(chip); 1709 return STATUS_FAIL; 1710 } 1711 1712 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1713 if (retval != STATUS_SUCCESS) { 1714 rtsx_trace(chip); 1715 return STATUS_FAIL; 1716 } 1717 1718 ms_set_err_code(chip, MS_NO_ERROR); 1719 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1720 if (retval != STATUS_SUCCESS) { 1721 rtsx_trace(chip); 1722 return STATUS_FAIL; 1723 } 1724 1725 if (val & INT_REG_CMDNK) { 1726 ms_set_err_code(chip, MS_CMD_NK); 1727 rtsx_trace(chip); 1728 return STATUS_FAIL; 1729 } 1730 1731 if (val & INT_REG_CED) { 1732 if (val & INT_REG_ERR) { 1733 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1734 rtsx_trace(chip); 1735 return STATUS_FAIL; 1736 } 1737 } 1738 1739 return STATUS_SUCCESS; 1740} 1741 1742 1743static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk) 1744{ 1745 struct ms_info *ms_card = &(chip->ms_card); 1746 int retval, i = 0; 1747 u8 val, data[6]; 1748 1749 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1750 SystemParm, 6); 1751 if (retval != STATUS_SUCCESS) { 1752 rtsx_trace(chip); 1753 return STATUS_FAIL; 1754 } 1755 1756 ms_set_err_code(chip, MS_NO_ERROR); 1757 1758 if (CHK_MS4BIT(ms_card)) 1759 data[0] = 0x88; 1760 else 1761 data[0] = 0x80; 1762 1763 data[1] = 0; 1764 data[2] = (u8)(phy_blk >> 8); 1765 data[3] = (u8)phy_blk; 1766 data[4] = 0; 1767 data[5] = 0; 1768 1769 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1770 if (retval != STATUS_SUCCESS) { 1771 rtsx_trace(chip); 1772 return STATUS_FAIL; 1773 } 1774 1775ERASE_RTY: 1776 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT); 1777 if (retval != STATUS_SUCCESS) { 1778 rtsx_trace(chip); 1779 return STATUS_FAIL; 1780 } 1781 1782 ms_set_err_code(chip, MS_NO_ERROR); 1783 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1784 if (retval != STATUS_SUCCESS) { 1785 rtsx_trace(chip); 1786 return STATUS_FAIL; 1787 } 1788 1789 if (val & INT_REG_CMDNK) { 1790 if (i < 3) { 1791 i++; 1792 goto ERASE_RTY; 1793 } 1794 1795 ms_set_err_code(chip, MS_CMD_NK); 1796 ms_set_bad_block(chip, phy_blk); 1797 rtsx_trace(chip); 1798 return STATUS_FAIL; 1799 } 1800 1801 if (val & INT_REG_CED) { 1802 if (val & INT_REG_ERR) { 1803 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1804 rtsx_trace(chip); 1805 return STATUS_FAIL; 1806 } 1807 } 1808 1809 return STATUS_SUCCESS; 1810} 1811 1812 1813static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len) 1814{ 1815 if (!extra || (extra_len < MS_EXTRA_SIZE)) 1816 return; 1817 1818 memset(extra, 0xFF, MS_EXTRA_SIZE); 1819 1820 if (type == setPS_NG) { 1821 /* set page status as 1:NG,and block status keep 1:OK */ 1822 extra[0] = 0xB8; 1823 } else { 1824 /* set page status as 0:Data Error,and block status keep 1:OK */ 1825 extra[0] = 0x98; 1826 } 1827 1828 extra[2] = (u8)(log_blk >> 8); 1829 extra[3] = (u8)log_blk; 1830} 1831 1832static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, 1833 u8 start_page, u8 end_page) 1834{ 1835 int retval; 1836 u8 extra[MS_EXTRA_SIZE], i; 1837 1838 memset(extra, 0xff, MS_EXTRA_SIZE); 1839 1840 extra[0] = 0xf8; /* Block, page OK, data erased */ 1841 extra[1] = 0xff; 1842 extra[2] = (u8)(log_blk >> 8); 1843 extra[3] = (u8)log_blk; 1844 1845 for (i = start_page; i < end_page; i++) { 1846 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1847 ms_set_err_code(chip, MS_NO_CARD); 1848 rtsx_trace(chip); 1849 return STATUS_FAIL; 1850 } 1851 1852 retval = ms_write_extra_data(chip, phy_blk, i, 1853 extra, MS_EXTRA_SIZE); 1854 if (retval != STATUS_SUCCESS) { 1855 rtsx_trace(chip); 1856 return STATUS_FAIL; 1857 } 1858 } 1859 1860 return STATUS_SUCCESS; 1861} 1862 1863static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 1864 u16 log_blk, u8 start_page, u8 end_page) 1865{ 1866 struct ms_info *ms_card = &(chip->ms_card); 1867 bool uncorrect_flag = false; 1868 int retval, rty_cnt; 1869 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; 1870 1871 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n", 1872 old_blk, new_blk, log_blk); 1873 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n", 1874 start_page, end_page); 1875 1876 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE); 1877 if (retval != STATUS_SUCCESS) { 1878 rtsx_trace(chip); 1879 return STATUS_FAIL; 1880 } 1881 1882 retval = ms_read_status_reg(chip); 1883 if (retval != STATUS_SUCCESS) { 1884 rtsx_trace(chip); 1885 return STATUS_FAIL; 1886 } 1887 1888 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1889 if (retval) { 1890 rtsx_trace(chip); 1891 return retval; 1892 } 1893 1894 if (val & BUF_FULL) { 1895 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); 1896 if (retval != STATUS_SUCCESS) { 1897 rtsx_trace(chip); 1898 return STATUS_FAIL; 1899 } 1900 1901 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1902 if (retval != STATUS_SUCCESS) { 1903 rtsx_trace(chip); 1904 return STATUS_FAIL; 1905 } 1906 1907 if (!(val & INT_REG_CED)) { 1908 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1909 rtsx_trace(chip); 1910 return STATUS_FAIL; 1911 } 1912 } 1913 1914 for (i = start_page; i < end_page; i++) { 1915 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1916 ms_set_err_code(chip, MS_NO_CARD); 1917 rtsx_trace(chip); 1918 return STATUS_FAIL; 1919 } 1920 1921 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE); 1922 1923 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1924 MS_EXTRA_SIZE, SystemParm, 6); 1925 if (retval != STATUS_SUCCESS) { 1926 rtsx_trace(chip); 1927 return STATUS_FAIL; 1928 } 1929 1930 ms_set_err_code(chip, MS_NO_ERROR); 1931 1932 if (CHK_MS4BIT(ms_card)) 1933 data[0] = 0x88; 1934 else 1935 data[0] = 0x80; 1936 1937 data[1] = 0; 1938 data[2] = (u8)(old_blk >> 8); 1939 data[3] = (u8)old_blk; 1940 data[4] = 0x20; 1941 data[5] = i; 1942 1943 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1944 data, 6); 1945 if (retval != STATUS_SUCCESS) { 1946 rtsx_trace(chip); 1947 return STATUS_FAIL; 1948 } 1949 1950 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1951 if (retval != STATUS_SUCCESS) { 1952 rtsx_trace(chip); 1953 return STATUS_FAIL; 1954 } 1955 1956 ms_set_err_code(chip, MS_NO_ERROR); 1957 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1958 if (retval != STATUS_SUCCESS) { 1959 rtsx_trace(chip); 1960 return STATUS_FAIL; 1961 } 1962 1963 if (val & INT_REG_CMDNK) { 1964 ms_set_err_code(chip, MS_CMD_NK); 1965 rtsx_trace(chip); 1966 return STATUS_FAIL; 1967 } 1968 1969 if (val & INT_REG_CED) { 1970 if (val & INT_REG_ERR) { 1971 retval = ms_read_status_reg(chip); 1972 if (retval != STATUS_SUCCESS) { 1973 uncorrect_flag = true; 1974 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n"); 1975 } else { 1976 uncorrect_flag = false; 1977 } 1978 1979 retval = ms_transfer_tpc(chip, 1980 MS_TM_NORMAL_READ, 1981 READ_PAGE_DATA, 1982 0, NO_WAIT_INT); 1983 if (retval != STATUS_SUCCESS) { 1984 rtsx_trace(chip); 1985 return STATUS_FAIL; 1986 } 1987 1988 if (uncorrect_flag) { 1989 ms_set_page_status(log_blk, setPS_NG, 1990 extra, MS_EXTRA_SIZE); 1991 if (i == 0) 1992 extra[0] &= 0xEF; 1993 1994 ms_write_extra_data(chip, old_blk, i, 1995 extra, MS_EXTRA_SIZE); 1996 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n", 1997 i, extra[0]); 1998 MS_SET_BAD_BLOCK_FLG(ms_card); 1999 2000 ms_set_page_status(log_blk, setPS_Error, 2001 extra, MS_EXTRA_SIZE); 2002 ms_write_extra_data(chip, new_blk, i, 2003 extra, MS_EXTRA_SIZE); 2004 continue; 2005 } 2006 2007 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; 2008 rty_cnt++) { 2009 retval = ms_transfer_tpc( 2010 chip, 2011 MS_TM_NORMAL_WRITE, 2012 WRITE_PAGE_DATA, 2013 0, NO_WAIT_INT); 2014 if (retval == STATUS_SUCCESS) 2015 break; 2016 } 2017 if (rty_cnt == MS_MAX_RETRY_COUNT) { 2018 rtsx_trace(chip); 2019 return STATUS_FAIL; 2020 } 2021 } 2022 2023 if (!(val & INT_REG_BREQ)) { 2024 ms_set_err_code(chip, MS_BREQ_ERROR); 2025 rtsx_trace(chip); 2026 return STATUS_FAIL; 2027 } 2028 } 2029 2030 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2031 MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE)); 2032 2033 ms_set_err_code(chip, MS_NO_ERROR); 2034 2035 if (CHK_MS4BIT(ms_card)) 2036 data[0] = 0x88; 2037 else 2038 data[0] = 0x80; 2039 2040 data[1] = 0; 2041 data[2] = (u8)(new_blk >> 8); 2042 data[3] = (u8)new_blk; 2043 data[4] = 0x20; 2044 data[5] = i; 2045 2046 if ((extra[0] & 0x60) != 0x60) 2047 data[6] = extra[0]; 2048 else 2049 data[6] = 0xF8; 2050 2051 data[6 + 1] = 0xFF; 2052 data[6 + 2] = (u8)(log_blk >> 8); 2053 data[6 + 3] = (u8)log_blk; 2054 2055 for (j = 4; j <= MS_EXTRA_SIZE; j++) 2056 data[6 + j] = 0xFF; 2057 2058 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 2059 NO_WAIT_INT, data, 16); 2060 if (retval != STATUS_SUCCESS) { 2061 rtsx_trace(chip); 2062 return STATUS_FAIL; 2063 } 2064 2065 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2066 if (retval != STATUS_SUCCESS) { 2067 rtsx_trace(chip); 2068 return STATUS_FAIL; 2069 } 2070 2071 ms_set_err_code(chip, MS_NO_ERROR); 2072 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 2073 if (retval != STATUS_SUCCESS) { 2074 rtsx_trace(chip); 2075 return STATUS_FAIL; 2076 } 2077 2078 if (val & INT_REG_CMDNK) { 2079 ms_set_err_code(chip, MS_CMD_NK); 2080 rtsx_trace(chip); 2081 return STATUS_FAIL; 2082 } 2083 2084 if (val & INT_REG_CED) { 2085 if (val & INT_REG_ERR) { 2086 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 2087 rtsx_trace(chip); 2088 return STATUS_FAIL; 2089 } 2090 } 2091 2092 if (i == 0) { 2093 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2094 MS_EXTRA_SIZE, SystemParm, 7); 2095 if (retval != STATUS_SUCCESS) { 2096 rtsx_trace(chip); 2097 return STATUS_FAIL; 2098 } 2099 2100 ms_set_err_code(chip, MS_NO_ERROR); 2101 2102 if (CHK_MS4BIT(ms_card)) 2103 data[0] = 0x88; 2104 else 2105 data[0] = 0x80; 2106 2107 data[1] = 0; 2108 data[2] = (u8)(old_blk >> 8); 2109 data[3] = (u8)old_blk; 2110 data[4] = 0x80; 2111 data[5] = 0; 2112 data[6] = 0xEF; 2113 data[7] = 0xFF; 2114 2115 retval = ms_write_bytes(chip, WRITE_REG, 7, 2116 NO_WAIT_INT, data, 8); 2117 if (retval != STATUS_SUCCESS) { 2118 rtsx_trace(chip); 2119 return STATUS_FAIL; 2120 } 2121 2122 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2123 if (retval != STATUS_SUCCESS) { 2124 rtsx_trace(chip); 2125 return STATUS_FAIL; 2126 } 2127 2128 ms_set_err_code(chip, MS_NO_ERROR); 2129 retval = ms_read_bytes(chip, GET_INT, 1, 2130 NO_WAIT_INT, &val, 1); 2131 if (retval != STATUS_SUCCESS) { 2132 rtsx_trace(chip); 2133 return STATUS_FAIL; 2134 } 2135 2136 if (val & INT_REG_CMDNK) { 2137 ms_set_err_code(chip, MS_CMD_NK); 2138 rtsx_trace(chip); 2139 return STATUS_FAIL; 2140 } 2141 2142 if (val & INT_REG_CED) { 2143 if (val & INT_REG_ERR) { 2144 ms_set_err_code(chip, 2145 MS_FLASH_WRITE_ERROR); 2146 rtsx_trace(chip); 2147 return STATUS_FAIL; 2148 } 2149 } 2150 } 2151 } 2152 2153 return STATUS_SUCCESS; 2154} 2155 2156 2157static int reset_ms(struct rtsx_chip *chip) 2158{ 2159 struct ms_info *ms_card = &(chip->ms_card); 2160 int retval; 2161 u16 i, reg_addr, block_size; 2162 u8 val, extra[MS_EXTRA_SIZE], j, *ptr; 2163#ifndef SUPPORT_MAGIC_GATE 2164 u16 eblock_cnt; 2165#endif 2166 2167 retval = ms_prepare_reset(chip); 2168 if (retval != STATUS_SUCCESS) { 2169 rtsx_trace(chip); 2170 return STATUS_FAIL; 2171 } 2172 2173 ms_card->ms_type |= TYPE_MS; 2174 2175 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT); 2176 if (retval != STATUS_SUCCESS) { 2177 rtsx_trace(chip); 2178 return STATUS_FAIL; 2179 } 2180 2181 retval = ms_read_status_reg(chip); 2182 if (retval != STATUS_SUCCESS) { 2183 rtsx_trace(chip); 2184 return STATUS_FAIL; 2185 } 2186 2187 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 2188 if (retval) { 2189 rtsx_trace(chip); 2190 return retval; 2191 } 2192 if (val & WRT_PRTCT) 2193 chip->card_wp |= MS_CARD; 2194 else 2195 chip->card_wp &= ~MS_CARD; 2196 2197 i = 0; 2198 2199RE_SEARCH: 2200 /* Search Boot Block */ 2201 while (i < (MAX_DEFECTIVE_BLOCK + 2)) { 2202 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 2203 ms_set_err_code(chip, MS_NO_CARD); 2204 rtsx_trace(chip); 2205 return STATUS_FAIL; 2206 } 2207 2208 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE); 2209 if (retval != STATUS_SUCCESS) { 2210 i++; 2211 continue; 2212 } 2213 2214 if (extra[0] & BLOCK_OK) { 2215 if (!(extra[1] & NOT_BOOT_BLOCK)) { 2216 ms_card->boot_block = i; 2217 break; 2218 } 2219 } 2220 i++; 2221 } 2222 2223 if (i == (MAX_DEFECTIVE_BLOCK + 2)) { 2224 dev_dbg(rtsx_dev(chip), "No boot block found!"); 2225 rtsx_trace(chip); 2226 return STATUS_FAIL; 2227 } 2228 2229 for (j = 0; j < 3; j++) { 2230 retval = ms_read_page(chip, ms_card->boot_block, j); 2231 if (retval != STATUS_SUCCESS) { 2232 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 2233 i = ms_card->boot_block + 1; 2234 ms_set_err_code(chip, MS_NO_ERROR); 2235 goto RE_SEARCH; 2236 } 2237 } 2238 } 2239 2240 retval = ms_read_page(chip, ms_card->boot_block, 0); 2241 if (retval != STATUS_SUCCESS) { 2242 rtsx_trace(chip); 2243 return STATUS_FAIL; 2244 } 2245 2246 /* Read MS system information as sys_info */ 2247 rtsx_init_cmd(chip); 2248 2249 for (i = 0; i < 96; i++) 2250 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0); 2251 2252 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2253 if (retval < 0) { 2254 rtsx_trace(chip); 2255 return STATUS_FAIL; 2256 } 2257 2258 ptr = rtsx_get_cmd_data(chip); 2259 memcpy(ms_card->raw_sys_info, ptr, 96); 2260 2261 /* Read useful block contents */ 2262 rtsx_init_cmd(chip); 2263 2264 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0); 2265 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0); 2266 2267 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; 2268 reg_addr++) 2269 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2270 2271 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) 2272 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2273 2274 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0); 2275 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0); 2276 2277 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2278 if (retval < 0) { 2279 rtsx_trace(chip); 2280 return STATUS_FAIL; 2281 } 2282 2283 ptr = rtsx_get_cmd_data(chip); 2284 2285 dev_dbg(rtsx_dev(chip), "Boot block data:\n"); 2286 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr); 2287 2288 /* Block ID error 2289 * HEADER_ID0, HEADER_ID1 2290 */ 2291 if (ptr[0] != 0x00 || ptr[1] != 0x01) { 2292 i = ms_card->boot_block + 1; 2293 goto RE_SEARCH; 2294 } 2295 2296 /* Page size error 2297 * PAGE_SIZE_0, PAGE_SIZE_1 2298 */ 2299 if (ptr[12] != 0x02 || ptr[13] != 0x00) { 2300 i = ms_card->boot_block + 1; 2301 goto RE_SEARCH; 2302 } 2303 2304 if ((ptr[14] == 1) || (ptr[14] == 3)) 2305 chip->card_wp |= MS_CARD; 2306 2307 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */ 2308 block_size = ((u16)ptr[6] << 8) | ptr[7]; 2309 if (block_size == 0x0010) { 2310 /* Block size 16KB */ 2311 ms_card->block_shift = 5; 2312 ms_card->page_off = 0x1F; 2313 } else if (block_size == 0x0008) { 2314 /* Block size 8KB */ 2315 ms_card->block_shift = 4; 2316 ms_card->page_off = 0x0F; 2317 } 2318 2319 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */ 2320 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9]; 2321 2322#ifdef SUPPORT_MAGIC_GATE 2323 j = ptr[10]; 2324 2325 if (ms_card->block_shift == 4) { /* 4MB or 8MB */ 2326 if (j < 2) { /* Effective block for 4MB: 0x1F0 */ 2327 ms_card->capacity = 0x1EE0; 2328 } else { /* Effective block for 8MB: 0x3E0 */ 2329 ms_card->capacity = 0x3DE0; 2330 } 2331 } else { /* 16MB, 32MB, 64MB or 128MB */ 2332 if (j < 5) { /* Effective block for 16MB: 0x3E0 */ 2333 ms_card->capacity = 0x7BC0; 2334 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */ 2335 ms_card->capacity = 0xF7C0; 2336 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */ 2337 ms_card->capacity = 0x1EF80; 2338 } else { /* Effective block for 128MB: 0x1F00 */ 2339 ms_card->capacity = 0x3DF00; 2340 } 2341 } 2342#else 2343 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */ 2344 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11]; 2345 2346 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift; 2347#endif 2348 2349 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 2350 2351 /* Switch I/F Mode */ 2352 if (ptr[15]) { 2353 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1); 2354 if (retval != STATUS_SUCCESS) { 2355 rtsx_trace(chip); 2356 return STATUS_FAIL; 2357 } 2358 2359 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); 2360 if (retval) { 2361 rtsx_trace(chip); 2362 return retval; 2363 } 2364 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); 2365 if (retval) { 2366 rtsx_trace(chip); 2367 return retval; 2368 } 2369 2370 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, 2371 NO_WAIT_INT); 2372 if (retval != STATUS_SUCCESS) { 2373 rtsx_trace(chip); 2374 return STATUS_FAIL; 2375 } 2376 2377 retval = rtsx_write_register(chip, MS_CFG, 2378 0x58 | MS_NO_CHECK_INT, 2379 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT); 2380 if (retval) { 2381 rtsx_trace(chip); 2382 return retval; 2383 } 2384 2385 ms_card->ms_type |= MS_4BIT; 2386 } 2387 2388 if (CHK_MS4BIT(ms_card)) 2389 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 2390 else 2391 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1; 2392 2393 return STATUS_SUCCESS; 2394} 2395 2396static int ms_init_l2p_tbl(struct rtsx_chip *chip) 2397{ 2398 struct ms_info *ms_card = &(chip->ms_card); 2399 int size, i, seg_no, retval; 2400 u16 defect_block, reg_addr; 2401 u8 val1, val2; 2402 2403 ms_card->segment_cnt = ms_card->total_block >> 9; 2404 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n", 2405 ms_card->segment_cnt); 2406 2407 size = ms_card->segment_cnt * sizeof(struct zone_entry); 2408 ms_card->segment = vzalloc(size); 2409 if (ms_card->segment == NULL) { 2410 rtsx_trace(chip); 2411 return STATUS_FAIL; 2412 } 2413 2414 retval = ms_read_page(chip, ms_card->boot_block, 1); 2415 if (retval != STATUS_SUCCESS) { 2416 rtsx_trace(chip); 2417 goto INIT_FAIL; 2418 } 2419 2420 reg_addr = PPBUF_BASE2; 2421 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) { 2422 int block_no; 2423 2424 retval = rtsx_read_register(chip, reg_addr++, &val1); 2425 if (retval != STATUS_SUCCESS) { 2426 rtsx_trace(chip); 2427 goto INIT_FAIL; 2428 } 2429 2430 retval = rtsx_read_register(chip, reg_addr++, &val2); 2431 if (retval != STATUS_SUCCESS) { 2432 rtsx_trace(chip); 2433 goto INIT_FAIL; 2434 } 2435 2436 defect_block = ((u16)val1 << 8) | val2; 2437 if (defect_block == 0xFFFF) 2438 break; 2439 2440 seg_no = defect_block / 512; 2441 2442 block_no = ms_card->segment[seg_no].disable_count++; 2443 ms_card->segment[seg_no].defect_list[block_no] = defect_block; 2444 } 2445 2446 for (i = 0; i < ms_card->segment_cnt; i++) { 2447 ms_card->segment[i].build_flag = 0; 2448 ms_card->segment[i].l2p_table = NULL; 2449 ms_card->segment[i].free_table = NULL; 2450 ms_card->segment[i].get_index = 0; 2451 ms_card->segment[i].set_index = 0; 2452 ms_card->segment[i].unused_blk_cnt = 0; 2453 2454 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n", 2455 i, ms_card->segment[i].disable_count); 2456 } 2457 2458 return STATUS_SUCCESS; 2459 2460INIT_FAIL: 2461 if (ms_card->segment) { 2462 vfree(ms_card->segment); 2463 ms_card->segment = NULL; 2464 } 2465 2466 return STATUS_FAIL; 2467} 2468 2469static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off) 2470{ 2471 struct ms_info *ms_card = &(chip->ms_card); 2472 struct zone_entry *segment; 2473 2474 if (ms_card->segment == NULL) 2475 return 0xFFFF; 2476 2477 segment = &(ms_card->segment[seg_no]); 2478 2479 if (segment->l2p_table) 2480 return segment->l2p_table[log_off]; 2481 2482 return 0xFFFF; 2483} 2484 2485static void ms_set_l2p_tbl(struct rtsx_chip *chip, 2486 int seg_no, u16 log_off, u16 phy_blk) 2487{ 2488 struct ms_info *ms_card = &(chip->ms_card); 2489 struct zone_entry *segment; 2490 2491 if (ms_card->segment == NULL) 2492 return; 2493 2494 segment = &(ms_card->segment[seg_no]); 2495 if (segment->l2p_table) 2496 segment->l2p_table[log_off] = phy_blk; 2497} 2498 2499static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk) 2500{ 2501 struct ms_info *ms_card = &(chip->ms_card); 2502 struct zone_entry *segment; 2503 int seg_no; 2504 2505 seg_no = (int)phy_blk >> 9; 2506 segment = &(ms_card->segment[seg_no]); 2507 2508 segment->free_table[segment->set_index++] = phy_blk; 2509 if (segment->set_index >= MS_FREE_TABLE_CNT) 2510 segment->set_index = 0; 2511 2512 segment->unused_blk_cnt++; 2513} 2514 2515static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no) 2516{ 2517 struct ms_info *ms_card = &(chip->ms_card); 2518 struct zone_entry *segment; 2519 u16 phy_blk; 2520 2521 segment = &(ms_card->segment[seg_no]); 2522 2523 if (segment->unused_blk_cnt <= 0) 2524 return 0xFFFF; 2525 2526 phy_blk = segment->free_table[segment->get_index]; 2527 segment->free_table[segment->get_index++] = 0xFFFF; 2528 if (segment->get_index >= MS_FREE_TABLE_CNT) 2529 segment->get_index = 0; 2530 2531 segment->unused_blk_cnt--; 2532 2533 return phy_blk; 2534} 2535 2536static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2537 2974, 3470, 3966, 4462, 4958, 2538 5454, 5950, 6446, 6942, 7438, 2539 7934}; 2540 2541static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, 2542 u16 log_off, u8 us1, u8 us2) 2543{ 2544 struct ms_info *ms_card = &(chip->ms_card); 2545 struct zone_entry *segment; 2546 int seg_no; 2547 u16 tmp_blk; 2548 2549 seg_no = (int)phy_blk >> 9; 2550 segment = &(ms_card->segment[seg_no]); 2551 tmp_blk = segment->l2p_table[log_off]; 2552 2553 if (us1 != us2) { 2554 if (us1 == 0) { 2555 if (!(chip->card_wp & MS_CARD)) 2556 ms_erase_block(chip, tmp_blk); 2557 2558 ms_set_unused_block(chip, tmp_blk); 2559 segment->l2p_table[log_off] = phy_blk; 2560 } else { 2561 if (!(chip->card_wp & MS_CARD)) 2562 ms_erase_block(chip, phy_blk); 2563 2564 ms_set_unused_block(chip, phy_blk); 2565 } 2566 } else { 2567 if (phy_blk < tmp_blk) { 2568 if (!(chip->card_wp & MS_CARD)) 2569 ms_erase_block(chip, phy_blk); 2570 2571 ms_set_unused_block(chip, phy_blk); 2572 } else { 2573 if (!(chip->card_wp & MS_CARD)) 2574 ms_erase_block(chip, tmp_blk); 2575 2576 ms_set_unused_block(chip, tmp_blk); 2577 segment->l2p_table[log_off] = phy_blk; 2578 } 2579 } 2580 2581 return STATUS_SUCCESS; 2582} 2583 2584static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no) 2585{ 2586 struct ms_info *ms_card = &(chip->ms_card); 2587 struct zone_entry *segment; 2588 bool defect_flag; 2589 int retval, table_size, disable_cnt, i; 2590 u16 start, end, phy_blk, log_blk, tmp_blk, idx; 2591 u8 extra[MS_EXTRA_SIZE], us1, us2; 2592 2593 dev_dbg(rtsx_dev(chip), "ms_build_l2p_tbl: %d\n", seg_no); 2594 2595 if (ms_card->segment == NULL) { 2596 retval = ms_init_l2p_tbl(chip); 2597 if (retval != STATUS_SUCCESS) { 2598 rtsx_trace(chip); 2599 return retval; 2600 } 2601 } 2602 2603 if (ms_card->segment[seg_no].build_flag) { 2604 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n", 2605 seg_no); 2606 return STATUS_SUCCESS; 2607 } 2608 2609 if (seg_no == 0) 2610 table_size = 494; 2611 else 2612 table_size = 496; 2613 2614 segment = &(ms_card->segment[seg_no]); 2615 2616 if (segment->l2p_table == NULL) { 2617 segment->l2p_table = vmalloc(table_size * 2); 2618 if (segment->l2p_table == NULL) { 2619 rtsx_trace(chip); 2620 goto BUILD_FAIL; 2621 } 2622 } 2623 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2); 2624 2625 if (segment->free_table == NULL) { 2626 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2); 2627 if (segment->free_table == NULL) { 2628 rtsx_trace(chip); 2629 goto BUILD_FAIL; 2630 } 2631 } 2632 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2); 2633 2634 start = (u16)seg_no << 9; 2635 end = (u16)(seg_no + 1) << 9; 2636 2637 disable_cnt = segment->disable_count; 2638 2639 segment->get_index = segment->set_index = 0; 2640 segment->unused_blk_cnt = 0; 2641 2642 for (phy_blk = start; phy_blk < end; phy_blk++) { 2643 if (disable_cnt) { 2644 defect_flag = false; 2645 for (i = 0; i < segment->disable_count; i++) { 2646 if (phy_blk == segment->defect_list[i]) { 2647 defect_flag = true; 2648 break; 2649 } 2650 } 2651 if (defect_flag) { 2652 disable_cnt--; 2653 continue; 2654 } 2655 } 2656 2657 retval = ms_read_extra_data(chip, phy_blk, 0, 2658 extra, MS_EXTRA_SIZE); 2659 if (retval != STATUS_SUCCESS) { 2660 dev_dbg(rtsx_dev(chip), "read extra data fail\n"); 2661 ms_set_bad_block(chip, phy_blk); 2662 continue; 2663 } 2664 2665 if (seg_no == ms_card->segment_cnt - 1) { 2666 if (!(extra[1] & NOT_TRANSLATION_TABLE)) { 2667 if (!(chip->card_wp & MS_CARD)) { 2668 retval = ms_erase_block(chip, phy_blk); 2669 if (retval != STATUS_SUCCESS) 2670 continue; 2671 extra[2] = 0xff; 2672 extra[3] = 0xff; 2673 } 2674 } 2675 } 2676 2677 if (!(extra[0] & BLOCK_OK)) 2678 continue; 2679 if (!(extra[1] & NOT_BOOT_BLOCK)) 2680 continue; 2681 if ((extra[0] & PAGE_OK) != PAGE_OK) 2682 continue; 2683 2684 log_blk = ((u16)extra[2] << 8) | extra[3]; 2685 2686 if (log_blk == 0xFFFF) { 2687 if (!(chip->card_wp & MS_CARD)) { 2688 retval = ms_erase_block(chip, phy_blk); 2689 if (retval != STATUS_SUCCESS) 2690 continue; 2691 } 2692 ms_set_unused_block(chip, phy_blk); 2693 continue; 2694 } 2695 2696 if ((log_blk < ms_start_idx[seg_no]) || 2697 (log_blk >= ms_start_idx[seg_no+1])) { 2698 if (!(chip->card_wp & MS_CARD)) { 2699 retval = ms_erase_block(chip, phy_blk); 2700 if (retval != STATUS_SUCCESS) 2701 continue; 2702 } 2703 ms_set_unused_block(chip, phy_blk); 2704 continue; 2705 } 2706 2707 idx = log_blk - ms_start_idx[seg_no]; 2708 2709 if (segment->l2p_table[idx] == 0xFFFF) { 2710 segment->l2p_table[idx] = phy_blk; 2711 continue; 2712 } 2713 2714 us1 = extra[0] & 0x10; 2715 tmp_blk = segment->l2p_table[idx]; 2716 retval = ms_read_extra_data(chip, tmp_blk, 0, 2717 extra, MS_EXTRA_SIZE); 2718 if (retval != STATUS_SUCCESS) 2719 continue; 2720 us2 = extra[0] & 0x10; 2721 2722 (void)ms_arbitrate_l2p(chip, phy_blk, 2723 log_blk-ms_start_idx[seg_no], us1, us2); 2724 continue; 2725 } 2726 2727 segment->build_flag = 1; 2728 2729 dev_dbg(rtsx_dev(chip), "unused block count: %d\n", 2730 segment->unused_blk_cnt); 2731 2732 /* Logical Address Confirmation Process */ 2733 if (seg_no == ms_card->segment_cnt - 1) { 2734 if (segment->unused_blk_cnt < 2) 2735 chip->card_wp |= MS_CARD; 2736 } else { 2737 if (segment->unused_blk_cnt < 1) 2738 chip->card_wp |= MS_CARD; 2739 } 2740 2741 if (chip->card_wp & MS_CARD) 2742 return STATUS_SUCCESS; 2743 2744 for (log_blk = ms_start_idx[seg_no]; 2745 log_blk < ms_start_idx[seg_no + 1]; log_blk++) { 2746 idx = log_blk - ms_start_idx[seg_no]; 2747 if (segment->l2p_table[idx] == 0xFFFF) { 2748 phy_blk = ms_get_unused_block(chip, seg_no); 2749 if (phy_blk == 0xFFFF) { 2750 chip->card_wp |= MS_CARD; 2751 return STATUS_SUCCESS; 2752 } 2753 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1); 2754 if (retval != STATUS_SUCCESS) { 2755 rtsx_trace(chip); 2756 goto BUILD_FAIL; 2757 } 2758 2759 segment->l2p_table[idx] = phy_blk; 2760 if (seg_no == ms_card->segment_cnt - 1) { 2761 if (segment->unused_blk_cnt < 2) { 2762 chip->card_wp |= MS_CARD; 2763 return STATUS_SUCCESS; 2764 } 2765 } else { 2766 if (segment->unused_blk_cnt < 1) { 2767 chip->card_wp |= MS_CARD; 2768 return STATUS_SUCCESS; 2769 } 2770 } 2771 } 2772 } 2773 2774 /* Make boot block be the first normal block */ 2775 if (seg_no == 0) { 2776 for (log_blk = 0; log_blk < 494; log_blk++) { 2777 tmp_blk = segment->l2p_table[log_blk]; 2778 if (tmp_blk < ms_card->boot_block) { 2779 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n"); 2780 2781 if (chip->card_wp & MS_CARD) 2782 break; 2783 2784 phy_blk = ms_get_unused_block(chip, 0); 2785 retval = ms_copy_page(chip, tmp_blk, phy_blk, 2786 log_blk, 0, ms_card->page_off + 1); 2787 if (retval != STATUS_SUCCESS) { 2788 rtsx_trace(chip); 2789 return STATUS_FAIL; 2790 } 2791 2792 segment->l2p_table[log_blk] = phy_blk; 2793 2794 retval = ms_set_bad_block(chip, tmp_blk); 2795 if (retval != STATUS_SUCCESS) { 2796 rtsx_trace(chip); 2797 return STATUS_FAIL; 2798 } 2799 } 2800 } 2801 } 2802 2803 return STATUS_SUCCESS; 2804 2805BUILD_FAIL: 2806 segment->build_flag = 0; 2807 if (segment->l2p_table) { 2808 vfree(segment->l2p_table); 2809 segment->l2p_table = NULL; 2810 } 2811 if (segment->free_table) { 2812 vfree(segment->free_table); 2813 segment->free_table = NULL; 2814 } 2815 2816 return STATUS_FAIL; 2817} 2818 2819 2820int reset_ms_card(struct rtsx_chip *chip) 2821{ 2822 struct ms_info *ms_card = &(chip->ms_card); 2823 int retval; 2824 2825 memset(ms_card, 0, sizeof(struct ms_info)); 2826 2827 retval = enable_card_clock(chip, MS_CARD); 2828 if (retval != STATUS_SUCCESS) { 2829 rtsx_trace(chip); 2830 return STATUS_FAIL; 2831 } 2832 2833 retval = select_card(chip, MS_CARD); 2834 if (retval != STATUS_SUCCESS) { 2835 rtsx_trace(chip); 2836 return STATUS_FAIL; 2837 } 2838 2839 ms_card->ms_type = 0; 2840 2841 retval = reset_ms_pro(chip); 2842 if (retval != STATUS_SUCCESS) { 2843 if (ms_card->check_ms_flow) { 2844 retval = reset_ms(chip); 2845 if (retval != STATUS_SUCCESS) { 2846 rtsx_trace(chip); 2847 return STATUS_FAIL; 2848 } 2849 } else { 2850 rtsx_trace(chip); 2851 return STATUS_FAIL; 2852 } 2853 } 2854 2855 retval = ms_set_init_para(chip); 2856 if (retval != STATUS_SUCCESS) { 2857 rtsx_trace(chip); 2858 return STATUS_FAIL; 2859 } 2860 2861 if (!CHK_MSPRO(ms_card)) { 2862 /* Build table for the last segment, 2863 * to check if L2P table block exists, erasing it 2864 */ 2865 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1); 2866 if (retval != STATUS_SUCCESS) { 2867 rtsx_trace(chip); 2868 return STATUS_FAIL; 2869 } 2870 } 2871 2872 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type); 2873 2874 return STATUS_SUCCESS; 2875} 2876 2877static int mspro_set_rw_cmd(struct rtsx_chip *chip, 2878 u32 start_sec, u16 sec_cnt, u8 cmd) 2879{ 2880 int retval, i; 2881 u8 data[8]; 2882 2883 data[0] = cmd; 2884 data[1] = (u8)(sec_cnt >> 8); 2885 data[2] = (u8)sec_cnt; 2886 data[3] = (u8)(start_sec >> 24); 2887 data[4] = (u8)(start_sec >> 16); 2888 data[5] = (u8)(start_sec >> 8); 2889 data[6] = (u8)start_sec; 2890 data[7] = 0; 2891 2892 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2893 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, 2894 WAIT_INT, data, 8); 2895 if (retval == STATUS_SUCCESS) 2896 break; 2897 } 2898 if (i == MS_MAX_RETRY_COUNT) { 2899 rtsx_trace(chip); 2900 return STATUS_FAIL; 2901 } 2902 2903 return STATUS_SUCCESS; 2904} 2905 2906 2907void mspro_stop_seq_mode(struct rtsx_chip *chip) 2908{ 2909 struct ms_info *ms_card = &(chip->ms_card); 2910 int retval; 2911 2912 if (ms_card->seq_mode) { 2913 retval = ms_switch_clock(chip); 2914 if (retval != STATUS_SUCCESS) 2915 return; 2916 2917 ms_card->seq_mode = 0; 2918 ms_card->total_sec_cnt = 0; 2919 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2920 2921 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 2922 } 2923} 2924 2925static inline int ms_auto_tune_clock(struct rtsx_chip *chip) 2926{ 2927 struct ms_info *ms_card = &(chip->ms_card); 2928 int retval; 2929 2930 if (chip->asic_code) { 2931 if (ms_card->ms_clock > 30) 2932 ms_card->ms_clock -= 20; 2933 } else { 2934 if (ms_card->ms_clock == CLK_80) 2935 ms_card->ms_clock = CLK_60; 2936 else if (ms_card->ms_clock == CLK_60) 2937 ms_card->ms_clock = CLK_40; 2938 } 2939 2940 retval = ms_switch_clock(chip); 2941 if (retval != STATUS_SUCCESS) { 2942 rtsx_trace(chip); 2943 return STATUS_FAIL; 2944 } 2945 2946 return STATUS_SUCCESS; 2947} 2948 2949static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 2950 struct rtsx_chip *chip, u32 start_sector, 2951 u16 sector_cnt) 2952{ 2953 struct ms_info *ms_card = &(chip->ms_card); 2954 bool mode_2k = false; 2955 int retval; 2956 u16 count; 2957 u8 val, trans_mode, rw_tpc, rw_cmd; 2958 2959 ms_set_err_code(chip, MS_NO_ERROR); 2960 2961 ms_card->cleanup_counter = 0; 2962 2963 if (CHK_MSHG(ms_card)) { 2964 if ((start_sector % 4) || (sector_cnt % 4)) { 2965 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2966 rw_tpc = PRO_READ_LONG_DATA; 2967 rw_cmd = PRO_READ_DATA; 2968 } else { 2969 rw_tpc = PRO_WRITE_LONG_DATA; 2970 rw_cmd = PRO_WRITE_DATA; 2971 } 2972 } else { 2973 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2974 rw_tpc = PRO_READ_QUAD_DATA; 2975 rw_cmd = PRO_READ_2K_DATA; 2976 } else { 2977 rw_tpc = PRO_WRITE_QUAD_DATA; 2978 rw_cmd = PRO_WRITE_2K_DATA; 2979 } 2980 mode_2k = true; 2981 } 2982 } else { 2983 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2984 rw_tpc = PRO_READ_LONG_DATA; 2985 rw_cmd = PRO_READ_DATA; 2986 } else { 2987 rw_tpc = PRO_WRITE_LONG_DATA; 2988 rw_cmd = PRO_WRITE_DATA; 2989 } 2990 } 2991 2992 retval = ms_switch_clock(chip); 2993 if (retval != STATUS_SUCCESS) { 2994 rtsx_trace(chip); 2995 return STATUS_FAIL; 2996 } 2997 2998 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2999 trans_mode = MS_TM_AUTO_READ; 3000 else 3001 trans_mode = MS_TM_AUTO_WRITE; 3002 3003 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3004 if (retval) { 3005 rtsx_trace(chip); 3006 return retval; 3007 } 3008 3009 if (ms_card->seq_mode) { 3010 if ((ms_card->pre_dir != srb->sc_data_direction) 3011 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector) 3012 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) 3013 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) 3014 || !(val & MS_INT_BREQ) 3015 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) { 3016 ms_card->seq_mode = 0; 3017 ms_card->total_sec_cnt = 0; 3018 if (val & MS_INT_BREQ) { 3019 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3020 if (retval != STATUS_SUCCESS) { 3021 rtsx_trace(chip); 3022 return STATUS_FAIL; 3023 } 3024 3025 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3026 } 3027 } 3028 } 3029 3030 if (!ms_card->seq_mode) { 3031 ms_card->total_sec_cnt = 0; 3032 if (sector_cnt >= SEQ_START_CRITERIA) { 3033 if ((ms_card->capacity - start_sector) > 0xFE00) 3034 count = 0xFE00; 3035 else 3036 count = (u16)(ms_card->capacity - start_sector); 3037 3038 if (count > sector_cnt) { 3039 if (mode_2k) 3040 ms_card->seq_mode = MODE_2K_SEQ; 3041 else 3042 ms_card->seq_mode = MODE_512_SEQ; 3043 } 3044 } else { 3045 count = sector_cnt; 3046 } 3047 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd); 3048 if (retval != STATUS_SUCCESS) { 3049 ms_card->seq_mode = 0; 3050 rtsx_trace(chip); 3051 return STATUS_FAIL; 3052 } 3053 } 3054 3055 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, 3056 WAIT_INT, mode_2k, scsi_sg_count(srb), 3057 scsi_sglist(srb), scsi_bufflen(srb)); 3058 if (retval != STATUS_SUCCESS) { 3059 ms_card->seq_mode = 0; 3060 rtsx_read_register(chip, MS_TRANS_CFG, &val); 3061 rtsx_clear_ms_error(chip); 3062 3063 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3064 chip->rw_need_retry = 0; 3065 dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n"); 3066 rtsx_trace(chip); 3067 return STATUS_FAIL; 3068 } 3069 3070 if (val & MS_INT_BREQ) 3071 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3072 3073 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3074 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n"); 3075 chip->rw_need_retry = 1; 3076 ms_auto_tune_clock(chip); 3077 } 3078 3079 rtsx_trace(chip); 3080 return retval; 3081 } 3082 3083 if (ms_card->seq_mode) { 3084 ms_card->pre_sec_addr = start_sector; 3085 ms_card->pre_sec_cnt = sector_cnt; 3086 ms_card->pre_dir = srb->sc_data_direction; 3087 ms_card->total_sec_cnt += sector_cnt; 3088 } 3089 3090 return STATUS_SUCCESS; 3091} 3092 3093static int mspro_read_format_progress(struct rtsx_chip *chip, 3094 const int short_data_len) 3095{ 3096 struct ms_info *ms_card = &(chip->ms_card); 3097 int retval, i; 3098 u32 total_progress, cur_progress; 3099 u8 cnt, tmp; 3100 u8 data[8]; 3101 3102 dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n", 3103 short_data_len); 3104 3105 retval = ms_switch_clock(chip); 3106 if (retval != STATUS_SUCCESS) { 3107 ms_card->format_status = FORMAT_FAIL; 3108 rtsx_trace(chip); 3109 return STATUS_FAIL; 3110 } 3111 3112 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3113 if (retval != STATUS_SUCCESS) { 3114 ms_card->format_status = FORMAT_FAIL; 3115 rtsx_trace(chip); 3116 return STATUS_FAIL; 3117 } 3118 3119 if (!(tmp & MS_INT_BREQ)) { 3120 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) { 3121 ms_card->format_status = FORMAT_SUCCESS; 3122 return STATUS_SUCCESS; 3123 } 3124 ms_card->format_status = FORMAT_FAIL; 3125 rtsx_trace(chip); 3126 return STATUS_FAIL; 3127 } 3128 3129 if (short_data_len >= 256) 3130 cnt = 0; 3131 else 3132 cnt = (u8)short_data_len; 3133 3134 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 3135 MS_NO_CHECK_INT); 3136 if (retval != STATUS_SUCCESS) { 3137 ms_card->format_status = FORMAT_FAIL; 3138 rtsx_trace(chip); 3139 return STATUS_FAIL; 3140 } 3141 3142 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, 3143 data, 8); 3144 if (retval != STATUS_SUCCESS) { 3145 ms_card->format_status = FORMAT_FAIL; 3146 rtsx_trace(chip); 3147 return STATUS_FAIL; 3148 } 3149 3150 total_progress = (data[0] << 24) | (data[1] << 16) | 3151 (data[2] << 8) | data[3]; 3152 cur_progress = (data[4] << 24) | (data[5] << 16) | 3153 (data[6] << 8) | data[7]; 3154 3155 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n", 3156 total_progress, cur_progress); 3157 3158 if (total_progress == 0) { 3159 ms_card->progress = 0; 3160 } else { 3161 u64 ulltmp = (u64)cur_progress * (u64)65535; 3162 3163 do_div(ulltmp, total_progress); 3164 ms_card->progress = (u16)ulltmp; 3165 } 3166 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress); 3167 3168 for (i = 0; i < 5000; i++) { 3169 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3170 if (retval != STATUS_SUCCESS) { 3171 ms_card->format_status = FORMAT_FAIL; 3172 rtsx_trace(chip); 3173 return STATUS_FAIL; 3174 } 3175 if (tmp & (MS_INT_CED | MS_INT_CMDNK | 3176 MS_INT_BREQ | MS_INT_ERR)) 3177 break; 3178 3179 wait_timeout(1); 3180 } 3181 3182 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); 3183 if (retval != STATUS_SUCCESS) { 3184 ms_card->format_status = FORMAT_FAIL; 3185 rtsx_trace(chip); 3186 return STATUS_FAIL; 3187 } 3188 3189 if (i == 5000) { 3190 ms_card->format_status = FORMAT_FAIL; 3191 rtsx_trace(chip); 3192 return STATUS_FAIL; 3193 } 3194 3195 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3196 ms_card->format_status = FORMAT_FAIL; 3197 rtsx_trace(chip); 3198 return STATUS_FAIL; 3199 } 3200 3201 if (tmp & MS_INT_CED) { 3202 ms_card->format_status = FORMAT_SUCCESS; 3203 ms_card->pro_under_formatting = 0; 3204 } else if (tmp & MS_INT_BREQ) { 3205 ms_card->format_status = FORMAT_IN_PROGRESS; 3206 } else { 3207 ms_card->format_status = FORMAT_FAIL; 3208 ms_card->pro_under_formatting = 0; 3209 rtsx_trace(chip); 3210 return STATUS_FAIL; 3211 } 3212 3213 return STATUS_SUCCESS; 3214} 3215 3216void mspro_polling_format_status(struct rtsx_chip *chip) 3217{ 3218 struct ms_info *ms_card = &(chip->ms_card); 3219 int i; 3220 3221 if (ms_card->pro_under_formatting && 3222 (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 3223 rtsx_set_stat(chip, RTSX_STAT_RUN); 3224 3225 for (i = 0; i < 65535; i++) { 3226 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN); 3227 if (ms_card->format_status != FORMAT_IN_PROGRESS) 3228 break; 3229 } 3230 } 3231} 3232 3233int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3234 int short_data_len, bool quick_format) 3235{ 3236 struct ms_info *ms_card = &(chip->ms_card); 3237 int retval, i; 3238 u8 buf[8], tmp; 3239 u16 para; 3240 3241 retval = ms_switch_clock(chip); 3242 if (retval != STATUS_SUCCESS) { 3243 rtsx_trace(chip); 3244 return STATUS_FAIL; 3245 } 3246 3247 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01); 3248 if (retval != STATUS_SUCCESS) { 3249 rtsx_trace(chip); 3250 return STATUS_FAIL; 3251 } 3252 3253 memset(buf, 0, 2); 3254 switch (short_data_len) { 3255 case 32: 3256 buf[0] = 0; 3257 break; 3258 case 64: 3259 buf[0] = 1; 3260 break; 3261 case 128: 3262 buf[0] = 2; 3263 break; 3264 case 256: 3265 default: 3266 buf[0] = 3; 3267 break; 3268 } 3269 3270 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3271 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, 3272 NO_WAIT_INT, buf, 2); 3273 if (retval == STATUS_SUCCESS) 3274 break; 3275 } 3276 if (i == MS_MAX_RETRY_COUNT) { 3277 rtsx_trace(chip); 3278 return STATUS_FAIL; 3279 } 3280 3281 if (quick_format) 3282 para = 0x0000; 3283 else 3284 para = 0x0001; 3285 3286 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT); 3287 if (retval != STATUS_SUCCESS) { 3288 rtsx_trace(chip); 3289 return STATUS_FAIL; 3290 } 3291 3292 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3293 if (retval) { 3294 rtsx_trace(chip); 3295 return retval; 3296 } 3297 3298 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3299 rtsx_trace(chip); 3300 return STATUS_FAIL; 3301 } 3302 3303 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) { 3304 ms_card->pro_under_formatting = 1; 3305 ms_card->progress = 0; 3306 ms_card->format_status = FORMAT_IN_PROGRESS; 3307 return STATUS_SUCCESS; 3308 } 3309 3310 if (tmp & MS_INT_CED) { 3311 ms_card->pro_under_formatting = 0; 3312 ms_card->progress = 0; 3313 ms_card->format_status = FORMAT_SUCCESS; 3314 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE); 3315 return STATUS_SUCCESS; 3316 } 3317 3318 rtsx_trace(chip); 3319 return STATUS_FAIL; 3320} 3321 3322 3323static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, 3324 u16 log_blk, u8 start_page, u8 end_page, 3325 u8 *buf, unsigned int *index, 3326 unsigned int *offset) 3327{ 3328 struct ms_info *ms_card = &(chip->ms_card); 3329 int retval, i; 3330 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; 3331 u8 *ptr; 3332 3333 retval = ms_read_extra_data(chip, phy_blk, start_page, 3334 extra, MS_EXTRA_SIZE); 3335 if (retval == STATUS_SUCCESS) { 3336 if ((extra[1] & 0x30) != 0x30) { 3337 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3338 rtsx_trace(chip); 3339 return STATUS_FAIL; 3340 } 3341 } 3342 3343 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3344 SystemParm, 6); 3345 if (retval != STATUS_SUCCESS) { 3346 rtsx_trace(chip); 3347 return STATUS_FAIL; 3348 } 3349 3350 if (CHK_MS4BIT(ms_card)) 3351 data[0] = 0x88; 3352 else 3353 data[0] = 0x80; 3354 3355 data[1] = 0; 3356 data[2] = (u8)(phy_blk >> 8); 3357 data[3] = (u8)phy_blk; 3358 data[4] = 0; 3359 data[5] = start_page; 3360 3361 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3362 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 3363 data, 6); 3364 if (retval == STATUS_SUCCESS) 3365 break; 3366 } 3367 if (i == MS_MAX_RETRY_COUNT) { 3368 rtsx_trace(chip); 3369 return STATUS_FAIL; 3370 } 3371 3372 ms_set_err_code(chip, MS_NO_ERROR); 3373 3374 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 3375 if (retval != STATUS_SUCCESS) { 3376 rtsx_trace(chip); 3377 return STATUS_FAIL; 3378 } 3379 3380 ptr = buf; 3381 3382 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3383 ms_set_err_code(chip, MS_NO_ERROR); 3384 3385 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3386 ms_set_err_code(chip, MS_NO_CARD); 3387 rtsx_trace(chip); 3388 return STATUS_FAIL; 3389 } 3390 3391 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3392 if (retval != STATUS_SUCCESS) { 3393 rtsx_trace(chip); 3394 return STATUS_FAIL; 3395 } 3396 3397 if (val & INT_REG_CMDNK) { 3398 ms_set_err_code(chip, MS_CMD_NK); 3399 rtsx_trace(chip); 3400 return STATUS_FAIL; 3401 } 3402 if (val & INT_REG_ERR) { 3403 if (val & INT_REG_BREQ) { 3404 retval = ms_read_status_reg(chip); 3405 if (retval != STATUS_SUCCESS) { 3406 if (!(chip->card_wp & MS_CARD)) { 3407 reset_ms(chip); 3408 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE); 3409 ms_write_extra_data(chip, phy_blk, 3410 page_addr, extra, MS_EXTRA_SIZE); 3411 } 3412 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3413 rtsx_trace(chip); 3414 return STATUS_FAIL; 3415 } 3416 } else { 3417 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3418 rtsx_trace(chip); 3419 return STATUS_FAIL; 3420 } 3421 } else { 3422 if (!(val & INT_REG_BREQ)) { 3423 ms_set_err_code(chip, MS_BREQ_ERROR); 3424 rtsx_trace(chip); 3425 return STATUS_FAIL; 3426 } 3427 } 3428 3429 if (page_addr == (end_page - 1)) { 3430 if (!(val & INT_REG_CED)) { 3431 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT); 3432 if (retval != STATUS_SUCCESS) { 3433 rtsx_trace(chip); 3434 return STATUS_FAIL; 3435 } 3436 } 3437 3438 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, 3439 &val, 1); 3440 if (retval != STATUS_SUCCESS) { 3441 rtsx_trace(chip); 3442 return STATUS_FAIL; 3443 } 3444 3445 if (!(val & INT_REG_CED)) { 3446 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3447 rtsx_trace(chip); 3448 return STATUS_FAIL; 3449 } 3450 3451 trans_cfg = NO_WAIT_INT; 3452 } else { 3453 trans_cfg = WAIT_INT; 3454 } 3455 3456 rtsx_init_cmd(chip); 3457 3458 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA); 3459 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3460 0xFF, trans_cfg); 3461 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3462 0x01, RING_BUFFER); 3463 3464 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512); 3465 3466 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3467 MS_TRANSFER_START | MS_TM_NORMAL_READ); 3468 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3469 MS_TRANSFER_END, MS_TRANSFER_END); 3470 3471 rtsx_send_cmd_no_wait(chip); 3472 3473 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 3474 512, scsi_sg_count(chip->srb), 3475 index, offset, DMA_FROM_DEVICE, 3476 chip->ms_timeout); 3477 if (retval < 0) { 3478 if (retval == -ETIMEDOUT) { 3479 ms_set_err_code(chip, MS_TO_ERROR); 3480 rtsx_clear_ms_error(chip); 3481 rtsx_trace(chip); 3482 return STATUS_TIMEDOUT; 3483 } 3484 3485 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3486 if (retval != STATUS_SUCCESS) { 3487 ms_set_err_code(chip, MS_TO_ERROR); 3488 rtsx_clear_ms_error(chip); 3489 rtsx_trace(chip); 3490 return STATUS_TIMEDOUT; 3491 } 3492 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3493 ms_set_err_code(chip, MS_CRC16_ERROR); 3494 rtsx_clear_ms_error(chip); 3495 rtsx_trace(chip); 3496 return STATUS_FAIL; 3497 } 3498 } 3499 3500 if (scsi_sg_count(chip->srb) == 0) 3501 ptr += 512; 3502 } 3503 3504 return STATUS_SUCCESS; 3505} 3506 3507static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, 3508 u16 new_blk, u16 log_blk, u8 start_page, 3509 u8 end_page, u8 *buf, unsigned int *index, 3510 unsigned int *offset) 3511{ 3512 struct ms_info *ms_card = &(chip->ms_card); 3513 int retval, i; 3514 u8 page_addr, val, data[16]; 3515 u8 *ptr; 3516 3517 if (!start_page) { 3518 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3519 SystemParm, 7); 3520 if (retval != STATUS_SUCCESS) { 3521 rtsx_trace(chip); 3522 return STATUS_FAIL; 3523 } 3524 3525 if (CHK_MS4BIT(ms_card)) 3526 data[0] = 0x88; 3527 else 3528 data[0] = 0x80; 3529 3530 data[1] = 0; 3531 data[2] = (u8)(old_blk >> 8); 3532 data[3] = (u8)old_blk; 3533 data[4] = 0x80; 3534 data[5] = 0; 3535 data[6] = 0xEF; 3536 data[7] = 0xFF; 3537 3538 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, 3539 data, 8); 3540 if (retval != STATUS_SUCCESS) { 3541 rtsx_trace(chip); 3542 return STATUS_FAIL; 3543 } 3544 3545 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3546 if (retval != STATUS_SUCCESS) { 3547 rtsx_trace(chip); 3548 return STATUS_FAIL; 3549 } 3550 3551 ms_set_err_code(chip, MS_NO_ERROR); 3552 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, 3553 NO_WAIT_INT); 3554 if (retval != STATUS_SUCCESS) { 3555 rtsx_trace(chip); 3556 return STATUS_FAIL; 3557 } 3558 } 3559 3560 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3561 SystemParm, (6 + MS_EXTRA_SIZE)); 3562 if (retval != STATUS_SUCCESS) { 3563 rtsx_trace(chip); 3564 return STATUS_FAIL; 3565 } 3566 3567 ms_set_err_code(chip, MS_NO_ERROR); 3568 3569 if (CHK_MS4BIT(ms_card)) 3570 data[0] = 0x88; 3571 else 3572 data[0] = 0x80; 3573 3574 data[1] = 0; 3575 data[2] = (u8)(new_blk >> 8); 3576 data[3] = (u8)new_blk; 3577 if ((end_page - start_page) == 1) 3578 data[4] = 0x20; 3579 else 3580 data[4] = 0; 3581 3582 data[5] = start_page; 3583 data[6] = 0xF8; 3584 data[7] = 0xFF; 3585 data[8] = (u8)(log_blk >> 8); 3586 data[9] = (u8)log_blk; 3587 3588 for (i = 0x0A; i < 0x10; i++) 3589 data[i] = 0xFF; 3590 3591 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3592 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, 3593 NO_WAIT_INT, data, 16); 3594 if (retval == STATUS_SUCCESS) 3595 break; 3596 } 3597 if (i == MS_MAX_RETRY_COUNT) { 3598 rtsx_trace(chip); 3599 return STATUS_FAIL; 3600 } 3601 3602 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3603 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3604 if (retval == STATUS_SUCCESS) 3605 break; 3606 } 3607 if (i == MS_MAX_RETRY_COUNT) { 3608 rtsx_trace(chip); 3609 return STATUS_FAIL; 3610 } 3611 3612 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3613 if (retval != STATUS_SUCCESS) { 3614 rtsx_trace(chip); 3615 return STATUS_FAIL; 3616 } 3617 3618 ptr = buf; 3619 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3620 ms_set_err_code(chip, MS_NO_ERROR); 3621 3622 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3623 ms_set_err_code(chip, MS_NO_CARD); 3624 rtsx_trace(chip); 3625 return STATUS_FAIL; 3626 } 3627 3628 if (val & INT_REG_CMDNK) { 3629 ms_set_err_code(chip, MS_CMD_NK); 3630 rtsx_trace(chip); 3631 return STATUS_FAIL; 3632 } 3633 if (val & INT_REG_ERR) { 3634 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3635 rtsx_trace(chip); 3636 return STATUS_FAIL; 3637 } 3638 if (!(val & INT_REG_BREQ)) { 3639 ms_set_err_code(chip, MS_BREQ_ERROR); 3640 rtsx_trace(chip); 3641 return STATUS_FAIL; 3642 } 3643 3644 udelay(30); 3645 3646 rtsx_init_cmd(chip); 3647 3648 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 3649 0xFF, WRITE_PAGE_DATA); 3650 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3651 0xFF, WAIT_INT); 3652 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3653 0x01, RING_BUFFER); 3654 3655 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 3656 3657 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3658 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 3659 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3660 MS_TRANSFER_END, MS_TRANSFER_END); 3661 3662 rtsx_send_cmd_no_wait(chip); 3663 3664 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 3665 512, scsi_sg_count(chip->srb), 3666 index, offset, DMA_TO_DEVICE, 3667 chip->ms_timeout); 3668 if (retval < 0) { 3669 ms_set_err_code(chip, MS_TO_ERROR); 3670 rtsx_clear_ms_error(chip); 3671 3672 if (retval == -ETIMEDOUT) { 3673 rtsx_trace(chip); 3674 return STATUS_TIMEDOUT; 3675 } 3676 rtsx_trace(chip); 3677 return STATUS_FAIL; 3678 } 3679 3680 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3681 if (retval != STATUS_SUCCESS) { 3682 rtsx_trace(chip); 3683 return STATUS_FAIL; 3684 } 3685 3686 if ((end_page - start_page) == 1) { 3687 if (!(val & INT_REG_CED)) { 3688 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3689 rtsx_trace(chip); 3690 return STATUS_FAIL; 3691 } 3692 } else { 3693 if (page_addr == (end_page - 1)) { 3694 if (!(val & INT_REG_CED)) { 3695 retval = ms_send_cmd(chip, BLOCK_END, 3696 WAIT_INT); 3697 if (retval != STATUS_SUCCESS) { 3698 rtsx_trace(chip); 3699 return STATUS_FAIL; 3700 } 3701 } 3702 3703 retval = ms_read_bytes(chip, GET_INT, 1, 3704 NO_WAIT_INT, &val, 1); 3705 if (retval != STATUS_SUCCESS) { 3706 rtsx_trace(chip); 3707 return STATUS_FAIL; 3708 } 3709 } 3710 3711 if ((page_addr == (end_page - 1)) || 3712 (page_addr == ms_card->page_off)) { 3713 if (!(val & INT_REG_CED)) { 3714 ms_set_err_code(chip, 3715 MS_FLASH_WRITE_ERROR); 3716 rtsx_trace(chip); 3717 return STATUS_FAIL; 3718 } 3719 } 3720 } 3721 3722 if (scsi_sg_count(chip->srb) == 0) 3723 ptr += 512; 3724 } 3725 3726 return STATUS_SUCCESS; 3727} 3728 3729 3730static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3731 u16 log_blk, u8 page_off) 3732{ 3733 struct ms_info *ms_card = &(chip->ms_card); 3734 int retval, seg_no; 3735 3736 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3737 page_off, ms_card->page_off + 1); 3738 if (retval != STATUS_SUCCESS) { 3739 rtsx_trace(chip); 3740 return STATUS_FAIL; 3741 } 3742 3743 seg_no = old_blk >> 9; 3744 3745 if (MS_TST_BAD_BLOCK_FLG(ms_card)) { 3746 MS_CLR_BAD_BLOCK_FLG(ms_card); 3747 ms_set_bad_block(chip, old_blk); 3748 } else { 3749 retval = ms_erase_block(chip, old_blk); 3750 if (retval == STATUS_SUCCESS) 3751 ms_set_unused_block(chip, old_blk); 3752 } 3753 3754 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk); 3755 3756 return STATUS_SUCCESS; 3757} 3758 3759static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3760 u16 log_blk, u8 start_page) 3761{ 3762 int retval; 3763 3764 if (start_page) { 3765 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3766 0, start_page); 3767 if (retval != STATUS_SUCCESS) { 3768 rtsx_trace(chip); 3769 return STATUS_FAIL; 3770 } 3771 } 3772 3773 return STATUS_SUCCESS; 3774} 3775 3776#ifdef MS_DELAY_WRITE 3777int ms_delay_write(struct rtsx_chip *chip) 3778{ 3779 struct ms_info *ms_card = &(chip->ms_card); 3780 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write); 3781 int retval; 3782 3783 if (delay_write->delay_write_flag) { 3784 retval = ms_set_init_para(chip); 3785 if (retval != STATUS_SUCCESS) { 3786 rtsx_trace(chip); 3787 return STATUS_FAIL; 3788 } 3789 3790 delay_write->delay_write_flag = 0; 3791 retval = ms_finish_write(chip, 3792 delay_write->old_phyblock, 3793 delay_write->new_phyblock, 3794 delay_write->logblock, 3795 delay_write->pageoff); 3796 if (retval != STATUS_SUCCESS) { 3797 rtsx_trace(chip); 3798 return STATUS_FAIL; 3799 } 3800 } 3801 3802 return STATUS_SUCCESS; 3803} 3804#endif 3805 3806static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3807{ 3808 if (srb->sc_data_direction == DMA_FROM_DEVICE) 3809 set_sense_type(chip, SCSI_LUN(srb), 3810 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3811 else 3812 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 3813} 3814 3815static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3816 u32 start_sector, u16 sector_cnt) 3817{ 3818 struct ms_info *ms_card = &(chip->ms_card); 3819 unsigned int lun = SCSI_LUN(srb); 3820 int retval, seg_no; 3821 unsigned int index = 0, offset = 0; 3822 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt; 3823 u8 start_page, end_page = 0, page_cnt; 3824 u8 *ptr; 3825#ifdef MS_DELAY_WRITE 3826 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write); 3827#endif 3828 3829 ms_set_err_code(chip, MS_NO_ERROR); 3830 3831 ms_card->cleanup_counter = 0; 3832 3833 ptr = (u8 *)scsi_sglist(srb); 3834 3835 retval = ms_switch_clock(chip); 3836 if (retval != STATUS_SUCCESS) { 3837 ms_rw_fail(srb, chip); 3838 rtsx_trace(chip); 3839 return STATUS_FAIL; 3840 } 3841 3842 log_blk = (u16)(start_sector >> ms_card->block_shift); 3843 start_page = (u8)(start_sector & ms_card->page_off); 3844 3845 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) { 3846 if (log_blk < ms_start_idx[seg_no+1]) 3847 break; 3848 } 3849 3850 if (ms_card->segment[seg_no].build_flag == 0) { 3851 retval = ms_build_l2p_tbl(chip, seg_no); 3852 if (retval != STATUS_SUCCESS) { 3853 chip->card_fail |= MS_CARD; 3854 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3855 rtsx_trace(chip); 3856 return STATUS_FAIL; 3857 } 3858 } 3859 3860 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3861#ifdef MS_DELAY_WRITE 3862 if (delay_write->delay_write_flag && 3863 (delay_write->logblock == log_blk) && 3864 (start_page > delay_write->pageoff)) { 3865 delay_write->delay_write_flag = 0; 3866 retval = ms_copy_page(chip, 3867 delay_write->old_phyblock, 3868 delay_write->new_phyblock, log_blk, 3869 delay_write->pageoff, start_page); 3870 if (retval != STATUS_SUCCESS) { 3871 set_sense_type(chip, lun, 3872 SENSE_TYPE_MEDIA_WRITE_ERR); 3873 rtsx_trace(chip); 3874 return STATUS_FAIL; 3875 } 3876 old_blk = delay_write->old_phyblock; 3877 new_blk = delay_write->new_phyblock; 3878 } else if (delay_write->delay_write_flag && 3879 (delay_write->logblock == log_blk) && 3880 (start_page == delay_write->pageoff)) { 3881 delay_write->delay_write_flag = 0; 3882 old_blk = delay_write->old_phyblock; 3883 new_blk = delay_write->new_phyblock; 3884 } else { 3885 retval = ms_delay_write(chip); 3886 if (retval != STATUS_SUCCESS) { 3887 set_sense_type(chip, lun, 3888 SENSE_TYPE_MEDIA_WRITE_ERR); 3889 rtsx_trace(chip); 3890 return STATUS_FAIL; 3891 } 3892#endif 3893 old_blk = ms_get_l2p_tbl(chip, seg_no, 3894 log_blk - ms_start_idx[seg_no]); 3895 new_blk = ms_get_unused_block(chip, seg_no); 3896 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) { 3897 set_sense_type(chip, lun, 3898 SENSE_TYPE_MEDIA_WRITE_ERR); 3899 rtsx_trace(chip); 3900 return STATUS_FAIL; 3901 } 3902 3903 retval = ms_prepare_write(chip, old_blk, new_blk, 3904 log_blk, start_page); 3905 if (retval != STATUS_SUCCESS) { 3906 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3907 set_sense_type(chip, lun, 3908 SENSE_TYPE_MEDIA_NOT_PRESENT); 3909 rtsx_trace(chip); 3910 return STATUS_FAIL; 3911 } 3912 set_sense_type(chip, lun, 3913 SENSE_TYPE_MEDIA_WRITE_ERR); 3914 rtsx_trace(chip); 3915 return STATUS_FAIL; 3916 } 3917#ifdef MS_DELAY_WRITE 3918 } 3919#endif 3920 } else { 3921#ifdef MS_DELAY_WRITE 3922 retval = ms_delay_write(chip); 3923 if (retval != STATUS_SUCCESS) { 3924 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3925 set_sense_type(chip, lun, 3926 SENSE_TYPE_MEDIA_NOT_PRESENT); 3927 rtsx_trace(chip); 3928 return STATUS_FAIL; 3929 } 3930 set_sense_type(chip, lun, 3931 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3932 rtsx_trace(chip); 3933 return STATUS_FAIL; 3934 } 3935#endif 3936 old_blk = ms_get_l2p_tbl(chip, seg_no, 3937 log_blk - ms_start_idx[seg_no]); 3938 if (old_blk == 0xFFFF) { 3939 set_sense_type(chip, lun, 3940 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3941 rtsx_trace(chip); 3942 return STATUS_FAIL; 3943 } 3944 } 3945 3946 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3947 seg_no, old_blk, new_blk); 3948 3949 while (total_sec_cnt) { 3950 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) 3951 end_page = ms_card->page_off + 1; 3952 else 3953 end_page = start_page + (u8)total_sec_cnt; 3954 3955 page_cnt = end_page - start_page; 3956 3957 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n", 3958 start_page, end_page, page_cnt); 3959 3960 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3961 retval = ms_read_multiple_pages(chip, 3962 old_blk, log_blk, start_page, end_page, 3963 ptr, &index, &offset); 3964 } else { 3965 retval = ms_write_multiple_pages(chip, old_blk, 3966 new_blk, log_blk, start_page, end_page, 3967 ptr, &index, &offset); 3968 } 3969 3970 if (retval != STATUS_SUCCESS) { 3971 toggle_gpio(chip, 1); 3972 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3973 set_sense_type(chip, lun, 3974 SENSE_TYPE_MEDIA_NOT_PRESENT); 3975 rtsx_trace(chip); 3976 return STATUS_FAIL; 3977 } 3978 ms_rw_fail(srb, chip); 3979 rtsx_trace(chip); 3980 return STATUS_FAIL; 3981 } 3982 3983 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3984 if (end_page == (ms_card->page_off + 1)) { 3985 retval = ms_erase_block(chip, old_blk); 3986 if (retval == STATUS_SUCCESS) 3987 ms_set_unused_block(chip, old_blk); 3988 3989 ms_set_l2p_tbl(chip, seg_no, 3990 log_blk - ms_start_idx[seg_no], 3991 new_blk); 3992 } 3993 } 3994 3995 total_sec_cnt -= page_cnt; 3996 if (scsi_sg_count(srb) == 0) 3997 ptr += page_cnt * 512; 3998 3999 if (total_sec_cnt == 0) 4000 break; 4001 4002 log_blk++; 4003 4004 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; 4005 seg_no++) { 4006 if (log_blk < ms_start_idx[seg_no+1]) 4007 break; 4008 } 4009 4010 if (ms_card->segment[seg_no].build_flag == 0) { 4011 retval = ms_build_l2p_tbl(chip, seg_no); 4012 if (retval != STATUS_SUCCESS) { 4013 chip->card_fail |= MS_CARD; 4014 set_sense_type(chip, lun, 4015 SENSE_TYPE_MEDIA_NOT_PRESENT); 4016 rtsx_trace(chip); 4017 return STATUS_FAIL; 4018 } 4019 } 4020 4021 old_blk = ms_get_l2p_tbl(chip, seg_no, 4022 log_blk - ms_start_idx[seg_no]); 4023 if (old_blk == 0xFFFF) { 4024 ms_rw_fail(srb, chip); 4025 rtsx_trace(chip); 4026 return STATUS_FAIL; 4027 } 4028 4029 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4030 new_blk = ms_get_unused_block(chip, seg_no); 4031 if (new_blk == 0xFFFF) { 4032 ms_rw_fail(srb, chip); 4033 rtsx_trace(chip); 4034 return STATUS_FAIL; 4035 } 4036 } 4037 4038 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 4039 seg_no, old_blk, new_blk); 4040 4041 start_page = 0; 4042 } 4043 4044 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4045 if (end_page < (ms_card->page_off + 1)) { 4046#ifdef MS_DELAY_WRITE 4047 delay_write->delay_write_flag = 1; 4048 delay_write->old_phyblock = old_blk; 4049 delay_write->new_phyblock = new_blk; 4050 delay_write->logblock = log_blk; 4051 delay_write->pageoff = end_page; 4052#else 4053 retval = ms_finish_write(chip, old_blk, new_blk, 4054 log_blk, end_page); 4055 if (retval != STATUS_SUCCESS) { 4056 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 4057 set_sense_type(chip, lun, 4058 SENSE_TYPE_MEDIA_NOT_PRESENT); 4059 rtsx_trace(chip); 4060 return STATUS_FAIL; 4061 } 4062 4063 ms_rw_fail(srb, chip); 4064 rtsx_trace(chip); 4065 return STATUS_FAIL; 4066 } 4067#endif 4068 } 4069 } 4070 4071 scsi_set_resid(srb, 0); 4072 4073 return STATUS_SUCCESS; 4074} 4075 4076int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 4077 u32 start_sector, u16 sector_cnt) 4078{ 4079 struct ms_info *ms_card = &(chip->ms_card); 4080 int retval; 4081 4082 if (CHK_MSPRO(ms_card)) 4083 retval = mspro_rw_multi_sector(srb, chip, start_sector, 4084 sector_cnt); 4085 else 4086 retval = ms_rw_multi_sector(srb, chip, start_sector, 4087 sector_cnt); 4088 4089 return retval; 4090} 4091 4092 4093void ms_free_l2p_tbl(struct rtsx_chip *chip) 4094{ 4095 struct ms_info *ms_card = &(chip->ms_card); 4096 int i = 0; 4097 4098 if (ms_card->segment != NULL) { 4099 for (i = 0; i < ms_card->segment_cnt; i++) { 4100 if (ms_card->segment[i].l2p_table != NULL) { 4101 vfree(ms_card->segment[i].l2p_table); 4102 ms_card->segment[i].l2p_table = NULL; 4103 } 4104 if (ms_card->segment[i].free_table != NULL) { 4105 vfree(ms_card->segment[i].free_table); 4106 ms_card->segment[i].free_table = NULL; 4107 } 4108 } 4109 vfree(ms_card->segment); 4110 ms_card->segment = NULL; 4111 } 4112} 4113 4114#ifdef SUPPORT_MAGIC_GATE 4115 4116#ifdef READ_BYTES_WAIT_INT 4117static int ms_poll_int(struct rtsx_chip *chip) 4118{ 4119 int retval; 4120 u8 val; 4121 4122 rtsx_init_cmd(chip); 4123 4124 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED); 4125 4126 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 4127 if (retval != STATUS_SUCCESS) { 4128 rtsx_trace(chip); 4129 return STATUS_FAIL; 4130 } 4131 4132 val = *rtsx_get_cmd_data(chip); 4133 if (val & MS_INT_ERR) { 4134 rtsx_trace(chip); 4135 return STATUS_FAIL; 4136 } 4137 4138 return STATUS_SUCCESS; 4139} 4140#endif 4141 4142#ifdef MS_SAMPLE_INT_ERR 4143static int check_ms_err(struct rtsx_chip *chip) 4144{ 4145 int retval; 4146 u8 val; 4147 4148 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4149 if (retval != STATUS_SUCCESS) 4150 return 1; 4151 if (val & MS_TRANSFER_ERR) 4152 return 1; 4153 4154 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 4155 if (retval != STATUS_SUCCESS) 4156 return 1; 4157 4158 if (val & (MS_INT_ERR | MS_INT_CMDNK)) 4159 return 1; 4160 4161 return 0; 4162} 4163#else 4164static int check_ms_err(struct rtsx_chip *chip) 4165{ 4166 int retval; 4167 u8 val; 4168 4169 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4170 if (retval != STATUS_SUCCESS) 4171 return 1; 4172 if (val & MS_TRANSFER_ERR) 4173 return 1; 4174 4175 return 0; 4176} 4177#endif 4178 4179static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num) 4180{ 4181 int retval, i; 4182 u8 data[8]; 4183 4184 data[0] = cmd; 4185 data[1] = 0; 4186 data[2] = 0; 4187 data[3] = 0; 4188 data[4] = 0; 4189 data[5] = 0; 4190 data[6] = entry_num; 4191 data[7] = 0; 4192 4193 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 4194 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, 4195 data, 8); 4196 if (retval == STATUS_SUCCESS) 4197 break; 4198 } 4199 if (i == MS_MAX_RETRY_COUNT) { 4200 rtsx_trace(chip); 4201 return STATUS_FAIL; 4202 } 4203 4204 if (check_ms_err(chip)) { 4205 rtsx_clear_ms_error(chip); 4206 rtsx_trace(chip); 4207 return STATUS_FAIL; 4208 } 4209 4210 return STATUS_SUCCESS; 4211} 4212 4213static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, 4214 u8 mg_entry_num) 4215{ 4216 int retval; 4217 u8 buf[6]; 4218 4219 if (type == 0) 4220 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1); 4221 else 4222 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 4223 4224 if (retval != STATUS_SUCCESS) { 4225 rtsx_trace(chip); 4226 return STATUS_FAIL; 4227 } 4228 4229 buf[0] = 0; 4230 buf[1] = 0; 4231 if (type == 1) { 4232 buf[2] = 0; 4233 buf[3] = 0; 4234 buf[4] = 0; 4235 buf[5] = mg_entry_num; 4236 } 4237 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, 4238 NO_WAIT_INT, buf, 6); 4239 if (retval != STATUS_SUCCESS) { 4240 rtsx_trace(chip); 4241 return STATUS_FAIL; 4242 } 4243 4244 return STATUS_SUCCESS; 4245} 4246 4247int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4248{ 4249 int retval; 4250 int i; 4251 unsigned int lun = SCSI_LUN(srb); 4252 u8 buf1[32], buf2[12]; 4253 4254 if (scsi_bufflen(srb) < 12) { 4255 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4256 rtsx_trace(chip); 4257 return STATUS_FAIL; 4258 } 4259 4260 ms_cleanup_work(chip); 4261 4262 retval = ms_switch_clock(chip); 4263 if (retval != STATUS_SUCCESS) { 4264 rtsx_trace(chip); 4265 return STATUS_FAIL; 4266 } 4267 4268 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0); 4269 if (retval != STATUS_SUCCESS) { 4270 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4271 rtsx_trace(chip); 4272 return STATUS_FAIL; 4273 } 4274 4275 memset(buf1, 0, 32); 4276 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb); 4277 for (i = 0; i < 8; i++) 4278 buf1[8+i] = buf2[4+i]; 4279 4280 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4281 buf1, 32); 4282 if (retval != STATUS_SUCCESS) { 4283 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4284 rtsx_trace(chip); 4285 return STATUS_FAIL; 4286 } 4287 if (check_ms_err(chip)) { 4288 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4289 rtsx_clear_ms_error(chip); 4290 rtsx_trace(chip); 4291 return STATUS_FAIL; 4292 } 4293 4294 return STATUS_SUCCESS; 4295} 4296 4297int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4298{ 4299 int retval = STATUS_FAIL; 4300 int bufflen; 4301 unsigned int lun = SCSI_LUN(srb); 4302 u8 *buf = NULL; 4303 4304 ms_cleanup_work(chip); 4305 4306 retval = ms_switch_clock(chip); 4307 if (retval != STATUS_SUCCESS) { 4308 rtsx_trace(chip); 4309 return STATUS_FAIL; 4310 } 4311 4312 buf = kmalloc(1540, GFP_KERNEL); 4313 if (!buf) { 4314 rtsx_trace(chip); 4315 return STATUS_ERROR; 4316 } 4317 4318 buf[0] = 0x04; 4319 buf[1] = 0x1A; 4320 buf[2] = 0x00; 4321 buf[3] = 0x00; 4322 4323 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0); 4324 if (retval != STATUS_SUCCESS) { 4325 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4326 rtsx_trace(chip); 4327 goto GetEKBFinish; 4328 } 4329 4330 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4331 3, WAIT_INT, 0, 0, buf + 4, 1536); 4332 if (retval != STATUS_SUCCESS) { 4333 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4334 rtsx_clear_ms_error(chip); 4335 rtsx_trace(chip); 4336 goto GetEKBFinish; 4337 } 4338 if (check_ms_err(chip)) { 4339 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4340 rtsx_clear_ms_error(chip); 4341 rtsx_trace(chip); 4342 return STATUS_FAIL; 4343 } 4344 4345 bufflen = min_t(int, 1052, scsi_bufflen(srb)); 4346 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4347 4348GetEKBFinish: 4349 kfree(buf); 4350 return retval; 4351} 4352 4353int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4354{ 4355 struct ms_info *ms_card = &(chip->ms_card); 4356 int retval; 4357 int bufflen; 4358 int i; 4359 unsigned int lun = SCSI_LUN(srb); 4360 u8 buf[32]; 4361 4362 ms_cleanup_work(chip); 4363 4364 retval = ms_switch_clock(chip); 4365 if (retval != STATUS_SUCCESS) { 4366 rtsx_trace(chip); 4367 return STATUS_FAIL; 4368 } 4369 4370 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0); 4371 if (retval != STATUS_SUCCESS) { 4372 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4373 rtsx_trace(chip); 4374 return STATUS_FAIL; 4375 } 4376 4377 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4378 buf, 32); 4379 if (retval != STATUS_SUCCESS) { 4380 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4381 rtsx_trace(chip); 4382 return STATUS_FAIL; 4383 } 4384 if (check_ms_err(chip)) { 4385 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4386 rtsx_clear_ms_error(chip); 4387 rtsx_trace(chip); 4388 return STATUS_FAIL; 4389 } 4390 4391 memcpy(ms_card->magic_gate_id, buf, 16); 4392 4393#ifdef READ_BYTES_WAIT_INT 4394 retval = ms_poll_int(chip); 4395 if (retval != STATUS_SUCCESS) { 4396 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4397 rtsx_trace(chip); 4398 return STATUS_FAIL; 4399 } 4400#endif 4401 4402 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0); 4403 if (retval != STATUS_SUCCESS) { 4404 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4405 rtsx_trace(chip); 4406 return STATUS_FAIL; 4407 } 4408 4409 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4410 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4411 4412 for (i = 0; i < 8; i++) 4413 buf[i] = buf[4+i]; 4414 4415 for (i = 0; i < 24; i++) 4416 buf[8+i] = 0; 4417 4418 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 4419 32, WAIT_INT, buf, 32); 4420 if (retval != STATUS_SUCCESS) { 4421 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4422 rtsx_trace(chip); 4423 return STATUS_FAIL; 4424 } 4425 if (check_ms_err(chip)) { 4426 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4427 rtsx_clear_ms_error(chip); 4428 rtsx_trace(chip); 4429 return STATUS_FAIL; 4430 } 4431 4432 ms_card->mg_auth = 0; 4433 4434 return STATUS_SUCCESS; 4435} 4436 4437int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4438{ 4439 struct ms_info *ms_card = &(chip->ms_card); 4440 int retval; 4441 int bufflen; 4442 unsigned int lun = SCSI_LUN(srb); 4443 u8 buf1[32], buf2[36]; 4444 4445 ms_cleanup_work(chip); 4446 4447 retval = ms_switch_clock(chip); 4448 if (retval != STATUS_SUCCESS) { 4449 rtsx_trace(chip); 4450 return STATUS_FAIL; 4451 } 4452 4453 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0); 4454 if (retval != STATUS_SUCCESS) { 4455 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4456 rtsx_trace(chip); 4457 return STATUS_FAIL; 4458 } 4459 4460 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4461 buf1, 32); 4462 if (retval != STATUS_SUCCESS) { 4463 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4464 rtsx_trace(chip); 4465 return STATUS_FAIL; 4466 } 4467 if (check_ms_err(chip)) { 4468 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4469 rtsx_clear_ms_error(chip); 4470 rtsx_trace(chip); 4471 return STATUS_FAIL; 4472 } 4473 4474 buf2[0] = 0x00; 4475 buf2[1] = 0x22; 4476 buf2[2] = 0x00; 4477 buf2[3] = 0x00; 4478 4479 memcpy(buf2 + 4, ms_card->magic_gate_id, 16); 4480 memcpy(buf2 + 20, buf1, 16); 4481 4482 bufflen = min_t(int, 36, scsi_bufflen(srb)); 4483 rtsx_stor_set_xfer_buf(buf2, bufflen, srb); 4484 4485#ifdef READ_BYTES_WAIT_INT 4486 retval = ms_poll_int(chip); 4487 if (retval != STATUS_SUCCESS) { 4488 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4489 rtsx_trace(chip); 4490 return STATUS_FAIL; 4491 } 4492#endif 4493 4494 return STATUS_SUCCESS; 4495} 4496 4497int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4498{ 4499 struct ms_info *ms_card = &(chip->ms_card); 4500 int retval; 4501 int i; 4502 int bufflen; 4503 unsigned int lun = SCSI_LUN(srb); 4504 u8 buf[32]; 4505 4506 ms_cleanup_work(chip); 4507 4508 retval = ms_switch_clock(chip); 4509 if (retval != STATUS_SUCCESS) { 4510 rtsx_trace(chip); 4511 return STATUS_FAIL; 4512 } 4513 4514 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0); 4515 if (retval != STATUS_SUCCESS) { 4516 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4517 rtsx_trace(chip); 4518 return STATUS_FAIL; 4519 } 4520 4521 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4522 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4523 4524 for (i = 0; i < 8; i++) 4525 buf[i] = buf[4+i]; 4526 4527 for (i = 0; i < 24; i++) 4528 buf[8+i] = 0; 4529 4530 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4531 buf, 32); 4532 if (retval != STATUS_SUCCESS) { 4533 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4534 rtsx_trace(chip); 4535 return STATUS_FAIL; 4536 } 4537 if (check_ms_err(chip)) { 4538 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4539 rtsx_clear_ms_error(chip); 4540 rtsx_trace(chip); 4541 return STATUS_FAIL; 4542 } 4543 4544 ms_card->mg_auth = 1; 4545 4546 return STATUS_SUCCESS; 4547} 4548 4549int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4550{ 4551 struct ms_info *ms_card = &(chip->ms_card); 4552 int retval; 4553 int bufflen; 4554 unsigned int lun = SCSI_LUN(srb); 4555 u8 *buf = NULL; 4556 4557 ms_cleanup_work(chip); 4558 4559 retval = ms_switch_clock(chip); 4560 if (retval != STATUS_SUCCESS) { 4561 rtsx_trace(chip); 4562 return STATUS_FAIL; 4563 } 4564 4565 buf = kmalloc(1028, GFP_KERNEL); 4566 if (!buf) { 4567 rtsx_trace(chip); 4568 return STATUS_ERROR; 4569 } 4570 4571 buf[0] = 0x04; 4572 buf[1] = 0x02; 4573 buf[2] = 0x00; 4574 buf[3] = 0x00; 4575 4576 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num); 4577 if (retval != STATUS_SUCCESS) { 4578 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4579 rtsx_trace(chip); 4580 goto GetICVFinish; 4581 } 4582 4583 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4584 2, WAIT_INT, 0, 0, buf + 4, 1024); 4585 if (retval != STATUS_SUCCESS) { 4586 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4587 rtsx_clear_ms_error(chip); 4588 rtsx_trace(chip); 4589 goto GetICVFinish; 4590 } 4591 if (check_ms_err(chip)) { 4592 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4593 rtsx_clear_ms_error(chip); 4594 rtsx_trace(chip); 4595 return STATUS_FAIL; 4596 } 4597 4598 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4599 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4600 4601GetICVFinish: 4602 kfree(buf); 4603 return retval; 4604} 4605 4606int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4607{ 4608 struct ms_info *ms_card = &(chip->ms_card); 4609 int retval; 4610 int bufflen; 4611#ifdef MG_SET_ICV_SLOW 4612 int i; 4613#endif 4614 unsigned int lun = SCSI_LUN(srb); 4615 u8 *buf = NULL; 4616 4617 ms_cleanup_work(chip); 4618 4619 retval = ms_switch_clock(chip); 4620 if (retval != STATUS_SUCCESS) { 4621 rtsx_trace(chip); 4622 return STATUS_FAIL; 4623 } 4624 4625 buf = kmalloc(1028, GFP_KERNEL); 4626 if (!buf) { 4627 rtsx_trace(chip); 4628 return STATUS_ERROR; 4629 } 4630 4631 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4632 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4633 4634 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num); 4635 if (retval != STATUS_SUCCESS) { 4636 if (ms_card->mg_auth == 0) { 4637 if ((buf[5] & 0xC0) != 0) 4638 set_sense_type(chip, lun, 4639 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4640 else 4641 set_sense_type(chip, lun, 4642 SENSE_TYPE_MG_WRITE_ERR); 4643 } else { 4644 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4645 } 4646 rtsx_trace(chip); 4647 goto SetICVFinish; 4648 } 4649 4650#ifdef MG_SET_ICV_SLOW 4651 for (i = 0; i < 2; i++) { 4652 udelay(50); 4653 4654 rtsx_init_cmd(chip); 4655 4656 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 4657 0xFF, PRO_WRITE_LONG_DATA); 4658 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT); 4659 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4660 0x01, RING_BUFFER); 4661 4662 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 4663 4664 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 4665 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 4666 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 4667 MS_TRANSFER_END, MS_TRANSFER_END); 4668 4669 rtsx_send_cmd_no_wait(chip); 4670 4671 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512, 4672 512, 0, DMA_TO_DEVICE, 3000); 4673 if ((retval < 0) || check_ms_err(chip)) { 4674 rtsx_clear_ms_error(chip); 4675 if (ms_card->mg_auth == 0) { 4676 if ((buf[5] & 0xC0) != 0) 4677 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4678 else 4679 set_sense_type(chip, lun, 4680 SENSE_TYPE_MG_WRITE_ERR); 4681 } else { 4682 set_sense_type(chip, lun, 4683 SENSE_TYPE_MG_WRITE_ERR); 4684 } 4685 retval = STATUS_FAIL; 4686 rtsx_trace(chip); 4687 goto SetICVFinish; 4688 } 4689 } 4690#else 4691 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA, 4692 2, WAIT_INT, 0, 0, buf + 4, 1024); 4693 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) { 4694 rtsx_clear_ms_error(chip); 4695 if (ms_card->mg_auth == 0) { 4696 if ((buf[5] & 0xC0) != 0) 4697 set_sense_type(chip, lun, 4698 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4699 else 4700 set_sense_type(chip, lun, 4701 SENSE_TYPE_MG_WRITE_ERR); 4702 } else { 4703 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4704 } 4705 rtsx_trace(chip); 4706 goto SetICVFinish; 4707 } 4708#endif 4709 4710SetICVFinish: 4711 kfree(buf); 4712 return retval; 4713} 4714 4715#endif /* SUPPORT_MAGIC_GATE */ 4716 4717void ms_cleanup_work(struct rtsx_chip *chip) 4718{ 4719 struct ms_info *ms_card = &(chip->ms_card); 4720 4721 if (CHK_MSPRO(ms_card)) { 4722 if (ms_card->seq_mode) { 4723 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n"); 4724 mspro_stop_seq_mode(chip); 4725 ms_card->cleanup_counter = 0; 4726 } 4727 if (CHK_MSHG(ms_card)) { 4728 rtsx_write_register(chip, MS_CFG, 4729 MS_2K_SECTOR_MODE, 0x00); 4730 } 4731 } 4732#ifdef MS_DELAY_WRITE 4733 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) { 4734 dev_dbg(rtsx_dev(chip), "MS: delay write\n"); 4735 ms_delay_write(chip); 4736 ms_card->cleanup_counter = 0; 4737 } 4738#endif 4739} 4740 4741int ms_power_off_card3v3(struct rtsx_chip *chip) 4742{ 4743 int retval; 4744 4745 retval = disable_card_clock(chip, MS_CARD); 4746 if (retval != STATUS_SUCCESS) { 4747 rtsx_trace(chip); 4748 return STATUS_FAIL; 4749 } 4750 4751 if (chip->asic_code) { 4752 retval = ms_pull_ctl_disable(chip); 4753 if (retval != STATUS_SUCCESS) { 4754 rtsx_trace(chip); 4755 return STATUS_FAIL; 4756 } 4757 } else { 4758 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4759 FPGA_MS_PULL_CTL_BIT | 0x20, 4760 FPGA_MS_PULL_CTL_BIT); 4761 if (retval) { 4762 rtsx_trace(chip); 4763 return retval; 4764 } 4765 } 4766 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 4767 if (retval) { 4768 rtsx_trace(chip); 4769 return retval; 4770 } 4771 if (!chip->ft2_fast_mode) { 4772 retval = card_power_off(chip, MS_CARD); 4773 if (retval != STATUS_SUCCESS) { 4774 rtsx_trace(chip); 4775 return STATUS_FAIL; 4776 } 4777 } 4778 4779 return STATUS_SUCCESS; 4780} 4781 4782int release_ms_card(struct rtsx_chip *chip) 4783{ 4784 struct ms_info *ms_card = &(chip->ms_card); 4785 int retval; 4786 4787#ifdef MS_DELAY_WRITE 4788 ms_card->delay_write.delay_write_flag = 0; 4789#endif 4790 ms_card->pro_under_formatting = 0; 4791 4792 chip->card_ready &= ~MS_CARD; 4793 chip->card_fail &= ~MS_CARD; 4794 chip->card_wp &= ~MS_CARD; 4795 4796 ms_free_l2p_tbl(chip); 4797 4798 memset(ms_card->raw_sys_info, 0, 96); 4799#ifdef SUPPORT_PCGL_1P18 4800 memset(ms_card->raw_model_name, 0, 48); 4801#endif 4802 4803 retval = ms_power_off_card3v3(chip); 4804 if (retval != STATUS_SUCCESS) { 4805 rtsx_trace(chip); 4806 return STATUS_FAIL; 4807 } 4808 4809 return STATUS_SUCCESS; 4810} 4811