1/* Driver for Realtek PCI-Express card reader 2 * Header file 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2, or (at your option) any 9 * later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * Author: 20 * Wei WANG (wei_wang@realsil.com.cn) 21 * Micky Ching (micky_ching@realsil.com.cn) 22 */ 23 24#ifndef __REALTEK_RTSX_SD_H 25#define __REALTEK_RTSX_SD_H 26 27#include "rtsx_chip.h" 28 29#define SUPPORT_VOLTAGE 0x003C0000 30 31/* Error Code */ 32#define SD_NO_ERROR 0x0 33#define SD_CRC_ERR 0x80 34#define SD_TO_ERR 0x40 35#define SD_NO_CARD 0x20 36#define SD_BUSY 0x10 37#define SD_STS_ERR 0x08 38#define SD_RSP_TIMEOUT 0x04 39#define SD_IO_ERR 0x02 40 41/* Return code for MMC switch bus */ 42#define SWITCH_SUCCESS 0 43#define SWITCH_ERR 1 44#define SWITCH_FAIL 2 45 46/* MMC/SD Command Index */ 47/* Basic command (class 0) */ 48#define GO_IDLE_STATE 0 49#define SEND_OP_COND 1 50#define ALL_SEND_CID 2 51#define SET_RELATIVE_ADDR 3 52#define SEND_RELATIVE_ADDR 3 53#define SET_DSR 4 54#define IO_SEND_OP_COND 5 55#define SWITCH 6 56#define SELECT_CARD 7 57#define DESELECT_CARD 7 58/* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec 59 * while is "SEND_IF_COND" for SD 2.0 60 */ 61#define SEND_EXT_CSD 8 62#define SEND_IF_COND 8 63 64#define SEND_CSD 9 65#define SEND_CID 10 66#define VOLTAGE_SWITCH 11 67#define READ_DAT_UTIL_STOP 11 68#define STOP_TRANSMISSION 12 69#define SEND_STATUS 13 70#define GO_INACTIVE_STATE 15 71 72#define SET_BLOCKLEN 16 73#define READ_SINGLE_BLOCK 17 74#define READ_MULTIPLE_BLOCK 18 75#define SEND_TUNING_PATTERN 19 76 77#define BUSTEST_R 14 78#define BUSTEST_W 19 79 80#define WRITE_BLOCK 24 81#define WRITE_MULTIPLE_BLOCK 25 82#define PROGRAM_CSD 27 83 84#define ERASE_WR_BLK_START 32 85#define ERASE_WR_BLK_END 33 86#define ERASE_CMD 38 87 88#define LOCK_UNLOCK 42 89#define IO_RW_DIRECT 52 90 91#define APP_CMD 55 92#define GEN_CMD 56 93 94#define SET_BUS_WIDTH 6 95#define SD_STATUS 13 96#define SEND_NUM_WR_BLOCKS 22 97#define SET_WR_BLK_ERASE_COUNT 23 98#define SD_APP_OP_COND 41 99#define SET_CLR_CARD_DETECT 42 100#define SEND_SCR 51 101 102#define SD_READ_COMPLETE 0x00 103#define SD_READ_TO 0x01 104#define SD_READ_ADVENCE 0x02 105 106#define SD_CHECK_MODE 0x00 107#define SD_SWITCH_MODE 0x80 108#define SD_FUNC_GROUP_1 0x01 109#define SD_FUNC_GROUP_2 0x02 110#define SD_FUNC_GROUP_3 0x03 111#define SD_FUNC_GROUP_4 0x04 112#define SD_CHECK_SPEC_V1_1 0xFF 113 114#define NO_ARGUMENT 0x00 115#define CHECK_PATTERN 0x000000AA 116#define VOLTAGE_SUPPLY_RANGE 0x00000100 117#define SUPPORT_HIGH_AND_EXTENDED_CAPACITY 0x40000000 118#define SUPPORT_MAX_POWER_PERMANCE 0x10000000 119#define SUPPORT_1V8 0x01000000 120 121#define SWTICH_NO_ERR 0x00 122#define CARD_NOT_EXIST 0x01 123#define SPEC_NOT_SUPPORT 0x02 124#define CHECK_MODE_ERR 0x03 125#define CHECK_NOT_READY 0x04 126#define SWITCH_CRC_ERR 0x05 127#define SWITCH_MODE_ERR 0x06 128#define SWITCH_PASS 0x07 129 130#ifdef SUPPORT_SD_LOCK 131#define SD_ERASE 0x08 132#define SD_LOCK 0x04 133#define SD_UNLOCK 0x00 134#define SD_CLR_PWD 0x02 135#define SD_SET_PWD 0x01 136 137#define SD_PWD_LEN 0x10 138 139#define SD_LOCKED 0x80 140#define SD_LOCK_1BIT_MODE 0x40 141#define SD_PWD_EXIST 0x20 142#define SD_UNLOCK_POW_ON 0x01 143#define SD_SDR_RST 0x02 144 145#define SD_NOT_ERASE 0x00 146#define SD_UNDER_ERASING 0x01 147#define SD_COMPLETE_ERASE 0x02 148 149#define SD_RW_FORBIDDEN 0x0F 150 151#endif 152 153#define HS_SUPPORT 0x01 154#define SDR50_SUPPORT 0x02 155#define SDR104_SUPPORT 0x03 156#define DDR50_SUPPORT 0x04 157 158#define HS_SUPPORT_MASK 0x02 159#define SDR50_SUPPORT_MASK 0x04 160#define SDR104_SUPPORT_MASK 0x08 161#define DDR50_SUPPORT_MASK 0x10 162 163#define HS_QUERY_SWITCH_OK 0x01 164#define SDR50_QUERY_SWITCH_OK 0x02 165#define SDR104_QUERY_SWITCH_OK 0x03 166#define DDR50_QUERY_SWITCH_OK 0x04 167 168#define HS_SWITCH_BUSY 0x02 169#define SDR50_SWITCH_BUSY 0x04 170#define SDR104_SWITCH_BUSY 0x08 171#define DDR50_SWITCH_BUSY 0x10 172 173#define FUNCTION_GROUP1_SUPPORT_OFFSET 0x0D 174#define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET 0x10 175#define FUNCTION_GROUP1_CHECK_BUSY_OFFSET 0x1D 176 177#define DRIVING_TYPE_A 0x01 178#define DRIVING_TYPE_B 0x00 179#define DRIVING_TYPE_C 0x02 180#define DRIVING_TYPE_D 0x03 181 182#define DRIVING_TYPE_A_MASK 0x02 183#define DRIVING_TYPE_B_MASK 0x01 184#define DRIVING_TYPE_C_MASK 0x04 185#define DRIVING_TYPE_D_MASK 0x08 186 187#define TYPE_A_QUERY_SWITCH_OK 0x01 188#define TYPE_B_QUERY_SWITCH_OK 0x00 189#define TYPE_C_QUERY_SWITCH_OK 0x02 190#define TYPE_D_QUERY_SWITCH_OK 0x03 191 192#define TYPE_A_SWITCH_BUSY 0x02 193#define TYPE_B_SWITCH_BUSY 0x01 194#define TYPE_C_SWITCH_BUSY 0x04 195#define TYPE_D_SWITCH_BUSY 0x08 196 197#define FUNCTION_GROUP3_SUPPORT_OFFSET 0x09 198#define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET 0x0F 199#define FUNCTION_GROUP3_CHECK_BUSY_OFFSET 0x19 200 201#define CURRENT_LIMIT_200 0x00 202#define CURRENT_LIMIT_400 0x01 203#define CURRENT_LIMIT_600 0x02 204#define CURRENT_LIMIT_800 0x03 205 206#define CURRENT_LIMIT_200_MASK 0x01 207#define CURRENT_LIMIT_400_MASK 0x02 208#define CURRENT_LIMIT_600_MASK 0x04 209#define CURRENT_LIMIT_800_MASK 0x08 210 211#define CURRENT_LIMIT_200_QUERY_SWITCH_OK 0x00 212#define CURRENT_LIMIT_400_QUERY_SWITCH_OK 0x01 213#define CURRENT_LIMIT_600_QUERY_SWITCH_OK 0x02 214#define CURRENT_LIMIT_800_QUERY_SWITCH_OK 0x03 215 216#define CURRENT_LIMIT_200_SWITCH_BUSY 0x01 217#define CURRENT_LIMIT_400_SWITCH_BUSY 0x02 218#define CURRENT_LIMIT_600_SWITCH_BUSY 0x04 219#define CURRENT_LIMIT_800_SWITCH_BUSY 0x08 220 221#define FUNCTION_GROUP4_SUPPORT_OFFSET 0x07 222#define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET 0x0F 223#define FUNCTION_GROUP4_CHECK_BUSY_OFFSET 0x17 224 225#define DATA_STRUCTURE_VER_OFFSET 0x11 226 227#define MAX_PHASE 31 228 229#define MMC_8BIT_BUS 0x0010 230#define MMC_4BIT_BUS 0x0020 231 232#define MMC_SWITCH_ERR 0x80 233 234#define SD_IO_3V3 0 235#define SD_IO_1V8 1 236 237#define TUNE_TX 0x00 238#define TUNE_RX 0x01 239 240#define CHANGE_TX 0x00 241#define CHANGE_RX 0x01 242 243#define DCM_HIGH_FREQUENCY_MODE 0x00 244#define DCM_LOW_FREQUENCY_MODE 0x01 245 246#define DCM_HIGH_FREQUENCY_MODE_SET 0x0C 247#define DCM_Low_FREQUENCY_MODE_SET 0x00 248 249#define MULTIPLY_BY_1 0x00 250#define MULTIPLY_BY_2 0x01 251#define MULTIPLY_BY_3 0x02 252#define MULTIPLY_BY_4 0x03 253#define MULTIPLY_BY_5 0x04 254#define MULTIPLY_BY_6 0x05 255#define MULTIPLY_BY_7 0x06 256#define MULTIPLY_BY_8 0x07 257#define MULTIPLY_BY_9 0x08 258#define MULTIPLY_BY_10 0x09 259 260#define DIVIDE_BY_2 0x01 261#define DIVIDE_BY_3 0x02 262#define DIVIDE_BY_4 0x03 263#define DIVIDE_BY_5 0x04 264#define DIVIDE_BY_6 0x05 265#define DIVIDE_BY_7 0x06 266#define DIVIDE_BY_8 0x07 267#define DIVIDE_BY_9 0x08 268#define DIVIDE_BY_10 0x09 269 270struct timing_phase_path { 271 int start; 272 int end; 273 int mid; 274 int len; 275}; 276 277int sd_select_card(struct rtsx_chip *chip, int select); 278int sd_pull_ctl_enable(struct rtsx_chip *chip); 279int reset_sd_card(struct rtsx_chip *chip); 280int sd_switch_clock(struct rtsx_chip *chip); 281void sd_stop_seq_mode(struct rtsx_chip *chip); 282int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 283 u32 start_sector, u16 sector_cnt); 284void sd_cleanup_work(struct rtsx_chip *chip); 285int sd_power_off_card3v3(struct rtsx_chip *chip); 286int release_sd_card(struct rtsx_chip *chip); 287#ifdef SUPPORT_CPRM 288int soft_reset_sd_card(struct rtsx_chip *chip); 289int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 290 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, bool special_check); 291int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type); 292 293int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip); 294int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 295int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 296int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 297int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip); 298int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip); 299#endif 300 301#endif /* __REALTEK_RTSX_SD_H */ 302