1/* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12#undef DEBUG 13#include <linux/module.h> 14#include <linux/pci.h> 15#include <linux/string.h> 16#include <linux/kernel.h> 17#include <linux/slab.h> 18#include <linux/delay.h> 19#include <linux/tty.h> 20#include <linux/serial_reg.h> 21#include <linux/serial_core.h> 22#include <linux/8250_pci.h> 23#include <linux/bitops.h> 24#include <linux/rational.h> 25 26#include <asm/byteorder.h> 27#include <asm/io.h> 28 29#include <linux/dmaengine.h> 30#include <linux/platform_data/dma-dw.h> 31#include <linux/platform_data/dma-hsu.h> 32 33#include "8250.h" 34 35/* 36 * init function returns: 37 * > 0 - number of ports 38 * = 0 - use board->num_ports 39 * < 0 - error 40 */ 41struct pci_serial_quirk { 42 u32 vendor; 43 u32 device; 44 u32 subvendor; 45 u32 subdevice; 46 int (*probe)(struct pci_dev *dev); 47 int (*init)(struct pci_dev *dev); 48 int (*setup)(struct serial_private *, 49 const struct pciserial_board *, 50 struct uart_8250_port *, int); 51 void (*exit)(struct pci_dev *dev); 52}; 53 54#define PCI_NUM_BAR_RESOURCES 6 55 56struct serial_private { 57 struct pci_dev *dev; 58 unsigned int nr; 59 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 60 struct pci_serial_quirk *quirk; 61 int line[0]; 62}; 63 64static int pci_default_setup(struct serial_private*, 65 const struct pciserial_board*, struct uart_8250_port *, int); 66 67static void moan_device(const char *str, struct pci_dev *dev) 68{ 69 dev_err(&dev->dev, 70 "%s: %s\n" 71 "Please send the output of lspci -vv, this\n" 72 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 73 "manufacturer and name of serial board or\n" 74 "modem board to <linux-serial@vger.kernel.org>.\n", 75 pci_name(dev), str, dev->vendor, dev->device, 76 dev->subsystem_vendor, dev->subsystem_device); 77} 78 79static int 80setup_port(struct serial_private *priv, struct uart_8250_port *port, 81 int bar, int offset, int regshift) 82{ 83 struct pci_dev *dev = priv->dev; 84 85 if (bar >= PCI_NUM_BAR_RESOURCES) 86 return -EINVAL; 87 88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 89 if (!priv->remapped_bar[bar]) 90 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar); 91 if (!priv->remapped_bar[bar]) 92 return -ENOMEM; 93 94 port->port.iotype = UPIO_MEM; 95 port->port.iobase = 0; 96 port->port.mapbase = pci_resource_start(dev, bar) + offset; 97 port->port.membase = priv->remapped_bar[bar] + offset; 98 port->port.regshift = regshift; 99 } else { 100 port->port.iotype = UPIO_PORT; 101 port->port.iobase = pci_resource_start(dev, bar) + offset; 102 port->port.mapbase = 0; 103 port->port.membase = NULL; 104 port->port.regshift = 0; 105 } 106 return 0; 107} 108 109/* 110 * ADDI-DATA GmbH communication cards <info@addi-data.com> 111 */ 112static int addidata_apci7800_setup(struct serial_private *priv, 113 const struct pciserial_board *board, 114 struct uart_8250_port *port, int idx) 115{ 116 unsigned int bar = 0, offset = board->first_offset; 117 bar = FL_GET_BASE(board->flags); 118 119 if (idx < 2) { 120 offset += idx * board->uart_offset; 121 } else if ((idx >= 2) && (idx < 4)) { 122 bar += 1; 123 offset += ((idx - 2) * board->uart_offset); 124 } else if ((idx >= 4) && (idx < 6)) { 125 bar += 2; 126 offset += ((idx - 4) * board->uart_offset); 127 } else if (idx >= 6) { 128 bar += 3; 129 offset += ((idx - 6) * board->uart_offset); 130 } 131 132 return setup_port(priv, port, bar, offset, board->reg_shift); 133} 134 135/* 136 * AFAVLAB uses a different mixture of BARs and offsets 137 * Not that ugly ;) -- HW 138 */ 139static int 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 141 struct uart_8250_port *port, int idx) 142{ 143 unsigned int bar, offset = board->first_offset; 144 145 bar = FL_GET_BASE(board->flags); 146 if (idx < 4) 147 bar += idx; 148 else { 149 bar = 4; 150 offset += (idx - 4) * board->uart_offset; 151 } 152 153 return setup_port(priv, port, bar, offset, board->reg_shift); 154} 155 156/* 157 * HP's Remote Management Console. The Diva chip came in several 158 * different versions. N-class, L2000 and A500 have two Diva chips, each 159 * with 3 UARTs (the third UART on the second chip is unused). Superdome 160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 161 * one Diva chip, but it has been expanded to 5 UARTs. 162 */ 163static int pci_hp_diva_init(struct pci_dev *dev) 164{ 165 int rc = 0; 166 167 switch (dev->subsystem_device) { 168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 171 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 172 rc = 3; 173 break; 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 175 rc = 2; 176 break; 177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 178 rc = 4; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 182 rc = 1; 183 break; 184 } 185 186 return rc; 187} 188 189/* 190 * HP's Diva chip puts the 4th/5th serial port further out, and 191 * some serial ports are supposed to be hidden on certain models. 192 */ 193static int 194pci_hp_diva_setup(struct serial_private *priv, 195 const struct pciserial_board *board, 196 struct uart_8250_port *port, int idx) 197{ 198 unsigned int offset = board->first_offset; 199 unsigned int bar = FL_GET_BASE(board->flags); 200 201 switch (priv->dev->subsystem_device) { 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 203 if (idx == 3) 204 idx++; 205 break; 206 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 207 if (idx > 0) 208 idx++; 209 if (idx > 2) 210 idx++; 211 break; 212 } 213 if (idx > 2) 214 offset = 0x18; 215 216 offset += idx * board->uart_offset; 217 218 return setup_port(priv, port, bar, offset, board->reg_shift); 219} 220 221/* 222 * Added for EKF Intel i960 serial boards 223 */ 224static int pci_inteli960ni_init(struct pci_dev *dev) 225{ 226 u32 oldval; 227 228 if (!(dev->subsystem_device & 0x1000)) 229 return -ENODEV; 230 231 /* is firmware started? */ 232 pci_read_config_dword(dev, 0x44, &oldval); 233 if (oldval == 0x00001000L) { /* RESET value */ 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 235 return -ENODEV; 236 } 237 return 0; 238} 239 240/* 241 * Some PCI serial cards using the PLX 9050 PCI interface chip require 242 * that the card interrupt be explicitly enabled or disabled. This 243 * seems to be mainly needed on card using the PLX which also use I/O 244 * mapped memory. 245 */ 246static int pci_plx9050_init(struct pci_dev *dev) 247{ 248 u8 irq_config; 249 void __iomem *p; 250 251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 252 moan_device("no memory in bar 0", dev); 253 return 0; 254 } 255 256 irq_config = 0x41; 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 259 irq_config = 0x43; 260 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 263 /* 264 * As the megawolf cards have the int pins active 265 * high, and have 2 UART chips, both ints must be 266 * enabled on the 9050. Also, the UARTS are set in 267 * 16450 mode by default, so we have to enable the 268 * 16C950 'enhanced' mode so that we can use the 269 * deep FIFOs 270 */ 271 irq_config = 0x5b; 272 /* 273 * enable/disable interrupts 274 */ 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 276 if (p == NULL) 277 return -ENOMEM; 278 writel(irq_config, p + 0x4c); 279 280 /* 281 * Read the register back to ensure that it took effect. 282 */ 283 readl(p + 0x4c); 284 iounmap(p); 285 286 return 0; 287} 288 289static void pci_plx9050_exit(struct pci_dev *dev) 290{ 291 u8 __iomem *p; 292 293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 294 return; 295 296 /* 297 * disable interrupts 298 */ 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 300 if (p != NULL) { 301 writel(0, p + 0x4c); 302 303 /* 304 * Read the register back to ensure that it took effect. 305 */ 306 readl(p + 0x4c); 307 iounmap(p); 308 } 309} 310 311#define NI8420_INT_ENABLE_REG 0x38 312#define NI8420_INT_ENABLE_BIT 0x2000 313 314static void pci_ni8420_exit(struct pci_dev *dev) 315{ 316 void __iomem *p; 317 unsigned int bar = 0; 318 319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 320 moan_device("no memory in bar", dev); 321 return; 322 } 323 324 p = pci_ioremap_bar(dev, bar); 325 if (p == NULL) 326 return; 327 328 /* Disable the CPU Interrupt */ 329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 330 p + NI8420_INT_ENABLE_REG); 331 iounmap(p); 332} 333 334 335/* MITE registers */ 336#define MITE_IOWBSR1 0xc4 337#define MITE_IOWCR1 0xf4 338#define MITE_LCIMR1 0x08 339#define MITE_LCIMR2 0x10 340 341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 342 343static void pci_ni8430_exit(struct pci_dev *dev) 344{ 345 void __iomem *p; 346 unsigned int bar = 0; 347 348 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 349 moan_device("no memory in bar", dev); 350 return; 351 } 352 353 p = pci_ioremap_bar(dev, bar); 354 if (p == NULL) 355 return; 356 357 /* Disable the CPU Interrupt */ 358 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 359 iounmap(p); 360} 361 362/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 363static int 364sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 365 struct uart_8250_port *port, int idx) 366{ 367 unsigned int bar, offset = board->first_offset; 368 369 bar = 0; 370 371 if (idx < 4) { 372 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 373 offset += idx * board->uart_offset; 374 } else if (idx < 8) { 375 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 376 offset += idx * board->uart_offset + 0xC00; 377 } else /* we have only 8 ports on PMC-OCTALPRO */ 378 return 1; 379 380 return setup_port(priv, port, bar, offset, board->reg_shift); 381} 382 383/* 384* This does initialization for PMC OCTALPRO cards: 385* maps the device memory, resets the UARTs (needed, bc 386* if the module is removed and inserted again, the card 387* is in the sleep mode) and enables global interrupt. 388*/ 389 390/* global control register offset for SBS PMC-OctalPro */ 391#define OCT_REG_CR_OFF 0x500 392 393static int sbs_init(struct pci_dev *dev) 394{ 395 u8 __iomem *p; 396 397 p = pci_ioremap_bar(dev, 0); 398 399 if (p == NULL) 400 return -ENOMEM; 401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 402 writeb(0x10, p + OCT_REG_CR_OFF); 403 udelay(50); 404 writeb(0x0, p + OCT_REG_CR_OFF); 405 406 /* Set bit-2 (INTENABLE) of Control Register */ 407 writeb(0x4, p + OCT_REG_CR_OFF); 408 iounmap(p); 409 410 return 0; 411} 412 413/* 414 * Disables the global interrupt of PMC-OctalPro 415 */ 416 417static void sbs_exit(struct pci_dev *dev) 418{ 419 u8 __iomem *p; 420 421 p = pci_ioremap_bar(dev, 0); 422 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 423 if (p != NULL) 424 writeb(0, p + OCT_REG_CR_OFF); 425 iounmap(p); 426} 427 428/* 429 * SIIG serial cards have an PCI interface chip which also controls 430 * the UART clocking frequency. Each UART can be clocked independently 431 * (except cards equipped with 4 UARTs) and initial clocking settings 432 * are stored in the EEPROM chip. It can cause problems because this 433 * version of serial driver doesn't support differently clocked UART's 434 * on single PCI card. To prevent this, initialization functions set 435 * high frequency clocking for all UART's on given card. It is safe (I 436 * hope) because it doesn't touch EEPROM settings to prevent conflicts 437 * with other OSes (like M$ DOS). 438 * 439 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 440 * 441 * There is two family of SIIG serial cards with different PCI 442 * interface chip and different configuration methods: 443 * - 10x cards have control registers in IO and/or memory space; 444 * - 20x cards have control registers in standard PCI configuration space. 445 * 446 * Note: all 10x cards have PCI device ids 0x10.. 447 * all 20x cards have PCI device ids 0x20.. 448 * 449 * There are also Quartet Serial cards which use Oxford Semiconductor 450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 451 * 452 * Note: some SIIG cards are probed by the parport_serial object. 453 */ 454 455#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 456#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 457 458static int pci_siig10x_init(struct pci_dev *dev) 459{ 460 u16 data; 461 void __iomem *p; 462 463 switch (dev->device & 0xfff8) { 464 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 465 data = 0xffdf; 466 break; 467 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 468 data = 0xf7ff; 469 break; 470 default: /* 1S1P, 4S */ 471 data = 0xfffb; 472 break; 473 } 474 475 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 476 if (p == NULL) 477 return -ENOMEM; 478 479 writew(readw(p + 0x28) & data, p + 0x28); 480 readw(p + 0x28); 481 iounmap(p); 482 return 0; 483} 484 485#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 486#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 487 488static int pci_siig20x_init(struct pci_dev *dev) 489{ 490 u8 data; 491 492 /* Change clock frequency for the first UART. */ 493 pci_read_config_byte(dev, 0x6f, &data); 494 pci_write_config_byte(dev, 0x6f, data & 0xef); 495 496 /* If this card has 2 UART, we have to do the same with second UART. */ 497 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 498 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 499 pci_read_config_byte(dev, 0x73, &data); 500 pci_write_config_byte(dev, 0x73, data & 0xef); 501 } 502 return 0; 503} 504 505static int pci_siig_init(struct pci_dev *dev) 506{ 507 unsigned int type = dev->device & 0xff00; 508 509 if (type == 0x1000) 510 return pci_siig10x_init(dev); 511 else if (type == 0x2000) 512 return pci_siig20x_init(dev); 513 514 moan_device("Unknown SIIG card", dev); 515 return -ENODEV; 516} 517 518static int pci_siig_setup(struct serial_private *priv, 519 const struct pciserial_board *board, 520 struct uart_8250_port *port, int idx) 521{ 522 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 523 524 if (idx > 3) { 525 bar = 4; 526 offset = (idx - 4) * 8; 527 } 528 529 return setup_port(priv, port, bar, offset, 0); 530} 531 532/* 533 * Timedia has an explosion of boards, and to avoid the PCI table from 534 * growing *huge*, we use this function to collapse some 70 entries 535 * in the PCI table into one, for sanity's and compactness's sake. 536 */ 537static const unsigned short timedia_single_port[] = { 538 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 539}; 540 541static const unsigned short timedia_dual_port[] = { 542 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 543 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 544 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 545 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 546 0xD079, 0 547}; 548 549static const unsigned short timedia_quad_port[] = { 550 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 551 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 552 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 553 0xB157, 0 554}; 555 556static const unsigned short timedia_eight_port[] = { 557 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 558 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 559}; 560 561static const struct timedia_struct { 562 int num; 563 const unsigned short *ids; 564} timedia_data[] = { 565 { 1, timedia_single_port }, 566 { 2, timedia_dual_port }, 567 { 4, timedia_quad_port }, 568 { 8, timedia_eight_port } 569}; 570 571/* 572 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 573 * listing them individually, this driver merely grabs them all with 574 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 575 * and should be left free to be claimed by parport_serial instead. 576 */ 577static int pci_timedia_probe(struct pci_dev *dev) 578{ 579 /* 580 * Check the third digit of the subdevice ID 581 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 582 */ 583 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 584 dev_info(&dev->dev, 585 "ignoring Timedia subdevice %04x for parport_serial\n", 586 dev->subsystem_device); 587 return -ENODEV; 588 } 589 590 return 0; 591} 592 593static int pci_timedia_init(struct pci_dev *dev) 594{ 595 const unsigned short *ids; 596 int i, j; 597 598 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 599 ids = timedia_data[i].ids; 600 for (j = 0; ids[j]; j++) 601 if (dev->subsystem_device == ids[j]) 602 return timedia_data[i].num; 603 } 604 return 0; 605} 606 607/* 608 * Timedia/SUNIX uses a mixture of BARs and offsets 609 * Ugh, this is ugly as all hell --- TYT 610 */ 611static int 612pci_timedia_setup(struct serial_private *priv, 613 const struct pciserial_board *board, 614 struct uart_8250_port *port, int idx) 615{ 616 unsigned int bar = 0, offset = board->first_offset; 617 618 switch (idx) { 619 case 0: 620 bar = 0; 621 break; 622 case 1: 623 offset = board->uart_offset; 624 bar = 0; 625 break; 626 case 2: 627 bar = 1; 628 break; 629 case 3: 630 offset = board->uart_offset; 631 /* FALLTHROUGH */ 632 case 4: /* BAR 2 */ 633 case 5: /* BAR 3 */ 634 case 6: /* BAR 4 */ 635 case 7: /* BAR 5 */ 636 bar = idx - 2; 637 } 638 639 return setup_port(priv, port, bar, offset, board->reg_shift); 640} 641 642/* 643 * Some Titan cards are also a little weird 644 */ 645static int 646titan_400l_800l_setup(struct serial_private *priv, 647 const struct pciserial_board *board, 648 struct uart_8250_port *port, int idx) 649{ 650 unsigned int bar, offset = board->first_offset; 651 652 switch (idx) { 653 case 0: 654 bar = 1; 655 break; 656 case 1: 657 bar = 2; 658 break; 659 default: 660 bar = 4; 661 offset = (idx - 2) * board->uart_offset; 662 } 663 664 return setup_port(priv, port, bar, offset, board->reg_shift); 665} 666 667static int pci_xircom_init(struct pci_dev *dev) 668{ 669 msleep(100); 670 return 0; 671} 672 673static int pci_ni8420_init(struct pci_dev *dev) 674{ 675 void __iomem *p; 676 unsigned int bar = 0; 677 678 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 679 moan_device("no memory in bar", dev); 680 return 0; 681 } 682 683 p = pci_ioremap_bar(dev, bar); 684 if (p == NULL) 685 return -ENOMEM; 686 687 /* Enable CPU Interrupt */ 688 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 689 p + NI8420_INT_ENABLE_REG); 690 691 iounmap(p); 692 return 0; 693} 694 695#define MITE_IOWBSR1_WSIZE 0xa 696#define MITE_IOWBSR1_WIN_OFFSET 0x800 697#define MITE_IOWBSR1_WENAB (1 << 7) 698#define MITE_LCIMR1_IO_IE_0 (1 << 24) 699#define MITE_LCIMR2_SET_CPU_IE (1 << 31) 700#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 701 702static int pci_ni8430_init(struct pci_dev *dev) 703{ 704 void __iomem *p; 705 struct pci_bus_region region; 706 u32 device_window; 707 unsigned int bar = 0; 708 709 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 710 moan_device("no memory in bar", dev); 711 return 0; 712 } 713 714 p = pci_ioremap_bar(dev, bar); 715 if (p == NULL) 716 return -ENOMEM; 717 718 /* 719 * Set device window address and size in BAR0, while acknowledging that 720 * the resource structure may contain a translated address that differs 721 * from the address the device responds to. 722 */ 723 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 724 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 725 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 726 writel(device_window, p + MITE_IOWBSR1); 727 728 /* Set window access to go to RAMSEL IO address space */ 729 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 730 p + MITE_IOWCR1); 731 732 /* Enable IO Bus Interrupt 0 */ 733 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 734 735 /* Enable CPU Interrupt */ 736 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 737 738 iounmap(p); 739 return 0; 740} 741 742/* UART Port Control Register */ 743#define NI8430_PORTCON 0x0f 744#define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 745 746static int 747pci_ni8430_setup(struct serial_private *priv, 748 const struct pciserial_board *board, 749 struct uart_8250_port *port, int idx) 750{ 751 struct pci_dev *dev = priv->dev; 752 void __iomem *p; 753 unsigned int bar, offset = board->first_offset; 754 755 if (idx >= board->num_ports) 756 return 1; 757 758 bar = FL_GET_BASE(board->flags); 759 offset += idx * board->uart_offset; 760 761 p = pci_ioremap_bar(dev, bar); 762 if (!p) 763 return -ENOMEM; 764 765 /* enable the transceiver */ 766 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 767 p + offset + NI8430_PORTCON); 768 769 iounmap(p); 770 771 return setup_port(priv, port, bar, offset, board->reg_shift); 772} 773 774static int pci_netmos_9900_setup(struct serial_private *priv, 775 const struct pciserial_board *board, 776 struct uart_8250_port *port, int idx) 777{ 778 unsigned int bar; 779 780 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 781 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 782 /* netmos apparently orders BARs by datasheet layout, so serial 783 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 784 */ 785 bar = 3 * idx; 786 787 return setup_port(priv, port, bar, 0, board->reg_shift); 788 } else { 789 return pci_default_setup(priv, board, port, idx); 790 } 791} 792 793/* the 99xx series comes with a range of device IDs and a variety 794 * of capabilities: 795 * 796 * 9900 has varying capabilities and can cascade to sub-controllers 797 * (cascading should be purely internal) 798 * 9904 is hardwired with 4 serial ports 799 * 9912 and 9922 are hardwired with 2 serial ports 800 */ 801static int pci_netmos_9900_numports(struct pci_dev *dev) 802{ 803 unsigned int c = dev->class; 804 unsigned int pi; 805 unsigned short sub_serports; 806 807 pi = (c & 0xff); 808 809 if (pi == 2) { 810 return 1; 811 } else if ((pi == 0) && 812 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 813 /* two possibilities: 0x30ps encodes number of parallel and 814 * serial ports, or 0x1000 indicates *something*. This is not 815 * immediately obvious, since the 2s1p+4s configuration seems 816 * to offer all functionality on functions 0..2, while still 817 * advertising the same function 3 as the 4s+2s1p config. 818 */ 819 sub_serports = dev->subsystem_device & 0xf; 820 if (sub_serports > 0) { 821 return sub_serports; 822 } else { 823 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 824 return 0; 825 } 826 } 827 828 moan_device("unknown NetMos/Mostech program interface", dev); 829 return 0; 830} 831 832static int pci_netmos_init(struct pci_dev *dev) 833{ 834 /* subdevice 0x00PS means <P> parallel, <S> serial */ 835 unsigned int num_serial = dev->subsystem_device & 0xf; 836 837 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 838 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 839 return 0; 840 841 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 842 dev->subsystem_device == 0x0299) 843 return 0; 844 845 switch (dev->device) { /* FALLTHROUGH on all */ 846 case PCI_DEVICE_ID_NETMOS_9904: 847 case PCI_DEVICE_ID_NETMOS_9912: 848 case PCI_DEVICE_ID_NETMOS_9922: 849 case PCI_DEVICE_ID_NETMOS_9900: 850 num_serial = pci_netmos_9900_numports(dev); 851 break; 852 853 default: 854 if (num_serial == 0 ) { 855 moan_device("unknown NetMos/Mostech device", dev); 856 } 857 } 858 859 if (num_serial == 0) 860 return -ENODEV; 861 862 return num_serial; 863} 864 865/* 866 * These chips are available with optionally one parallel port and up to 867 * two serial ports. Unfortunately they all have the same product id. 868 * 869 * Basic configuration is done over a region of 32 I/O ports. The base 870 * ioport is called INTA or INTC, depending on docs/other drivers. 871 * 872 * The region of the 32 I/O ports is configured in POSIO0R... 873 */ 874 875/* registers */ 876#define ITE_887x_MISCR 0x9c 877#define ITE_887x_INTCBAR 0x78 878#define ITE_887x_UARTBAR 0x7c 879#define ITE_887x_PS0BAR 0x10 880#define ITE_887x_POSIO0 0x60 881 882/* I/O space size */ 883#define ITE_887x_IOSIZE 32 884/* I/O space size (bits 26-24; 8 bytes = 011b) */ 885#define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 886/* I/O space size (bits 26-24; 32 bytes = 101b) */ 887#define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 888/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 889#define ITE_887x_POSIO_SPEED (3 << 29) 890/* enable IO_Space bit */ 891#define ITE_887x_POSIO_ENABLE (1 << 31) 892 893static int pci_ite887x_init(struct pci_dev *dev) 894{ 895 /* inta_addr are the configuration addresses of the ITE */ 896 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 897 0x200, 0x280, 0 }; 898 int ret, i, type; 899 struct resource *iobase = NULL; 900 u32 miscr, uartbar, ioport; 901 902 /* search for the base-ioport */ 903 i = 0; 904 while (inta_addr[i] && iobase == NULL) { 905 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 906 "ite887x"); 907 if (iobase != NULL) { 908 /* write POSIO0R - speed | size | ioport */ 909 pci_write_config_dword(dev, ITE_887x_POSIO0, 910 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 911 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 912 /* write INTCBAR - ioport */ 913 pci_write_config_dword(dev, ITE_887x_INTCBAR, 914 inta_addr[i]); 915 ret = inb(inta_addr[i]); 916 if (ret != 0xff) { 917 /* ioport connected */ 918 break; 919 } 920 release_region(iobase->start, ITE_887x_IOSIZE); 921 iobase = NULL; 922 } 923 i++; 924 } 925 926 if (!inta_addr[i]) { 927 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 928 return -ENODEV; 929 } 930 931 /* start of undocumented type checking (see parport_pc.c) */ 932 type = inb(iobase->start + 0x18) & 0x0f; 933 934 switch (type) { 935 case 0x2: /* ITE8871 (1P) */ 936 case 0xa: /* ITE8875 (1P) */ 937 ret = 0; 938 break; 939 case 0xe: /* ITE8872 (2S1P) */ 940 ret = 2; 941 break; 942 case 0x6: /* ITE8873 (1S) */ 943 ret = 1; 944 break; 945 case 0x8: /* ITE8874 (2S) */ 946 ret = 2; 947 break; 948 default: 949 moan_device("Unknown ITE887x", dev); 950 ret = -ENODEV; 951 } 952 953 /* configure all serial ports */ 954 for (i = 0; i < ret; i++) { 955 /* read the I/O port from the device */ 956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 957 &ioport); 958 ioport &= 0x0000FF00; /* the actual base address */ 959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 961 ITE_887x_POSIO_IOSIZE_8 | ioport); 962 963 /* write the ioport to the UARTBAR */ 964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 966 uartbar |= (ioport << (16 * i)); /* set the ioport */ 967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 968 969 /* get current config */ 970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 971 /* disable interrupts (UARTx_Routing[3:0]) */ 972 miscr &= ~(0xf << (12 - 4 * i)); 973 /* activate the UART (UARTx_En) */ 974 miscr |= 1 << (23 - i); 975 /* write new config with activated UART */ 976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 977 } 978 979 if (ret <= 0) { 980 /* the device has no UARTs if we get here */ 981 release_region(iobase->start, ITE_887x_IOSIZE); 982 } 983 984 return ret; 985} 986 987static void pci_ite887x_exit(struct pci_dev *dev) 988{ 989 u32 ioport; 990 /* the ioport is bit 0-15 in POSIO0R */ 991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 992 ioport &= 0xffff; 993 release_region(ioport, ITE_887x_IOSIZE); 994} 995 996/* 997 * EndRun Technologies. 998 * Determine the number of ports available on the device. 999 */ 1000#define PCI_VENDOR_ID_ENDRUN 0x7401 1001#define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1002 1003static int pci_endrun_init(struct pci_dev *dev) 1004{ 1005 u8 __iomem *p; 1006 unsigned long deviceID; 1007 unsigned int number_uarts = 0; 1008 1009 /* EndRun device is all 0xexxx */ 1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1011 (dev->device & 0xf000) != 0xe000) 1012 return 0; 1013 1014 p = pci_iomap(dev, 0, 5); 1015 if (p == NULL) 1016 return -ENOMEM; 1017 1018 deviceID = ioread32(p); 1019 /* EndRun device */ 1020 if (deviceID == 0x07000200) { 1021 number_uarts = ioread8(p + 4); 1022 dev_dbg(&dev->dev, 1023 "%d ports detected on EndRun PCI Express device\n", 1024 number_uarts); 1025 } 1026 pci_iounmap(dev, p); 1027 return number_uarts; 1028} 1029 1030/* 1031 * Oxford Semiconductor Inc. 1032 * Check that device is part of the Tornado range of devices, then determine 1033 * the number of ports available on the device. 1034 */ 1035static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1036{ 1037 u8 __iomem *p; 1038 unsigned long deviceID; 1039 unsigned int number_uarts = 0; 1040 1041 /* OxSemi Tornado devices are all 0xCxxx */ 1042 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1043 (dev->device & 0xF000) != 0xC000) 1044 return 0; 1045 1046 p = pci_iomap(dev, 0, 5); 1047 if (p == NULL) 1048 return -ENOMEM; 1049 1050 deviceID = ioread32(p); 1051 /* Tornado device */ 1052 if (deviceID == 0x07000200) { 1053 number_uarts = ioread8(p + 4); 1054 dev_dbg(&dev->dev, 1055 "%d ports detected on Oxford PCI Express device\n", 1056 number_uarts); 1057 } 1058 pci_iounmap(dev, p); 1059 return number_uarts; 1060} 1061 1062static int pci_asix_setup(struct serial_private *priv, 1063 const struct pciserial_board *board, 1064 struct uart_8250_port *port, int idx) 1065{ 1066 port->bugs |= UART_BUG_PARITY; 1067 return pci_default_setup(priv, board, port, idx); 1068} 1069 1070/* Quatech devices have their own extra interface features */ 1071 1072struct quatech_feature { 1073 u16 devid; 1074 bool amcc; 1075}; 1076 1077#define QPCR_TEST_FOR1 0x3F 1078#define QPCR_TEST_GET1 0x00 1079#define QPCR_TEST_FOR2 0x40 1080#define QPCR_TEST_GET2 0x40 1081#define QPCR_TEST_FOR3 0x80 1082#define QPCR_TEST_GET3 0x40 1083#define QPCR_TEST_FOR4 0xC0 1084#define QPCR_TEST_GET4 0x80 1085 1086#define QOPR_CLOCK_X1 0x0000 1087#define QOPR_CLOCK_X2 0x0001 1088#define QOPR_CLOCK_X4 0x0002 1089#define QOPR_CLOCK_X8 0x0003 1090#define QOPR_CLOCK_RATE_MASK 0x0003 1091 1092 1093static struct quatech_feature quatech_cards[] = { 1094 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1095 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1096 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1097 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1098 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1099 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1100 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1101 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1102 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1104 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1105 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1106 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1107 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1108 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1109 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1110 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1111 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1112 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1113 { 0, } 1114}; 1115 1116static int pci_quatech_amcc(u16 devid) 1117{ 1118 struct quatech_feature *qf = &quatech_cards[0]; 1119 while (qf->devid) { 1120 if (qf->devid == devid) 1121 return qf->amcc; 1122 qf++; 1123 } 1124 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1125 return 0; 1126}; 1127 1128static int pci_quatech_rqopr(struct uart_8250_port *port) 1129{ 1130 unsigned long base = port->port.iobase; 1131 u8 LCR, val; 1132 1133 LCR = inb(base + UART_LCR); 1134 outb(0xBF, base + UART_LCR); 1135 val = inb(base + UART_SCR); 1136 outb(LCR, base + UART_LCR); 1137 return val; 1138} 1139 1140static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1141{ 1142 unsigned long base = port->port.iobase; 1143 u8 LCR, val; 1144 1145 LCR = inb(base + UART_LCR); 1146 outb(0xBF, base + UART_LCR); 1147 val = inb(base + UART_SCR); 1148 outb(qopr, base + UART_SCR); 1149 outb(LCR, base + UART_LCR); 1150} 1151 1152static int pci_quatech_rqmcr(struct uart_8250_port *port) 1153{ 1154 unsigned long base = port->port.iobase; 1155 u8 LCR, val, qmcr; 1156 1157 LCR = inb(base + UART_LCR); 1158 outb(0xBF, base + UART_LCR); 1159 val = inb(base + UART_SCR); 1160 outb(val | 0x10, base + UART_SCR); 1161 qmcr = inb(base + UART_MCR); 1162 outb(val, base + UART_SCR); 1163 outb(LCR, base + UART_LCR); 1164 1165 return qmcr; 1166} 1167 1168static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1169{ 1170 unsigned long base = port->port.iobase; 1171 u8 LCR, val; 1172 1173 LCR = inb(base + UART_LCR); 1174 outb(0xBF, base + UART_LCR); 1175 val = inb(base + UART_SCR); 1176 outb(val | 0x10, base + UART_SCR); 1177 outb(qmcr, base + UART_MCR); 1178 outb(val, base + UART_SCR); 1179 outb(LCR, base + UART_LCR); 1180} 1181 1182static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1183{ 1184 unsigned long base = port->port.iobase; 1185 u8 LCR, val; 1186 1187 LCR = inb(base + UART_LCR); 1188 outb(0xBF, base + UART_LCR); 1189 val = inb(base + UART_SCR); 1190 if (val & 0x20) { 1191 outb(0x80, UART_LCR); 1192 if (!(inb(UART_SCR) & 0x20)) { 1193 outb(LCR, base + UART_LCR); 1194 return 1; 1195 } 1196 } 1197 return 0; 1198} 1199 1200static int pci_quatech_test(struct uart_8250_port *port) 1201{ 1202 u8 reg; 1203 u8 qopr = pci_quatech_rqopr(port); 1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1205 reg = pci_quatech_rqopr(port) & 0xC0; 1206 if (reg != QPCR_TEST_GET1) 1207 return -EINVAL; 1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1209 reg = pci_quatech_rqopr(port) & 0xC0; 1210 if (reg != QPCR_TEST_GET2) 1211 return -EINVAL; 1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1213 reg = pci_quatech_rqopr(port) & 0xC0; 1214 if (reg != QPCR_TEST_GET3) 1215 return -EINVAL; 1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1217 reg = pci_quatech_rqopr(port) & 0xC0; 1218 if (reg != QPCR_TEST_GET4) 1219 return -EINVAL; 1220 1221 pci_quatech_wqopr(port, qopr); 1222 return 0; 1223} 1224 1225static int pci_quatech_clock(struct uart_8250_port *port) 1226{ 1227 u8 qopr, reg, set; 1228 unsigned long clock; 1229 1230 if (pci_quatech_test(port) < 0) 1231 return 1843200; 1232 1233 qopr = pci_quatech_rqopr(port); 1234 1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1236 reg = pci_quatech_rqopr(port); 1237 if (reg & QOPR_CLOCK_X8) { 1238 clock = 1843200; 1239 goto out; 1240 } 1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1242 reg = pci_quatech_rqopr(port); 1243 if (!(reg & QOPR_CLOCK_X8)) { 1244 clock = 1843200; 1245 goto out; 1246 } 1247 reg &= QOPR_CLOCK_X8; 1248 if (reg == QOPR_CLOCK_X2) { 1249 clock = 3685400; 1250 set = QOPR_CLOCK_X2; 1251 } else if (reg == QOPR_CLOCK_X4) { 1252 clock = 7372800; 1253 set = QOPR_CLOCK_X4; 1254 } else if (reg == QOPR_CLOCK_X8) { 1255 clock = 14745600; 1256 set = QOPR_CLOCK_X8; 1257 } else { 1258 clock = 1843200; 1259 set = QOPR_CLOCK_X1; 1260 } 1261 qopr &= ~QOPR_CLOCK_RATE_MASK; 1262 qopr |= set; 1263 1264out: 1265 pci_quatech_wqopr(port, qopr); 1266 return clock; 1267} 1268 1269static int pci_quatech_rs422(struct uart_8250_port *port) 1270{ 1271 u8 qmcr; 1272 int rs422 = 0; 1273 1274 if (!pci_quatech_has_qmcr(port)) 1275 return 0; 1276 qmcr = pci_quatech_rqmcr(port); 1277 pci_quatech_wqmcr(port, 0xFF); 1278 if (pci_quatech_rqmcr(port)) 1279 rs422 = 1; 1280 pci_quatech_wqmcr(port, qmcr); 1281 return rs422; 1282} 1283 1284static int pci_quatech_init(struct pci_dev *dev) 1285{ 1286 if (pci_quatech_amcc(dev->device)) { 1287 unsigned long base = pci_resource_start(dev, 0); 1288 if (base) { 1289 u32 tmp; 1290 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1291 tmp = inl(base + 0x3c); 1292 outl(tmp | 0x01000000, base + 0x3c); 1293 outl(tmp &= ~0x01000000, base + 0x3c); 1294 } 1295 } 1296 return 0; 1297} 1298 1299static int pci_quatech_setup(struct serial_private *priv, 1300 const struct pciserial_board *board, 1301 struct uart_8250_port *port, int idx) 1302{ 1303 /* Needed by pci_quatech calls below */ 1304 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1305 /* Set up the clocking */ 1306 port->port.uartclk = pci_quatech_clock(port); 1307 /* For now just warn about RS422 */ 1308 if (pci_quatech_rs422(port)) 1309 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1310 return pci_default_setup(priv, board, port, idx); 1311} 1312 1313static void pci_quatech_exit(struct pci_dev *dev) 1314{ 1315} 1316 1317static int pci_default_setup(struct serial_private *priv, 1318 const struct pciserial_board *board, 1319 struct uart_8250_port *port, int idx) 1320{ 1321 unsigned int bar, offset = board->first_offset, maxnr; 1322 1323 bar = FL_GET_BASE(board->flags); 1324 if (board->flags & FL_BASE_BARS) 1325 bar += idx; 1326 else 1327 offset += idx * board->uart_offset; 1328 1329 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1330 (board->reg_shift + 3); 1331 1332 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1333 return 1; 1334 1335 return setup_port(priv, port, bar, offset, board->reg_shift); 1336} 1337 1338static int pci_pericom_setup(struct serial_private *priv, 1339 const struct pciserial_board *board, 1340 struct uart_8250_port *port, int idx) 1341{ 1342 unsigned int bar, offset = board->first_offset, maxnr; 1343 1344 bar = FL_GET_BASE(board->flags); 1345 if (board->flags & FL_BASE_BARS) 1346 bar += idx; 1347 else 1348 offset += idx * board->uart_offset; 1349 1350 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1351 (board->reg_shift + 3); 1352 1353 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1354 return 1; 1355 1356 port->port.uartclk = 14745600; 1357 1358 return setup_port(priv, port, bar, offset, board->reg_shift); 1359} 1360 1361static int 1362ce4100_serial_setup(struct serial_private *priv, 1363 const struct pciserial_board *board, 1364 struct uart_8250_port *port, int idx) 1365{ 1366 int ret; 1367 1368 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1369 port->port.iotype = UPIO_MEM32; 1370 port->port.type = PORT_XSCALE; 1371 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1372 port->port.regshift = 2; 1373 1374 return ret; 1375} 1376 1377#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1378#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1379 1380#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a 1381#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c 1382 1383#define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3 1384#define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4 1385 1386#define BYT_PRV_CLK 0x800 1387#define BYT_PRV_CLK_EN (1 << 0) 1388#define BYT_PRV_CLK_M_VAL_SHIFT 1 1389#define BYT_PRV_CLK_N_VAL_SHIFT 16 1390#define BYT_PRV_CLK_UPDATE (1 << 31) 1391 1392#define BYT_TX_OVF_INT 0x820 1393#define BYT_TX_OVF_INT_MASK (1 << 1) 1394 1395static void 1396byt_set_termios(struct uart_port *p, struct ktermios *termios, 1397 struct ktermios *old) 1398{ 1399 unsigned int baud = tty_termios_baud_rate(termios); 1400 unsigned long fref = 100000000, fuart = baud * 16; 1401 unsigned long w = BIT(15) - 1; 1402 unsigned long m, n; 1403 u32 reg; 1404 1405 /* Gracefully handle the B0 case: fall back to B9600 */ 1406 fuart = fuart ? fuart : 9600 * 16; 1407 1408 /* Get Fuart closer to Fref */ 1409 fuart *= rounddown_pow_of_two(fref / fuart); 1410 1411 /* 1412 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 1413 * dividers must be adjusted. 1414 * 1415 * uartclk = (m / n) * 100 MHz, where m <= n 1416 */ 1417 rational_best_approximation(fuart, fref, w, w, &m, &n); 1418 p->uartclk = fuart; 1419 1420 /* Reset the clock */ 1421 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 1422 writel(reg, p->membase + BYT_PRV_CLK); 1423 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 1424 writel(reg, p->membase + BYT_PRV_CLK); 1425 1426 serial8250_do_set_termios(p, termios, old); 1427} 1428 1429static bool byt_dma_filter(struct dma_chan *chan, void *param) 1430{ 1431 struct dw_dma_slave *dws = param; 1432 1433 if (dws->dma_dev != chan->device->dev) 1434 return false; 1435 1436 chan->private = dws; 1437 return true; 1438} 1439 1440static int 1441byt_serial_setup(struct serial_private *priv, 1442 const struct pciserial_board *board, 1443 struct uart_8250_port *port, int idx) 1444{ 1445 struct pci_dev *pdev = priv->dev; 1446 struct device *dev = port->port.dev; 1447 struct uart_8250_dma *dma; 1448 struct dw_dma_slave *tx_param, *rx_param; 1449 struct pci_dev *dma_dev; 1450 int ret; 1451 1452 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 1453 if (!dma) 1454 return -ENOMEM; 1455 1456 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); 1457 if (!tx_param) 1458 return -ENOMEM; 1459 1460 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); 1461 if (!rx_param) 1462 return -ENOMEM; 1463 1464 switch (pdev->device) { 1465 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1466 case PCI_DEVICE_ID_INTEL_BSW_UART1: 1467 case PCI_DEVICE_ID_INTEL_BDW_UART1: 1468 rx_param->src_id = 3; 1469 tx_param->dst_id = 2; 1470 break; 1471 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1472 case PCI_DEVICE_ID_INTEL_BSW_UART2: 1473 case PCI_DEVICE_ID_INTEL_BDW_UART2: 1474 rx_param->src_id = 5; 1475 tx_param->dst_id = 4; 1476 break; 1477 default: 1478 return -EINVAL; 1479 } 1480 1481 rx_param->src_master = 1; 1482 rx_param->dst_master = 0; 1483 1484 dma->rxconf.src_maxburst = 16; 1485 1486 tx_param->src_master = 1; 1487 tx_param->dst_master = 0; 1488 1489 dma->txconf.dst_maxburst = 16; 1490 1491 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 1492 rx_param->dma_dev = &dma_dev->dev; 1493 tx_param->dma_dev = &dma_dev->dev; 1494 1495 dma->fn = byt_dma_filter; 1496 dma->rx_param = rx_param; 1497 dma->tx_param = tx_param; 1498 1499 ret = pci_default_setup(priv, board, port, idx); 1500 port->port.iotype = UPIO_MEM; 1501 port->port.type = PORT_16550A; 1502 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1503 port->port.set_termios = byt_set_termios; 1504 port->port.fifosize = 64; 1505 port->tx_loadsz = 64; 1506 port->dma = dma; 1507 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; 1508 1509 /* Disable Tx counter interrupts */ 1510 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); 1511 1512 return ret; 1513} 1514 1515#define INTEL_MID_UART_PS 0x30 1516#define INTEL_MID_UART_MUL 0x34 1517#define INTEL_MID_UART_DIV 0x38 1518 1519static void intel_mid_set_termios(struct uart_port *p, 1520 struct ktermios *termios, 1521 struct ktermios *old, 1522 unsigned long fref) 1523{ 1524 unsigned int baud = tty_termios_baud_rate(termios); 1525 unsigned short ps = 16; 1526 unsigned long fuart = baud * ps; 1527 unsigned long w = BIT(24) - 1; 1528 unsigned long mul, div; 1529 1530 if (fref < fuart) { 1531 /* Find prescaler value that satisfies Fuart < Fref */ 1532 if (fref > baud) 1533 ps = fref / baud; /* baud rate too high */ 1534 else 1535 ps = 1; /* PLL case */ 1536 fuart = baud * ps; 1537 } else { 1538 /* Get Fuart closer to Fref */ 1539 fuart *= rounddown_pow_of_two(fref / fuart); 1540 } 1541 1542 rational_best_approximation(fuart, fref, w, w, &mul, &div); 1543 p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */ 1544 1545 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ 1546 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ 1547 writel(div, p->membase + INTEL_MID_UART_DIV); 1548 1549 serial8250_do_set_termios(p, termios, old); 1550} 1551 1552static void intel_mid_set_termios_38_4M(struct uart_port *p, 1553 struct ktermios *termios, 1554 struct ktermios *old) 1555{ 1556 intel_mid_set_termios(p, termios, old, 38400000); 1557} 1558 1559static void intel_mid_set_termios_50M(struct uart_port *p, 1560 struct ktermios *termios, 1561 struct ktermios *old) 1562{ 1563 /* 1564 * The uart clk is 50Mhz, and the baud rate come from: 1565 * baud = 50M * MUL / (DIV * PS * DLAB) 1566 */ 1567 intel_mid_set_termios(p, termios, old, 50000000); 1568} 1569 1570static bool intel_mid_dma_filter(struct dma_chan *chan, void *param) 1571{ 1572 struct hsu_dma_slave *s = param; 1573 1574 if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id) 1575 return false; 1576 1577 chan->private = s; 1578 return true; 1579} 1580 1581static int intel_mid_serial_setup(struct serial_private *priv, 1582 const struct pciserial_board *board, 1583 struct uart_8250_port *port, int idx, 1584 int index, struct pci_dev *dma_dev) 1585{ 1586 struct device *dev = port->port.dev; 1587 struct uart_8250_dma *dma; 1588 struct hsu_dma_slave *tx_param, *rx_param; 1589 1590 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 1591 if (!dma) 1592 return -ENOMEM; 1593 1594 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); 1595 if (!tx_param) 1596 return -ENOMEM; 1597 1598 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); 1599 if (!rx_param) 1600 return -ENOMEM; 1601 1602 rx_param->chan_id = index * 2 + 1; 1603 tx_param->chan_id = index * 2; 1604 1605 dma->rxconf.src_maxburst = 64; 1606 dma->txconf.dst_maxburst = 64; 1607 1608 rx_param->dma_dev = &dma_dev->dev; 1609 tx_param->dma_dev = &dma_dev->dev; 1610 1611 dma->fn = intel_mid_dma_filter; 1612 dma->rx_param = rx_param; 1613 dma->tx_param = tx_param; 1614 1615 port->port.type = PORT_16750; 1616 port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE; 1617 port->dma = dma; 1618 1619 return pci_default_setup(priv, board, port, idx); 1620} 1621 1622#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b 1623#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c 1624#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d 1625 1626static int pnw_serial_setup(struct serial_private *priv, 1627 const struct pciserial_board *board, 1628 struct uart_8250_port *port, int idx) 1629{ 1630 struct pci_dev *pdev = priv->dev; 1631 struct pci_dev *dma_dev; 1632 int index; 1633 1634 switch (pdev->device) { 1635 case PCI_DEVICE_ID_INTEL_PNW_UART1: 1636 index = 0; 1637 break; 1638 case PCI_DEVICE_ID_INTEL_PNW_UART2: 1639 index = 1; 1640 break; 1641 case PCI_DEVICE_ID_INTEL_PNW_UART3: 1642 index = 2; 1643 break; 1644 default: 1645 return -EINVAL; 1646 } 1647 1648 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3)); 1649 1650 port->port.set_termios = intel_mid_set_termios_50M; 1651 1652 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev); 1653} 1654 1655#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191 1656 1657static int tng_serial_setup(struct serial_private *priv, 1658 const struct pciserial_board *board, 1659 struct uart_8250_port *port, int idx) 1660{ 1661 struct pci_dev *pdev = priv->dev; 1662 struct pci_dev *dma_dev; 1663 int index = PCI_FUNC(pdev->devfn); 1664 1665 /* Currently no support for HSU port0 */ 1666 if (index-- == 0) 1667 return -ENODEV; 1668 1669 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0)); 1670 1671 port->port.set_termios = intel_mid_set_termios_38_4M; 1672 1673 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev); 1674} 1675 1676static int 1677pci_omegapci_setup(struct serial_private *priv, 1678 const struct pciserial_board *board, 1679 struct uart_8250_port *port, int idx) 1680{ 1681 return setup_port(priv, port, 2, idx * 8, 0); 1682} 1683 1684static int 1685pci_brcm_trumanage_setup(struct serial_private *priv, 1686 const struct pciserial_board *board, 1687 struct uart_8250_port *port, int idx) 1688{ 1689 int ret = pci_default_setup(priv, board, port, idx); 1690 1691 port->port.type = PORT_BRCM_TRUMANAGE; 1692 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1693 return ret; 1694} 1695 1696static int pci_fintek_setup(struct serial_private *priv, 1697 const struct pciserial_board *board, 1698 struct uart_8250_port *port, int idx) 1699{ 1700 struct pci_dev *pdev = priv->dev; 1701 u8 config_base; 1702 u16 iobase; 1703 1704 config_base = 0x40 + 0x08 * idx; 1705 1706 /* Get the io address from configuration space */ 1707 pci_read_config_word(pdev, config_base + 4, &iobase); 1708 1709 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1710 1711 port->port.iotype = UPIO_PORT; 1712 port->port.iobase = iobase; 1713 1714 return 0; 1715} 1716 1717static int pci_fintek_init(struct pci_dev *dev) 1718{ 1719 unsigned long iobase; 1720 u32 max_port, i; 1721 u32 bar_data[3]; 1722 u8 config_base; 1723 1724 switch (dev->device) { 1725 case 0x1104: /* 4 ports */ 1726 case 0x1108: /* 8 ports */ 1727 max_port = dev->device & 0xff; 1728 break; 1729 case 0x1112: /* 12 ports */ 1730 max_port = 12; 1731 break; 1732 default: 1733 return -EINVAL; 1734 } 1735 1736 /* Get the io address dispatch from the BIOS */ 1737 pci_read_config_dword(dev, 0x24, &bar_data[0]); 1738 pci_read_config_dword(dev, 0x20, &bar_data[1]); 1739 pci_read_config_dword(dev, 0x1c, &bar_data[2]); 1740 1741 for (i = 0; i < max_port; ++i) { 1742 /* UART0 configuration offset start from 0x40 */ 1743 config_base = 0x40 + 0x08 * i; 1744 1745 /* Calculate Real IO Port */ 1746 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1747 1748 /* Enable UART I/O port */ 1749 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1750 1751 /* Select 128-byte FIFO and 8x FIFO threshold */ 1752 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1753 1754 /* LSB UART */ 1755 pci_write_config_byte(dev, config_base + 0x04, 1756 (u8)(iobase & 0xff)); 1757 1758 /* MSB UART */ 1759 pci_write_config_byte(dev, config_base + 0x05, 1760 (u8)((iobase & 0xff00) >> 8)); 1761 1762 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1763 } 1764 1765 return max_port; 1766} 1767 1768static int skip_tx_en_setup(struct serial_private *priv, 1769 const struct pciserial_board *board, 1770 struct uart_8250_port *port, int idx) 1771{ 1772 port->port.flags |= UPF_NO_TXEN_TEST; 1773 dev_dbg(&priv->dev->dev, 1774 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1775 priv->dev->vendor, priv->dev->device, 1776 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1777 1778 return pci_default_setup(priv, board, port, idx); 1779} 1780 1781static void kt_handle_break(struct uart_port *p) 1782{ 1783 struct uart_8250_port *up = up_to_u8250p(p); 1784 /* 1785 * On receipt of a BI, serial device in Intel ME (Intel 1786 * management engine) needs to have its fifos cleared for sane 1787 * SOL (Serial Over Lan) output. 1788 */ 1789 serial8250_clear_and_reinit_fifos(up); 1790} 1791 1792static unsigned int kt_serial_in(struct uart_port *p, int offset) 1793{ 1794 struct uart_8250_port *up = up_to_u8250p(p); 1795 unsigned int val; 1796 1797 /* 1798 * When the Intel ME (management engine) gets reset its serial 1799 * port registers could return 0 momentarily. Functions like 1800 * serial8250_console_write, read and save the IER, perform 1801 * some operation and then restore it. In order to avoid 1802 * setting IER register inadvertently to 0, if the value read 1803 * is 0, double check with ier value in uart_8250_port and use 1804 * that instead. up->ier should be the same value as what is 1805 * currently configured. 1806 */ 1807 val = inb(p->iobase + offset); 1808 if (offset == UART_IER) { 1809 if (val == 0) 1810 val = up->ier; 1811 } 1812 return val; 1813} 1814 1815static int kt_serial_setup(struct serial_private *priv, 1816 const struct pciserial_board *board, 1817 struct uart_8250_port *port, int idx) 1818{ 1819 port->port.flags |= UPF_BUG_THRE; 1820 port->port.serial_in = kt_serial_in; 1821 port->port.handle_break = kt_handle_break; 1822 return skip_tx_en_setup(priv, board, port, idx); 1823} 1824 1825static int pci_eg20t_init(struct pci_dev *dev) 1826{ 1827#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1828 return -ENODEV; 1829#else 1830 return 0; 1831#endif 1832} 1833 1834static int 1835pci_xr17c154_setup(struct serial_private *priv, 1836 const struct pciserial_board *board, 1837 struct uart_8250_port *port, int idx) 1838{ 1839 port->port.flags |= UPF_EXAR_EFR; 1840 return pci_default_setup(priv, board, port, idx); 1841} 1842 1843static int 1844pci_xr17v35x_setup(struct serial_private *priv, 1845 const struct pciserial_board *board, 1846 struct uart_8250_port *port, int idx) 1847{ 1848 u8 __iomem *p; 1849 1850 p = pci_ioremap_bar(priv->dev, 0); 1851 if (p == NULL) 1852 return -ENOMEM; 1853 1854 port->port.flags |= UPF_EXAR_EFR; 1855 1856 /* 1857 * Setup Multipurpose Input/Output pins. 1858 */ 1859 if (idx == 0) { 1860 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1861 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1862 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1863 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1864 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1865 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1866 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1867 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1868 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1869 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1870 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1871 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1872 } 1873 writeb(0x00, p + UART_EXAR_8XMODE); 1874 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1875 writeb(128, p + UART_EXAR_TXTRG); 1876 writeb(128, p + UART_EXAR_RXTRG); 1877 iounmap(p); 1878 1879 return pci_default_setup(priv, board, port, idx); 1880} 1881 1882#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1883#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1884#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1885#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1886 1887static int 1888pci_fastcom335_setup(struct serial_private *priv, 1889 const struct pciserial_board *board, 1890 struct uart_8250_port *port, int idx) 1891{ 1892 u8 __iomem *p; 1893 1894 p = pci_ioremap_bar(priv->dev, 0); 1895 if (p == NULL) 1896 return -ENOMEM; 1897 1898 port->port.flags |= UPF_EXAR_EFR; 1899 1900 /* 1901 * Setup Multipurpose Input/Output pins. 1902 */ 1903 if (idx == 0) { 1904 switch (priv->dev->device) { 1905 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1906 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1907 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1908 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1909 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1910 break; 1911 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1912 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1913 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1914 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1915 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1916 break; 1917 } 1918 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1919 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1920 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1921 } 1922 writeb(0x00, p + UART_EXAR_8XMODE); 1923 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1924 writeb(32, p + UART_EXAR_TXTRG); 1925 writeb(32, p + UART_EXAR_RXTRG); 1926 iounmap(p); 1927 1928 return pci_default_setup(priv, board, port, idx); 1929} 1930 1931static int 1932pci_wch_ch353_setup(struct serial_private *priv, 1933 const struct pciserial_board *board, 1934 struct uart_8250_port *port, int idx) 1935{ 1936 port->port.flags |= UPF_FIXED_TYPE; 1937 port->port.type = PORT_16550A; 1938 return pci_default_setup(priv, board, port, idx); 1939} 1940 1941static int 1942pci_wch_ch38x_setup(struct serial_private *priv, 1943 const struct pciserial_board *board, 1944 struct uart_8250_port *port, int idx) 1945{ 1946 port->port.flags |= UPF_FIXED_TYPE; 1947 port->port.type = PORT_16850; 1948 return pci_default_setup(priv, board, port, idx); 1949} 1950 1951#define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1952#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1953#define PCI_DEVICE_ID_OCTPRO 0x0001 1954#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1955#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1956#define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1957#define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1958#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1959#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1960#define PCI_VENDOR_ID_ADVANTECH 0x13fe 1961#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1962#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1963#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1964#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1965#define PCI_DEVICE_ID_TITAN_200I 0x8028 1966#define PCI_DEVICE_ID_TITAN_400I 0x8048 1967#define PCI_DEVICE_ID_TITAN_800I 0x8088 1968#define PCI_DEVICE_ID_TITAN_800EH 0xA007 1969#define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1970#define PCI_DEVICE_ID_TITAN_400EH 0xA009 1971#define PCI_DEVICE_ID_TITAN_100E 0xA010 1972#define PCI_DEVICE_ID_TITAN_200E 0xA012 1973#define PCI_DEVICE_ID_TITAN_400E 0xA013 1974#define PCI_DEVICE_ID_TITAN_800E 0xA014 1975#define PCI_DEVICE_ID_TITAN_200EI 0xA016 1976#define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1977#define PCI_DEVICE_ID_TITAN_200V3 0xA306 1978#define PCI_DEVICE_ID_TITAN_400V3 0xA310 1979#define PCI_DEVICE_ID_TITAN_410V3 0xA312 1980#define PCI_DEVICE_ID_TITAN_800V3 0xA314 1981#define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1982#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1983#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1984#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1985#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1986#define PCI_VENDOR_ID_WCH 0x4348 1987#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1988#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1989#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1990#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1991#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1992#define PCI_VENDOR_ID_AGESTAR 0x5372 1993#define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1994#define PCI_VENDOR_ID_ASIX 0x9710 1995#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1996#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1997#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1998#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1999#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 2000#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 2001 2002#define PCI_VENDOR_ID_SUNIX 0x1fd4 2003#define PCI_DEVICE_ID_SUNIX_1999 0x1999 2004 2005#define PCIE_VENDOR_ID_WCH 0x1c00 2006#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 2007#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 2008#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 2009 2010#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 2011#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 2012 2013#define PCI_VENDOR_ID_PERICOM 0x12D8 2014#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 2015#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 2016#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 2017#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 2018 2019/* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 2020#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 2021#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 2022 2023/* 2024 * Master list of serial port init/setup/exit quirks. 2025 * This does not describe the general nature of the port. 2026 * (ie, baud base, number and location of ports, etc) 2027 * 2028 * This list is ordered alphabetically by vendor then device. 2029 * Specific entries must come before more generic entries. 2030 */ 2031static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 2032 /* 2033 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2034 */ 2035 { 2036 .vendor = PCI_VENDOR_ID_AMCC, 2037 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2038 .subvendor = PCI_ANY_ID, 2039 .subdevice = PCI_ANY_ID, 2040 .setup = addidata_apci7800_setup, 2041 }, 2042 /* 2043 * AFAVLAB cards - these may be called via parport_serial 2044 * It is not clear whether this applies to all products. 2045 */ 2046 { 2047 .vendor = PCI_VENDOR_ID_AFAVLAB, 2048 .device = PCI_ANY_ID, 2049 .subvendor = PCI_ANY_ID, 2050 .subdevice = PCI_ANY_ID, 2051 .setup = afavlab_setup, 2052 }, 2053 /* 2054 * HP Diva 2055 */ 2056 { 2057 .vendor = PCI_VENDOR_ID_HP, 2058 .device = PCI_DEVICE_ID_HP_DIVA, 2059 .subvendor = PCI_ANY_ID, 2060 .subdevice = PCI_ANY_ID, 2061 .init = pci_hp_diva_init, 2062 .setup = pci_hp_diva_setup, 2063 }, 2064 /* 2065 * Intel 2066 */ 2067 { 2068 .vendor = PCI_VENDOR_ID_INTEL, 2069 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2070 .subvendor = 0xe4bf, 2071 .subdevice = PCI_ANY_ID, 2072 .init = pci_inteli960ni_init, 2073 .setup = pci_default_setup, 2074 }, 2075 { 2076 .vendor = PCI_VENDOR_ID_INTEL, 2077 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2078 .subvendor = PCI_ANY_ID, 2079 .subdevice = PCI_ANY_ID, 2080 .setup = skip_tx_en_setup, 2081 }, 2082 { 2083 .vendor = PCI_VENDOR_ID_INTEL, 2084 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2085 .subvendor = PCI_ANY_ID, 2086 .subdevice = PCI_ANY_ID, 2087 .setup = skip_tx_en_setup, 2088 }, 2089 { 2090 .vendor = PCI_VENDOR_ID_INTEL, 2091 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2092 .subvendor = PCI_ANY_ID, 2093 .subdevice = PCI_ANY_ID, 2094 .setup = skip_tx_en_setup, 2095 }, 2096 { 2097 .vendor = PCI_VENDOR_ID_INTEL, 2098 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2099 .subvendor = PCI_ANY_ID, 2100 .subdevice = PCI_ANY_ID, 2101 .setup = ce4100_serial_setup, 2102 }, 2103 { 2104 .vendor = PCI_VENDOR_ID_INTEL, 2105 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2106 .subvendor = PCI_ANY_ID, 2107 .subdevice = PCI_ANY_ID, 2108 .setup = kt_serial_setup, 2109 }, 2110 { 2111 .vendor = PCI_VENDOR_ID_INTEL, 2112 .device = PCI_DEVICE_ID_INTEL_BYT_UART1, 2113 .subvendor = PCI_ANY_ID, 2114 .subdevice = PCI_ANY_ID, 2115 .setup = byt_serial_setup, 2116 }, 2117 { 2118 .vendor = PCI_VENDOR_ID_INTEL, 2119 .device = PCI_DEVICE_ID_INTEL_BYT_UART2, 2120 .subvendor = PCI_ANY_ID, 2121 .subdevice = PCI_ANY_ID, 2122 .setup = byt_serial_setup, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_INTEL, 2126 .device = PCI_DEVICE_ID_INTEL_PNW_UART1, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .setup = pnw_serial_setup, 2130 }, 2131 { 2132 .vendor = PCI_VENDOR_ID_INTEL, 2133 .device = PCI_DEVICE_ID_INTEL_PNW_UART2, 2134 .subvendor = PCI_ANY_ID, 2135 .subdevice = PCI_ANY_ID, 2136 .setup = pnw_serial_setup, 2137 }, 2138 { 2139 .vendor = PCI_VENDOR_ID_INTEL, 2140 .device = PCI_DEVICE_ID_INTEL_PNW_UART3, 2141 .subvendor = PCI_ANY_ID, 2142 .subdevice = PCI_ANY_ID, 2143 .setup = pnw_serial_setup, 2144 }, 2145 { 2146 .vendor = PCI_VENDOR_ID_INTEL, 2147 .device = PCI_DEVICE_ID_INTEL_TNG_UART, 2148 .subvendor = PCI_ANY_ID, 2149 .subdevice = PCI_ANY_ID, 2150 .setup = tng_serial_setup, 2151 }, 2152 { 2153 .vendor = PCI_VENDOR_ID_INTEL, 2154 .device = PCI_DEVICE_ID_INTEL_BSW_UART1, 2155 .subvendor = PCI_ANY_ID, 2156 .subdevice = PCI_ANY_ID, 2157 .setup = byt_serial_setup, 2158 }, 2159 { 2160 .vendor = PCI_VENDOR_ID_INTEL, 2161 .device = PCI_DEVICE_ID_INTEL_BSW_UART2, 2162 .subvendor = PCI_ANY_ID, 2163 .subdevice = PCI_ANY_ID, 2164 .setup = byt_serial_setup, 2165 }, 2166 { 2167 .vendor = PCI_VENDOR_ID_INTEL, 2168 .device = PCI_DEVICE_ID_INTEL_BDW_UART1, 2169 .subvendor = PCI_ANY_ID, 2170 .subdevice = PCI_ANY_ID, 2171 .setup = byt_serial_setup, 2172 }, 2173 { 2174 .vendor = PCI_VENDOR_ID_INTEL, 2175 .device = PCI_DEVICE_ID_INTEL_BDW_UART2, 2176 .subvendor = PCI_ANY_ID, 2177 .subdevice = PCI_ANY_ID, 2178 .setup = byt_serial_setup, 2179 }, 2180 /* 2181 * ITE 2182 */ 2183 { 2184 .vendor = PCI_VENDOR_ID_ITE, 2185 .device = PCI_DEVICE_ID_ITE_8872, 2186 .subvendor = PCI_ANY_ID, 2187 .subdevice = PCI_ANY_ID, 2188 .init = pci_ite887x_init, 2189 .setup = pci_default_setup, 2190 .exit = pci_ite887x_exit, 2191 }, 2192 /* 2193 * National Instruments 2194 */ 2195 { 2196 .vendor = PCI_VENDOR_ID_NI, 2197 .device = PCI_DEVICE_ID_NI_PCI23216, 2198 .subvendor = PCI_ANY_ID, 2199 .subdevice = PCI_ANY_ID, 2200 .init = pci_ni8420_init, 2201 .setup = pci_default_setup, 2202 .exit = pci_ni8420_exit, 2203 }, 2204 { 2205 .vendor = PCI_VENDOR_ID_NI, 2206 .device = PCI_DEVICE_ID_NI_PCI2328, 2207 .subvendor = PCI_ANY_ID, 2208 .subdevice = PCI_ANY_ID, 2209 .init = pci_ni8420_init, 2210 .setup = pci_default_setup, 2211 .exit = pci_ni8420_exit, 2212 }, 2213 { 2214 .vendor = PCI_VENDOR_ID_NI, 2215 .device = PCI_DEVICE_ID_NI_PCI2324, 2216 .subvendor = PCI_ANY_ID, 2217 .subdevice = PCI_ANY_ID, 2218 .init = pci_ni8420_init, 2219 .setup = pci_default_setup, 2220 .exit = pci_ni8420_exit, 2221 }, 2222 { 2223 .vendor = PCI_VENDOR_ID_NI, 2224 .device = PCI_DEVICE_ID_NI_PCI2322, 2225 .subvendor = PCI_ANY_ID, 2226 .subdevice = PCI_ANY_ID, 2227 .init = pci_ni8420_init, 2228 .setup = pci_default_setup, 2229 .exit = pci_ni8420_exit, 2230 }, 2231 { 2232 .vendor = PCI_VENDOR_ID_NI, 2233 .device = PCI_DEVICE_ID_NI_PCI2324I, 2234 .subvendor = PCI_ANY_ID, 2235 .subdevice = PCI_ANY_ID, 2236 .init = pci_ni8420_init, 2237 .setup = pci_default_setup, 2238 .exit = pci_ni8420_exit, 2239 }, 2240 { 2241 .vendor = PCI_VENDOR_ID_NI, 2242 .device = PCI_DEVICE_ID_NI_PCI2322I, 2243 .subvendor = PCI_ANY_ID, 2244 .subdevice = PCI_ANY_ID, 2245 .init = pci_ni8420_init, 2246 .setup = pci_default_setup, 2247 .exit = pci_ni8420_exit, 2248 }, 2249 { 2250 .vendor = PCI_VENDOR_ID_NI, 2251 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2252 .subvendor = PCI_ANY_ID, 2253 .subdevice = PCI_ANY_ID, 2254 .init = pci_ni8420_init, 2255 .setup = pci_default_setup, 2256 .exit = pci_ni8420_exit, 2257 }, 2258 { 2259 .vendor = PCI_VENDOR_ID_NI, 2260 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2261 .subvendor = PCI_ANY_ID, 2262 .subdevice = PCI_ANY_ID, 2263 .init = pci_ni8420_init, 2264 .setup = pci_default_setup, 2265 .exit = pci_ni8420_exit, 2266 }, 2267 { 2268 .vendor = PCI_VENDOR_ID_NI, 2269 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2270 .subvendor = PCI_ANY_ID, 2271 .subdevice = PCI_ANY_ID, 2272 .init = pci_ni8420_init, 2273 .setup = pci_default_setup, 2274 .exit = pci_ni8420_exit, 2275 }, 2276 { 2277 .vendor = PCI_VENDOR_ID_NI, 2278 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2279 .subvendor = PCI_ANY_ID, 2280 .subdevice = PCI_ANY_ID, 2281 .init = pci_ni8420_init, 2282 .setup = pci_default_setup, 2283 .exit = pci_ni8420_exit, 2284 }, 2285 { 2286 .vendor = PCI_VENDOR_ID_NI, 2287 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2288 .subvendor = PCI_ANY_ID, 2289 .subdevice = PCI_ANY_ID, 2290 .init = pci_ni8420_init, 2291 .setup = pci_default_setup, 2292 .exit = pci_ni8420_exit, 2293 }, 2294 { 2295 .vendor = PCI_VENDOR_ID_NI, 2296 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2297 .subvendor = PCI_ANY_ID, 2298 .subdevice = PCI_ANY_ID, 2299 .init = pci_ni8420_init, 2300 .setup = pci_default_setup, 2301 .exit = pci_ni8420_exit, 2302 }, 2303 { 2304 .vendor = PCI_VENDOR_ID_NI, 2305 .device = PCI_ANY_ID, 2306 .subvendor = PCI_ANY_ID, 2307 .subdevice = PCI_ANY_ID, 2308 .init = pci_ni8430_init, 2309 .setup = pci_ni8430_setup, 2310 .exit = pci_ni8430_exit, 2311 }, 2312 /* Quatech */ 2313 { 2314 .vendor = PCI_VENDOR_ID_QUATECH, 2315 .device = PCI_ANY_ID, 2316 .subvendor = PCI_ANY_ID, 2317 .subdevice = PCI_ANY_ID, 2318 .init = pci_quatech_init, 2319 .setup = pci_quatech_setup, 2320 .exit = pci_quatech_exit, 2321 }, 2322 /* 2323 * Panacom 2324 */ 2325 { 2326 .vendor = PCI_VENDOR_ID_PANACOM, 2327 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2328 .subvendor = PCI_ANY_ID, 2329 .subdevice = PCI_ANY_ID, 2330 .init = pci_plx9050_init, 2331 .setup = pci_default_setup, 2332 .exit = pci_plx9050_exit, 2333 }, 2334 { 2335 .vendor = PCI_VENDOR_ID_PANACOM, 2336 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2337 .subvendor = PCI_ANY_ID, 2338 .subdevice = PCI_ANY_ID, 2339 .init = pci_plx9050_init, 2340 .setup = pci_default_setup, 2341 .exit = pci_plx9050_exit, 2342 }, 2343 /* 2344 * Pericom 2345 */ 2346 { 2347 .vendor = PCI_VENDOR_ID_PERICOM, 2348 .device = PCI_ANY_ID, 2349 .subvendor = PCI_ANY_ID, 2350 .subdevice = PCI_ANY_ID, 2351 .setup = pci_pericom_setup, 2352 }, 2353 /* 2354 * PLX 2355 */ 2356 { 2357 .vendor = PCI_VENDOR_ID_PLX, 2358 .device = PCI_DEVICE_ID_PLX_9050, 2359 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2360 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2361 .init = pci_plx9050_init, 2362 .setup = pci_default_setup, 2363 .exit = pci_plx9050_exit, 2364 }, 2365 { 2366 .vendor = PCI_VENDOR_ID_PLX, 2367 .device = PCI_DEVICE_ID_PLX_9050, 2368 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2369 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2370 .init = pci_plx9050_init, 2371 .setup = pci_default_setup, 2372 .exit = pci_plx9050_exit, 2373 }, 2374 { 2375 .vendor = PCI_VENDOR_ID_PLX, 2376 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2377 .subvendor = PCI_VENDOR_ID_PLX, 2378 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2379 .init = pci_plx9050_init, 2380 .setup = pci_default_setup, 2381 .exit = pci_plx9050_exit, 2382 }, 2383 /* 2384 * SBS Technologies, Inc., PMC-OCTALPRO 232 2385 */ 2386 { 2387 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2388 .device = PCI_DEVICE_ID_OCTPRO, 2389 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2390 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2391 .init = sbs_init, 2392 .setup = sbs_setup, 2393 .exit = sbs_exit, 2394 }, 2395 /* 2396 * SBS Technologies, Inc., PMC-OCTALPRO 422 2397 */ 2398 { 2399 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2400 .device = PCI_DEVICE_ID_OCTPRO, 2401 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2402 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2403 .init = sbs_init, 2404 .setup = sbs_setup, 2405 .exit = sbs_exit, 2406 }, 2407 /* 2408 * SBS Technologies, Inc., P-Octal 232 2409 */ 2410 { 2411 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2412 .device = PCI_DEVICE_ID_OCTPRO, 2413 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2414 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2415 .init = sbs_init, 2416 .setup = sbs_setup, 2417 .exit = sbs_exit, 2418 }, 2419 /* 2420 * SBS Technologies, Inc., P-Octal 422 2421 */ 2422 { 2423 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2424 .device = PCI_DEVICE_ID_OCTPRO, 2425 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2426 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2427 .init = sbs_init, 2428 .setup = sbs_setup, 2429 .exit = sbs_exit, 2430 }, 2431 /* 2432 * SIIG cards - these may be called via parport_serial 2433 */ 2434 { 2435 .vendor = PCI_VENDOR_ID_SIIG, 2436 .device = PCI_ANY_ID, 2437 .subvendor = PCI_ANY_ID, 2438 .subdevice = PCI_ANY_ID, 2439 .init = pci_siig_init, 2440 .setup = pci_siig_setup, 2441 }, 2442 /* 2443 * Titan cards 2444 */ 2445 { 2446 .vendor = PCI_VENDOR_ID_TITAN, 2447 .device = PCI_DEVICE_ID_TITAN_400L, 2448 .subvendor = PCI_ANY_ID, 2449 .subdevice = PCI_ANY_ID, 2450 .setup = titan_400l_800l_setup, 2451 }, 2452 { 2453 .vendor = PCI_VENDOR_ID_TITAN, 2454 .device = PCI_DEVICE_ID_TITAN_800L, 2455 .subvendor = PCI_ANY_ID, 2456 .subdevice = PCI_ANY_ID, 2457 .setup = titan_400l_800l_setup, 2458 }, 2459 /* 2460 * Timedia cards 2461 */ 2462 { 2463 .vendor = PCI_VENDOR_ID_TIMEDIA, 2464 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2465 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2466 .subdevice = PCI_ANY_ID, 2467 .probe = pci_timedia_probe, 2468 .init = pci_timedia_init, 2469 .setup = pci_timedia_setup, 2470 }, 2471 { 2472 .vendor = PCI_VENDOR_ID_TIMEDIA, 2473 .device = PCI_ANY_ID, 2474 .subvendor = PCI_ANY_ID, 2475 .subdevice = PCI_ANY_ID, 2476 .setup = pci_timedia_setup, 2477 }, 2478 /* 2479 * SUNIX (Timedia) cards 2480 * Do not "probe" for these cards as there is at least one combination 2481 * card that should be handled by parport_pc that doesn't match the 2482 * rule in pci_timedia_probe. 2483 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2484 * There are some boards with part number SER5037AL that report 2485 * subdevice ID 0x0002. 2486 */ 2487 { 2488 .vendor = PCI_VENDOR_ID_SUNIX, 2489 .device = PCI_DEVICE_ID_SUNIX_1999, 2490 .subvendor = PCI_VENDOR_ID_SUNIX, 2491 .subdevice = PCI_ANY_ID, 2492 .init = pci_timedia_init, 2493 .setup = pci_timedia_setup, 2494 }, 2495 /* 2496 * Exar cards 2497 */ 2498 { 2499 .vendor = PCI_VENDOR_ID_EXAR, 2500 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2501 .subvendor = PCI_ANY_ID, 2502 .subdevice = PCI_ANY_ID, 2503 .setup = pci_xr17c154_setup, 2504 }, 2505 { 2506 .vendor = PCI_VENDOR_ID_EXAR, 2507 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2508 .subvendor = PCI_ANY_ID, 2509 .subdevice = PCI_ANY_ID, 2510 .setup = pci_xr17c154_setup, 2511 }, 2512 { 2513 .vendor = PCI_VENDOR_ID_EXAR, 2514 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2515 .subvendor = PCI_ANY_ID, 2516 .subdevice = PCI_ANY_ID, 2517 .setup = pci_xr17c154_setup, 2518 }, 2519 { 2520 .vendor = PCI_VENDOR_ID_EXAR, 2521 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2522 .subvendor = PCI_ANY_ID, 2523 .subdevice = PCI_ANY_ID, 2524 .setup = pci_xr17v35x_setup, 2525 }, 2526 { 2527 .vendor = PCI_VENDOR_ID_EXAR, 2528 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2529 .subvendor = PCI_ANY_ID, 2530 .subdevice = PCI_ANY_ID, 2531 .setup = pci_xr17v35x_setup, 2532 }, 2533 { 2534 .vendor = PCI_VENDOR_ID_EXAR, 2535 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2536 .subvendor = PCI_ANY_ID, 2537 .subdevice = PCI_ANY_ID, 2538 .setup = pci_xr17v35x_setup, 2539 }, 2540 { 2541 .vendor = PCI_VENDOR_ID_EXAR, 2542 .device = PCI_DEVICE_ID_EXAR_XR17V4358, 2543 .subvendor = PCI_ANY_ID, 2544 .subdevice = PCI_ANY_ID, 2545 .setup = pci_xr17v35x_setup, 2546 }, 2547 { 2548 .vendor = PCI_VENDOR_ID_EXAR, 2549 .device = PCI_DEVICE_ID_EXAR_XR17V8358, 2550 .subvendor = PCI_ANY_ID, 2551 .subdevice = PCI_ANY_ID, 2552 .setup = pci_xr17v35x_setup, 2553 }, 2554 /* 2555 * Xircom cards 2556 */ 2557 { 2558 .vendor = PCI_VENDOR_ID_XIRCOM, 2559 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2560 .subvendor = PCI_ANY_ID, 2561 .subdevice = PCI_ANY_ID, 2562 .init = pci_xircom_init, 2563 .setup = pci_default_setup, 2564 }, 2565 /* 2566 * Netmos cards - these may be called via parport_serial 2567 */ 2568 { 2569 .vendor = PCI_VENDOR_ID_NETMOS, 2570 .device = PCI_ANY_ID, 2571 .subvendor = PCI_ANY_ID, 2572 .subdevice = PCI_ANY_ID, 2573 .init = pci_netmos_init, 2574 .setup = pci_netmos_9900_setup, 2575 }, 2576 /* 2577 * EndRun Technologies 2578 */ 2579 { 2580 .vendor = PCI_VENDOR_ID_ENDRUN, 2581 .device = PCI_ANY_ID, 2582 .subvendor = PCI_ANY_ID, 2583 .subdevice = PCI_ANY_ID, 2584 .init = pci_endrun_init, 2585 .setup = pci_default_setup, 2586 }, 2587 /* 2588 * For Oxford Semiconductor Tornado based devices 2589 */ 2590 { 2591 .vendor = PCI_VENDOR_ID_OXSEMI, 2592 .device = PCI_ANY_ID, 2593 .subvendor = PCI_ANY_ID, 2594 .subdevice = PCI_ANY_ID, 2595 .init = pci_oxsemi_tornado_init, 2596 .setup = pci_default_setup, 2597 }, 2598 { 2599 .vendor = PCI_VENDOR_ID_MAINPINE, 2600 .device = PCI_ANY_ID, 2601 .subvendor = PCI_ANY_ID, 2602 .subdevice = PCI_ANY_ID, 2603 .init = pci_oxsemi_tornado_init, 2604 .setup = pci_default_setup, 2605 }, 2606 { 2607 .vendor = PCI_VENDOR_ID_DIGI, 2608 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2609 .subvendor = PCI_SUBVENDOR_ID_IBM, 2610 .subdevice = PCI_ANY_ID, 2611 .init = pci_oxsemi_tornado_init, 2612 .setup = pci_default_setup, 2613 }, 2614 { 2615 .vendor = PCI_VENDOR_ID_INTEL, 2616 .device = 0x8811, 2617 .subvendor = PCI_ANY_ID, 2618 .subdevice = PCI_ANY_ID, 2619 .init = pci_eg20t_init, 2620 .setup = pci_default_setup, 2621 }, 2622 { 2623 .vendor = PCI_VENDOR_ID_INTEL, 2624 .device = 0x8812, 2625 .subvendor = PCI_ANY_ID, 2626 .subdevice = PCI_ANY_ID, 2627 .init = pci_eg20t_init, 2628 .setup = pci_default_setup, 2629 }, 2630 { 2631 .vendor = PCI_VENDOR_ID_INTEL, 2632 .device = 0x8813, 2633 .subvendor = PCI_ANY_ID, 2634 .subdevice = PCI_ANY_ID, 2635 .init = pci_eg20t_init, 2636 .setup = pci_default_setup, 2637 }, 2638 { 2639 .vendor = PCI_VENDOR_ID_INTEL, 2640 .device = 0x8814, 2641 .subvendor = PCI_ANY_ID, 2642 .subdevice = PCI_ANY_ID, 2643 .init = pci_eg20t_init, 2644 .setup = pci_default_setup, 2645 }, 2646 { 2647 .vendor = 0x10DB, 2648 .device = 0x8027, 2649 .subvendor = PCI_ANY_ID, 2650 .subdevice = PCI_ANY_ID, 2651 .init = pci_eg20t_init, 2652 .setup = pci_default_setup, 2653 }, 2654 { 2655 .vendor = 0x10DB, 2656 .device = 0x8028, 2657 .subvendor = PCI_ANY_ID, 2658 .subdevice = PCI_ANY_ID, 2659 .init = pci_eg20t_init, 2660 .setup = pci_default_setup, 2661 }, 2662 { 2663 .vendor = 0x10DB, 2664 .device = 0x8029, 2665 .subvendor = PCI_ANY_ID, 2666 .subdevice = PCI_ANY_ID, 2667 .init = pci_eg20t_init, 2668 .setup = pci_default_setup, 2669 }, 2670 { 2671 .vendor = 0x10DB, 2672 .device = 0x800C, 2673 .subvendor = PCI_ANY_ID, 2674 .subdevice = PCI_ANY_ID, 2675 .init = pci_eg20t_init, 2676 .setup = pci_default_setup, 2677 }, 2678 { 2679 .vendor = 0x10DB, 2680 .device = 0x800D, 2681 .subvendor = PCI_ANY_ID, 2682 .subdevice = PCI_ANY_ID, 2683 .init = pci_eg20t_init, 2684 .setup = pci_default_setup, 2685 }, 2686 /* 2687 * Cronyx Omega PCI (PLX-chip based) 2688 */ 2689 { 2690 .vendor = PCI_VENDOR_ID_PLX, 2691 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2692 .subvendor = PCI_ANY_ID, 2693 .subdevice = PCI_ANY_ID, 2694 .setup = pci_omegapci_setup, 2695 }, 2696 /* WCH CH353 1S1P card (16550 clone) */ 2697 { 2698 .vendor = PCI_VENDOR_ID_WCH, 2699 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2700 .subvendor = PCI_ANY_ID, 2701 .subdevice = PCI_ANY_ID, 2702 .setup = pci_wch_ch353_setup, 2703 }, 2704 /* WCH CH353 2S1P card (16550 clone) */ 2705 { 2706 .vendor = PCI_VENDOR_ID_WCH, 2707 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2708 .subvendor = PCI_ANY_ID, 2709 .subdevice = PCI_ANY_ID, 2710 .setup = pci_wch_ch353_setup, 2711 }, 2712 /* WCH CH353 4S card (16550 clone) */ 2713 { 2714 .vendor = PCI_VENDOR_ID_WCH, 2715 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2716 .subvendor = PCI_ANY_ID, 2717 .subdevice = PCI_ANY_ID, 2718 .setup = pci_wch_ch353_setup, 2719 }, 2720 /* WCH CH353 2S1PF card (16550 clone) */ 2721 { 2722 .vendor = PCI_VENDOR_ID_WCH, 2723 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2724 .subvendor = PCI_ANY_ID, 2725 .subdevice = PCI_ANY_ID, 2726 .setup = pci_wch_ch353_setup, 2727 }, 2728 /* WCH CH352 2S card (16550 clone) */ 2729 { 2730 .vendor = PCI_VENDOR_ID_WCH, 2731 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2732 .subvendor = PCI_ANY_ID, 2733 .subdevice = PCI_ANY_ID, 2734 .setup = pci_wch_ch353_setup, 2735 }, 2736 /* WCH CH382 2S card (16850 clone) */ 2737 { 2738 .vendor = PCIE_VENDOR_ID_WCH, 2739 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2740 .subvendor = PCI_ANY_ID, 2741 .subdevice = PCI_ANY_ID, 2742 .setup = pci_wch_ch38x_setup, 2743 }, 2744 /* WCH CH382 2S1P card (16850 clone) */ 2745 { 2746 .vendor = PCIE_VENDOR_ID_WCH, 2747 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2748 .subvendor = PCI_ANY_ID, 2749 .subdevice = PCI_ANY_ID, 2750 .setup = pci_wch_ch38x_setup, 2751 }, 2752 /* WCH CH384 4S card (16850 clone) */ 2753 { 2754 .vendor = PCIE_VENDOR_ID_WCH, 2755 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2756 .subvendor = PCI_ANY_ID, 2757 .subdevice = PCI_ANY_ID, 2758 .setup = pci_wch_ch38x_setup, 2759 }, 2760 /* 2761 * ASIX devices with FIFO bug 2762 */ 2763 { 2764 .vendor = PCI_VENDOR_ID_ASIX, 2765 .device = PCI_ANY_ID, 2766 .subvendor = PCI_ANY_ID, 2767 .subdevice = PCI_ANY_ID, 2768 .setup = pci_asix_setup, 2769 }, 2770 /* 2771 * Commtech, Inc. Fastcom adapters 2772 * 2773 */ 2774 { 2775 .vendor = PCI_VENDOR_ID_COMMTECH, 2776 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2777 .subvendor = PCI_ANY_ID, 2778 .subdevice = PCI_ANY_ID, 2779 .setup = pci_fastcom335_setup, 2780 }, 2781 { 2782 .vendor = PCI_VENDOR_ID_COMMTECH, 2783 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2784 .subvendor = PCI_ANY_ID, 2785 .subdevice = PCI_ANY_ID, 2786 .setup = pci_fastcom335_setup, 2787 }, 2788 { 2789 .vendor = PCI_VENDOR_ID_COMMTECH, 2790 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2791 .subvendor = PCI_ANY_ID, 2792 .subdevice = PCI_ANY_ID, 2793 .setup = pci_fastcom335_setup, 2794 }, 2795 { 2796 .vendor = PCI_VENDOR_ID_COMMTECH, 2797 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2798 .subvendor = PCI_ANY_ID, 2799 .subdevice = PCI_ANY_ID, 2800 .setup = pci_fastcom335_setup, 2801 }, 2802 { 2803 .vendor = PCI_VENDOR_ID_COMMTECH, 2804 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2805 .subvendor = PCI_ANY_ID, 2806 .subdevice = PCI_ANY_ID, 2807 .setup = pci_xr17v35x_setup, 2808 }, 2809 { 2810 .vendor = PCI_VENDOR_ID_COMMTECH, 2811 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2812 .subvendor = PCI_ANY_ID, 2813 .subdevice = PCI_ANY_ID, 2814 .setup = pci_xr17v35x_setup, 2815 }, 2816 { 2817 .vendor = PCI_VENDOR_ID_COMMTECH, 2818 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2819 .subvendor = PCI_ANY_ID, 2820 .subdevice = PCI_ANY_ID, 2821 .setup = pci_xr17v35x_setup, 2822 }, 2823 /* 2824 * Broadcom TruManage (NetXtreme) 2825 */ 2826 { 2827 .vendor = PCI_VENDOR_ID_BROADCOM, 2828 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2829 .subvendor = PCI_ANY_ID, 2830 .subdevice = PCI_ANY_ID, 2831 .setup = pci_brcm_trumanage_setup, 2832 }, 2833 { 2834 .vendor = 0x1c29, 2835 .device = 0x1104, 2836 .subvendor = PCI_ANY_ID, 2837 .subdevice = PCI_ANY_ID, 2838 .setup = pci_fintek_setup, 2839 .init = pci_fintek_init, 2840 }, 2841 { 2842 .vendor = 0x1c29, 2843 .device = 0x1108, 2844 .subvendor = PCI_ANY_ID, 2845 .subdevice = PCI_ANY_ID, 2846 .setup = pci_fintek_setup, 2847 .init = pci_fintek_init, 2848 }, 2849 { 2850 .vendor = 0x1c29, 2851 .device = 0x1112, 2852 .subvendor = PCI_ANY_ID, 2853 .subdevice = PCI_ANY_ID, 2854 .setup = pci_fintek_setup, 2855 .init = pci_fintek_init, 2856 }, 2857 2858 /* 2859 * Default "match everything" terminator entry 2860 */ 2861 { 2862 .vendor = PCI_ANY_ID, 2863 .device = PCI_ANY_ID, 2864 .subvendor = PCI_ANY_ID, 2865 .subdevice = PCI_ANY_ID, 2866 .setup = pci_default_setup, 2867 } 2868}; 2869 2870static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2871{ 2872 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2873} 2874 2875static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2876{ 2877 struct pci_serial_quirk *quirk; 2878 2879 for (quirk = pci_serial_quirks; ; quirk++) 2880 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2881 quirk_id_matches(quirk->device, dev->device) && 2882 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2883 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2884 break; 2885 return quirk; 2886} 2887 2888static inline int get_pci_irq(struct pci_dev *dev, 2889 const struct pciserial_board *board) 2890{ 2891 if (board->flags & FL_NOIRQ) 2892 return 0; 2893 else 2894 return dev->irq; 2895} 2896 2897/* 2898 * This is the configuration table for all of the PCI serial boards 2899 * which we support. It is directly indexed by the pci_board_num_t enum 2900 * value, which is encoded in the pci_device_id PCI probe table's 2901 * driver_data member. 2902 * 2903 * The makeup of these names are: 2904 * pbn_bn{_bt}_n_baud{_offsetinhex} 2905 * 2906 * bn = PCI BAR number 2907 * bt = Index using PCI BARs 2908 * n = number of serial ports 2909 * baud = baud rate 2910 * offsetinhex = offset for each sequential port (in hex) 2911 * 2912 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2913 * 2914 * Please note: in theory if n = 1, _bt infix should make no difference. 2915 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2916 */ 2917enum pci_board_num_t { 2918 pbn_default = 0, 2919 2920 pbn_b0_1_115200, 2921 pbn_b0_2_115200, 2922 pbn_b0_4_115200, 2923 pbn_b0_5_115200, 2924 pbn_b0_8_115200, 2925 2926 pbn_b0_1_921600, 2927 pbn_b0_2_921600, 2928 pbn_b0_4_921600, 2929 2930 pbn_b0_2_1130000, 2931 2932 pbn_b0_4_1152000, 2933 2934 pbn_b0_2_1152000_200, 2935 pbn_b0_4_1152000_200, 2936 pbn_b0_8_1152000_200, 2937 2938 pbn_b0_2_1843200, 2939 pbn_b0_4_1843200, 2940 2941 pbn_b0_2_1843200_200, 2942 pbn_b0_4_1843200_200, 2943 pbn_b0_8_1843200_200, 2944 2945 pbn_b0_1_4000000, 2946 2947 pbn_b0_bt_1_115200, 2948 pbn_b0_bt_2_115200, 2949 pbn_b0_bt_4_115200, 2950 pbn_b0_bt_8_115200, 2951 2952 pbn_b0_bt_1_460800, 2953 pbn_b0_bt_2_460800, 2954 pbn_b0_bt_4_460800, 2955 2956 pbn_b0_bt_1_921600, 2957 pbn_b0_bt_2_921600, 2958 pbn_b0_bt_4_921600, 2959 pbn_b0_bt_8_921600, 2960 2961 pbn_b1_1_115200, 2962 pbn_b1_2_115200, 2963 pbn_b1_4_115200, 2964 pbn_b1_8_115200, 2965 pbn_b1_16_115200, 2966 2967 pbn_b1_1_921600, 2968 pbn_b1_2_921600, 2969 pbn_b1_4_921600, 2970 pbn_b1_8_921600, 2971 2972 pbn_b1_2_1250000, 2973 2974 pbn_b1_bt_1_115200, 2975 pbn_b1_bt_2_115200, 2976 pbn_b1_bt_4_115200, 2977 2978 pbn_b1_bt_2_921600, 2979 2980 pbn_b1_1_1382400, 2981 pbn_b1_2_1382400, 2982 pbn_b1_4_1382400, 2983 pbn_b1_8_1382400, 2984 2985 pbn_b2_1_115200, 2986 pbn_b2_2_115200, 2987 pbn_b2_4_115200, 2988 pbn_b2_8_115200, 2989 2990 pbn_b2_1_460800, 2991 pbn_b2_4_460800, 2992 pbn_b2_8_460800, 2993 pbn_b2_16_460800, 2994 2995 pbn_b2_1_921600, 2996 pbn_b2_4_921600, 2997 pbn_b2_8_921600, 2998 2999 pbn_b2_8_1152000, 3000 3001 pbn_b2_bt_1_115200, 3002 pbn_b2_bt_2_115200, 3003 pbn_b2_bt_4_115200, 3004 3005 pbn_b2_bt_2_921600, 3006 pbn_b2_bt_4_921600, 3007 3008 pbn_b3_2_115200, 3009 pbn_b3_4_115200, 3010 pbn_b3_8_115200, 3011 3012 pbn_b4_bt_2_921600, 3013 pbn_b4_bt_4_921600, 3014 pbn_b4_bt_8_921600, 3015 3016 /* 3017 * Board-specific versions. 3018 */ 3019 pbn_panacom, 3020 pbn_panacom2, 3021 pbn_panacom4, 3022 pbn_plx_romulus, 3023 pbn_endrun_2_4000000, 3024 pbn_oxsemi, 3025 pbn_oxsemi_1_4000000, 3026 pbn_oxsemi_2_4000000, 3027 pbn_oxsemi_4_4000000, 3028 pbn_oxsemi_8_4000000, 3029 pbn_intel_i960, 3030 pbn_sgi_ioc3, 3031 pbn_computone_4, 3032 pbn_computone_6, 3033 pbn_computone_8, 3034 pbn_sbsxrsio, 3035 pbn_exar_XR17C152, 3036 pbn_exar_XR17C154, 3037 pbn_exar_XR17C158, 3038 pbn_exar_XR17V352, 3039 pbn_exar_XR17V354, 3040 pbn_exar_XR17V358, 3041 pbn_exar_XR17V4358, 3042 pbn_exar_XR17V8358, 3043 pbn_exar_ibm_saturn, 3044 pbn_pasemi_1682M, 3045 pbn_ni8430_2, 3046 pbn_ni8430_4, 3047 pbn_ni8430_8, 3048 pbn_ni8430_16, 3049 pbn_ADDIDATA_PCIe_1_3906250, 3050 pbn_ADDIDATA_PCIe_2_3906250, 3051 pbn_ADDIDATA_PCIe_4_3906250, 3052 pbn_ADDIDATA_PCIe_8_3906250, 3053 pbn_ce4100_1_115200, 3054 pbn_byt, 3055 pbn_pnw, 3056 pbn_tng, 3057 pbn_qrk, 3058 pbn_omegapci, 3059 pbn_NETMOS9900_2s_115200, 3060 pbn_brcm_trumanage, 3061 pbn_fintek_4, 3062 pbn_fintek_8, 3063 pbn_fintek_12, 3064 pbn_wch382_2, 3065 pbn_wch384_4, 3066 pbn_pericom_PI7C9X7951, 3067 pbn_pericom_PI7C9X7952, 3068 pbn_pericom_PI7C9X7954, 3069 pbn_pericom_PI7C9X7958, 3070}; 3071 3072/* 3073 * uart_offset - the space between channels 3074 * reg_shift - describes how the UART registers are mapped 3075 * to PCI memory by the card. 3076 * For example IER register on SBS, Inc. PMC-OctPro is located at 3077 * offset 0x10 from the UART base, while UART_IER is defined as 1 3078 * in include/linux/serial_reg.h, 3079 * see first lines of serial_in() and serial_out() in 8250.c 3080*/ 3081 3082static struct pciserial_board pci_boards[] = { 3083 [pbn_default] = { 3084 .flags = FL_BASE0, 3085 .num_ports = 1, 3086 .base_baud = 115200, 3087 .uart_offset = 8, 3088 }, 3089 [pbn_b0_1_115200] = { 3090 .flags = FL_BASE0, 3091 .num_ports = 1, 3092 .base_baud = 115200, 3093 .uart_offset = 8, 3094 }, 3095 [pbn_b0_2_115200] = { 3096 .flags = FL_BASE0, 3097 .num_ports = 2, 3098 .base_baud = 115200, 3099 .uart_offset = 8, 3100 }, 3101 [pbn_b0_4_115200] = { 3102 .flags = FL_BASE0, 3103 .num_ports = 4, 3104 .base_baud = 115200, 3105 .uart_offset = 8, 3106 }, 3107 [pbn_b0_5_115200] = { 3108 .flags = FL_BASE0, 3109 .num_ports = 5, 3110 .base_baud = 115200, 3111 .uart_offset = 8, 3112 }, 3113 [pbn_b0_8_115200] = { 3114 .flags = FL_BASE0, 3115 .num_ports = 8, 3116 .base_baud = 115200, 3117 .uart_offset = 8, 3118 }, 3119 [pbn_b0_1_921600] = { 3120 .flags = FL_BASE0, 3121 .num_ports = 1, 3122 .base_baud = 921600, 3123 .uart_offset = 8, 3124 }, 3125 [pbn_b0_2_921600] = { 3126 .flags = FL_BASE0, 3127 .num_ports = 2, 3128 .base_baud = 921600, 3129 .uart_offset = 8, 3130 }, 3131 [pbn_b0_4_921600] = { 3132 .flags = FL_BASE0, 3133 .num_ports = 4, 3134 .base_baud = 921600, 3135 .uart_offset = 8, 3136 }, 3137 3138 [pbn_b0_2_1130000] = { 3139 .flags = FL_BASE0, 3140 .num_ports = 2, 3141 .base_baud = 1130000, 3142 .uart_offset = 8, 3143 }, 3144 3145 [pbn_b0_4_1152000] = { 3146 .flags = FL_BASE0, 3147 .num_ports = 4, 3148 .base_baud = 1152000, 3149 .uart_offset = 8, 3150 }, 3151 3152 [pbn_b0_2_1152000_200] = { 3153 .flags = FL_BASE0, 3154 .num_ports = 2, 3155 .base_baud = 1152000, 3156 .uart_offset = 0x200, 3157 }, 3158 3159 [pbn_b0_4_1152000_200] = { 3160 .flags = FL_BASE0, 3161 .num_ports = 4, 3162 .base_baud = 1152000, 3163 .uart_offset = 0x200, 3164 }, 3165 3166 [pbn_b0_8_1152000_200] = { 3167 .flags = FL_BASE0, 3168 .num_ports = 8, 3169 .base_baud = 1152000, 3170 .uart_offset = 0x200, 3171 }, 3172 3173 [pbn_b0_2_1843200] = { 3174 .flags = FL_BASE0, 3175 .num_ports = 2, 3176 .base_baud = 1843200, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b0_4_1843200] = { 3180 .flags = FL_BASE0, 3181 .num_ports = 4, 3182 .base_baud = 1843200, 3183 .uart_offset = 8, 3184 }, 3185 3186 [pbn_b0_2_1843200_200] = { 3187 .flags = FL_BASE0, 3188 .num_ports = 2, 3189 .base_baud = 1843200, 3190 .uart_offset = 0x200, 3191 }, 3192 [pbn_b0_4_1843200_200] = { 3193 .flags = FL_BASE0, 3194 .num_ports = 4, 3195 .base_baud = 1843200, 3196 .uart_offset = 0x200, 3197 }, 3198 [pbn_b0_8_1843200_200] = { 3199 .flags = FL_BASE0, 3200 .num_ports = 8, 3201 .base_baud = 1843200, 3202 .uart_offset = 0x200, 3203 }, 3204 [pbn_b0_1_4000000] = { 3205 .flags = FL_BASE0, 3206 .num_ports = 1, 3207 .base_baud = 4000000, 3208 .uart_offset = 8, 3209 }, 3210 3211 [pbn_b0_bt_1_115200] = { 3212 .flags = FL_BASE0|FL_BASE_BARS, 3213 .num_ports = 1, 3214 .base_baud = 115200, 3215 .uart_offset = 8, 3216 }, 3217 [pbn_b0_bt_2_115200] = { 3218 .flags = FL_BASE0|FL_BASE_BARS, 3219 .num_ports = 2, 3220 .base_baud = 115200, 3221 .uart_offset = 8, 3222 }, 3223 [pbn_b0_bt_4_115200] = { 3224 .flags = FL_BASE0|FL_BASE_BARS, 3225 .num_ports = 4, 3226 .base_baud = 115200, 3227 .uart_offset = 8, 3228 }, 3229 [pbn_b0_bt_8_115200] = { 3230 .flags = FL_BASE0|FL_BASE_BARS, 3231 .num_ports = 8, 3232 .base_baud = 115200, 3233 .uart_offset = 8, 3234 }, 3235 3236 [pbn_b0_bt_1_460800] = { 3237 .flags = FL_BASE0|FL_BASE_BARS, 3238 .num_ports = 1, 3239 .base_baud = 460800, 3240 .uart_offset = 8, 3241 }, 3242 [pbn_b0_bt_2_460800] = { 3243 .flags = FL_BASE0|FL_BASE_BARS, 3244 .num_ports = 2, 3245 .base_baud = 460800, 3246 .uart_offset = 8, 3247 }, 3248 [pbn_b0_bt_4_460800] = { 3249 .flags = FL_BASE0|FL_BASE_BARS, 3250 .num_ports = 4, 3251 .base_baud = 460800, 3252 .uart_offset = 8, 3253 }, 3254 3255 [pbn_b0_bt_1_921600] = { 3256 .flags = FL_BASE0|FL_BASE_BARS, 3257 .num_ports = 1, 3258 .base_baud = 921600, 3259 .uart_offset = 8, 3260 }, 3261 [pbn_b0_bt_2_921600] = { 3262 .flags = FL_BASE0|FL_BASE_BARS, 3263 .num_ports = 2, 3264 .base_baud = 921600, 3265 .uart_offset = 8, 3266 }, 3267 [pbn_b0_bt_4_921600] = { 3268 .flags = FL_BASE0|FL_BASE_BARS, 3269 .num_ports = 4, 3270 .base_baud = 921600, 3271 .uart_offset = 8, 3272 }, 3273 [pbn_b0_bt_8_921600] = { 3274 .flags = FL_BASE0|FL_BASE_BARS, 3275 .num_ports = 8, 3276 .base_baud = 921600, 3277 .uart_offset = 8, 3278 }, 3279 3280 [pbn_b1_1_115200] = { 3281 .flags = FL_BASE1, 3282 .num_ports = 1, 3283 .base_baud = 115200, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b1_2_115200] = { 3287 .flags = FL_BASE1, 3288 .num_ports = 2, 3289 .base_baud = 115200, 3290 .uart_offset = 8, 3291 }, 3292 [pbn_b1_4_115200] = { 3293 .flags = FL_BASE1, 3294 .num_ports = 4, 3295 .base_baud = 115200, 3296 .uart_offset = 8, 3297 }, 3298 [pbn_b1_8_115200] = { 3299 .flags = FL_BASE1, 3300 .num_ports = 8, 3301 .base_baud = 115200, 3302 .uart_offset = 8, 3303 }, 3304 [pbn_b1_16_115200] = { 3305 .flags = FL_BASE1, 3306 .num_ports = 16, 3307 .base_baud = 115200, 3308 .uart_offset = 8, 3309 }, 3310 3311 [pbn_b1_1_921600] = { 3312 .flags = FL_BASE1, 3313 .num_ports = 1, 3314 .base_baud = 921600, 3315 .uart_offset = 8, 3316 }, 3317 [pbn_b1_2_921600] = { 3318 .flags = FL_BASE1, 3319 .num_ports = 2, 3320 .base_baud = 921600, 3321 .uart_offset = 8, 3322 }, 3323 [pbn_b1_4_921600] = { 3324 .flags = FL_BASE1, 3325 .num_ports = 4, 3326 .base_baud = 921600, 3327 .uart_offset = 8, 3328 }, 3329 [pbn_b1_8_921600] = { 3330 .flags = FL_BASE1, 3331 .num_ports = 8, 3332 .base_baud = 921600, 3333 .uart_offset = 8, 3334 }, 3335 [pbn_b1_2_1250000] = { 3336 .flags = FL_BASE1, 3337 .num_ports = 2, 3338 .base_baud = 1250000, 3339 .uart_offset = 8, 3340 }, 3341 3342 [pbn_b1_bt_1_115200] = { 3343 .flags = FL_BASE1|FL_BASE_BARS, 3344 .num_ports = 1, 3345 .base_baud = 115200, 3346 .uart_offset = 8, 3347 }, 3348 [pbn_b1_bt_2_115200] = { 3349 .flags = FL_BASE1|FL_BASE_BARS, 3350 .num_ports = 2, 3351 .base_baud = 115200, 3352 .uart_offset = 8, 3353 }, 3354 [pbn_b1_bt_4_115200] = { 3355 .flags = FL_BASE1|FL_BASE_BARS, 3356 .num_ports = 4, 3357 .base_baud = 115200, 3358 .uart_offset = 8, 3359 }, 3360 3361 [pbn_b1_bt_2_921600] = { 3362 .flags = FL_BASE1|FL_BASE_BARS, 3363 .num_ports = 2, 3364 .base_baud = 921600, 3365 .uart_offset = 8, 3366 }, 3367 3368 [pbn_b1_1_1382400] = { 3369 .flags = FL_BASE1, 3370 .num_ports = 1, 3371 .base_baud = 1382400, 3372 .uart_offset = 8, 3373 }, 3374 [pbn_b1_2_1382400] = { 3375 .flags = FL_BASE1, 3376 .num_ports = 2, 3377 .base_baud = 1382400, 3378 .uart_offset = 8, 3379 }, 3380 [pbn_b1_4_1382400] = { 3381 .flags = FL_BASE1, 3382 .num_ports = 4, 3383 .base_baud = 1382400, 3384 .uart_offset = 8, 3385 }, 3386 [pbn_b1_8_1382400] = { 3387 .flags = FL_BASE1, 3388 .num_ports = 8, 3389 .base_baud = 1382400, 3390 .uart_offset = 8, 3391 }, 3392 3393 [pbn_b2_1_115200] = { 3394 .flags = FL_BASE2, 3395 .num_ports = 1, 3396 .base_baud = 115200, 3397 .uart_offset = 8, 3398 }, 3399 [pbn_b2_2_115200] = { 3400 .flags = FL_BASE2, 3401 .num_ports = 2, 3402 .base_baud = 115200, 3403 .uart_offset = 8, 3404 }, 3405 [pbn_b2_4_115200] = { 3406 .flags = FL_BASE2, 3407 .num_ports = 4, 3408 .base_baud = 115200, 3409 .uart_offset = 8, 3410 }, 3411 [pbn_b2_8_115200] = { 3412 .flags = FL_BASE2, 3413 .num_ports = 8, 3414 .base_baud = 115200, 3415 .uart_offset = 8, 3416 }, 3417 3418 [pbn_b2_1_460800] = { 3419 .flags = FL_BASE2, 3420 .num_ports = 1, 3421 .base_baud = 460800, 3422 .uart_offset = 8, 3423 }, 3424 [pbn_b2_4_460800] = { 3425 .flags = FL_BASE2, 3426 .num_ports = 4, 3427 .base_baud = 460800, 3428 .uart_offset = 8, 3429 }, 3430 [pbn_b2_8_460800] = { 3431 .flags = FL_BASE2, 3432 .num_ports = 8, 3433 .base_baud = 460800, 3434 .uart_offset = 8, 3435 }, 3436 [pbn_b2_16_460800] = { 3437 .flags = FL_BASE2, 3438 .num_ports = 16, 3439 .base_baud = 460800, 3440 .uart_offset = 8, 3441 }, 3442 3443 [pbn_b2_1_921600] = { 3444 .flags = FL_BASE2, 3445 .num_ports = 1, 3446 .base_baud = 921600, 3447 .uart_offset = 8, 3448 }, 3449 [pbn_b2_4_921600] = { 3450 .flags = FL_BASE2, 3451 .num_ports = 4, 3452 .base_baud = 921600, 3453 .uart_offset = 8, 3454 }, 3455 [pbn_b2_8_921600] = { 3456 .flags = FL_BASE2, 3457 .num_ports = 8, 3458 .base_baud = 921600, 3459 .uart_offset = 8, 3460 }, 3461 3462 [pbn_b2_8_1152000] = { 3463 .flags = FL_BASE2, 3464 .num_ports = 8, 3465 .base_baud = 1152000, 3466 .uart_offset = 8, 3467 }, 3468 3469 [pbn_b2_bt_1_115200] = { 3470 .flags = FL_BASE2|FL_BASE_BARS, 3471 .num_ports = 1, 3472 .base_baud = 115200, 3473 .uart_offset = 8, 3474 }, 3475 [pbn_b2_bt_2_115200] = { 3476 .flags = FL_BASE2|FL_BASE_BARS, 3477 .num_ports = 2, 3478 .base_baud = 115200, 3479 .uart_offset = 8, 3480 }, 3481 [pbn_b2_bt_4_115200] = { 3482 .flags = FL_BASE2|FL_BASE_BARS, 3483 .num_ports = 4, 3484 .base_baud = 115200, 3485 .uart_offset = 8, 3486 }, 3487 3488 [pbn_b2_bt_2_921600] = { 3489 .flags = FL_BASE2|FL_BASE_BARS, 3490 .num_ports = 2, 3491 .base_baud = 921600, 3492 .uart_offset = 8, 3493 }, 3494 [pbn_b2_bt_4_921600] = { 3495 .flags = FL_BASE2|FL_BASE_BARS, 3496 .num_ports = 4, 3497 .base_baud = 921600, 3498 .uart_offset = 8, 3499 }, 3500 3501 [pbn_b3_2_115200] = { 3502 .flags = FL_BASE3, 3503 .num_ports = 2, 3504 .base_baud = 115200, 3505 .uart_offset = 8, 3506 }, 3507 [pbn_b3_4_115200] = { 3508 .flags = FL_BASE3, 3509 .num_ports = 4, 3510 .base_baud = 115200, 3511 .uart_offset = 8, 3512 }, 3513 [pbn_b3_8_115200] = { 3514 .flags = FL_BASE3, 3515 .num_ports = 8, 3516 .base_baud = 115200, 3517 .uart_offset = 8, 3518 }, 3519 3520 [pbn_b4_bt_2_921600] = { 3521 .flags = FL_BASE4, 3522 .num_ports = 2, 3523 .base_baud = 921600, 3524 .uart_offset = 8, 3525 }, 3526 [pbn_b4_bt_4_921600] = { 3527 .flags = FL_BASE4, 3528 .num_ports = 4, 3529 .base_baud = 921600, 3530 .uart_offset = 8, 3531 }, 3532 [pbn_b4_bt_8_921600] = { 3533 .flags = FL_BASE4, 3534 .num_ports = 8, 3535 .base_baud = 921600, 3536 .uart_offset = 8, 3537 }, 3538 3539 /* 3540 * Entries following this are board-specific. 3541 */ 3542 3543 /* 3544 * Panacom - IOMEM 3545 */ 3546 [pbn_panacom] = { 3547 .flags = FL_BASE2, 3548 .num_ports = 2, 3549 .base_baud = 921600, 3550 .uart_offset = 0x400, 3551 .reg_shift = 7, 3552 }, 3553 [pbn_panacom2] = { 3554 .flags = FL_BASE2|FL_BASE_BARS, 3555 .num_ports = 2, 3556 .base_baud = 921600, 3557 .uart_offset = 0x400, 3558 .reg_shift = 7, 3559 }, 3560 [pbn_panacom4] = { 3561 .flags = FL_BASE2|FL_BASE_BARS, 3562 .num_ports = 4, 3563 .base_baud = 921600, 3564 .uart_offset = 0x400, 3565 .reg_shift = 7, 3566 }, 3567 3568 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3569 [pbn_plx_romulus] = { 3570 .flags = FL_BASE2, 3571 .num_ports = 4, 3572 .base_baud = 921600, 3573 .uart_offset = 8 << 2, 3574 .reg_shift = 2, 3575 .first_offset = 0x03, 3576 }, 3577 3578 /* 3579 * EndRun Technologies 3580 * Uses the size of PCI Base region 0 to 3581 * signal now many ports are available 3582 * 2 port 952 Uart support 3583 */ 3584 [pbn_endrun_2_4000000] = { 3585 .flags = FL_BASE0, 3586 .num_ports = 2, 3587 .base_baud = 4000000, 3588 .uart_offset = 0x200, 3589 .first_offset = 0x1000, 3590 }, 3591 3592 /* 3593 * This board uses the size of PCI Base region 0 to 3594 * signal now many ports are available 3595 */ 3596 [pbn_oxsemi] = { 3597 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3598 .num_ports = 32, 3599 .base_baud = 115200, 3600 .uart_offset = 8, 3601 }, 3602 [pbn_oxsemi_1_4000000] = { 3603 .flags = FL_BASE0, 3604 .num_ports = 1, 3605 .base_baud = 4000000, 3606 .uart_offset = 0x200, 3607 .first_offset = 0x1000, 3608 }, 3609 [pbn_oxsemi_2_4000000] = { 3610 .flags = FL_BASE0, 3611 .num_ports = 2, 3612 .base_baud = 4000000, 3613 .uart_offset = 0x200, 3614 .first_offset = 0x1000, 3615 }, 3616 [pbn_oxsemi_4_4000000] = { 3617 .flags = FL_BASE0, 3618 .num_ports = 4, 3619 .base_baud = 4000000, 3620 .uart_offset = 0x200, 3621 .first_offset = 0x1000, 3622 }, 3623 [pbn_oxsemi_8_4000000] = { 3624 .flags = FL_BASE0, 3625 .num_ports = 8, 3626 .base_baud = 4000000, 3627 .uart_offset = 0x200, 3628 .first_offset = 0x1000, 3629 }, 3630 3631 3632 /* 3633 * EKF addition for i960 Boards form EKF with serial port. 3634 * Max 256 ports. 3635 */ 3636 [pbn_intel_i960] = { 3637 .flags = FL_BASE0, 3638 .num_ports = 32, 3639 .base_baud = 921600, 3640 .uart_offset = 8 << 2, 3641 .reg_shift = 2, 3642 .first_offset = 0x10000, 3643 }, 3644 [pbn_sgi_ioc3] = { 3645 .flags = FL_BASE0|FL_NOIRQ, 3646 .num_ports = 1, 3647 .base_baud = 458333, 3648 .uart_offset = 8, 3649 .reg_shift = 0, 3650 .first_offset = 0x20178, 3651 }, 3652 3653 /* 3654 * Computone - uses IOMEM. 3655 */ 3656 [pbn_computone_4] = { 3657 .flags = FL_BASE0, 3658 .num_ports = 4, 3659 .base_baud = 921600, 3660 .uart_offset = 0x40, 3661 .reg_shift = 2, 3662 .first_offset = 0x200, 3663 }, 3664 [pbn_computone_6] = { 3665 .flags = FL_BASE0, 3666 .num_ports = 6, 3667 .base_baud = 921600, 3668 .uart_offset = 0x40, 3669 .reg_shift = 2, 3670 .first_offset = 0x200, 3671 }, 3672 [pbn_computone_8] = { 3673 .flags = FL_BASE0, 3674 .num_ports = 8, 3675 .base_baud = 921600, 3676 .uart_offset = 0x40, 3677 .reg_shift = 2, 3678 .first_offset = 0x200, 3679 }, 3680 [pbn_sbsxrsio] = { 3681 .flags = FL_BASE0, 3682 .num_ports = 8, 3683 .base_baud = 460800, 3684 .uart_offset = 256, 3685 .reg_shift = 4, 3686 }, 3687 /* 3688 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3689 * Only basic 16550A support. 3690 * XR17C15[24] are not tested, but they should work. 3691 */ 3692 [pbn_exar_XR17C152] = { 3693 .flags = FL_BASE0, 3694 .num_ports = 2, 3695 .base_baud = 921600, 3696 .uart_offset = 0x200, 3697 }, 3698 [pbn_exar_XR17C154] = { 3699 .flags = FL_BASE0, 3700 .num_ports = 4, 3701 .base_baud = 921600, 3702 .uart_offset = 0x200, 3703 }, 3704 [pbn_exar_XR17C158] = { 3705 .flags = FL_BASE0, 3706 .num_ports = 8, 3707 .base_baud = 921600, 3708 .uart_offset = 0x200, 3709 }, 3710 [pbn_exar_XR17V352] = { 3711 .flags = FL_BASE0, 3712 .num_ports = 2, 3713 .base_baud = 7812500, 3714 .uart_offset = 0x400, 3715 .reg_shift = 0, 3716 .first_offset = 0, 3717 }, 3718 [pbn_exar_XR17V354] = { 3719 .flags = FL_BASE0, 3720 .num_ports = 4, 3721 .base_baud = 7812500, 3722 .uart_offset = 0x400, 3723 .reg_shift = 0, 3724 .first_offset = 0, 3725 }, 3726 [pbn_exar_XR17V358] = { 3727 .flags = FL_BASE0, 3728 .num_ports = 8, 3729 .base_baud = 7812500, 3730 .uart_offset = 0x400, 3731 .reg_shift = 0, 3732 .first_offset = 0, 3733 }, 3734 [pbn_exar_XR17V4358] = { 3735 .flags = FL_BASE0, 3736 .num_ports = 12, 3737 .base_baud = 7812500, 3738 .uart_offset = 0x400, 3739 .reg_shift = 0, 3740 .first_offset = 0, 3741 }, 3742 [pbn_exar_XR17V8358] = { 3743 .flags = FL_BASE0, 3744 .num_ports = 16, 3745 .base_baud = 7812500, 3746 .uart_offset = 0x400, 3747 .reg_shift = 0, 3748 .first_offset = 0, 3749 }, 3750 [pbn_exar_ibm_saturn] = { 3751 .flags = FL_BASE0, 3752 .num_ports = 1, 3753 .base_baud = 921600, 3754 .uart_offset = 0x200, 3755 }, 3756 3757 /* 3758 * PA Semi PWRficient PA6T-1682M on-chip UART 3759 */ 3760 [pbn_pasemi_1682M] = { 3761 .flags = FL_BASE0, 3762 .num_ports = 1, 3763 .base_baud = 8333333, 3764 }, 3765 /* 3766 * National Instruments 843x 3767 */ 3768 [pbn_ni8430_16] = { 3769 .flags = FL_BASE0, 3770 .num_ports = 16, 3771 .base_baud = 3686400, 3772 .uart_offset = 0x10, 3773 .first_offset = 0x800, 3774 }, 3775 [pbn_ni8430_8] = { 3776 .flags = FL_BASE0, 3777 .num_ports = 8, 3778 .base_baud = 3686400, 3779 .uart_offset = 0x10, 3780 .first_offset = 0x800, 3781 }, 3782 [pbn_ni8430_4] = { 3783 .flags = FL_BASE0, 3784 .num_ports = 4, 3785 .base_baud = 3686400, 3786 .uart_offset = 0x10, 3787 .first_offset = 0x800, 3788 }, 3789 [pbn_ni8430_2] = { 3790 .flags = FL_BASE0, 3791 .num_ports = 2, 3792 .base_baud = 3686400, 3793 .uart_offset = 0x10, 3794 .first_offset = 0x800, 3795 }, 3796 /* 3797 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3798 */ 3799 [pbn_ADDIDATA_PCIe_1_3906250] = { 3800 .flags = FL_BASE0, 3801 .num_ports = 1, 3802 .base_baud = 3906250, 3803 .uart_offset = 0x200, 3804 .first_offset = 0x1000, 3805 }, 3806 [pbn_ADDIDATA_PCIe_2_3906250] = { 3807 .flags = FL_BASE0, 3808 .num_ports = 2, 3809 .base_baud = 3906250, 3810 .uart_offset = 0x200, 3811 .first_offset = 0x1000, 3812 }, 3813 [pbn_ADDIDATA_PCIe_4_3906250] = { 3814 .flags = FL_BASE0, 3815 .num_ports = 4, 3816 .base_baud = 3906250, 3817 .uart_offset = 0x200, 3818 .first_offset = 0x1000, 3819 }, 3820 [pbn_ADDIDATA_PCIe_8_3906250] = { 3821 .flags = FL_BASE0, 3822 .num_ports = 8, 3823 .base_baud = 3906250, 3824 .uart_offset = 0x200, 3825 .first_offset = 0x1000, 3826 }, 3827 [pbn_ce4100_1_115200] = { 3828 .flags = FL_BASE_BARS, 3829 .num_ports = 2, 3830 .base_baud = 921600, 3831 .reg_shift = 2, 3832 }, 3833 /* 3834 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, 3835 * but is overridden by byt_set_termios. 3836 */ 3837 [pbn_byt] = { 3838 .flags = FL_BASE0, 3839 .num_ports = 1, 3840 .base_baud = 2764800, 3841 .uart_offset = 0x80, 3842 .reg_shift = 2, 3843 }, 3844 [pbn_pnw] = { 3845 .flags = FL_BASE0, 3846 .num_ports = 1, 3847 .base_baud = 115200, 3848 }, 3849 [pbn_tng] = { 3850 .flags = FL_BASE0, 3851 .num_ports = 1, 3852 .base_baud = 1843200, 3853 }, 3854 [pbn_qrk] = { 3855 .flags = FL_BASE0, 3856 .num_ports = 1, 3857 .base_baud = 2764800, 3858 .reg_shift = 2, 3859 }, 3860 [pbn_omegapci] = { 3861 .flags = FL_BASE0, 3862 .num_ports = 8, 3863 .base_baud = 115200, 3864 .uart_offset = 0x200, 3865 }, 3866 [pbn_NETMOS9900_2s_115200] = { 3867 .flags = FL_BASE0, 3868 .num_ports = 2, 3869 .base_baud = 115200, 3870 }, 3871 [pbn_brcm_trumanage] = { 3872 .flags = FL_BASE0, 3873 .num_ports = 1, 3874 .reg_shift = 2, 3875 .base_baud = 115200, 3876 }, 3877 [pbn_fintek_4] = { 3878 .num_ports = 4, 3879 .uart_offset = 8, 3880 .base_baud = 115200, 3881 .first_offset = 0x40, 3882 }, 3883 [pbn_fintek_8] = { 3884 .num_ports = 8, 3885 .uart_offset = 8, 3886 .base_baud = 115200, 3887 .first_offset = 0x40, 3888 }, 3889 [pbn_fintek_12] = { 3890 .num_ports = 12, 3891 .uart_offset = 8, 3892 .base_baud = 115200, 3893 .first_offset = 0x40, 3894 }, 3895 [pbn_wch382_2] = { 3896 .flags = FL_BASE0, 3897 .num_ports = 2, 3898 .base_baud = 115200, 3899 .uart_offset = 8, 3900 .first_offset = 0xC0, 3901 }, 3902 [pbn_wch384_4] = { 3903 .flags = FL_BASE0, 3904 .num_ports = 4, 3905 .base_baud = 115200, 3906 .uart_offset = 8, 3907 .first_offset = 0xC0, 3908 }, 3909 /* 3910 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3911 */ 3912 [pbn_pericom_PI7C9X7951] = { 3913 .flags = FL_BASE0, 3914 .num_ports = 1, 3915 .base_baud = 921600, 3916 .uart_offset = 0x8, 3917 }, 3918 [pbn_pericom_PI7C9X7952] = { 3919 .flags = FL_BASE0, 3920 .num_ports = 2, 3921 .base_baud = 921600, 3922 .uart_offset = 0x8, 3923 }, 3924 [pbn_pericom_PI7C9X7954] = { 3925 .flags = FL_BASE0, 3926 .num_ports = 4, 3927 .base_baud = 921600, 3928 .uart_offset = 0x8, 3929 }, 3930 [pbn_pericom_PI7C9X7958] = { 3931 .flags = FL_BASE0, 3932 .num_ports = 8, 3933 .base_baud = 921600, 3934 .uart_offset = 0x8, 3935 }, 3936}; 3937 3938static const struct pci_device_id blacklist[] = { 3939 /* softmodems */ 3940 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3941 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3942 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3943 3944 /* multi-io cards handled by parport_serial */ 3945 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3946 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3947 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3948 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ 3949}; 3950 3951/* 3952 * Given a complete unknown PCI device, try to use some heuristics to 3953 * guess what the configuration might be, based on the pitiful PCI 3954 * serial specs. Returns 0 on success, 1 on failure. 3955 */ 3956static int 3957serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3958{ 3959 const struct pci_device_id *bldev; 3960 int num_iomem, num_port, first_port = -1, i; 3961 3962 /* 3963 * If it is not a communications device or the programming 3964 * interface is greater than 6, give up. 3965 * 3966 * (Should we try to make guesses for multiport serial devices 3967 * later?) 3968 */ 3969 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3970 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3971 (dev->class & 0xff) > 6) 3972 return -ENODEV; 3973 3974 /* 3975 * Do not access blacklisted devices that are known not to 3976 * feature serial ports or are handled by other modules. 3977 */ 3978 for (bldev = blacklist; 3979 bldev < blacklist + ARRAY_SIZE(blacklist); 3980 bldev++) { 3981 if (dev->vendor == bldev->vendor && 3982 dev->device == bldev->device) 3983 return -ENODEV; 3984 } 3985 3986 num_iomem = num_port = 0; 3987 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3988 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3989 num_port++; 3990 if (first_port == -1) 3991 first_port = i; 3992 } 3993 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3994 num_iomem++; 3995 } 3996 3997 /* 3998 * If there is 1 or 0 iomem regions, and exactly one port, 3999 * use it. We guess the number of ports based on the IO 4000 * region size. 4001 */ 4002 if (num_iomem <= 1 && num_port == 1) { 4003 board->flags = first_port; 4004 board->num_ports = pci_resource_len(dev, first_port) / 8; 4005 return 0; 4006 } 4007 4008 /* 4009 * Now guess if we've got a board which indexes by BARs. 4010 * Each IO BAR should be 8 bytes, and they should follow 4011 * consecutively. 4012 */ 4013 first_port = -1; 4014 num_port = 0; 4015 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 4016 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 4017 pci_resource_len(dev, i) == 8 && 4018 (first_port == -1 || (first_port + num_port) == i)) { 4019 num_port++; 4020 if (first_port == -1) 4021 first_port = i; 4022 } 4023 } 4024 4025 if (num_port > 1) { 4026 board->flags = first_port | FL_BASE_BARS; 4027 board->num_ports = num_port; 4028 return 0; 4029 } 4030 4031 return -ENODEV; 4032} 4033 4034static inline int 4035serial_pci_matches(const struct pciserial_board *board, 4036 const struct pciserial_board *guessed) 4037{ 4038 return 4039 board->num_ports == guessed->num_ports && 4040 board->base_baud == guessed->base_baud && 4041 board->uart_offset == guessed->uart_offset && 4042 board->reg_shift == guessed->reg_shift && 4043 board->first_offset == guessed->first_offset; 4044} 4045 4046struct serial_private * 4047pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 4048{ 4049 struct uart_8250_port uart; 4050 struct serial_private *priv; 4051 struct pci_serial_quirk *quirk; 4052 int rc, nr_ports, i; 4053 4054 nr_ports = board->num_ports; 4055 4056 /* 4057 * Find an init and setup quirks. 4058 */ 4059 quirk = find_quirk(dev); 4060 4061 /* 4062 * Run the new-style initialization function. 4063 * The initialization function returns: 4064 * <0 - error 4065 * 0 - use board->num_ports 4066 * >0 - number of ports 4067 */ 4068 if (quirk->init) { 4069 rc = quirk->init(dev); 4070 if (rc < 0) { 4071 priv = ERR_PTR(rc); 4072 goto err_out; 4073 } 4074 if (rc) 4075 nr_ports = rc; 4076 } 4077 4078 priv = kzalloc(sizeof(struct serial_private) + 4079 sizeof(unsigned int) * nr_ports, 4080 GFP_KERNEL); 4081 if (!priv) { 4082 priv = ERR_PTR(-ENOMEM); 4083 goto err_deinit; 4084 } 4085 4086 priv->dev = dev; 4087 priv->quirk = quirk; 4088 4089 memset(&uart, 0, sizeof(uart)); 4090 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 4091 uart.port.uartclk = board->base_baud * 16; 4092 uart.port.irq = get_pci_irq(dev, board); 4093 uart.port.dev = &dev->dev; 4094 4095 for (i = 0; i < nr_ports; i++) { 4096 if (quirk->setup(priv, board, &uart, i)) 4097 break; 4098 4099 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4100 uart.port.iobase, uart.port.irq, uart.port.iotype); 4101 4102 priv->line[i] = serial8250_register_8250_port(&uart); 4103 if (priv->line[i] < 0) { 4104 dev_err(&dev->dev, 4105 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4106 uart.port.iobase, uart.port.irq, 4107 uart.port.iotype, priv->line[i]); 4108 break; 4109 } 4110 } 4111 priv->nr = i; 4112 return priv; 4113 4114err_deinit: 4115 if (quirk->exit) 4116 quirk->exit(dev); 4117err_out: 4118 return priv; 4119} 4120EXPORT_SYMBOL_GPL(pciserial_init_ports); 4121 4122void pciserial_remove_ports(struct serial_private *priv) 4123{ 4124 struct pci_serial_quirk *quirk; 4125 int i; 4126 4127 for (i = 0; i < priv->nr; i++) 4128 serial8250_unregister_port(priv->line[i]); 4129 4130 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 4131 if (priv->remapped_bar[i]) 4132 iounmap(priv->remapped_bar[i]); 4133 priv->remapped_bar[i] = NULL; 4134 } 4135 4136 /* 4137 * Find the exit quirks. 4138 */ 4139 quirk = find_quirk(priv->dev); 4140 if (quirk->exit) 4141 quirk->exit(priv->dev); 4142 4143 kfree(priv); 4144} 4145EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4146 4147void pciserial_suspend_ports(struct serial_private *priv) 4148{ 4149 int i; 4150 4151 for (i = 0; i < priv->nr; i++) 4152 if (priv->line[i] >= 0) 4153 serial8250_suspend_port(priv->line[i]); 4154 4155 /* 4156 * Ensure that every init quirk is properly torn down 4157 */ 4158 if (priv->quirk->exit) 4159 priv->quirk->exit(priv->dev); 4160} 4161EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4162 4163void pciserial_resume_ports(struct serial_private *priv) 4164{ 4165 int i; 4166 4167 /* 4168 * Ensure that the board is correctly configured. 4169 */ 4170 if (priv->quirk->init) 4171 priv->quirk->init(priv->dev); 4172 4173 for (i = 0; i < priv->nr; i++) 4174 if (priv->line[i] >= 0) 4175 serial8250_resume_port(priv->line[i]); 4176} 4177EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4178 4179/* 4180 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4181 * to the arrangement of serial ports on a PCI card. 4182 */ 4183static int 4184pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4185{ 4186 struct pci_serial_quirk *quirk; 4187 struct serial_private *priv; 4188 const struct pciserial_board *board; 4189 struct pciserial_board tmp; 4190 int rc; 4191 4192 quirk = find_quirk(dev); 4193 if (quirk->probe) { 4194 rc = quirk->probe(dev); 4195 if (rc) 4196 return rc; 4197 } 4198 4199 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4200 dev_err(&dev->dev, "invalid driver_data: %ld\n", 4201 ent->driver_data); 4202 return -EINVAL; 4203 } 4204 4205 board = &pci_boards[ent->driver_data]; 4206 4207 rc = pci_enable_device(dev); 4208 pci_save_state(dev); 4209 if (rc) 4210 return rc; 4211 4212 if (ent->driver_data == pbn_default) { 4213 /* 4214 * Use a copy of the pci_board entry for this; 4215 * avoid changing entries in the table. 4216 */ 4217 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4218 board = &tmp; 4219 4220 /* 4221 * We matched one of our class entries. Try to 4222 * determine the parameters of this board. 4223 */ 4224 rc = serial_pci_guess_board(dev, &tmp); 4225 if (rc) 4226 goto disable; 4227 } else { 4228 /* 4229 * We matched an explicit entry. If we are able to 4230 * detect this boards settings with our heuristic, 4231 * then we no longer need this entry. 4232 */ 4233 memcpy(&tmp, &pci_boards[pbn_default], 4234 sizeof(struct pciserial_board)); 4235 rc = serial_pci_guess_board(dev, &tmp); 4236 if (rc == 0 && serial_pci_matches(board, &tmp)) 4237 moan_device("Redundant entry in serial pci_table.", 4238 dev); 4239 } 4240 4241 priv = pciserial_init_ports(dev, board); 4242 if (!IS_ERR(priv)) { 4243 pci_set_drvdata(dev, priv); 4244 return 0; 4245 } 4246 4247 rc = PTR_ERR(priv); 4248 4249 disable: 4250 pci_disable_device(dev); 4251 return rc; 4252} 4253 4254static void pciserial_remove_one(struct pci_dev *dev) 4255{ 4256 struct serial_private *priv = pci_get_drvdata(dev); 4257 4258 pciserial_remove_ports(priv); 4259 4260 pci_disable_device(dev); 4261} 4262 4263#ifdef CONFIG_PM_SLEEP 4264static int pciserial_suspend_one(struct device *dev) 4265{ 4266 struct pci_dev *pdev = to_pci_dev(dev); 4267 struct serial_private *priv = pci_get_drvdata(pdev); 4268 4269 if (priv) 4270 pciserial_suspend_ports(priv); 4271 4272 return 0; 4273} 4274 4275static int pciserial_resume_one(struct device *dev) 4276{ 4277 struct pci_dev *pdev = to_pci_dev(dev); 4278 struct serial_private *priv = pci_get_drvdata(pdev); 4279 int err; 4280 4281 if (priv) { 4282 /* 4283 * The device may have been disabled. Re-enable it. 4284 */ 4285 err = pci_enable_device(pdev); 4286 /* FIXME: We cannot simply error out here */ 4287 if (err) 4288 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4289 pciserial_resume_ports(priv); 4290 } 4291 return 0; 4292} 4293#endif 4294 4295static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4296 pciserial_resume_one); 4297 4298static struct pci_device_id serial_pci_tbl[] = { 4299 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4300 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4301 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4302 pbn_b2_8_921600 }, 4303 /* Advantech also use 0x3618 and 0xf618 */ 4304 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4305 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4306 pbn_b0_4_921600 }, 4307 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4308 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4309 pbn_b0_4_921600 }, 4310 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4311 PCI_SUBVENDOR_ID_CONNECT_TECH, 4312 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4313 pbn_b1_8_1382400 }, 4314 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4315 PCI_SUBVENDOR_ID_CONNECT_TECH, 4316 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4317 pbn_b1_4_1382400 }, 4318 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4319 PCI_SUBVENDOR_ID_CONNECT_TECH, 4320 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4321 pbn_b1_2_1382400 }, 4322 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4323 PCI_SUBVENDOR_ID_CONNECT_TECH, 4324 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4325 pbn_b1_8_1382400 }, 4326 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4327 PCI_SUBVENDOR_ID_CONNECT_TECH, 4328 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4329 pbn_b1_4_1382400 }, 4330 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4331 PCI_SUBVENDOR_ID_CONNECT_TECH, 4332 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4333 pbn_b1_2_1382400 }, 4334 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4335 PCI_SUBVENDOR_ID_CONNECT_TECH, 4336 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4337 pbn_b1_8_921600 }, 4338 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4339 PCI_SUBVENDOR_ID_CONNECT_TECH, 4340 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4341 pbn_b1_8_921600 }, 4342 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4343 PCI_SUBVENDOR_ID_CONNECT_TECH, 4344 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4345 pbn_b1_4_921600 }, 4346 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4347 PCI_SUBVENDOR_ID_CONNECT_TECH, 4348 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4349 pbn_b1_4_921600 }, 4350 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4351 PCI_SUBVENDOR_ID_CONNECT_TECH, 4352 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4353 pbn_b1_2_921600 }, 4354 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4355 PCI_SUBVENDOR_ID_CONNECT_TECH, 4356 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4357 pbn_b1_8_921600 }, 4358 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4359 PCI_SUBVENDOR_ID_CONNECT_TECH, 4360 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4361 pbn_b1_8_921600 }, 4362 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4363 PCI_SUBVENDOR_ID_CONNECT_TECH, 4364 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4365 pbn_b1_4_921600 }, 4366 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4367 PCI_SUBVENDOR_ID_CONNECT_TECH, 4368 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4369 pbn_b1_2_1250000 }, 4370 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4371 PCI_SUBVENDOR_ID_CONNECT_TECH, 4372 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4373 pbn_b0_2_1843200 }, 4374 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4375 PCI_SUBVENDOR_ID_CONNECT_TECH, 4376 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4377 pbn_b0_4_1843200 }, 4378 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4379 PCI_VENDOR_ID_AFAVLAB, 4380 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4381 pbn_b0_4_1152000 }, 4382 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4383 PCI_SUBVENDOR_ID_CONNECT_TECH, 4384 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 4385 pbn_b0_2_1843200_200 }, 4386 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4387 PCI_SUBVENDOR_ID_CONNECT_TECH, 4388 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 4389 pbn_b0_4_1843200_200 }, 4390 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4391 PCI_SUBVENDOR_ID_CONNECT_TECH, 4392 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 4393 pbn_b0_8_1843200_200 }, 4394 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4395 PCI_SUBVENDOR_ID_CONNECT_TECH, 4396 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 4397 pbn_b0_2_1843200_200 }, 4398 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4399 PCI_SUBVENDOR_ID_CONNECT_TECH, 4400 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 4401 pbn_b0_4_1843200_200 }, 4402 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4403 PCI_SUBVENDOR_ID_CONNECT_TECH, 4404 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 4405 pbn_b0_8_1843200_200 }, 4406 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4407 PCI_SUBVENDOR_ID_CONNECT_TECH, 4408 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 4409 pbn_b0_2_1843200_200 }, 4410 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4411 PCI_SUBVENDOR_ID_CONNECT_TECH, 4412 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4413 pbn_b0_4_1843200_200 }, 4414 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4415 PCI_SUBVENDOR_ID_CONNECT_TECH, 4416 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4417 pbn_b0_8_1843200_200 }, 4418 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4419 PCI_SUBVENDOR_ID_CONNECT_TECH, 4420 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4421 pbn_b0_2_1843200_200 }, 4422 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4423 PCI_SUBVENDOR_ID_CONNECT_TECH, 4424 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4425 pbn_b0_4_1843200_200 }, 4426 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4427 PCI_SUBVENDOR_ID_CONNECT_TECH, 4428 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4429 pbn_b0_8_1843200_200 }, 4430 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4431 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4432 0, 0, pbn_exar_ibm_saturn }, 4433 4434 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_b2_bt_1_115200 }, 4437 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4439 pbn_b2_bt_2_115200 }, 4440 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_b2_bt_4_115200 }, 4443 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4445 pbn_b2_bt_2_115200 }, 4446 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4448 pbn_b2_bt_4_115200 }, 4449 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4451 pbn_b2_8_115200 }, 4452 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4454 pbn_b2_8_460800 }, 4455 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4457 pbn_b2_8_115200 }, 4458 4459 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_b2_bt_2_115200 }, 4462 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_b2_bt_2_921600 }, 4465 /* 4466 * VScom SPCOM800, from sl@s.pl 4467 */ 4468 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_b2_8_921600 }, 4471 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4473 pbn_b2_4_921600 }, 4474 /* Unknown card - subdevice 0x1584 */ 4475 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4476 PCI_VENDOR_ID_PLX, 4477 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4478 pbn_b2_4_115200 }, 4479 /* Unknown card - subdevice 0x1588 */ 4480 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4481 PCI_VENDOR_ID_PLX, 4482 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4483 pbn_b2_8_115200 }, 4484 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4485 PCI_SUBVENDOR_ID_KEYSPAN, 4486 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4487 pbn_panacom }, 4488 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_panacom4 }, 4491 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_panacom2 }, 4494 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4495 PCI_VENDOR_ID_ESDGMBH, 4496 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4497 pbn_b2_4_115200 }, 4498 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4499 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4500 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4501 pbn_b2_4_460800 }, 4502 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4503 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4504 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4505 pbn_b2_8_460800 }, 4506 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4507 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4508 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4509 pbn_b2_16_460800 }, 4510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4511 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4512 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4513 pbn_b2_16_460800 }, 4514 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4515 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4516 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4517 pbn_b2_4_460800 }, 4518 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4519 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4520 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4521 pbn_b2_8_460800 }, 4522 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4523 PCI_SUBVENDOR_ID_EXSYS, 4524 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4525 pbn_b2_4_115200 }, 4526 /* 4527 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4528 * (Exoray@isys.ca) 4529 */ 4530 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4531 0x10b5, 0x106a, 0, 0, 4532 pbn_plx_romulus }, 4533 /* 4534 * EndRun Technologies. PCI express device range. 4535 * EndRun PTP/1588 has 2 Native UARTs. 4536 */ 4537 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4539 pbn_endrun_2_4000000 }, 4540 /* 4541 * Quatech cards. These actually have configurable clocks but for 4542 * now we just use the default. 4543 * 4544 * 100 series are RS232, 200 series RS422, 4545 */ 4546 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4548 pbn_b1_4_115200 }, 4549 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4551 pbn_b1_2_115200 }, 4552 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4554 pbn_b2_2_115200 }, 4555 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4557 pbn_b1_2_115200 }, 4558 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4560 pbn_b2_2_115200 }, 4561 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4563 pbn_b1_4_115200 }, 4564 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4566 pbn_b1_8_115200 }, 4567 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4569 pbn_b1_8_115200 }, 4570 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4572 pbn_b1_4_115200 }, 4573 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4575 pbn_b1_2_115200 }, 4576 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4578 pbn_b1_4_115200 }, 4579 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4581 pbn_b1_2_115200 }, 4582 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4584 pbn_b2_4_115200 }, 4585 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4587 pbn_b2_2_115200 }, 4588 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4590 pbn_b2_1_115200 }, 4591 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4593 pbn_b2_4_115200 }, 4594 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4596 pbn_b2_2_115200 }, 4597 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_b2_1_115200 }, 4600 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_b0_8_115200 }, 4603 4604 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4605 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4606 0, 0, 4607 pbn_b0_4_921600 }, 4608 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4609 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4610 0, 0, 4611 pbn_b0_4_1152000 }, 4612 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_b0_bt_2_921600 }, 4615 4616 /* 4617 * The below card is a little controversial since it is the 4618 * subject of a PCI vendor/device ID clash. (See 4619 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4620 * For now just used the hex ID 0x950a. 4621 */ 4622 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4623 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4624 0, 0, pbn_b0_2_115200 }, 4625 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4626 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4627 0, 0, pbn_b0_2_115200 }, 4628 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_b0_2_1130000 }, 4631 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4632 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4633 pbn_b0_1_921600 }, 4634 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_b0_4_115200 }, 4637 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_b0_bt_2_921600 }, 4640 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4641 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 4642 pbn_b2_8_1152000 }, 4643 4644 /* 4645 * Oxford Semiconductor Inc. Tornado PCI express device range. 4646 */ 4647 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_b0_1_4000000 }, 4650 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_b0_1_4000000 }, 4653 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_oxsemi_1_4000000 }, 4656 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_oxsemi_1_4000000 }, 4659 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_1_4000000 }, 4662 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b0_1_4000000 }, 4665 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_oxsemi_1_4000000 }, 4668 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_oxsemi_1_4000000 }, 4671 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b0_1_4000000 }, 4674 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4676 pbn_b0_1_4000000 }, 4677 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b0_1_4000000 }, 4680 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b0_1_4000000 }, 4683 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_oxsemi_2_4000000 }, 4686 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_oxsemi_2_4000000 }, 4689 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_oxsemi_4_4000000 }, 4692 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_oxsemi_4_4000000 }, 4695 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_oxsemi_8_4000000 }, 4698 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_oxsemi_8_4000000 }, 4701 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_oxsemi_1_4000000 }, 4704 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_oxsemi_1_4000000 }, 4707 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_oxsemi_1_4000000 }, 4710 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4712 pbn_oxsemi_1_4000000 }, 4713 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4715 pbn_oxsemi_1_4000000 }, 4716 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4718 pbn_oxsemi_1_4000000 }, 4719 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_oxsemi_1_4000000 }, 4722 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_oxsemi_1_4000000 }, 4725 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_oxsemi_1_4000000 }, 4728 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4730 pbn_oxsemi_1_4000000 }, 4731 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4733 pbn_oxsemi_1_4000000 }, 4734 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4736 pbn_oxsemi_1_4000000 }, 4737 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4739 pbn_oxsemi_1_4000000 }, 4740 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4742 pbn_oxsemi_1_4000000 }, 4743 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4745 pbn_oxsemi_1_4000000 }, 4746 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4748 pbn_oxsemi_1_4000000 }, 4749 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4751 pbn_oxsemi_1_4000000 }, 4752 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4754 pbn_oxsemi_1_4000000 }, 4755 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4757 pbn_oxsemi_1_4000000 }, 4758 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4760 pbn_oxsemi_1_4000000 }, 4761 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4763 pbn_oxsemi_1_4000000 }, 4764 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4766 pbn_oxsemi_1_4000000 }, 4767 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4769 pbn_oxsemi_1_4000000 }, 4770 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4772 pbn_oxsemi_1_4000000 }, 4773 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4775 pbn_oxsemi_1_4000000 }, 4776 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4778 pbn_oxsemi_1_4000000 }, 4779 /* 4780 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4781 */ 4782 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4783 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4784 pbn_oxsemi_1_4000000 }, 4785 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4786 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4787 pbn_oxsemi_2_4000000 }, 4788 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4789 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4790 pbn_oxsemi_4_4000000 }, 4791 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4792 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4793 pbn_oxsemi_8_4000000 }, 4794 4795 /* 4796 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4797 */ 4798 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4799 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4800 pbn_oxsemi_2_4000000 }, 4801 4802 /* 4803 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4804 * from skokodyn@yahoo.com 4805 */ 4806 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4807 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4808 pbn_sbsxrsio }, 4809 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4810 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4811 pbn_sbsxrsio }, 4812 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4813 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4814 pbn_sbsxrsio }, 4815 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4816 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4817 pbn_sbsxrsio }, 4818 4819 /* 4820 * Digitan DS560-558, from jimd@esoft.com 4821 */ 4822 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4824 pbn_b1_1_115200 }, 4825 4826 /* 4827 * Titan Electronic cards 4828 * The 400L and 800L have a custom setup quirk. 4829 */ 4830 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4832 pbn_b0_1_921600 }, 4833 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4835 pbn_b0_2_921600 }, 4836 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4838 pbn_b0_4_921600 }, 4839 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4841 pbn_b0_4_921600 }, 4842 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4844 pbn_b1_1_921600 }, 4845 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4847 pbn_b1_bt_2_921600 }, 4848 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4850 pbn_b0_bt_4_921600 }, 4851 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4853 pbn_b0_bt_8_921600 }, 4854 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_b4_bt_2_921600 }, 4857 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_b4_bt_4_921600 }, 4860 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b4_bt_8_921600 }, 4863 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_4_921600 }, 4866 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4868 pbn_b0_4_921600 }, 4869 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b0_4_921600 }, 4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4874 pbn_oxsemi_1_4000000 }, 4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4877 pbn_oxsemi_2_4000000 }, 4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4880 pbn_oxsemi_4_4000000 }, 4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_oxsemi_8_4000000 }, 4884 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4886 pbn_oxsemi_2_4000000 }, 4887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4889 pbn_oxsemi_2_4000000 }, 4890 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4892 pbn_b0_bt_2_921600 }, 4893 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4895 pbn_b0_4_921600 }, 4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4898 pbn_b0_4_921600 }, 4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4901 pbn_b0_4_921600 }, 4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4904 pbn_b0_4_921600 }, 4905 4906 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4908 pbn_b2_1_460800 }, 4909 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4911 pbn_b2_1_460800 }, 4912 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4914 pbn_b2_1_460800 }, 4915 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4917 pbn_b2_bt_2_921600 }, 4918 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4920 pbn_b2_bt_2_921600 }, 4921 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4923 pbn_b2_bt_2_921600 }, 4924 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4926 pbn_b2_bt_4_921600 }, 4927 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4929 pbn_b2_bt_4_921600 }, 4930 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4932 pbn_b2_bt_4_921600 }, 4933 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4935 pbn_b0_1_921600 }, 4936 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4938 pbn_b0_1_921600 }, 4939 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4941 pbn_b0_1_921600 }, 4942 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4944 pbn_b0_bt_2_921600 }, 4945 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4947 pbn_b0_bt_2_921600 }, 4948 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4950 pbn_b0_bt_2_921600 }, 4951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4953 pbn_b0_bt_4_921600 }, 4954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4956 pbn_b0_bt_4_921600 }, 4957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4959 pbn_b0_bt_4_921600 }, 4960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4962 pbn_b0_bt_8_921600 }, 4963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4965 pbn_b0_bt_8_921600 }, 4966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4968 pbn_b0_bt_8_921600 }, 4969 4970 /* 4971 * Computone devices submitted by Doug McNash dmcnash@computone.com 4972 */ 4973 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4974 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4975 0, 0, pbn_computone_4 }, 4976 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4977 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4978 0, 0, pbn_computone_8 }, 4979 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4980 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4981 0, 0, pbn_computone_6 }, 4982 4983 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4985 pbn_oxsemi }, 4986 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4987 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4988 pbn_b0_bt_1_921600 }, 4989 4990 /* 4991 * SUNIX (TIMEDIA) 4992 */ 4993 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4994 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4995 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4996 pbn_b0_bt_1_921600 }, 4997 4998 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4999 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 5000 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5001 pbn_b0_bt_1_921600 }, 5002 5003 /* 5004 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 5005 */ 5006 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5008 pbn_b0_bt_8_115200 }, 5009 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5011 pbn_b0_bt_8_115200 }, 5012 5013 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_b0_bt_2_115200 }, 5016 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5018 pbn_b0_bt_2_115200 }, 5019 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5021 pbn_b0_bt_2_115200 }, 5022 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5024 pbn_b0_bt_2_115200 }, 5025 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5027 pbn_b0_bt_2_115200 }, 5028 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5030 pbn_b0_bt_4_460800 }, 5031 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_b0_bt_4_460800 }, 5034 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_b0_bt_2_460800 }, 5037 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5039 pbn_b0_bt_2_460800 }, 5040 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5042 pbn_b0_bt_2_460800 }, 5043 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5045 pbn_b0_bt_1_115200 }, 5046 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5048 pbn_b0_bt_1_460800 }, 5049 5050 /* 5051 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 5052 * Cards are identified by their subsystem vendor IDs, which 5053 * (in hex) match the model number. 5054 * 5055 * Note that JC140x are RS422/485 cards which require ox950 5056 * ACR = 0x10, and as such are not currently fully supported. 5057 */ 5058 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5059 0x1204, 0x0004, 0, 0, 5060 pbn_b0_4_921600 }, 5061 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5062 0x1208, 0x0004, 0, 0, 5063 pbn_b0_4_921600 }, 5064/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5065 0x1402, 0x0002, 0, 0, 5066 pbn_b0_2_921600 }, */ 5067/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5068 0x1404, 0x0004, 0, 0, 5069 pbn_b0_4_921600 }, */ 5070 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 5071 0x1208, 0x0004, 0, 0, 5072 pbn_b0_4_921600 }, 5073 5074 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5075 0x1204, 0x0004, 0, 0, 5076 pbn_b0_4_921600 }, 5077 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5078 0x1208, 0x0004, 0, 0, 5079 pbn_b0_4_921600 }, 5080 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 5081 0x1208, 0x0004, 0, 0, 5082 pbn_b0_4_921600 }, 5083 /* 5084 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 5085 */ 5086 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5088 pbn_b1_1_1382400 }, 5089 5090 /* 5091 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 5092 */ 5093 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5095 pbn_b1_1_1382400 }, 5096 5097 /* 5098 * RAStel 2 port modem, gerg@moreton.com.au 5099 */ 5100 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5102 pbn_b2_bt_2_115200 }, 5103 5104 /* 5105 * EKF addition for i960 Boards form EKF with serial port 5106 */ 5107 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5108 0xE4BF, PCI_ANY_ID, 0, 0, 5109 pbn_intel_i960 }, 5110 5111 /* 5112 * Xircom Cardbus/Ethernet combos 5113 */ 5114 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 5115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5116 pbn_b0_1_115200 }, 5117 /* 5118 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5119 */ 5120 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 5121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5122 pbn_b0_1_115200 }, 5123 5124 /* 5125 * Untested PCI modems, sent in from various folks... 5126 */ 5127 5128 /* 5129 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 5130 */ 5131 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 5132 0x1048, 0x1500, 0, 0, 5133 pbn_b1_1_115200 }, 5134 5135 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5136 0xFF00, 0, 0, 0, 5137 pbn_sgi_ioc3 }, 5138 5139 /* 5140 * HP Diva card 5141 */ 5142 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5143 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5144 pbn_b1_1_115200 }, 5145 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5147 pbn_b0_5_115200 }, 5148 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5150 pbn_b2_1_115200 }, 5151 5152 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5154 pbn_b3_2_115200 }, 5155 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5157 pbn_b3_4_115200 }, 5158 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5160 pbn_b3_8_115200 }, 5161 5162 /* 5163 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 5164 */ 5165 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 5166 PCI_ANY_ID, PCI_ANY_ID, 5167 0, 5168 0, pbn_exar_XR17C152 }, 5169 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 5170 PCI_ANY_ID, PCI_ANY_ID, 5171 0, 5172 0, pbn_exar_XR17C154 }, 5173 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 5174 PCI_ANY_ID, PCI_ANY_ID, 5175 0, 5176 0, pbn_exar_XR17C158 }, 5177 /* 5178 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs 5179 */ 5180 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 5181 PCI_ANY_ID, PCI_ANY_ID, 5182 0, 5183 0, pbn_exar_XR17V352 }, 5184 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 5185 PCI_ANY_ID, PCI_ANY_ID, 5186 0, 5187 0, pbn_exar_XR17V354 }, 5188 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 5189 PCI_ANY_ID, PCI_ANY_ID, 5190 0, 5191 0, pbn_exar_XR17V358 }, 5192 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358, 5193 PCI_ANY_ID, PCI_ANY_ID, 5194 0, 5195 0, pbn_exar_XR17V4358 }, 5196 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358, 5197 PCI_ANY_ID, PCI_ANY_ID, 5198 0, 5199 0, pbn_exar_XR17V8358 }, 5200 /* 5201 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5202 */ 5203 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 5204 PCI_ANY_ID, PCI_ANY_ID, 5205 0, 5206 0, pbn_pericom_PI7C9X7951 }, 5207 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 5208 PCI_ANY_ID, PCI_ANY_ID, 5209 0, 5210 0, pbn_pericom_PI7C9X7952 }, 5211 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 5212 PCI_ANY_ID, PCI_ANY_ID, 5213 0, 5214 0, pbn_pericom_PI7C9X7954 }, 5215 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5216 PCI_ANY_ID, PCI_ANY_ID, 5217 0, 5218 0, pbn_pericom_PI7C9X7958 }, 5219 /* 5220 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5221 */ 5222 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5224 pbn_b0_1_115200 }, 5225 /* 5226 * ITE 5227 */ 5228 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5229 PCI_ANY_ID, PCI_ANY_ID, 5230 0, 0, 5231 pbn_b1_bt_1_115200 }, 5232 5233 /* 5234 * IntaShield IS-200 5235 */ 5236 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5238 pbn_b2_2_115200 }, 5239 /* 5240 * IntaShield IS-400 5241 */ 5242 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5244 pbn_b2_4_115200 }, 5245 /* 5246 * Perle PCI-RAS cards 5247 */ 5248 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5249 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5250 0, 0, pbn_b2_4_921600 }, 5251 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5252 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5253 0, 0, pbn_b2_8_921600 }, 5254 5255 /* 5256 * Mainpine series cards: Fairly standard layout but fools 5257 * parts of the autodetect in some cases and uses otherwise 5258 * unmatched communications subclasses in the PCI Express case 5259 */ 5260 5261 { /* RockForceDUO */ 5262 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5263 PCI_VENDOR_ID_MAINPINE, 0x0200, 5264 0, 0, pbn_b0_2_115200 }, 5265 { /* RockForceQUATRO */ 5266 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5267 PCI_VENDOR_ID_MAINPINE, 0x0300, 5268 0, 0, pbn_b0_4_115200 }, 5269 { /* RockForceDUO+ */ 5270 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5271 PCI_VENDOR_ID_MAINPINE, 0x0400, 5272 0, 0, pbn_b0_2_115200 }, 5273 { /* RockForceQUATRO+ */ 5274 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5275 PCI_VENDOR_ID_MAINPINE, 0x0500, 5276 0, 0, pbn_b0_4_115200 }, 5277 { /* RockForce+ */ 5278 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5279 PCI_VENDOR_ID_MAINPINE, 0x0600, 5280 0, 0, pbn_b0_2_115200 }, 5281 { /* RockForce+ */ 5282 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5283 PCI_VENDOR_ID_MAINPINE, 0x0700, 5284 0, 0, pbn_b0_4_115200 }, 5285 { /* RockForceOCTO+ */ 5286 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5287 PCI_VENDOR_ID_MAINPINE, 0x0800, 5288 0, 0, pbn_b0_8_115200 }, 5289 { /* RockForceDUO+ */ 5290 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5291 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5292 0, 0, pbn_b0_2_115200 }, 5293 { /* RockForceQUARTRO+ */ 5294 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5295 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5296 0, 0, pbn_b0_4_115200 }, 5297 { /* RockForceOCTO+ */ 5298 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5299 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5300 0, 0, pbn_b0_8_115200 }, 5301 { /* RockForceD1 */ 5302 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5303 PCI_VENDOR_ID_MAINPINE, 0x2000, 5304 0, 0, pbn_b0_1_115200 }, 5305 { /* RockForceF1 */ 5306 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5307 PCI_VENDOR_ID_MAINPINE, 0x2100, 5308 0, 0, pbn_b0_1_115200 }, 5309 { /* RockForceD2 */ 5310 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5311 PCI_VENDOR_ID_MAINPINE, 0x2200, 5312 0, 0, pbn_b0_2_115200 }, 5313 { /* RockForceF2 */ 5314 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5315 PCI_VENDOR_ID_MAINPINE, 0x2300, 5316 0, 0, pbn_b0_2_115200 }, 5317 { /* RockForceD4 */ 5318 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5319 PCI_VENDOR_ID_MAINPINE, 0x2400, 5320 0, 0, pbn_b0_4_115200 }, 5321 { /* RockForceF4 */ 5322 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5323 PCI_VENDOR_ID_MAINPINE, 0x2500, 5324 0, 0, pbn_b0_4_115200 }, 5325 { /* RockForceD8 */ 5326 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5327 PCI_VENDOR_ID_MAINPINE, 0x2600, 5328 0, 0, pbn_b0_8_115200 }, 5329 { /* RockForceF8 */ 5330 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5331 PCI_VENDOR_ID_MAINPINE, 0x2700, 5332 0, 0, pbn_b0_8_115200 }, 5333 { /* IQ Express D1 */ 5334 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5335 PCI_VENDOR_ID_MAINPINE, 0x3000, 5336 0, 0, pbn_b0_1_115200 }, 5337 { /* IQ Express F1 */ 5338 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5339 PCI_VENDOR_ID_MAINPINE, 0x3100, 5340 0, 0, pbn_b0_1_115200 }, 5341 { /* IQ Express D2 */ 5342 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5343 PCI_VENDOR_ID_MAINPINE, 0x3200, 5344 0, 0, pbn_b0_2_115200 }, 5345 { /* IQ Express F2 */ 5346 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5347 PCI_VENDOR_ID_MAINPINE, 0x3300, 5348 0, 0, pbn_b0_2_115200 }, 5349 { /* IQ Express D4 */ 5350 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5351 PCI_VENDOR_ID_MAINPINE, 0x3400, 5352 0, 0, pbn_b0_4_115200 }, 5353 { /* IQ Express F4 */ 5354 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5355 PCI_VENDOR_ID_MAINPINE, 0x3500, 5356 0, 0, pbn_b0_4_115200 }, 5357 { /* IQ Express D8 */ 5358 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5359 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5360 0, 0, pbn_b0_8_115200 }, 5361 { /* IQ Express F8 */ 5362 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5363 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5364 0, 0, pbn_b0_8_115200 }, 5365 5366 5367 /* 5368 * PA Semi PA6T-1682M on-chip UART 5369 */ 5370 { PCI_VENDOR_ID_PASEMI, 0xa004, 5371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5372 pbn_pasemi_1682M }, 5373 5374 /* 5375 * National Instruments 5376 */ 5377 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5379 pbn_b1_16_115200 }, 5380 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5382 pbn_b1_8_115200 }, 5383 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5385 pbn_b1_bt_4_115200 }, 5386 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5388 pbn_b1_bt_2_115200 }, 5389 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5391 pbn_b1_bt_4_115200 }, 5392 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5394 pbn_b1_bt_2_115200 }, 5395 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5397 pbn_b1_16_115200 }, 5398 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5400 pbn_b1_8_115200 }, 5401 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5403 pbn_b1_bt_4_115200 }, 5404 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5406 pbn_b1_bt_2_115200 }, 5407 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5409 pbn_b1_bt_4_115200 }, 5410 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5412 pbn_b1_bt_2_115200 }, 5413 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5415 pbn_ni8430_2 }, 5416 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5418 pbn_ni8430_2 }, 5419 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5421 pbn_ni8430_4 }, 5422 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5424 pbn_ni8430_4 }, 5425 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5427 pbn_ni8430_8 }, 5428 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5430 pbn_ni8430_8 }, 5431 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5433 pbn_ni8430_16 }, 5434 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5436 pbn_ni8430_16 }, 5437 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5439 pbn_ni8430_2 }, 5440 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5442 pbn_ni8430_2 }, 5443 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5445 pbn_ni8430_4 }, 5446 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5448 pbn_ni8430_4 }, 5449 5450 /* 5451 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5452 */ 5453 { PCI_VENDOR_ID_ADDIDATA, 5454 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5455 PCI_ANY_ID, 5456 PCI_ANY_ID, 5457 0, 5458 0, 5459 pbn_b0_4_115200 }, 5460 5461 { PCI_VENDOR_ID_ADDIDATA, 5462 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5463 PCI_ANY_ID, 5464 PCI_ANY_ID, 5465 0, 5466 0, 5467 pbn_b0_2_115200 }, 5468 5469 { PCI_VENDOR_ID_ADDIDATA, 5470 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5471 PCI_ANY_ID, 5472 PCI_ANY_ID, 5473 0, 5474 0, 5475 pbn_b0_1_115200 }, 5476 5477 { PCI_VENDOR_ID_AMCC, 5478 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5479 PCI_ANY_ID, 5480 PCI_ANY_ID, 5481 0, 5482 0, 5483 pbn_b1_8_115200 }, 5484 5485 { PCI_VENDOR_ID_ADDIDATA, 5486 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5487 PCI_ANY_ID, 5488 PCI_ANY_ID, 5489 0, 5490 0, 5491 pbn_b0_4_115200 }, 5492 5493 { PCI_VENDOR_ID_ADDIDATA, 5494 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5495 PCI_ANY_ID, 5496 PCI_ANY_ID, 5497 0, 5498 0, 5499 pbn_b0_2_115200 }, 5500 5501 { PCI_VENDOR_ID_ADDIDATA, 5502 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5503 PCI_ANY_ID, 5504 PCI_ANY_ID, 5505 0, 5506 0, 5507 pbn_b0_1_115200 }, 5508 5509 { PCI_VENDOR_ID_ADDIDATA, 5510 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5511 PCI_ANY_ID, 5512 PCI_ANY_ID, 5513 0, 5514 0, 5515 pbn_b0_4_115200 }, 5516 5517 { PCI_VENDOR_ID_ADDIDATA, 5518 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5519 PCI_ANY_ID, 5520 PCI_ANY_ID, 5521 0, 5522 0, 5523 pbn_b0_2_115200 }, 5524 5525 { PCI_VENDOR_ID_ADDIDATA, 5526 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5527 PCI_ANY_ID, 5528 PCI_ANY_ID, 5529 0, 5530 0, 5531 pbn_b0_1_115200 }, 5532 5533 { PCI_VENDOR_ID_ADDIDATA, 5534 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5535 PCI_ANY_ID, 5536 PCI_ANY_ID, 5537 0, 5538 0, 5539 pbn_b0_8_115200 }, 5540 5541 { PCI_VENDOR_ID_ADDIDATA, 5542 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5543 PCI_ANY_ID, 5544 PCI_ANY_ID, 5545 0, 5546 0, 5547 pbn_ADDIDATA_PCIe_4_3906250 }, 5548 5549 { PCI_VENDOR_ID_ADDIDATA, 5550 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5551 PCI_ANY_ID, 5552 PCI_ANY_ID, 5553 0, 5554 0, 5555 pbn_ADDIDATA_PCIe_2_3906250 }, 5556 5557 { PCI_VENDOR_ID_ADDIDATA, 5558 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5559 PCI_ANY_ID, 5560 PCI_ANY_ID, 5561 0, 5562 0, 5563 pbn_ADDIDATA_PCIe_1_3906250 }, 5564 5565 { PCI_VENDOR_ID_ADDIDATA, 5566 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5567 PCI_ANY_ID, 5568 PCI_ANY_ID, 5569 0, 5570 0, 5571 pbn_ADDIDATA_PCIe_8_3906250 }, 5572 5573 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5574 PCI_VENDOR_ID_IBM, 0x0299, 5575 0, 0, pbn_b0_bt_2_115200 }, 5576 5577 /* 5578 * other NetMos 9835 devices are most likely handled by the 5579 * parport_serial driver, check drivers/parport/parport_serial.c 5580 * before adding them here. 5581 */ 5582 5583 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5584 0xA000, 0x1000, 5585 0, 0, pbn_b0_1_115200 }, 5586 5587 /* the 9901 is a rebranded 9912 */ 5588 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5589 0xA000, 0x1000, 5590 0, 0, pbn_b0_1_115200 }, 5591 5592 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5593 0xA000, 0x1000, 5594 0, 0, pbn_b0_1_115200 }, 5595 5596 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5597 0xA000, 0x1000, 5598 0, 0, pbn_b0_1_115200 }, 5599 5600 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5601 0xA000, 0x1000, 5602 0, 0, pbn_b0_1_115200 }, 5603 5604 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5605 0xA000, 0x3002, 5606 0, 0, pbn_NETMOS9900_2s_115200 }, 5607 5608 /* 5609 * Best Connectivity and Rosewill PCI Multi I/O cards 5610 */ 5611 5612 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5613 0xA000, 0x1000, 5614 0, 0, pbn_b0_1_115200 }, 5615 5616 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5617 0xA000, 0x3002, 5618 0, 0, pbn_b0_bt_2_115200 }, 5619 5620 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5621 0xA000, 0x3004, 5622 0, 0, pbn_b0_bt_4_115200 }, 5623 /* Intel CE4100 */ 5624 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5625 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5626 pbn_ce4100_1_115200 }, 5627 /* Intel BayTrail */ 5628 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, 5629 PCI_ANY_ID, PCI_ANY_ID, 5630 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5631 pbn_byt }, 5632 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5633 PCI_ANY_ID, PCI_ANY_ID, 5634 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5635 pbn_byt }, 5636 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, 5637 PCI_ANY_ID, PCI_ANY_ID, 5638 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5639 pbn_byt }, 5640 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, 5641 PCI_ANY_ID, PCI_ANY_ID, 5642 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5643 pbn_byt }, 5644 5645 /* Intel Broadwell */ 5646 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1, 5647 PCI_ANY_ID, PCI_ANY_ID, 5648 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5649 pbn_byt }, 5650 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2, 5651 PCI_ANY_ID, PCI_ANY_ID, 5652 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5653 pbn_byt }, 5654 5655 /* 5656 * Intel Penwell 5657 */ 5658 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1, 5659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5660 pbn_pnw}, 5661 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2, 5662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5663 pbn_pnw}, 5664 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3, 5665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5666 pbn_pnw}, 5667 5668 /* 5669 * Intel Tangier 5670 */ 5671 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART, 5672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5673 pbn_tng}, 5674 5675 /* 5676 * Intel Quark x1000 5677 */ 5678 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, 5679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5680 pbn_qrk }, 5681 /* 5682 * Cronyx Omega PCI 5683 */ 5684 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5686 pbn_omegapci }, 5687 5688 /* 5689 * Broadcom TruManage 5690 */ 5691 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5693 pbn_brcm_trumanage }, 5694 5695 /* 5696 * AgeStar as-prs2-009 5697 */ 5698 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5699 PCI_ANY_ID, PCI_ANY_ID, 5700 0, 0, pbn_b0_bt_2_115200 }, 5701 5702 /* 5703 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5704 * so not listed here. 5705 */ 5706 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5707 PCI_ANY_ID, PCI_ANY_ID, 5708 0, 0, pbn_b0_bt_4_115200 }, 5709 5710 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5711 PCI_ANY_ID, PCI_ANY_ID, 5712 0, 0, pbn_b0_bt_2_115200 }, 5713 5714 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5715 PCI_ANY_ID, PCI_ANY_ID, 5716 0, 0, pbn_wch382_2 }, 5717 5718 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5719 PCI_ANY_ID, PCI_ANY_ID, 5720 0, 0, pbn_wch384_4 }, 5721 5722 /* 5723 * Commtech, Inc. Fastcom adapters 5724 */ 5725 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5726 PCI_ANY_ID, PCI_ANY_ID, 5727 0, 5728 0, pbn_b0_2_1152000_200 }, 5729 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5730 PCI_ANY_ID, PCI_ANY_ID, 5731 0, 5732 0, pbn_b0_4_1152000_200 }, 5733 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5734 PCI_ANY_ID, PCI_ANY_ID, 5735 0, 5736 0, pbn_b0_4_1152000_200 }, 5737 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5738 PCI_ANY_ID, PCI_ANY_ID, 5739 0, 5740 0, pbn_b0_8_1152000_200 }, 5741 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5742 PCI_ANY_ID, PCI_ANY_ID, 5743 0, 5744 0, pbn_exar_XR17V352 }, 5745 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5746 PCI_ANY_ID, PCI_ANY_ID, 5747 0, 5748 0, pbn_exar_XR17V354 }, 5749 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5750 PCI_ANY_ID, PCI_ANY_ID, 5751 0, 5752 0, pbn_exar_XR17V358 }, 5753 5754 /* Fintek PCI serial cards */ 5755 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5756 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5757 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5758 5759 /* 5760 * These entries match devices with class COMMUNICATION_SERIAL, 5761 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5762 */ 5763 { PCI_ANY_ID, PCI_ANY_ID, 5764 PCI_ANY_ID, PCI_ANY_ID, 5765 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5766 0xffff00, pbn_default }, 5767 { PCI_ANY_ID, PCI_ANY_ID, 5768 PCI_ANY_ID, PCI_ANY_ID, 5769 PCI_CLASS_COMMUNICATION_MODEM << 8, 5770 0xffff00, pbn_default }, 5771 { PCI_ANY_ID, PCI_ANY_ID, 5772 PCI_ANY_ID, PCI_ANY_ID, 5773 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5774 0xffff00, pbn_default }, 5775 { 0, } 5776}; 5777 5778static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5779 pci_channel_state_t state) 5780{ 5781 struct serial_private *priv = pci_get_drvdata(dev); 5782 5783 if (state == pci_channel_io_perm_failure) 5784 return PCI_ERS_RESULT_DISCONNECT; 5785 5786 if (priv) 5787 pciserial_suspend_ports(priv); 5788 5789 pci_disable_device(dev); 5790 5791 return PCI_ERS_RESULT_NEED_RESET; 5792} 5793 5794static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5795{ 5796 int rc; 5797 5798 rc = pci_enable_device(dev); 5799 5800 if (rc) 5801 return PCI_ERS_RESULT_DISCONNECT; 5802 5803 pci_restore_state(dev); 5804 pci_save_state(dev); 5805 5806 return PCI_ERS_RESULT_RECOVERED; 5807} 5808 5809static void serial8250_io_resume(struct pci_dev *dev) 5810{ 5811 struct serial_private *priv = pci_get_drvdata(dev); 5812 5813 if (priv) 5814 pciserial_resume_ports(priv); 5815} 5816 5817static const struct pci_error_handlers serial8250_err_handler = { 5818 .error_detected = serial8250_io_error_detected, 5819 .slot_reset = serial8250_io_slot_reset, 5820 .resume = serial8250_io_resume, 5821}; 5822 5823static struct pci_driver serial_pci_driver = { 5824 .name = "serial", 5825 .probe = pciserial_init_one, 5826 .remove = pciserial_remove_one, 5827 .driver = { 5828 .pm = &pciserial_pm_ops, 5829 }, 5830 .id_table = serial_pci_tbl, 5831 .err_handler = &serial8250_err_handler, 5832}; 5833 5834module_pci_driver(serial_pci_driver); 5835 5836MODULE_LICENSE("GPL"); 5837MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5838MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5839