1/* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25#include <linux/module.h> 26#include <linux/tty.h> 27#include <linux/ioport.h> 28#include <linux/slab.h> 29#include <linux/init.h> 30#include <linux/serial.h> 31#include <linux/clk.h> 32#include <linux/console.h> 33#include <linux/sysrq.h> 34#include <linux/tty_flip.h> 35#include <linux/platform_device.h> 36#include <linux/of.h> 37#include <linux/of_device.h> 38#include <linux/of_gpio.h> 39#include <linux/dma-mapping.h> 40#include <linux/dmaengine.h> 41#include <linux/atmel_pdc.h> 42#include <linux/atmel_serial.h> 43#include <linux/uaccess.h> 44#include <linux/platform_data/atmel.h> 45#include <linux/timer.h> 46#include <linux/gpio.h> 47#include <linux/gpio/consumer.h> 48#include <linux/err.h> 49#include <linux/irq.h> 50#include <linux/suspend.h> 51 52#include <asm/io.h> 53#include <asm/ioctls.h> 54 55#define PDC_BUFFER_SIZE 512 56/* Revisit: We should calculate this based on the actual port settings */ 57#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 58 59#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 60#define SUPPORT_SYSRQ 61#endif 62 63#include <linux/serial_core.h> 64 65#include "serial_mctrl_gpio.h" 66 67static void atmel_start_rx(struct uart_port *port); 68static void atmel_stop_rx(struct uart_port *port); 69 70#ifdef CONFIG_SERIAL_ATMEL_TTYAT 71 72/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 73 * should coexist with the 8250 driver, such as if we have an external 16C550 74 * UART. */ 75#define SERIAL_ATMEL_MAJOR 204 76#define MINOR_START 154 77#define ATMEL_DEVICENAME "ttyAT" 78 79#else 80 81/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 82 * name, but it is legally reserved for the 8250 driver. */ 83#define SERIAL_ATMEL_MAJOR TTY_MAJOR 84#define MINOR_START 64 85#define ATMEL_DEVICENAME "ttyS" 86 87#endif 88 89#define ATMEL_ISR_PASS_LIMIT 256 90 91/* UART registers. CR is write-only, hence no GET macro */ 92#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR) 93#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR) 94#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR) 95#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER) 96#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR) 97#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR) 98#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR) 99#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR) 100#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR) 101#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR) 102#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR) 103#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR) 104#define UART_PUT_TTGR(port, v) __raw_writel(v, (port)->membase + ATMEL_US_TTGR) 105#define UART_GET_IP_NAME(port) __raw_readl((port)->membase + ATMEL_US_NAME) 106#define UART_GET_IP_VERSION(port) __raw_readl((port)->membase + ATMEL_US_VERSION) 107 108 /* PDC registers */ 109#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR) 110#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR) 111 112#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR) 113#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR) 114#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR) 115#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR) 116#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR) 117 118#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR) 119#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR) 120#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR) 121 122struct atmel_dma_buffer { 123 unsigned char *buf; 124 dma_addr_t dma_addr; 125 unsigned int dma_size; 126 unsigned int ofs; 127}; 128 129struct atmel_uart_char { 130 u16 status; 131 u16 ch; 132}; 133 134#define ATMEL_SERIAL_RINGSIZE 1024 135 136/* 137 * We wrap our port structure around the generic uart_port. 138 */ 139struct atmel_uart_port { 140 struct uart_port uart; /* uart */ 141 struct clk *clk; /* uart clock */ 142 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 143 u32 backup_imr; /* IMR saved during suspend */ 144 int break_active; /* break being received */ 145 146 bool use_dma_rx; /* enable DMA receiver */ 147 bool use_pdc_rx; /* enable PDC receiver */ 148 short pdc_rx_idx; /* current PDC RX buffer */ 149 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 150 151 bool use_dma_tx; /* enable DMA transmitter */ 152 bool use_pdc_tx; /* enable PDC transmitter */ 153 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 154 155 spinlock_t lock_tx; /* port lock */ 156 spinlock_t lock_rx; /* port lock */ 157 struct dma_chan *chan_tx; 158 struct dma_chan *chan_rx; 159 struct dma_async_tx_descriptor *desc_tx; 160 struct dma_async_tx_descriptor *desc_rx; 161 dma_cookie_t cookie_tx; 162 dma_cookie_t cookie_rx; 163 struct scatterlist sg_tx; 164 struct scatterlist sg_rx; 165 struct tasklet_struct tasklet; 166 unsigned int irq_status; 167 unsigned int irq_status_prev; 168 169 struct circ_buf rx_ring; 170 171 struct mctrl_gpios *gpios; 172 int gpio_irq[UART_GPIO_MAX]; 173 unsigned int tx_done_mask; 174 bool ms_irq_enabled; 175 bool is_usart; /* usart or uart */ 176 struct timer_list uart_timer; /* uart timer */ 177 178 bool suspended; 179 unsigned int pending; 180 unsigned int pending_status; 181 spinlock_t lock_suspended; 182 183 int (*prepare_rx)(struct uart_port *port); 184 int (*prepare_tx)(struct uart_port *port); 185 void (*schedule_rx)(struct uart_port *port); 186 void (*schedule_tx)(struct uart_port *port); 187 void (*release_rx)(struct uart_port *port); 188 void (*release_tx)(struct uart_port *port); 189}; 190 191static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 192static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 193 194#ifdef SUPPORT_SYSRQ 195static struct console atmel_console; 196#endif 197 198#if defined(CONFIG_OF) 199static const struct of_device_id atmel_serial_dt_ids[] = { 200 { .compatible = "atmel,at91rm9200-usart" }, 201 { .compatible = "atmel,at91sam9260-usart" }, 202 { /* sentinel */ } 203}; 204 205MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); 206#endif 207 208static inline struct atmel_uart_port * 209to_atmel_uart_port(struct uart_port *uart) 210{ 211 return container_of(uart, struct atmel_uart_port, uart); 212} 213 214#ifdef CONFIG_SERIAL_ATMEL_PDC 215static bool atmel_use_pdc_rx(struct uart_port *port) 216{ 217 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 218 219 return atmel_port->use_pdc_rx; 220} 221 222static bool atmel_use_pdc_tx(struct uart_port *port) 223{ 224 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 225 226 return atmel_port->use_pdc_tx; 227} 228#else 229static bool atmel_use_pdc_rx(struct uart_port *port) 230{ 231 return false; 232} 233 234static bool atmel_use_pdc_tx(struct uart_port *port) 235{ 236 return false; 237} 238#endif 239 240static bool atmel_use_dma_tx(struct uart_port *port) 241{ 242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 243 244 return atmel_port->use_dma_tx; 245} 246 247static bool atmel_use_dma_rx(struct uart_port *port) 248{ 249 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 250 251 return atmel_port->use_dma_rx; 252} 253 254static unsigned int atmel_get_lines_status(struct uart_port *port) 255{ 256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 257 unsigned int status, ret = 0; 258 259 status = UART_GET_CSR(port); 260 261 mctrl_gpio_get(atmel_port->gpios, &ret); 262 263 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 264 UART_GPIO_CTS))) { 265 if (ret & TIOCM_CTS) 266 status &= ~ATMEL_US_CTS; 267 else 268 status |= ATMEL_US_CTS; 269 } 270 271 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 272 UART_GPIO_DSR))) { 273 if (ret & TIOCM_DSR) 274 status &= ~ATMEL_US_DSR; 275 else 276 status |= ATMEL_US_DSR; 277 } 278 279 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 280 UART_GPIO_RI))) { 281 if (ret & TIOCM_RI) 282 status &= ~ATMEL_US_RI; 283 else 284 status |= ATMEL_US_RI; 285 } 286 287 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 288 UART_GPIO_DCD))) { 289 if (ret & TIOCM_CD) 290 status &= ~ATMEL_US_DCD; 291 else 292 status |= ATMEL_US_DCD; 293 } 294 295 return status; 296} 297 298/* Enable or disable the rs485 support */ 299static int atmel_config_rs485(struct uart_port *port, 300 struct serial_rs485 *rs485conf) 301{ 302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 303 unsigned int mode; 304 305 /* Disable interrupts */ 306 UART_PUT_IDR(port, atmel_port->tx_done_mask); 307 308 mode = UART_GET_MR(port); 309 310 /* Resetting serial mode to RS232 (0x0) */ 311 mode &= ~ATMEL_US_USMODE; 312 313 port->rs485 = *rs485conf; 314 315 if (rs485conf->flags & SER_RS485_ENABLED) { 316 dev_dbg(port->dev, "Setting UART to RS485\n"); 317 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 318 UART_PUT_TTGR(port, rs485conf->delay_rts_after_send); 319 mode |= ATMEL_US_USMODE_RS485; 320 } else { 321 dev_dbg(port->dev, "Setting UART to RS232\n"); 322 if (atmel_use_pdc_tx(port)) 323 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 324 ATMEL_US_TXBUFE; 325 else 326 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 327 } 328 UART_PUT_MR(port, mode); 329 330 /* Enable interrupts */ 331 UART_PUT_IER(port, atmel_port->tx_done_mask); 332 333 return 0; 334} 335 336/* 337 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 338 */ 339static u_int atmel_tx_empty(struct uart_port *port) 340{ 341 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0; 342} 343 344/* 345 * Set state of the modem control output lines 346 */ 347static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 348{ 349 unsigned int control = 0; 350 unsigned int mode = UART_GET_MR(port); 351 unsigned int rts_paused, rts_ready; 352 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 353 354 /* override mode to RS485 if needed, otherwise keep the current mode */ 355 if (port->rs485.flags & SER_RS485_ENABLED) { 356 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 357 mode &= ~ATMEL_US_USMODE; 358 mode |= ATMEL_US_USMODE_RS485; 359 } 360 361 /* set the RTS line state according to the mode */ 362 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 363 /* force RTS line to high level */ 364 rts_paused = ATMEL_US_RTSEN; 365 366 /* give the control of the RTS line back to the hardware */ 367 rts_ready = ATMEL_US_RTSDIS; 368 } else { 369 /* force RTS line to high level */ 370 rts_paused = ATMEL_US_RTSDIS; 371 372 /* force RTS line to low level */ 373 rts_ready = ATMEL_US_RTSEN; 374 } 375 376 if (mctrl & TIOCM_RTS) 377 control |= rts_ready; 378 else 379 control |= rts_paused; 380 381 if (mctrl & TIOCM_DTR) 382 control |= ATMEL_US_DTREN; 383 else 384 control |= ATMEL_US_DTRDIS; 385 386 UART_PUT_CR(port, control); 387 388 mctrl_gpio_set(atmel_port->gpios, mctrl); 389 390 /* Local loopback mode? */ 391 mode &= ~ATMEL_US_CHMODE; 392 if (mctrl & TIOCM_LOOP) 393 mode |= ATMEL_US_CHMODE_LOC_LOOP; 394 else 395 mode |= ATMEL_US_CHMODE_NORMAL; 396 397 UART_PUT_MR(port, mode); 398} 399 400/* 401 * Get state of the modem control input lines 402 */ 403static u_int atmel_get_mctrl(struct uart_port *port) 404{ 405 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 406 unsigned int ret = 0, status; 407 408 status = UART_GET_CSR(port); 409 410 /* 411 * The control signals are active low. 412 */ 413 if (!(status & ATMEL_US_DCD)) 414 ret |= TIOCM_CD; 415 if (!(status & ATMEL_US_CTS)) 416 ret |= TIOCM_CTS; 417 if (!(status & ATMEL_US_DSR)) 418 ret |= TIOCM_DSR; 419 if (!(status & ATMEL_US_RI)) 420 ret |= TIOCM_RI; 421 422 return mctrl_gpio_get(atmel_port->gpios, &ret); 423} 424 425/* 426 * Stop transmitting. 427 */ 428static void atmel_stop_tx(struct uart_port *port) 429{ 430 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 431 432 if (atmel_use_pdc_tx(port)) { 433 /* disable PDC transmit */ 434 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 435 } 436 /* Disable interrupts */ 437 UART_PUT_IDR(port, atmel_port->tx_done_mask); 438 439 if ((port->rs485.flags & SER_RS485_ENABLED) && 440 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 441 atmel_start_rx(port); 442} 443 444/* 445 * Start transmitting. 446 */ 447static void atmel_start_tx(struct uart_port *port) 448{ 449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 450 451 if (atmel_use_pdc_tx(port)) { 452 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN) 453 /* The transmitter is already running. Yes, we 454 really need this.*/ 455 return; 456 457 if ((port->rs485.flags & SER_RS485_ENABLED) && 458 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 459 atmel_stop_rx(port); 460 461 /* re-enable PDC transmit */ 462 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 463 } 464 /* Enable interrupts */ 465 UART_PUT_IER(port, atmel_port->tx_done_mask); 466} 467 468/* 469 * start receiving - port is in process of being opened. 470 */ 471static void atmel_start_rx(struct uart_port *port) 472{ 473 UART_PUT_CR(port, ATMEL_US_RSTSTA); /* reset status and receiver */ 474 475 UART_PUT_CR(port, ATMEL_US_RXEN); 476 477 if (atmel_use_pdc_rx(port)) { 478 /* enable PDC controller */ 479 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 480 port->read_status_mask); 481 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 482 } else { 483 UART_PUT_IER(port, ATMEL_US_RXRDY); 484 } 485} 486 487/* 488 * Stop receiving - port is in process of being closed. 489 */ 490static void atmel_stop_rx(struct uart_port *port) 491{ 492 UART_PUT_CR(port, ATMEL_US_RXDIS); 493 494 if (atmel_use_pdc_rx(port)) { 495 /* disable PDC receive */ 496 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); 497 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 498 port->read_status_mask); 499 } else { 500 UART_PUT_IDR(port, ATMEL_US_RXRDY); 501 } 502} 503 504/* 505 * Enable modem status interrupts 506 */ 507static void atmel_enable_ms(struct uart_port *port) 508{ 509 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 510 uint32_t ier = 0; 511 512 /* 513 * Interrupt should not be enabled twice 514 */ 515 if (atmel_port->ms_irq_enabled) 516 return; 517 518 atmel_port->ms_irq_enabled = true; 519 520 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 521 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 522 else 523 ier |= ATMEL_US_CTSIC; 524 525 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 526 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 527 else 528 ier |= ATMEL_US_DSRIC; 529 530 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 531 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 532 else 533 ier |= ATMEL_US_RIIC; 534 535 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 536 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 537 else 538 ier |= ATMEL_US_DCDIC; 539 540 UART_PUT_IER(port, ier); 541} 542 543/* 544 * Disable modem status interrupts 545 */ 546static void atmel_disable_ms(struct uart_port *port) 547{ 548 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 549 uint32_t idr = 0; 550 551 /* 552 * Interrupt should not be disabled twice 553 */ 554 if (!atmel_port->ms_irq_enabled) 555 return; 556 557 atmel_port->ms_irq_enabled = false; 558 559 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) 560 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); 561 else 562 idr |= ATMEL_US_CTSIC; 563 564 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) 565 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); 566 else 567 idr |= ATMEL_US_DSRIC; 568 569 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) 570 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); 571 else 572 idr |= ATMEL_US_RIIC; 573 574 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) 575 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); 576 else 577 idr |= ATMEL_US_DCDIC; 578 579 UART_PUT_IDR(port, idr); 580} 581 582/* 583 * Control the transmission of a break signal 584 */ 585static void atmel_break_ctl(struct uart_port *port, int break_state) 586{ 587 if (break_state != 0) 588 UART_PUT_CR(port, ATMEL_US_STTBRK); /* start break */ 589 else 590 UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */ 591} 592 593/* 594 * Stores the incoming character in the ring buffer 595 */ 596static void 597atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 598 unsigned int ch) 599{ 600 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 601 struct circ_buf *ring = &atmel_port->rx_ring; 602 struct atmel_uart_char *c; 603 604 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 605 /* Buffer overflow, ignore char */ 606 return; 607 608 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 609 c->status = status; 610 c->ch = ch; 611 612 /* Make sure the character is stored before we update head. */ 613 smp_wmb(); 614 615 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 616} 617 618/* 619 * Deal with parity, framing and overrun errors. 620 */ 621static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 622{ 623 /* clear error */ 624 UART_PUT_CR(port, ATMEL_US_RSTSTA); 625 626 if (status & ATMEL_US_RXBRK) { 627 /* ignore side-effect */ 628 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 629 port->icount.brk++; 630 } 631 if (status & ATMEL_US_PARE) 632 port->icount.parity++; 633 if (status & ATMEL_US_FRAME) 634 port->icount.frame++; 635 if (status & ATMEL_US_OVRE) 636 port->icount.overrun++; 637} 638 639/* 640 * Characters received (called from interrupt handler) 641 */ 642static void atmel_rx_chars(struct uart_port *port) 643{ 644 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 645 unsigned int status, ch; 646 647 status = UART_GET_CSR(port); 648 while (status & ATMEL_US_RXRDY) { 649 ch = UART_GET_CHAR(port); 650 651 /* 652 * note that the error handling code is 653 * out of the main execution path 654 */ 655 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 656 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 657 || atmel_port->break_active)) { 658 659 /* clear error */ 660 UART_PUT_CR(port, ATMEL_US_RSTSTA); 661 662 if (status & ATMEL_US_RXBRK 663 && !atmel_port->break_active) { 664 atmel_port->break_active = 1; 665 UART_PUT_IER(port, ATMEL_US_RXBRK); 666 } else { 667 /* 668 * This is either the end-of-break 669 * condition or we've received at 670 * least one character without RXBRK 671 * being set. In both cases, the next 672 * RXBRK will indicate start-of-break. 673 */ 674 UART_PUT_IDR(port, ATMEL_US_RXBRK); 675 status &= ~ATMEL_US_RXBRK; 676 atmel_port->break_active = 0; 677 } 678 } 679 680 atmel_buffer_rx_char(port, status, ch); 681 status = UART_GET_CSR(port); 682 } 683 684 tasklet_schedule(&atmel_port->tasklet); 685} 686 687/* 688 * Transmit characters (called from tasklet with TXRDY interrupt 689 * disabled) 690 */ 691static void atmel_tx_chars(struct uart_port *port) 692{ 693 struct circ_buf *xmit = &port->state->xmit; 694 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 695 696 if (port->x_char && UART_GET_CSR(port) & atmel_port->tx_done_mask) { 697 UART_PUT_CHAR(port, port->x_char); 698 port->icount.tx++; 699 port->x_char = 0; 700 } 701 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 702 return; 703 704 while (UART_GET_CSR(port) & atmel_port->tx_done_mask) { 705 UART_PUT_CHAR(port, xmit->buf[xmit->tail]); 706 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 707 port->icount.tx++; 708 if (uart_circ_empty(xmit)) 709 break; 710 } 711 712 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 713 uart_write_wakeup(port); 714 715 if (!uart_circ_empty(xmit)) 716 /* Enable interrupts */ 717 UART_PUT_IER(port, atmel_port->tx_done_mask); 718} 719 720static void atmel_complete_tx_dma(void *arg) 721{ 722 struct atmel_uart_port *atmel_port = arg; 723 struct uart_port *port = &atmel_port->uart; 724 struct circ_buf *xmit = &port->state->xmit; 725 struct dma_chan *chan = atmel_port->chan_tx; 726 unsigned long flags; 727 728 spin_lock_irqsave(&port->lock, flags); 729 730 if (chan) 731 dmaengine_terminate_all(chan); 732 xmit->tail += sg_dma_len(&atmel_port->sg_tx); 733 xmit->tail &= UART_XMIT_SIZE - 1; 734 735 port->icount.tx += sg_dma_len(&atmel_port->sg_tx); 736 737 spin_lock_irq(&atmel_port->lock_tx); 738 async_tx_ack(atmel_port->desc_tx); 739 atmel_port->cookie_tx = -EINVAL; 740 atmel_port->desc_tx = NULL; 741 spin_unlock_irq(&atmel_port->lock_tx); 742 743 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 744 uart_write_wakeup(port); 745 746 /* 747 * xmit is a circular buffer so, if we have just send data from 748 * xmit->tail to the end of xmit->buf, now we have to transmit the 749 * remaining data from the beginning of xmit->buf to xmit->head. 750 */ 751 if (!uart_circ_empty(xmit)) 752 tasklet_schedule(&atmel_port->tasklet); 753 754 spin_unlock_irqrestore(&port->lock, flags); 755} 756 757static void atmel_release_tx_dma(struct uart_port *port) 758{ 759 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 760 struct dma_chan *chan = atmel_port->chan_tx; 761 762 if (chan) { 763 dmaengine_terminate_all(chan); 764 dma_release_channel(chan); 765 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 766 DMA_TO_DEVICE); 767 } 768 769 atmel_port->desc_tx = NULL; 770 atmel_port->chan_tx = NULL; 771 atmel_port->cookie_tx = -EINVAL; 772} 773 774/* 775 * Called from tasklet with TXRDY interrupt is disabled. 776 */ 777static void atmel_tx_dma(struct uart_port *port) 778{ 779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 780 struct circ_buf *xmit = &port->state->xmit; 781 struct dma_chan *chan = atmel_port->chan_tx; 782 struct dma_async_tx_descriptor *desc; 783 struct scatterlist *sg = &atmel_port->sg_tx; 784 785 /* Make sure we have an idle channel */ 786 if (atmel_port->desc_tx != NULL) 787 return; 788 789 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 790 /* 791 * DMA is idle now. 792 * Port xmit buffer is already mapped, 793 * and it is one page... Just adjust 794 * offsets and lengths. Since it is a circular buffer, 795 * we have to transmit till the end, and then the rest. 796 * Take the port lock to get a 797 * consistent xmit buffer state. 798 */ 799 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); 800 sg_dma_address(sg) = (sg_dma_address(sg) & 801 ~(UART_XMIT_SIZE - 1)) 802 + sg->offset; 803 sg_dma_len(sg) = CIRC_CNT_TO_END(xmit->head, 804 xmit->tail, 805 UART_XMIT_SIZE); 806 BUG_ON(!sg_dma_len(sg)); 807 808 desc = dmaengine_prep_slave_sg(chan, 809 sg, 810 1, 811 DMA_MEM_TO_DEV, 812 DMA_PREP_INTERRUPT | 813 DMA_CTRL_ACK); 814 if (!desc) { 815 dev_err(port->dev, "Failed to send via dma!\n"); 816 return; 817 } 818 819 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); 820 821 atmel_port->desc_tx = desc; 822 desc->callback = atmel_complete_tx_dma; 823 desc->callback_param = atmel_port; 824 atmel_port->cookie_tx = dmaengine_submit(desc); 825 826 } else { 827 if (port->rs485.flags & SER_RS485_ENABLED) { 828 /* DMA done, stop TX, start RX for RS485 */ 829 atmel_start_rx(port); 830 } 831 } 832 833 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 834 uart_write_wakeup(port); 835} 836 837static int atmel_prepare_tx_dma(struct uart_port *port) 838{ 839 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 840 dma_cap_mask_t mask; 841 struct dma_slave_config config; 842 int ret, nent; 843 844 dma_cap_zero(mask); 845 dma_cap_set(DMA_SLAVE, mask); 846 847 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 848 if (atmel_port->chan_tx == NULL) 849 goto chan_err; 850 dev_info(port->dev, "using %s for tx DMA transfers\n", 851 dma_chan_name(atmel_port->chan_tx)); 852 853 spin_lock_init(&atmel_port->lock_tx); 854 sg_init_table(&atmel_port->sg_tx, 1); 855 /* UART circular tx buffer is an aligned page. */ 856 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 857 sg_set_page(&atmel_port->sg_tx, 858 virt_to_page(port->state->xmit.buf), 859 UART_XMIT_SIZE, 860 (int)port->state->xmit.buf & ~PAGE_MASK); 861 nent = dma_map_sg(port->dev, 862 &atmel_port->sg_tx, 863 1, 864 DMA_TO_DEVICE); 865 866 if (!nent) { 867 dev_dbg(port->dev, "need to release resource of dma\n"); 868 goto chan_err; 869 } else { 870 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 871 sg_dma_len(&atmel_port->sg_tx), 872 port->state->xmit.buf, 873 sg_dma_address(&atmel_port->sg_tx)); 874 } 875 876 /* Configure the slave DMA */ 877 memset(&config, 0, sizeof(config)); 878 config.direction = DMA_MEM_TO_DEV; 879 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 880 config.dst_addr = port->mapbase + ATMEL_US_THR; 881 config.dst_maxburst = 1; 882 883 ret = dmaengine_slave_config(atmel_port->chan_tx, 884 &config); 885 if (ret) { 886 dev_err(port->dev, "DMA tx slave configuration failed\n"); 887 goto chan_err; 888 } 889 890 return 0; 891 892chan_err: 893 dev_err(port->dev, "TX channel not available, switch to pio\n"); 894 atmel_port->use_dma_tx = 0; 895 if (atmel_port->chan_tx) 896 atmel_release_tx_dma(port); 897 return -EINVAL; 898} 899 900static void atmel_complete_rx_dma(void *arg) 901{ 902 struct uart_port *port = arg; 903 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 904 905 tasklet_schedule(&atmel_port->tasklet); 906} 907 908static void atmel_release_rx_dma(struct uart_port *port) 909{ 910 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 911 struct dma_chan *chan = atmel_port->chan_rx; 912 913 if (chan) { 914 dmaengine_terminate_all(chan); 915 dma_release_channel(chan); 916 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 917 DMA_FROM_DEVICE); 918 } 919 920 atmel_port->desc_rx = NULL; 921 atmel_port->chan_rx = NULL; 922 atmel_port->cookie_rx = -EINVAL; 923} 924 925static void atmel_rx_from_dma(struct uart_port *port) 926{ 927 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 928 struct tty_port *tport = &port->state->port; 929 struct circ_buf *ring = &atmel_port->rx_ring; 930 struct dma_chan *chan = atmel_port->chan_rx; 931 struct dma_tx_state state; 932 enum dma_status dmastat; 933 size_t count; 934 935 936 /* Reset the UART timeout early so that we don't miss one */ 937 UART_PUT_CR(port, ATMEL_US_STTTO); 938 dmastat = dmaengine_tx_status(chan, 939 atmel_port->cookie_rx, 940 &state); 941 /* Restart a new tasklet if DMA status is error */ 942 if (dmastat == DMA_ERROR) { 943 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 944 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 945 tasklet_schedule(&atmel_port->tasklet); 946 return; 947 } 948 949 /* CPU claims ownership of RX DMA buffer */ 950 dma_sync_sg_for_cpu(port->dev, 951 &atmel_port->sg_rx, 952 1, 953 DMA_FROM_DEVICE); 954 955 /* 956 * ring->head points to the end of data already written by the DMA. 957 * ring->tail points to the beginning of data to be read by the 958 * framework. 959 * The current transfer size should not be larger than the dma buffer 960 * length. 961 */ 962 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 963 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 964 /* 965 * At this point ring->head may point to the first byte right after the 966 * last byte of the dma buffer: 967 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 968 * 969 * However ring->tail must always points inside the dma buffer: 970 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 971 * 972 * Since we use a ring buffer, we have to handle the case 973 * where head is lower than tail. In such a case, we first read from 974 * tail to the end of the buffer then reset tail. 975 */ 976 if (ring->head < ring->tail) { 977 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 978 979 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 980 ring->tail = 0; 981 port->icount.rx += count; 982 } 983 984 /* Finally we read data from tail to head */ 985 if (ring->tail < ring->head) { 986 count = ring->head - ring->tail; 987 988 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 989 /* Wrap ring->head if needed */ 990 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 991 ring->head = 0; 992 ring->tail = ring->head; 993 port->icount.rx += count; 994 } 995 996 /* USART retreives ownership of RX DMA buffer */ 997 dma_sync_sg_for_device(port->dev, 998 &atmel_port->sg_rx, 999 1, 1000 DMA_FROM_DEVICE); 1001 1002 /* 1003 * Drop the lock here since it might end up calling 1004 * uart_start(), which takes the lock. 1005 */ 1006 spin_unlock(&port->lock); 1007 tty_flip_buffer_push(tport); 1008 spin_lock(&port->lock); 1009 1010 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1011} 1012 1013static int atmel_prepare_rx_dma(struct uart_port *port) 1014{ 1015 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1016 struct dma_async_tx_descriptor *desc; 1017 dma_cap_mask_t mask; 1018 struct dma_slave_config config; 1019 struct circ_buf *ring; 1020 int ret, nent; 1021 1022 ring = &atmel_port->rx_ring; 1023 1024 dma_cap_zero(mask); 1025 dma_cap_set(DMA_CYCLIC, mask); 1026 1027 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 1028 if (atmel_port->chan_rx == NULL) 1029 goto chan_err; 1030 dev_info(port->dev, "using %s for rx DMA transfers\n", 1031 dma_chan_name(atmel_port->chan_rx)); 1032 1033 spin_lock_init(&atmel_port->lock_rx); 1034 sg_init_table(&atmel_port->sg_rx, 1); 1035 /* UART circular rx buffer is an aligned page. */ 1036 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1037 sg_set_page(&atmel_port->sg_rx, 1038 virt_to_page(ring->buf), 1039 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1040 (int)ring->buf & ~PAGE_MASK); 1041 nent = dma_map_sg(port->dev, 1042 &atmel_port->sg_rx, 1043 1, 1044 DMA_FROM_DEVICE); 1045 1046 if (!nent) { 1047 dev_dbg(port->dev, "need to release resource of dma\n"); 1048 goto chan_err; 1049 } else { 1050 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, 1051 sg_dma_len(&atmel_port->sg_rx), 1052 ring->buf, 1053 sg_dma_address(&atmel_port->sg_rx)); 1054 } 1055 1056 /* Configure the slave DMA */ 1057 memset(&config, 0, sizeof(config)); 1058 config.direction = DMA_DEV_TO_MEM; 1059 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1060 config.src_addr = port->mapbase + ATMEL_US_RHR; 1061 config.src_maxburst = 1; 1062 1063 ret = dmaengine_slave_config(atmel_port->chan_rx, 1064 &config); 1065 if (ret) { 1066 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1067 goto chan_err; 1068 } 1069 /* 1070 * Prepare a cyclic dma transfer, assign 2 descriptors, 1071 * each one is half ring buffer size 1072 */ 1073 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1074 sg_dma_address(&atmel_port->sg_rx), 1075 sg_dma_len(&atmel_port->sg_rx), 1076 sg_dma_len(&atmel_port->sg_rx)/2, 1077 DMA_DEV_TO_MEM, 1078 DMA_PREP_INTERRUPT); 1079 desc->callback = atmel_complete_rx_dma; 1080 desc->callback_param = port; 1081 atmel_port->desc_rx = desc; 1082 atmel_port->cookie_rx = dmaengine_submit(desc); 1083 1084 return 0; 1085 1086chan_err: 1087 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1088 atmel_port->use_dma_rx = 0; 1089 if (atmel_port->chan_rx) 1090 atmel_release_rx_dma(port); 1091 return -EINVAL; 1092} 1093 1094static void atmel_uart_timer_callback(unsigned long data) 1095{ 1096 struct uart_port *port = (void *)data; 1097 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1098 1099 tasklet_schedule(&atmel_port->tasklet); 1100 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1101} 1102 1103/* 1104 * receive interrupt handler. 1105 */ 1106static void 1107atmel_handle_receive(struct uart_port *port, unsigned int pending) 1108{ 1109 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1110 1111 if (atmel_use_pdc_rx(port)) { 1112 /* 1113 * PDC receive. Just schedule the tasklet and let it 1114 * figure out the details. 1115 * 1116 * TODO: We're not handling error flags correctly at 1117 * the moment. 1118 */ 1119 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1120 UART_PUT_IDR(port, (ATMEL_US_ENDRX 1121 | ATMEL_US_TIMEOUT)); 1122 tasklet_schedule(&atmel_port->tasklet); 1123 } 1124 1125 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1126 ATMEL_US_FRAME | ATMEL_US_PARE)) 1127 atmel_pdc_rxerr(port, pending); 1128 } 1129 1130 if (atmel_use_dma_rx(port)) { 1131 if (pending & ATMEL_US_TIMEOUT) { 1132 UART_PUT_IDR(port, ATMEL_US_TIMEOUT); 1133 tasklet_schedule(&atmel_port->tasklet); 1134 } 1135 } 1136 1137 /* Interrupt receive */ 1138 if (pending & ATMEL_US_RXRDY) 1139 atmel_rx_chars(port); 1140 else if (pending & ATMEL_US_RXBRK) { 1141 /* 1142 * End of break detected. If it came along with a 1143 * character, atmel_rx_chars will handle it. 1144 */ 1145 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1146 UART_PUT_IDR(port, ATMEL_US_RXBRK); 1147 atmel_port->break_active = 0; 1148 } 1149} 1150 1151/* 1152 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1153 */ 1154static void 1155atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1156{ 1157 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1158 1159 if (pending & atmel_port->tx_done_mask) { 1160 /* Either PDC or interrupt transmission */ 1161 UART_PUT_IDR(port, atmel_port->tx_done_mask); 1162 tasklet_schedule(&atmel_port->tasklet); 1163 } 1164} 1165 1166/* 1167 * status flags interrupt handler. 1168 */ 1169static void 1170atmel_handle_status(struct uart_port *port, unsigned int pending, 1171 unsigned int status) 1172{ 1173 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1174 1175 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1176 | ATMEL_US_CTSIC)) { 1177 atmel_port->irq_status = status; 1178 tasklet_schedule(&atmel_port->tasklet); 1179 } 1180} 1181 1182/* 1183 * Interrupt handler 1184 */ 1185static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1186{ 1187 struct uart_port *port = dev_id; 1188 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1189 unsigned int status, pending, mask, pass_counter = 0; 1190 bool gpio_handled = false; 1191 1192 spin_lock(&atmel_port->lock_suspended); 1193 1194 do { 1195 status = atmel_get_lines_status(port); 1196 mask = UART_GET_IMR(port); 1197 pending = status & mask; 1198 if (!gpio_handled) { 1199 /* 1200 * Dealing with GPIO interrupt 1201 */ 1202 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) 1203 pending |= ATMEL_US_CTSIC; 1204 1205 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) 1206 pending |= ATMEL_US_DSRIC; 1207 1208 if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) 1209 pending |= ATMEL_US_RIIC; 1210 1211 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) 1212 pending |= ATMEL_US_DCDIC; 1213 1214 gpio_handled = true; 1215 } 1216 if (!pending) 1217 break; 1218 1219 if (atmel_port->suspended) { 1220 atmel_port->pending |= pending; 1221 atmel_port->pending_status = status; 1222 UART_PUT_IDR(port, mask); 1223 pm_system_wakeup(); 1224 break; 1225 } 1226 1227 atmel_handle_receive(port, pending); 1228 atmel_handle_status(port, pending, status); 1229 atmel_handle_transmit(port, pending); 1230 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1231 1232 spin_unlock(&atmel_port->lock_suspended); 1233 1234 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1235} 1236 1237static void atmel_release_tx_pdc(struct uart_port *port) 1238{ 1239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1240 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1241 1242 dma_unmap_single(port->dev, 1243 pdc->dma_addr, 1244 pdc->dma_size, 1245 DMA_TO_DEVICE); 1246} 1247 1248/* 1249 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1250 */ 1251static void atmel_tx_pdc(struct uart_port *port) 1252{ 1253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1254 struct circ_buf *xmit = &port->state->xmit; 1255 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1256 int count; 1257 1258 /* nothing left to transmit? */ 1259 if (UART_GET_TCR(port)) 1260 return; 1261 1262 xmit->tail += pdc->ofs; 1263 xmit->tail &= UART_XMIT_SIZE - 1; 1264 1265 port->icount.tx += pdc->ofs; 1266 pdc->ofs = 0; 1267 1268 /* more to transmit - setup next transfer */ 1269 1270 /* disable PDC transmit */ 1271 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 1272 1273 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1274 dma_sync_single_for_device(port->dev, 1275 pdc->dma_addr, 1276 pdc->dma_size, 1277 DMA_TO_DEVICE); 1278 1279 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1280 pdc->ofs = count; 1281 1282 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail); 1283 UART_PUT_TCR(port, count); 1284 /* re-enable PDC transmit */ 1285 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 1286 /* Enable interrupts */ 1287 UART_PUT_IER(port, atmel_port->tx_done_mask); 1288 } else { 1289 if ((port->rs485.flags & SER_RS485_ENABLED) && 1290 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1291 /* DMA done, stop TX, start RX for RS485 */ 1292 atmel_start_rx(port); 1293 } 1294 } 1295 1296 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1297 uart_write_wakeup(port); 1298} 1299 1300static int atmel_prepare_tx_pdc(struct uart_port *port) 1301{ 1302 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1303 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1304 struct circ_buf *xmit = &port->state->xmit; 1305 1306 pdc->buf = xmit->buf; 1307 pdc->dma_addr = dma_map_single(port->dev, 1308 pdc->buf, 1309 UART_XMIT_SIZE, 1310 DMA_TO_DEVICE); 1311 pdc->dma_size = UART_XMIT_SIZE; 1312 pdc->ofs = 0; 1313 1314 return 0; 1315} 1316 1317static void atmel_rx_from_ring(struct uart_port *port) 1318{ 1319 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1320 struct circ_buf *ring = &atmel_port->rx_ring; 1321 unsigned int flg; 1322 unsigned int status; 1323 1324 while (ring->head != ring->tail) { 1325 struct atmel_uart_char c; 1326 1327 /* Make sure c is loaded after head. */ 1328 smp_rmb(); 1329 1330 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1331 1332 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1333 1334 port->icount.rx++; 1335 status = c.status; 1336 flg = TTY_NORMAL; 1337 1338 /* 1339 * note that the error handling code is 1340 * out of the main execution path 1341 */ 1342 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1343 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1344 if (status & ATMEL_US_RXBRK) { 1345 /* ignore side-effect */ 1346 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1347 1348 port->icount.brk++; 1349 if (uart_handle_break(port)) 1350 continue; 1351 } 1352 if (status & ATMEL_US_PARE) 1353 port->icount.parity++; 1354 if (status & ATMEL_US_FRAME) 1355 port->icount.frame++; 1356 if (status & ATMEL_US_OVRE) 1357 port->icount.overrun++; 1358 1359 status &= port->read_status_mask; 1360 1361 if (status & ATMEL_US_RXBRK) 1362 flg = TTY_BREAK; 1363 else if (status & ATMEL_US_PARE) 1364 flg = TTY_PARITY; 1365 else if (status & ATMEL_US_FRAME) 1366 flg = TTY_FRAME; 1367 } 1368 1369 1370 if (uart_handle_sysrq_char(port, c.ch)) 1371 continue; 1372 1373 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1374 } 1375 1376 /* 1377 * Drop the lock here since it might end up calling 1378 * uart_start(), which takes the lock. 1379 */ 1380 spin_unlock(&port->lock); 1381 tty_flip_buffer_push(&port->state->port); 1382 spin_lock(&port->lock); 1383} 1384 1385static void atmel_release_rx_pdc(struct uart_port *port) 1386{ 1387 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1388 int i; 1389 1390 for (i = 0; i < 2; i++) { 1391 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1392 1393 dma_unmap_single(port->dev, 1394 pdc->dma_addr, 1395 pdc->dma_size, 1396 DMA_FROM_DEVICE); 1397 kfree(pdc->buf); 1398 } 1399} 1400 1401static void atmel_rx_from_pdc(struct uart_port *port) 1402{ 1403 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1404 struct tty_port *tport = &port->state->port; 1405 struct atmel_dma_buffer *pdc; 1406 int rx_idx = atmel_port->pdc_rx_idx; 1407 unsigned int head; 1408 unsigned int tail; 1409 unsigned int count; 1410 1411 do { 1412 /* Reset the UART timeout early so that we don't miss one */ 1413 UART_PUT_CR(port, ATMEL_US_STTTO); 1414 1415 pdc = &atmel_port->pdc_rx[rx_idx]; 1416 head = UART_GET_RPR(port) - pdc->dma_addr; 1417 tail = pdc->ofs; 1418 1419 /* If the PDC has switched buffers, RPR won't contain 1420 * any address within the current buffer. Since head 1421 * is unsigned, we just need a one-way comparison to 1422 * find out. 1423 * 1424 * In this case, we just need to consume the entire 1425 * buffer and resubmit it for DMA. This will clear the 1426 * ENDRX bit as well, so that we can safely re-enable 1427 * all interrupts below. 1428 */ 1429 head = min(head, pdc->dma_size); 1430 1431 if (likely(head != tail)) { 1432 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1433 pdc->dma_size, DMA_FROM_DEVICE); 1434 1435 /* 1436 * head will only wrap around when we recycle 1437 * the DMA buffer, and when that happens, we 1438 * explicitly set tail to 0. So head will 1439 * always be greater than tail. 1440 */ 1441 count = head - tail; 1442 1443 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1444 count); 1445 1446 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1447 pdc->dma_size, DMA_FROM_DEVICE); 1448 1449 port->icount.rx += count; 1450 pdc->ofs = head; 1451 } 1452 1453 /* 1454 * If the current buffer is full, we need to check if 1455 * the next one contains any additional data. 1456 */ 1457 if (head >= pdc->dma_size) { 1458 pdc->ofs = 0; 1459 UART_PUT_RNPR(port, pdc->dma_addr); 1460 UART_PUT_RNCR(port, pdc->dma_size); 1461 1462 rx_idx = !rx_idx; 1463 atmel_port->pdc_rx_idx = rx_idx; 1464 } 1465 } while (head >= pdc->dma_size); 1466 1467 /* 1468 * Drop the lock here since it might end up calling 1469 * uart_start(), which takes the lock. 1470 */ 1471 spin_unlock(&port->lock); 1472 tty_flip_buffer_push(tport); 1473 spin_lock(&port->lock); 1474 1475 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1476} 1477 1478static int atmel_prepare_rx_pdc(struct uart_port *port) 1479{ 1480 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1481 int i; 1482 1483 for (i = 0; i < 2; i++) { 1484 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1485 1486 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1487 if (pdc->buf == NULL) { 1488 if (i != 0) { 1489 dma_unmap_single(port->dev, 1490 atmel_port->pdc_rx[0].dma_addr, 1491 PDC_BUFFER_SIZE, 1492 DMA_FROM_DEVICE); 1493 kfree(atmel_port->pdc_rx[0].buf); 1494 } 1495 atmel_port->use_pdc_rx = 0; 1496 return -ENOMEM; 1497 } 1498 pdc->dma_addr = dma_map_single(port->dev, 1499 pdc->buf, 1500 PDC_BUFFER_SIZE, 1501 DMA_FROM_DEVICE); 1502 pdc->dma_size = PDC_BUFFER_SIZE; 1503 pdc->ofs = 0; 1504 } 1505 1506 atmel_port->pdc_rx_idx = 0; 1507 1508 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr); 1509 UART_PUT_RCR(port, PDC_BUFFER_SIZE); 1510 1511 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr); 1512 UART_PUT_RNCR(port, PDC_BUFFER_SIZE); 1513 1514 return 0; 1515} 1516 1517/* 1518 * tasklet handling tty stuff outside the interrupt handler. 1519 */ 1520static void atmel_tasklet_func(unsigned long data) 1521{ 1522 struct uart_port *port = (struct uart_port *)data; 1523 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1524 unsigned int status; 1525 unsigned int status_change; 1526 1527 /* The interrupt handler does not take the lock */ 1528 spin_lock(&port->lock); 1529 1530 atmel_port->schedule_tx(port); 1531 1532 status = atmel_port->irq_status; 1533 status_change = status ^ atmel_port->irq_status_prev; 1534 1535 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1536 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1537 /* TODO: All reads to CSR will clear these interrupts! */ 1538 if (status_change & ATMEL_US_RI) 1539 port->icount.rng++; 1540 if (status_change & ATMEL_US_DSR) 1541 port->icount.dsr++; 1542 if (status_change & ATMEL_US_DCD) 1543 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1544 if (status_change & ATMEL_US_CTS) 1545 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1546 1547 wake_up_interruptible(&port->state->port.delta_msr_wait); 1548 1549 atmel_port->irq_status_prev = status; 1550 } 1551 1552 atmel_port->schedule_rx(port); 1553 1554 spin_unlock(&port->lock); 1555} 1556 1557static void atmel_init_property(struct atmel_uart_port *atmel_port, 1558 struct platform_device *pdev) 1559{ 1560 struct device_node *np = pdev->dev.of_node; 1561 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1562 1563 if (np) { 1564 /* DMA/PDC usage specification */ 1565 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1566 if (of_get_property(np, "dmas", NULL)) { 1567 atmel_port->use_dma_rx = true; 1568 atmel_port->use_pdc_rx = false; 1569 } else { 1570 atmel_port->use_dma_rx = false; 1571 atmel_port->use_pdc_rx = true; 1572 } 1573 } else { 1574 atmel_port->use_dma_rx = false; 1575 atmel_port->use_pdc_rx = false; 1576 } 1577 1578 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1579 if (of_get_property(np, "dmas", NULL)) { 1580 atmel_port->use_dma_tx = true; 1581 atmel_port->use_pdc_tx = false; 1582 } else { 1583 atmel_port->use_dma_tx = false; 1584 atmel_port->use_pdc_tx = true; 1585 } 1586 } else { 1587 atmel_port->use_dma_tx = false; 1588 atmel_port->use_pdc_tx = false; 1589 } 1590 1591 } else { 1592 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1593 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1594 atmel_port->use_dma_rx = false; 1595 atmel_port->use_dma_tx = false; 1596 } 1597 1598} 1599 1600static void atmel_init_rs485(struct uart_port *port, 1601 struct platform_device *pdev) 1602{ 1603 struct device_node *np = pdev->dev.of_node; 1604 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1605 1606 if (np) { 1607 u32 rs485_delay[2]; 1608 /* rs485 properties */ 1609 if (of_property_read_u32_array(np, "rs485-rts-delay", 1610 rs485_delay, 2) == 0) { 1611 struct serial_rs485 *rs485conf = &port->rs485; 1612 1613 rs485conf->delay_rts_before_send = rs485_delay[0]; 1614 rs485conf->delay_rts_after_send = rs485_delay[1]; 1615 rs485conf->flags = 0; 1616 1617 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1618 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1619 1620 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1621 NULL)) 1622 rs485conf->flags |= SER_RS485_ENABLED; 1623 } 1624 } else { 1625 port->rs485 = pdata->rs485; 1626 } 1627 1628} 1629 1630static void atmel_set_ops(struct uart_port *port) 1631{ 1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1633 1634 if (atmel_use_dma_rx(port)) { 1635 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1636 atmel_port->schedule_rx = &atmel_rx_from_dma; 1637 atmel_port->release_rx = &atmel_release_rx_dma; 1638 } else if (atmel_use_pdc_rx(port)) { 1639 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1640 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1641 atmel_port->release_rx = &atmel_release_rx_pdc; 1642 } else { 1643 atmel_port->prepare_rx = NULL; 1644 atmel_port->schedule_rx = &atmel_rx_from_ring; 1645 atmel_port->release_rx = NULL; 1646 } 1647 1648 if (atmel_use_dma_tx(port)) { 1649 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1650 atmel_port->schedule_tx = &atmel_tx_dma; 1651 atmel_port->release_tx = &atmel_release_tx_dma; 1652 } else if (atmel_use_pdc_tx(port)) { 1653 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1654 atmel_port->schedule_tx = &atmel_tx_pdc; 1655 atmel_port->release_tx = &atmel_release_tx_pdc; 1656 } else { 1657 atmel_port->prepare_tx = NULL; 1658 atmel_port->schedule_tx = &atmel_tx_chars; 1659 atmel_port->release_tx = NULL; 1660 } 1661} 1662 1663/* 1664 * Get ip name usart or uart 1665 */ 1666static void atmel_get_ip_name(struct uart_port *port) 1667{ 1668 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1669 int name = UART_GET_IP_NAME(port); 1670 u32 version; 1671 int usart, uart; 1672 /* usart and uart ascii */ 1673 usart = 0x55534152; 1674 uart = 0x44424755; 1675 1676 atmel_port->is_usart = false; 1677 1678 if (name == usart) { 1679 dev_dbg(port->dev, "This is usart\n"); 1680 atmel_port->is_usart = true; 1681 } else if (name == uart) { 1682 dev_dbg(port->dev, "This is uart\n"); 1683 atmel_port->is_usart = false; 1684 } else { 1685 /* fallback for older SoCs: use version field */ 1686 version = UART_GET_IP_VERSION(port); 1687 switch (version) { 1688 case 0x302: 1689 case 0x10213: 1690 dev_dbg(port->dev, "This version is usart\n"); 1691 atmel_port->is_usart = true; 1692 break; 1693 case 0x203: 1694 case 0x10202: 1695 dev_dbg(port->dev, "This version is uart\n"); 1696 atmel_port->is_usart = false; 1697 break; 1698 default: 1699 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1700 } 1701 } 1702} 1703 1704static void atmel_free_gpio_irq(struct uart_port *port) 1705{ 1706 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1707 enum mctrl_gpio_idx i; 1708 1709 for (i = 0; i < UART_GPIO_MAX; i++) 1710 if (atmel_port->gpio_irq[i] >= 0) 1711 free_irq(atmel_port->gpio_irq[i], port); 1712} 1713 1714static int atmel_request_gpio_irq(struct uart_port *port) 1715{ 1716 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1717 int *irq = atmel_port->gpio_irq; 1718 enum mctrl_gpio_idx i; 1719 int err = 0; 1720 1721 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1722 if (irq[i] < 0) 1723 continue; 1724 1725 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1726 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, 1727 "atmel_serial", port); 1728 if (err) 1729 dev_err(port->dev, "atmel_startup - Can't get %d irq\n", 1730 irq[i]); 1731 } 1732 1733 /* 1734 * If something went wrong, rollback. 1735 */ 1736 while (err && (--i >= 0)) 1737 if (irq[i] >= 0) 1738 free_irq(irq[i], port); 1739 1740 return err; 1741} 1742 1743/* 1744 * Perform initialization and enable port for reception 1745 */ 1746static int atmel_startup(struct uart_port *port) 1747{ 1748 struct platform_device *pdev = to_platform_device(port->dev); 1749 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1750 struct tty_struct *tty = port->state->port.tty; 1751 int retval; 1752 1753 /* 1754 * Ensure that no interrupts are enabled otherwise when 1755 * request_irq() is called we could get stuck trying to 1756 * handle an unexpected interrupt 1757 */ 1758 UART_PUT_IDR(port, -1); 1759 atmel_port->ms_irq_enabled = false; 1760 1761 /* 1762 * Allocate the IRQ 1763 */ 1764 retval = request_irq(port->irq, atmel_interrupt, 1765 IRQF_SHARED | IRQF_COND_SUSPEND, 1766 tty ? tty->name : "atmel_serial", port); 1767 if (retval) { 1768 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1769 return retval; 1770 } 1771 1772 /* 1773 * Get the GPIO lines IRQ 1774 */ 1775 retval = atmel_request_gpio_irq(port); 1776 if (retval) 1777 goto free_irq; 1778 1779 tasklet_enable(&atmel_port->tasklet); 1780 1781 /* 1782 * Initialize DMA (if necessary) 1783 */ 1784 atmel_init_property(atmel_port, pdev); 1785 atmel_set_ops(port); 1786 1787 if (atmel_port->prepare_rx) { 1788 retval = atmel_port->prepare_rx(port); 1789 if (retval < 0) 1790 atmel_set_ops(port); 1791 } 1792 1793 if (atmel_port->prepare_tx) { 1794 retval = atmel_port->prepare_tx(port); 1795 if (retval < 0) 1796 atmel_set_ops(port); 1797 } 1798 1799 /* Save current CSR for comparison in atmel_tasklet_func() */ 1800 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1801 atmel_port->irq_status = atmel_port->irq_status_prev; 1802 1803 /* 1804 * Finally, enable the serial port 1805 */ 1806 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1807 /* enable xmit & rcvr */ 1808 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1809 1810 setup_timer(&atmel_port->uart_timer, 1811 atmel_uart_timer_callback, 1812 (unsigned long)port); 1813 1814 if (atmel_use_pdc_rx(port)) { 1815 /* set UART timeout */ 1816 if (!atmel_port->is_usart) { 1817 mod_timer(&atmel_port->uart_timer, 1818 jiffies + uart_poll_timeout(port)); 1819 /* set USART timeout */ 1820 } else { 1821 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1822 UART_PUT_CR(port, ATMEL_US_STTTO); 1823 1824 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1825 } 1826 /* enable PDC controller */ 1827 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); 1828 } else if (atmel_use_dma_rx(port)) { 1829 /* set UART timeout */ 1830 if (!atmel_port->is_usart) { 1831 mod_timer(&atmel_port->uart_timer, 1832 jiffies + uart_poll_timeout(port)); 1833 /* set USART timeout */ 1834 } else { 1835 UART_PUT_RTOR(port, PDC_RX_TIMEOUT); 1836 UART_PUT_CR(port, ATMEL_US_STTTO); 1837 1838 UART_PUT_IER(port, ATMEL_US_TIMEOUT); 1839 } 1840 } else { 1841 /* enable receive only */ 1842 UART_PUT_IER(port, ATMEL_US_RXRDY); 1843 } 1844 1845 return 0; 1846 1847free_irq: 1848 free_irq(port->irq, port); 1849 1850 return retval; 1851} 1852 1853/* 1854 * Flush any TX data submitted for DMA. Called when the TX circular 1855 * buffer is reset. 1856 */ 1857static void atmel_flush_buffer(struct uart_port *port) 1858{ 1859 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1860 1861 if (atmel_use_pdc_tx(port)) { 1862 UART_PUT_TCR(port, 0); 1863 atmel_port->pdc_tx.ofs = 0; 1864 } 1865} 1866 1867/* 1868 * Disable the port 1869 */ 1870static void atmel_shutdown(struct uart_port *port) 1871{ 1872 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1873 1874 /* 1875 * Prevent any tasklets being scheduled during 1876 * cleanup 1877 */ 1878 del_timer_sync(&atmel_port->uart_timer); 1879 1880 /* 1881 * Clear out any scheduled tasklets before 1882 * we destroy the buffers 1883 */ 1884 tasklet_disable(&atmel_port->tasklet); 1885 tasklet_kill(&atmel_port->tasklet); 1886 1887 /* 1888 * Ensure everything is stopped and 1889 * disable all interrupts, port and break condition. 1890 */ 1891 atmel_stop_rx(port); 1892 atmel_stop_tx(port); 1893 1894 UART_PUT_CR(port, ATMEL_US_RSTSTA); 1895 UART_PUT_IDR(port, -1); 1896 1897 1898 /* 1899 * Shut-down the DMA. 1900 */ 1901 if (atmel_port->release_rx) 1902 atmel_port->release_rx(port); 1903 if (atmel_port->release_tx) 1904 atmel_port->release_tx(port); 1905 1906 /* 1907 * Reset ring buffer pointers 1908 */ 1909 atmel_port->rx_ring.head = 0; 1910 atmel_port->rx_ring.tail = 0; 1911 1912 /* 1913 * Free the interrupts 1914 */ 1915 free_irq(port->irq, port); 1916 atmel_free_gpio_irq(port); 1917 1918 atmel_port->ms_irq_enabled = false; 1919 1920 atmel_flush_buffer(port); 1921} 1922 1923/* 1924 * Power / Clock management. 1925 */ 1926static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1927 unsigned int oldstate) 1928{ 1929 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1930 1931 switch (state) { 1932 case 0: 1933 /* 1934 * Enable the peripheral clock for this serial port. 1935 * This is called on uart_open() or a resume event. 1936 */ 1937 clk_prepare_enable(atmel_port->clk); 1938 1939 /* re-enable interrupts if we disabled some on suspend */ 1940 UART_PUT_IER(port, atmel_port->backup_imr); 1941 break; 1942 case 3: 1943 /* Back up the interrupt mask and disable all interrupts */ 1944 atmel_port->backup_imr = UART_GET_IMR(port); 1945 UART_PUT_IDR(port, -1); 1946 1947 /* 1948 * Disable the peripheral clock for this serial port. 1949 * This is called on uart_close() or a suspend event. 1950 */ 1951 clk_disable_unprepare(atmel_port->clk); 1952 break; 1953 default: 1954 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1955 } 1956} 1957 1958/* 1959 * Change the port parameters 1960 */ 1961static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1962 struct ktermios *old) 1963{ 1964 unsigned long flags; 1965 unsigned int old_mode, mode, imr, quot, baud; 1966 1967 /* save the current mode register */ 1968 mode = old_mode = UART_GET_MR(port); 1969 1970 /* reset the mode, clock divisor, parity, stop bits and data size */ 1971 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 1972 ATMEL_US_PAR | ATMEL_US_USMODE); 1973 1974 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1975 quot = uart_get_divisor(port, baud); 1976 1977 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 1978 quot /= 8; 1979 mode |= ATMEL_US_USCLKS_MCK_DIV8; 1980 } 1981 1982 /* byte size */ 1983 switch (termios->c_cflag & CSIZE) { 1984 case CS5: 1985 mode |= ATMEL_US_CHRL_5; 1986 break; 1987 case CS6: 1988 mode |= ATMEL_US_CHRL_6; 1989 break; 1990 case CS7: 1991 mode |= ATMEL_US_CHRL_7; 1992 break; 1993 default: 1994 mode |= ATMEL_US_CHRL_8; 1995 break; 1996 } 1997 1998 /* stop bits */ 1999 if (termios->c_cflag & CSTOPB) 2000 mode |= ATMEL_US_NBSTOP_2; 2001 2002 /* parity */ 2003 if (termios->c_cflag & PARENB) { 2004 /* Mark or Space parity */ 2005 if (termios->c_cflag & CMSPAR) { 2006 if (termios->c_cflag & PARODD) 2007 mode |= ATMEL_US_PAR_MARK; 2008 else 2009 mode |= ATMEL_US_PAR_SPACE; 2010 } else if (termios->c_cflag & PARODD) 2011 mode |= ATMEL_US_PAR_ODD; 2012 else 2013 mode |= ATMEL_US_PAR_EVEN; 2014 } else 2015 mode |= ATMEL_US_PAR_NONE; 2016 2017 spin_lock_irqsave(&port->lock, flags); 2018 2019 port->read_status_mask = ATMEL_US_OVRE; 2020 if (termios->c_iflag & INPCK) 2021 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2022 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2023 port->read_status_mask |= ATMEL_US_RXBRK; 2024 2025 if (atmel_use_pdc_rx(port)) 2026 /* need to enable error interrupts */ 2027 UART_PUT_IER(port, port->read_status_mask); 2028 2029 /* 2030 * Characters to ignore 2031 */ 2032 port->ignore_status_mask = 0; 2033 if (termios->c_iflag & IGNPAR) 2034 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2035 if (termios->c_iflag & IGNBRK) { 2036 port->ignore_status_mask |= ATMEL_US_RXBRK; 2037 /* 2038 * If we're ignoring parity and break indicators, 2039 * ignore overruns too (for real raw support). 2040 */ 2041 if (termios->c_iflag & IGNPAR) 2042 port->ignore_status_mask |= ATMEL_US_OVRE; 2043 } 2044 /* TODO: Ignore all characters if CREAD is set.*/ 2045 2046 /* update the per-port timeout */ 2047 uart_update_timeout(port, termios->c_cflag, baud); 2048 2049 /* 2050 * save/disable interrupts. The tty layer will ensure that the 2051 * transmitter is empty if requested by the caller, so there's 2052 * no need to wait for it here. 2053 */ 2054 imr = UART_GET_IMR(port); 2055 UART_PUT_IDR(port, -1); 2056 2057 /* disable receiver and transmitter */ 2058 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2059 2060 /* mode */ 2061 if (port->rs485.flags & SER_RS485_ENABLED) { 2062 UART_PUT_TTGR(port, port->rs485.delay_rts_after_send); 2063 mode |= ATMEL_US_USMODE_RS485; 2064 } else if (termios->c_cflag & CRTSCTS) { 2065 /* RS232 with hardware handshake (RTS/CTS) */ 2066 mode |= ATMEL_US_USMODE_HWHS; 2067 } else { 2068 /* RS232 without hadware handshake */ 2069 mode |= ATMEL_US_USMODE_NORMAL; 2070 } 2071 2072 /* set the mode, clock divisor, parity, stop bits and data size */ 2073 UART_PUT_MR(port, mode); 2074 2075 /* 2076 * when switching the mode, set the RTS line state according to the 2077 * new mode, otherwise keep the former state 2078 */ 2079 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2080 unsigned int rts_state; 2081 2082 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2083 /* let the hardware control the RTS line */ 2084 rts_state = ATMEL_US_RTSDIS; 2085 } else { 2086 /* force RTS line to low level */ 2087 rts_state = ATMEL_US_RTSEN; 2088 } 2089 2090 UART_PUT_CR(port, rts_state); 2091 } 2092 2093 /* set the baud rate */ 2094 UART_PUT_BRGR(port, quot); 2095 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2096 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2097 2098 /* restore interrupts */ 2099 UART_PUT_IER(port, imr); 2100 2101 /* CTS flow-control and modem-status interrupts */ 2102 if (UART_ENABLE_MS(port, termios->c_cflag)) 2103 atmel_enable_ms(port); 2104 else 2105 atmel_disable_ms(port); 2106 2107 spin_unlock_irqrestore(&port->lock, flags); 2108} 2109 2110static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2111{ 2112 if (termios->c_line == N_PPS) { 2113 port->flags |= UPF_HARDPPS_CD; 2114 spin_lock_irq(&port->lock); 2115 atmel_enable_ms(port); 2116 spin_unlock_irq(&port->lock); 2117 } else { 2118 port->flags &= ~UPF_HARDPPS_CD; 2119 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2120 spin_lock_irq(&port->lock); 2121 atmel_disable_ms(port); 2122 spin_unlock_irq(&port->lock); 2123 } 2124 } 2125} 2126 2127/* 2128 * Return string describing the specified port 2129 */ 2130static const char *atmel_type(struct uart_port *port) 2131{ 2132 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2133} 2134 2135/* 2136 * Release the memory region(s) being used by 'port'. 2137 */ 2138static void atmel_release_port(struct uart_port *port) 2139{ 2140 struct platform_device *pdev = to_platform_device(port->dev); 2141 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2142 2143 release_mem_region(port->mapbase, size); 2144 2145 if (port->flags & UPF_IOREMAP) { 2146 iounmap(port->membase); 2147 port->membase = NULL; 2148 } 2149} 2150 2151/* 2152 * Request the memory region(s) being used by 'port'. 2153 */ 2154static int atmel_request_port(struct uart_port *port) 2155{ 2156 struct platform_device *pdev = to_platform_device(port->dev); 2157 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2158 2159 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2160 return -EBUSY; 2161 2162 if (port->flags & UPF_IOREMAP) { 2163 port->membase = ioremap(port->mapbase, size); 2164 if (port->membase == NULL) { 2165 release_mem_region(port->mapbase, size); 2166 return -ENOMEM; 2167 } 2168 } 2169 2170 return 0; 2171} 2172 2173/* 2174 * Configure/autoconfigure the port. 2175 */ 2176static void atmel_config_port(struct uart_port *port, int flags) 2177{ 2178 if (flags & UART_CONFIG_TYPE) { 2179 port->type = PORT_ATMEL; 2180 atmel_request_port(port); 2181 } 2182} 2183 2184/* 2185 * Verify the new serial_struct (for TIOCSSERIAL). 2186 */ 2187static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2188{ 2189 int ret = 0; 2190 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2191 ret = -EINVAL; 2192 if (port->irq != ser->irq) 2193 ret = -EINVAL; 2194 if (ser->io_type != SERIAL_IO_MEM) 2195 ret = -EINVAL; 2196 if (port->uartclk / 16 != ser->baud_base) 2197 ret = -EINVAL; 2198 if ((void *)port->mapbase != ser->iomem_base) 2199 ret = -EINVAL; 2200 if (port->iobase != ser->port) 2201 ret = -EINVAL; 2202 if (ser->hub6 != 0) 2203 ret = -EINVAL; 2204 return ret; 2205} 2206 2207#ifdef CONFIG_CONSOLE_POLL 2208static int atmel_poll_get_char(struct uart_port *port) 2209{ 2210 while (!(UART_GET_CSR(port) & ATMEL_US_RXRDY)) 2211 cpu_relax(); 2212 2213 return UART_GET_CHAR(port); 2214} 2215 2216static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2217{ 2218 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2219 cpu_relax(); 2220 2221 UART_PUT_CHAR(port, ch); 2222} 2223#endif 2224 2225static struct uart_ops atmel_pops = { 2226 .tx_empty = atmel_tx_empty, 2227 .set_mctrl = atmel_set_mctrl, 2228 .get_mctrl = atmel_get_mctrl, 2229 .stop_tx = atmel_stop_tx, 2230 .start_tx = atmel_start_tx, 2231 .stop_rx = atmel_stop_rx, 2232 .enable_ms = atmel_enable_ms, 2233 .break_ctl = atmel_break_ctl, 2234 .startup = atmel_startup, 2235 .shutdown = atmel_shutdown, 2236 .flush_buffer = atmel_flush_buffer, 2237 .set_termios = atmel_set_termios, 2238 .set_ldisc = atmel_set_ldisc, 2239 .type = atmel_type, 2240 .release_port = atmel_release_port, 2241 .request_port = atmel_request_port, 2242 .config_port = atmel_config_port, 2243 .verify_port = atmel_verify_port, 2244 .pm = atmel_serial_pm, 2245#ifdef CONFIG_CONSOLE_POLL 2246 .poll_get_char = atmel_poll_get_char, 2247 .poll_put_char = atmel_poll_put_char, 2248#endif 2249}; 2250 2251/* 2252 * Configure the port from the platform device resource info. 2253 */ 2254static int atmel_init_port(struct atmel_uart_port *atmel_port, 2255 struct platform_device *pdev) 2256{ 2257 int ret; 2258 struct uart_port *port = &atmel_port->uart; 2259 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2260 2261 atmel_init_property(atmel_port, pdev); 2262 atmel_set_ops(port); 2263 2264 atmel_init_rs485(port, pdev); 2265 2266 port->iotype = UPIO_MEM; 2267 port->flags = UPF_BOOT_AUTOCONF; 2268 port->ops = &atmel_pops; 2269 port->fifosize = 1; 2270 port->dev = &pdev->dev; 2271 port->mapbase = pdev->resource[0].start; 2272 port->irq = pdev->resource[1].start; 2273 port->rs485_config = atmel_config_rs485; 2274 2275 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2276 (unsigned long)port); 2277 tasklet_disable(&atmel_port->tasklet); 2278 2279 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2280 2281 if (pdata && pdata->regs) { 2282 /* Already mapped by setup code */ 2283 port->membase = pdata->regs; 2284 } else { 2285 port->flags |= UPF_IOREMAP; 2286 port->membase = NULL; 2287 } 2288 2289 /* for console, the clock could already be configured */ 2290 if (!atmel_port->clk) { 2291 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2292 if (IS_ERR(atmel_port->clk)) { 2293 ret = PTR_ERR(atmel_port->clk); 2294 atmel_port->clk = NULL; 2295 return ret; 2296 } 2297 ret = clk_prepare_enable(atmel_port->clk); 2298 if (ret) { 2299 clk_put(atmel_port->clk); 2300 atmel_port->clk = NULL; 2301 return ret; 2302 } 2303 port->uartclk = clk_get_rate(atmel_port->clk); 2304 clk_disable_unprepare(atmel_port->clk); 2305 /* only enable clock when USART is in use */ 2306 } 2307 2308 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2309 if (port->rs485.flags & SER_RS485_ENABLED) 2310 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2311 else if (atmel_use_pdc_tx(port)) { 2312 port->fifosize = PDC_BUFFER_SIZE; 2313 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2314 } else { 2315 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2316 } 2317 2318 return 0; 2319} 2320 2321struct platform_device *atmel_default_console_device; /* the serial console device */ 2322 2323#ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2324static void atmel_console_putchar(struct uart_port *port, int ch) 2325{ 2326 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY)) 2327 cpu_relax(); 2328 UART_PUT_CHAR(port, ch); 2329} 2330 2331/* 2332 * Interrupts are disabled on entering 2333 */ 2334static void atmel_console_write(struct console *co, const char *s, u_int count) 2335{ 2336 struct uart_port *port = &atmel_ports[co->index].uart; 2337 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2338 unsigned int status, imr; 2339 unsigned int pdc_tx; 2340 2341 /* 2342 * First, save IMR and then disable interrupts 2343 */ 2344 imr = UART_GET_IMR(port); 2345 UART_PUT_IDR(port, ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2346 2347 /* Store PDC transmit status and disable it */ 2348 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN; 2349 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); 2350 2351 uart_console_write(port, s, count, atmel_console_putchar); 2352 2353 /* 2354 * Finally, wait for transmitter to become empty 2355 * and restore IMR 2356 */ 2357 do { 2358 status = UART_GET_CSR(port); 2359 } while (!(status & ATMEL_US_TXRDY)); 2360 2361 /* Restore PDC transmit status */ 2362 if (pdc_tx) 2363 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); 2364 2365 /* set interrupts back the way they were */ 2366 UART_PUT_IER(port, imr); 2367} 2368 2369/* 2370 * If the port was already initialised (eg, by a boot loader), 2371 * try to determine the current setup. 2372 */ 2373static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2374 int *parity, int *bits) 2375{ 2376 unsigned int mr, quot; 2377 2378 /* 2379 * If the baud rate generator isn't running, the port wasn't 2380 * initialized by the boot loader. 2381 */ 2382 quot = UART_GET_BRGR(port) & ATMEL_US_CD; 2383 if (!quot) 2384 return; 2385 2386 mr = UART_GET_MR(port) & ATMEL_US_CHRL; 2387 if (mr == ATMEL_US_CHRL_8) 2388 *bits = 8; 2389 else 2390 *bits = 7; 2391 2392 mr = UART_GET_MR(port) & ATMEL_US_PAR; 2393 if (mr == ATMEL_US_PAR_EVEN) 2394 *parity = 'e'; 2395 else if (mr == ATMEL_US_PAR_ODD) 2396 *parity = 'o'; 2397 2398 /* 2399 * The serial core only rounds down when matching this to a 2400 * supported baud rate. Make sure we don't end up slightly 2401 * lower than one of those, as it would make us fall through 2402 * to a much lower baud rate than we really want. 2403 */ 2404 *baud = port->uartclk / (16 * (quot - 1)); 2405} 2406 2407static int __init atmel_console_setup(struct console *co, char *options) 2408{ 2409 int ret; 2410 struct uart_port *port = &atmel_ports[co->index].uart; 2411 int baud = 115200; 2412 int bits = 8; 2413 int parity = 'n'; 2414 int flow = 'n'; 2415 2416 if (port->membase == NULL) { 2417 /* Port not initialized yet - delay setup */ 2418 return -ENODEV; 2419 } 2420 2421 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2422 if (ret) 2423 return ret; 2424 2425 UART_PUT_IDR(port, -1); 2426 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2427 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 2428 2429 if (options) 2430 uart_parse_options(options, &baud, &parity, &bits, &flow); 2431 else 2432 atmel_console_get_options(port, &baud, &parity, &bits); 2433 2434 return uart_set_options(port, co, baud, parity, bits, flow); 2435} 2436 2437static struct uart_driver atmel_uart; 2438 2439static struct console atmel_console = { 2440 .name = ATMEL_DEVICENAME, 2441 .write = atmel_console_write, 2442 .device = uart_console_device, 2443 .setup = atmel_console_setup, 2444 .flags = CON_PRINTBUFFER, 2445 .index = -1, 2446 .data = &atmel_uart, 2447}; 2448 2449#define ATMEL_CONSOLE_DEVICE (&atmel_console) 2450 2451/* 2452 * Early console initialization (before VM subsystem initialized). 2453 */ 2454static int __init atmel_console_init(void) 2455{ 2456 int ret; 2457 if (atmel_default_console_device) { 2458 struct atmel_uart_data *pdata = 2459 dev_get_platdata(&atmel_default_console_device->dev); 2460 int id = pdata->num; 2461 struct atmel_uart_port *port = &atmel_ports[id]; 2462 2463 port->backup_imr = 0; 2464 port->uart.line = id; 2465 2466 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2467 ret = atmel_init_port(port, atmel_default_console_device); 2468 if (ret) 2469 return ret; 2470 register_console(&atmel_console); 2471 } 2472 2473 return 0; 2474} 2475 2476console_initcall(atmel_console_init); 2477 2478/* 2479 * Late console initialization. 2480 */ 2481static int __init atmel_late_console_init(void) 2482{ 2483 if (atmel_default_console_device 2484 && !(atmel_console.flags & CON_ENABLED)) 2485 register_console(&atmel_console); 2486 2487 return 0; 2488} 2489 2490core_initcall(atmel_late_console_init); 2491 2492static inline bool atmel_is_console_port(struct uart_port *port) 2493{ 2494 return port->cons && port->cons->index == port->line; 2495} 2496 2497#else 2498#define ATMEL_CONSOLE_DEVICE NULL 2499 2500static inline bool atmel_is_console_port(struct uart_port *port) 2501{ 2502 return false; 2503} 2504#endif 2505 2506static struct uart_driver atmel_uart = { 2507 .owner = THIS_MODULE, 2508 .driver_name = "atmel_serial", 2509 .dev_name = ATMEL_DEVICENAME, 2510 .major = SERIAL_ATMEL_MAJOR, 2511 .minor = MINOR_START, 2512 .nr = ATMEL_MAX_UART, 2513 .cons = ATMEL_CONSOLE_DEVICE, 2514}; 2515 2516#ifdef CONFIG_PM 2517static bool atmel_serial_clk_will_stop(void) 2518{ 2519#ifdef CONFIG_ARCH_AT91 2520 return at91_suspend_entering_slow_clock(); 2521#else 2522 return false; 2523#endif 2524} 2525 2526static int atmel_serial_suspend(struct platform_device *pdev, 2527 pm_message_t state) 2528{ 2529 struct uart_port *port = platform_get_drvdata(pdev); 2530 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2531 2532 if (atmel_is_console_port(port) && console_suspend_enabled) { 2533 /* Drain the TX shifter */ 2534 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) 2535 cpu_relax(); 2536 } 2537 2538 /* we can not wake up if we're running on slow clock */ 2539 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2540 if (atmel_serial_clk_will_stop()) { 2541 unsigned long flags; 2542 2543 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2544 atmel_port->suspended = true; 2545 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2546 device_set_wakeup_enable(&pdev->dev, 0); 2547 } 2548 2549 uart_suspend_port(&atmel_uart, port); 2550 2551 return 0; 2552} 2553 2554static int atmel_serial_resume(struct platform_device *pdev) 2555{ 2556 struct uart_port *port = platform_get_drvdata(pdev); 2557 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2558 unsigned long flags; 2559 2560 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2561 if (atmel_port->pending) { 2562 atmel_handle_receive(port, atmel_port->pending); 2563 atmel_handle_status(port, atmel_port->pending, 2564 atmel_port->pending_status); 2565 atmel_handle_transmit(port, atmel_port->pending); 2566 atmel_port->pending = 0; 2567 } 2568 atmel_port->suspended = false; 2569 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2570 2571 uart_resume_port(&atmel_uart, port); 2572 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2573 2574 return 0; 2575} 2576#else 2577#define atmel_serial_suspend NULL 2578#define atmel_serial_resume NULL 2579#endif 2580 2581static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) 2582{ 2583 enum mctrl_gpio_idx i; 2584 struct gpio_desc *gpiod; 2585 2586 p->gpios = mctrl_gpio_init(dev, 0); 2587 if (IS_ERR(p->gpios)) 2588 return PTR_ERR(p->gpios); 2589 2590 for (i = 0; i < UART_GPIO_MAX; i++) { 2591 gpiod = mctrl_gpio_to_gpiod(p->gpios, i); 2592 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) 2593 p->gpio_irq[i] = gpiod_to_irq(gpiod); 2594 else 2595 p->gpio_irq[i] = -EINVAL; 2596 } 2597 2598 return 0; 2599} 2600 2601static int atmel_serial_probe(struct platform_device *pdev) 2602{ 2603 struct atmel_uart_port *port; 2604 struct device_node *np = pdev->dev.of_node; 2605 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2606 void *data; 2607 int ret = -ENODEV; 2608 bool rs485_enabled; 2609 2610 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2611 2612 if (np) 2613 ret = of_alias_get_id(np, "serial"); 2614 else 2615 if (pdata) 2616 ret = pdata->num; 2617 2618 if (ret < 0) 2619 /* port id not found in platform data nor device-tree aliases: 2620 * auto-enumerate it */ 2621 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2622 2623 if (ret >= ATMEL_MAX_UART) { 2624 ret = -ENODEV; 2625 goto err; 2626 } 2627 2628 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2629 /* port already in use */ 2630 ret = -EBUSY; 2631 goto err; 2632 } 2633 2634 port = &atmel_ports[ret]; 2635 port->backup_imr = 0; 2636 port->uart.line = ret; 2637 2638 spin_lock_init(&port->lock_suspended); 2639 2640 ret = atmel_init_gpios(port, &pdev->dev); 2641 if (ret < 0) { 2642 dev_err(&pdev->dev, "Failed to initialize GPIOs."); 2643 goto err_clear_bit; 2644 } 2645 2646 ret = atmel_init_port(port, pdev); 2647 if (ret) 2648 goto err_clear_bit; 2649 2650 if (!atmel_use_pdc_rx(&port->uart)) { 2651 ret = -ENOMEM; 2652 data = kmalloc(sizeof(struct atmel_uart_char) 2653 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2654 if (!data) 2655 goto err_alloc_ring; 2656 port->rx_ring.buf = data; 2657 } 2658 2659 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED; 2660 2661 ret = uart_add_one_port(&atmel_uart, &port->uart); 2662 if (ret) 2663 goto err_add_port; 2664 2665#ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2666 if (atmel_is_console_port(&port->uart) 2667 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2668 /* 2669 * The serial core enabled the clock for us, so undo 2670 * the clk_prepare_enable() in atmel_console_setup() 2671 */ 2672 clk_disable_unprepare(port->clk); 2673 } 2674#endif 2675 2676 device_init_wakeup(&pdev->dev, 1); 2677 platform_set_drvdata(pdev, port); 2678 2679 /* 2680 * The peripheral clock has been disabled by atmel_init_port(): 2681 * enable it before accessing I/O registers 2682 */ 2683 clk_prepare_enable(port->clk); 2684 2685 if (rs485_enabled) { 2686 UART_PUT_MR(&port->uart, ATMEL_US_USMODE_NORMAL); 2687 UART_PUT_CR(&port->uart, ATMEL_US_RTSEN); 2688 } 2689 2690 /* 2691 * Get port name of usart or uart 2692 */ 2693 atmel_get_ip_name(&port->uart); 2694 2695 /* 2696 * The peripheral clock can now safely be disabled till the port 2697 * is used 2698 */ 2699 clk_disable_unprepare(port->clk); 2700 2701 return 0; 2702 2703err_add_port: 2704 kfree(port->rx_ring.buf); 2705 port->rx_ring.buf = NULL; 2706err_alloc_ring: 2707 if (!atmel_is_console_port(&port->uart)) { 2708 clk_put(port->clk); 2709 port->clk = NULL; 2710 } 2711err_clear_bit: 2712 clear_bit(port->uart.line, atmel_ports_in_use); 2713err: 2714 return ret; 2715} 2716 2717static int atmel_serial_remove(struct platform_device *pdev) 2718{ 2719 struct uart_port *port = platform_get_drvdata(pdev); 2720 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2721 int ret = 0; 2722 2723 tasklet_kill(&atmel_port->tasklet); 2724 2725 device_init_wakeup(&pdev->dev, 0); 2726 2727 ret = uart_remove_one_port(&atmel_uart, port); 2728 2729 kfree(atmel_port->rx_ring.buf); 2730 2731 /* "port" is allocated statically, so we shouldn't free it */ 2732 2733 clear_bit(port->line, atmel_ports_in_use); 2734 2735 clk_put(atmel_port->clk); 2736 2737 return ret; 2738} 2739 2740static struct platform_driver atmel_serial_driver = { 2741 .probe = atmel_serial_probe, 2742 .remove = atmel_serial_remove, 2743 .suspend = atmel_serial_suspend, 2744 .resume = atmel_serial_resume, 2745 .driver = { 2746 .name = "atmel_usart", 2747 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2748 }, 2749}; 2750 2751static int __init atmel_serial_init(void) 2752{ 2753 int ret; 2754 2755 ret = uart_register_driver(&atmel_uart); 2756 if (ret) 2757 return ret; 2758 2759 ret = platform_driver_register(&atmel_serial_driver); 2760 if (ret) 2761 uart_unregister_driver(&atmel_uart); 2762 2763 return ret; 2764} 2765 2766static void __exit atmel_serial_exit(void) 2767{ 2768 platform_driver_unregister(&atmel_serial_driver); 2769 uart_unregister_driver(&atmel_uart); 2770} 2771 2772module_init(atmel_serial_init); 2773module_exit(atmel_serial_exit); 2774 2775MODULE_AUTHOR("Rick Bronson"); 2776MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); 2777MODULE_LICENSE("GPL"); 2778MODULE_ALIAS("platform:atmel_usart"); 2779