1/* 2 * Driver for CPM (SCC/SMC) serial ports; core driver 3 * 4 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek 5 * Based on ppc8xx.c by Thomas Gleixner 6 * Based on drivers/serial/amba.c by Russell King 7 * 8 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 9 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 10 * 11 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. 12 * (C) 2004 Intracom, S.A. 13 * (C) 2005-2006 MontaVista Software, Inc. 14 * Vitaly Bordug <vbordug@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 * 30 */ 31 32#include <linux/module.h> 33#include <linux/tty.h> 34#include <linux/tty_flip.h> 35#include <linux/ioport.h> 36#include <linux/init.h> 37#include <linux/serial.h> 38#include <linux/console.h> 39#include <linux/sysrq.h> 40#include <linux/device.h> 41#include <linux/bootmem.h> 42#include <linux/dma-mapping.h> 43#include <linux/fs_uart_pd.h> 44#include <linux/of_address.h> 45#include <linux/of_irq.h> 46#include <linux/of_platform.h> 47#include <linux/gpio.h> 48#include <linux/of_gpio.h> 49#include <linux/clk.h> 50 51#include <asm/io.h> 52#include <asm/irq.h> 53#include <asm/delay.h> 54#include <asm/fs_pd.h> 55#include <asm/udbg.h> 56 57#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 58#define SUPPORT_SYSRQ 59#endif 60 61#include <linux/serial_core.h> 62#include <linux/kernel.h> 63 64#include "cpm_uart.h" 65 66 67/**************************************************************/ 68 69static int cpm_uart_tx_pump(struct uart_port *port); 70static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); 71static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); 72static void cpm_uart_initbd(struct uart_cpm_port *pinfo); 73 74/**************************************************************/ 75 76#define HW_BUF_SPD_THRESHOLD 2400 77 78/* 79 * Check, if transmit buffers are processed 80*/ 81static unsigned int cpm_uart_tx_empty(struct uart_port *port) 82{ 83 struct uart_cpm_port *pinfo = 84 container_of(port, struct uart_cpm_port, port); 85 cbd_t __iomem *bdp = pinfo->tx_bd_base; 86 int ret = 0; 87 88 while (1) { 89 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) 90 break; 91 92 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { 93 ret = TIOCSER_TEMT; 94 break; 95 } 96 bdp++; 97 } 98 99 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); 100 101 return ret; 102} 103 104static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 105{ 106 struct uart_cpm_port *pinfo = 107 container_of(port, struct uart_cpm_port, port); 108 109 if (pinfo->gpios[GPIO_RTS] >= 0) 110 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); 111 112 if (pinfo->gpios[GPIO_DTR] >= 0) 113 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); 114} 115 116static unsigned int cpm_uart_get_mctrl(struct uart_port *port) 117{ 118 struct uart_cpm_port *pinfo = 119 container_of(port, struct uart_cpm_port, port); 120 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 121 122 if (pinfo->gpios[GPIO_CTS] >= 0) { 123 if (gpio_get_value(pinfo->gpios[GPIO_CTS])) 124 mctrl &= ~TIOCM_CTS; 125 } 126 127 if (pinfo->gpios[GPIO_DSR] >= 0) { 128 if (gpio_get_value(pinfo->gpios[GPIO_DSR])) 129 mctrl &= ~TIOCM_DSR; 130 } 131 132 if (pinfo->gpios[GPIO_DCD] >= 0) { 133 if (gpio_get_value(pinfo->gpios[GPIO_DCD])) 134 mctrl &= ~TIOCM_CAR; 135 } 136 137 if (pinfo->gpios[GPIO_RI] >= 0) { 138 if (!gpio_get_value(pinfo->gpios[GPIO_RI])) 139 mctrl |= TIOCM_RNG; 140 } 141 142 return mctrl; 143} 144 145/* 146 * Stop transmitter 147 */ 148static void cpm_uart_stop_tx(struct uart_port *port) 149{ 150 struct uart_cpm_port *pinfo = 151 container_of(port, struct uart_cpm_port, port); 152 smc_t __iomem *smcp = pinfo->smcp; 153 scc_t __iomem *sccp = pinfo->sccp; 154 155 pr_debug("CPM uart[%d]:stop tx\n", port->line); 156 157 if (IS_SMC(pinfo)) 158 clrbits8(&smcp->smc_smcm, SMCM_TX); 159 else 160 clrbits16(&sccp->scc_sccm, UART_SCCM_TX); 161} 162 163/* 164 * Start transmitter 165 */ 166static void cpm_uart_start_tx(struct uart_port *port) 167{ 168 struct uart_cpm_port *pinfo = 169 container_of(port, struct uart_cpm_port, port); 170 smc_t __iomem *smcp = pinfo->smcp; 171 scc_t __iomem *sccp = pinfo->sccp; 172 173 pr_debug("CPM uart[%d]:start tx\n", port->line); 174 175 if (IS_SMC(pinfo)) { 176 if (in_8(&smcp->smc_smcm) & SMCM_TX) 177 return; 178 } else { 179 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) 180 return; 181 } 182 183 if (cpm_uart_tx_pump(port) != 0) { 184 if (IS_SMC(pinfo)) { 185 setbits8(&smcp->smc_smcm, SMCM_TX); 186 } else { 187 setbits16(&sccp->scc_sccm, UART_SCCM_TX); 188 } 189 } 190} 191 192/* 193 * Stop receiver 194 */ 195static void cpm_uart_stop_rx(struct uart_port *port) 196{ 197 struct uart_cpm_port *pinfo = 198 container_of(port, struct uart_cpm_port, port); 199 smc_t __iomem *smcp = pinfo->smcp; 200 scc_t __iomem *sccp = pinfo->sccp; 201 202 pr_debug("CPM uart[%d]:stop rx\n", port->line); 203 204 if (IS_SMC(pinfo)) 205 clrbits8(&smcp->smc_smcm, SMCM_RX); 206 else 207 clrbits16(&sccp->scc_sccm, UART_SCCM_RX); 208} 209 210/* 211 * Generate a break. 212 */ 213static void cpm_uart_break_ctl(struct uart_port *port, int break_state) 214{ 215 struct uart_cpm_port *pinfo = 216 container_of(port, struct uart_cpm_port, port); 217 218 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, 219 break_state); 220 221 if (break_state) 222 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 223 else 224 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 225} 226 227/* 228 * Transmit characters, refill buffer descriptor, if possible 229 */ 230static void cpm_uart_int_tx(struct uart_port *port) 231{ 232 pr_debug("CPM uart[%d]:TX INT\n", port->line); 233 234 cpm_uart_tx_pump(port); 235} 236 237#ifdef CONFIG_CONSOLE_POLL 238static int serial_polled; 239#endif 240 241/* 242 * Receive characters 243 */ 244static void cpm_uart_int_rx(struct uart_port *port) 245{ 246 int i; 247 unsigned char ch; 248 u8 *cp; 249 struct tty_port *tport = &port->state->port; 250 struct uart_cpm_port *pinfo = 251 container_of(port, struct uart_cpm_port, port); 252 cbd_t __iomem *bdp; 253 u16 status; 254 unsigned int flg; 255 256 pr_debug("CPM uart[%d]:RX INT\n", port->line); 257 258 /* Just loop through the closed BDs and copy the characters into 259 * the buffer. 260 */ 261 bdp = pinfo->rx_cur; 262 for (;;) { 263#ifdef CONFIG_CONSOLE_POLL 264 if (unlikely(serial_polled)) { 265 serial_polled = 0; 266 return; 267 } 268#endif 269 /* get status */ 270 status = in_be16(&bdp->cbd_sc); 271 /* If this one is empty, return happy */ 272 if (status & BD_SC_EMPTY) 273 break; 274 275 /* get number of characters, and check spce in flip-buffer */ 276 i = in_be16(&bdp->cbd_datlen); 277 278 /* If we have not enough room in tty flip buffer, then we try 279 * later, which will be the next rx-interrupt or a timeout 280 */ 281 if (tty_buffer_request_room(tport, i) < i) { 282 printk(KERN_WARNING "No room in flip buffer\n"); 283 return; 284 } 285 286 /* get pointer */ 287 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 288 289 /* loop through the buffer */ 290 while (i-- > 0) { 291 ch = *cp++; 292 port->icount.rx++; 293 flg = TTY_NORMAL; 294 295 if (status & 296 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 297 goto handle_error; 298 if (uart_handle_sysrq_char(port, ch)) 299 continue; 300#ifdef CONFIG_CONSOLE_POLL 301 if (unlikely(serial_polled)) { 302 serial_polled = 0; 303 return; 304 } 305#endif 306 error_return: 307 tty_insert_flip_char(tport, ch, flg); 308 309 } /* End while (i--) */ 310 311 /* This BD is ready to be used again. Clear status. get next */ 312 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | 313 BD_SC_OV | BD_SC_ID); 314 setbits16(&bdp->cbd_sc, BD_SC_EMPTY); 315 316 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 317 bdp = pinfo->rx_bd_base; 318 else 319 bdp++; 320 321 } /* End for (;;) */ 322 323 /* Write back buffer pointer */ 324 pinfo->rx_cur = bdp; 325 326 /* activate BH processing */ 327 tty_flip_buffer_push(tport); 328 329 return; 330 331 /* Error processing */ 332 333 handle_error: 334 /* Statistics */ 335 if (status & BD_SC_BR) 336 port->icount.brk++; 337 if (status & BD_SC_PR) 338 port->icount.parity++; 339 if (status & BD_SC_FR) 340 port->icount.frame++; 341 if (status & BD_SC_OV) 342 port->icount.overrun++; 343 344 /* Mask out ignored conditions */ 345 status &= port->read_status_mask; 346 347 /* Handle the remaining ones */ 348 if (status & BD_SC_BR) 349 flg = TTY_BREAK; 350 else if (status & BD_SC_PR) 351 flg = TTY_PARITY; 352 else if (status & BD_SC_FR) 353 flg = TTY_FRAME; 354 355 /* overrun does not affect the current character ! */ 356 if (status & BD_SC_OV) { 357 ch = 0; 358 flg = TTY_OVERRUN; 359 /* We skip this buffer */ 360 /* CHECK: Is really nothing senseful there */ 361 /* ASSUMPTION: it contains nothing valid */ 362 i = 0; 363 } 364#ifdef SUPPORT_SYSRQ 365 port->sysrq = 0; 366#endif 367 goto error_return; 368} 369 370/* 371 * Asynchron mode interrupt handler 372 */ 373static irqreturn_t cpm_uart_int(int irq, void *data) 374{ 375 u8 events; 376 struct uart_port *port = data; 377 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 378 smc_t __iomem *smcp = pinfo->smcp; 379 scc_t __iomem *sccp = pinfo->sccp; 380 381 pr_debug("CPM uart[%d]:IRQ\n", port->line); 382 383 if (IS_SMC(pinfo)) { 384 events = in_8(&smcp->smc_smce); 385 out_8(&smcp->smc_smce, events); 386 if (events & SMCM_BRKE) 387 uart_handle_break(port); 388 if (events & SMCM_RX) 389 cpm_uart_int_rx(port); 390 if (events & SMCM_TX) 391 cpm_uart_int_tx(port); 392 } else { 393 events = in_be16(&sccp->scc_scce); 394 out_be16(&sccp->scc_scce, events); 395 if (events & UART_SCCM_BRKE) 396 uart_handle_break(port); 397 if (events & UART_SCCM_RX) 398 cpm_uart_int_rx(port); 399 if (events & UART_SCCM_TX) 400 cpm_uart_int_tx(port); 401 } 402 return (events) ? IRQ_HANDLED : IRQ_NONE; 403} 404 405static int cpm_uart_startup(struct uart_port *port) 406{ 407 int retval; 408 struct uart_cpm_port *pinfo = 409 container_of(port, struct uart_cpm_port, port); 410 411 pr_debug("CPM uart[%d]:startup\n", port->line); 412 413 /* If the port is not the console, make sure rx is disabled. */ 414 if (!(pinfo->flags & FLAG_CONSOLE)) { 415 /* Disable UART rx */ 416 if (IS_SMC(pinfo)) { 417 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); 418 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 419 } else { 420 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); 421 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 422 } 423 cpm_uart_initbd(pinfo); 424 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 425 } 426 /* Install interrupt handler. */ 427 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); 428 if (retval) 429 return retval; 430 431 /* Startup rx-int */ 432 if (IS_SMC(pinfo)) { 433 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 434 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); 435 } else { 436 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 437 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); 438 } 439 440 return 0; 441} 442 443inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) 444{ 445 set_current_state(TASK_UNINTERRUPTIBLE); 446 schedule_timeout(pinfo->wait_closing); 447} 448 449/* 450 * Shutdown the uart 451 */ 452static void cpm_uart_shutdown(struct uart_port *port) 453{ 454 struct uart_cpm_port *pinfo = 455 container_of(port, struct uart_cpm_port, port); 456 457 pr_debug("CPM uart[%d]:shutdown\n", port->line); 458 459 /* free interrupt handler */ 460 free_irq(port->irq, port); 461 462 /* If the port is not the console, disable Rx and Tx. */ 463 if (!(pinfo->flags & FLAG_CONSOLE)) { 464 /* Wait for all the BDs marked sent */ 465 while(!cpm_uart_tx_empty(port)) { 466 set_current_state(TASK_UNINTERRUPTIBLE); 467 schedule_timeout(2); 468 } 469 470 if (pinfo->wait_closing) 471 cpm_uart_wait_until_send(pinfo); 472 473 /* Stop uarts */ 474 if (IS_SMC(pinfo)) { 475 smc_t __iomem *smcp = pinfo->smcp; 476 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 477 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); 478 } else { 479 scc_t __iomem *sccp = pinfo->sccp; 480 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 481 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 482 } 483 484 /* Shut them really down and reinit buffer descriptors */ 485 if (IS_SMC(pinfo)) { 486 out_be16(&pinfo->smcup->smc_brkcr, 0); 487 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 488 } else { 489 out_be16(&pinfo->sccup->scc_brkcr, 0); 490 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 491 } 492 493 cpm_uart_initbd(pinfo); 494 } 495} 496 497static void cpm_uart_set_termios(struct uart_port *port, 498 struct ktermios *termios, 499 struct ktermios *old) 500{ 501 int baud; 502 unsigned long flags; 503 u16 cval, scval, prev_mode; 504 int bits, sbits; 505 struct uart_cpm_port *pinfo = 506 container_of(port, struct uart_cpm_port, port); 507 smc_t __iomem *smcp = pinfo->smcp; 508 scc_t __iomem *sccp = pinfo->sccp; 509 int maxidl; 510 511 pr_debug("CPM uart[%d]:set_termios\n", port->line); 512 513 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 514 if (baud < HW_BUF_SPD_THRESHOLD || 515 (pinfo->port.state && pinfo->port.state->port.low_latency)) 516 pinfo->rx_fifosize = 1; 517 else 518 pinfo->rx_fifosize = RX_BUF_SIZE; 519 520 /* MAXIDL is the timeout after which a receive buffer is closed 521 * when not full if no more characters are received. 522 * We calculate it from the baudrate so that the duration is 523 * always the same at standard rates: about 4ms. 524 */ 525 maxidl = baud / 2400; 526 if (maxidl < 1) 527 maxidl = 1; 528 if (maxidl > 0x10) 529 maxidl = 0x10; 530 531 /* Character length programmed into the mode register is the 532 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, 533 * 1 or 2 stop bits, minus 1. 534 * The value 'bits' counts this for us. 535 */ 536 cval = 0; 537 scval = 0; 538 539 /* byte size */ 540 switch (termios->c_cflag & CSIZE) { 541 case CS5: 542 bits = 5; 543 break; 544 case CS6: 545 bits = 6; 546 break; 547 case CS7: 548 bits = 7; 549 break; 550 case CS8: 551 bits = 8; 552 break; 553 /* Never happens, but GCC is too dumb to figure it out */ 554 default: 555 bits = 8; 556 break; 557 } 558 sbits = bits - 5; 559 560 if (termios->c_cflag & CSTOPB) { 561 cval |= SMCMR_SL; /* Two stops */ 562 scval |= SCU_PSMR_SL; 563 bits++; 564 } 565 566 if (termios->c_cflag & PARENB) { 567 cval |= SMCMR_PEN; 568 scval |= SCU_PSMR_PEN; 569 bits++; 570 if (!(termios->c_cflag & PARODD)) { 571 cval |= SMCMR_PM_EVEN; 572 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); 573 } 574 } 575 576 /* 577 * Update the timeout 578 */ 579 uart_update_timeout(port, termios->c_cflag, baud); 580 581 /* 582 * Set up parity check flag 583 */ 584#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) 585 586 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); 587 if (termios->c_iflag & INPCK) 588 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 589 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) 590 port->read_status_mask |= BD_SC_BR; 591 592 /* 593 * Characters to ignore 594 */ 595 port->ignore_status_mask = 0; 596 if (termios->c_iflag & IGNPAR) 597 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 598 if (termios->c_iflag & IGNBRK) { 599 port->ignore_status_mask |= BD_SC_BR; 600 /* 601 * If we're ignore parity and break indicators, ignore 602 * overruns too. (For real raw support). 603 */ 604 if (termios->c_iflag & IGNPAR) 605 port->ignore_status_mask |= BD_SC_OV; 606 } 607 /* 608 * !!! ignore all characters if CREAD is not set 609 */ 610 if ((termios->c_cflag & CREAD) == 0) 611 port->read_status_mask &= ~BD_SC_EMPTY; 612 613 spin_lock_irqsave(&port->lock, flags); 614 615 /* Start bit has not been added (so don't, because we would just 616 * subtract it later), and we need to add one for the number of 617 * stops bits (there is always at least one). 618 */ 619 bits++; 620 if (IS_SMC(pinfo)) { 621 /* 622 * MRBLR can be changed while an SMC/SCC is operating only 623 * if it is done in a single bus cycle with one 16-bit move 624 * (not two 8-bit bus cycles back-to-back). This occurs when 625 * the cp shifts control to the next RxBD, so the change does 626 * not take effect immediately. To guarantee the exact RxBD 627 * on which the change occurs, change MRBLR only while the 628 * SMC/SCC receiver is disabled. 629 */ 630 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); 631 out_be16(&pinfo->smcup->smc_maxidl, maxidl); 632 633 /* Set the mode register. We want to keep a copy of the 634 * enables, because we want to put them back if they were 635 * present. 636 */ 637 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); 638 /* Output in *one* operation, so we don't interrupt RX/TX if they 639 * were already enabled. */ 640 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | 641 SMCMR_SM_UART | prev_mode); 642 } else { 643 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 644 out_be16(&pinfo->sccup->scc_maxidl, maxidl); 645 out_be16(&sccp->scc_psmr, (sbits << 12) | scval); 646 } 647 648 if (pinfo->clk) 649 clk_set_rate(pinfo->clk, baud); 650 else 651 cpm_set_brg(pinfo->brg - 1, baud); 652 spin_unlock_irqrestore(&port->lock, flags); 653} 654 655static const char *cpm_uart_type(struct uart_port *port) 656{ 657 pr_debug("CPM uart[%d]:uart_type\n", port->line); 658 659 return port->type == PORT_CPM ? "CPM UART" : NULL; 660} 661 662/* 663 * verify the new serial_struct (for TIOCSSERIAL). 664 */ 665static int cpm_uart_verify_port(struct uart_port *port, 666 struct serial_struct *ser) 667{ 668 int ret = 0; 669 670 pr_debug("CPM uart[%d]:verify_port\n", port->line); 671 672 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 673 ret = -EINVAL; 674 if (ser->irq < 0 || ser->irq >= nr_irqs) 675 ret = -EINVAL; 676 if (ser->baud_base < 9600) 677 ret = -EINVAL; 678 return ret; 679} 680 681/* 682 * Transmit characters, refill buffer descriptor, if possible 683 */ 684static int cpm_uart_tx_pump(struct uart_port *port) 685{ 686 cbd_t __iomem *bdp; 687 u8 *p; 688 int count; 689 struct uart_cpm_port *pinfo = 690 container_of(port, struct uart_cpm_port, port); 691 struct circ_buf *xmit = &port->state->xmit; 692 693 /* Handle xon/xoff */ 694 if (port->x_char) { 695 /* Pick next descriptor and fill from buffer */ 696 bdp = pinfo->tx_cur; 697 698 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 699 700 *p++ = port->x_char; 701 702 out_be16(&bdp->cbd_datlen, 1); 703 setbits16(&bdp->cbd_sc, BD_SC_READY); 704 /* Get next BD. */ 705 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 706 bdp = pinfo->tx_bd_base; 707 else 708 bdp++; 709 pinfo->tx_cur = bdp; 710 711 port->icount.tx++; 712 port->x_char = 0; 713 return 1; 714 } 715 716 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 717 cpm_uart_stop_tx(port); 718 return 0; 719 } 720 721 /* Pick next descriptor and fill from buffer */ 722 bdp = pinfo->tx_cur; 723 724 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && 725 xmit->tail != xmit->head) { 726 count = 0; 727 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 728 while (count < pinfo->tx_fifosize) { 729 *p++ = xmit->buf[xmit->tail]; 730 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 731 port->icount.tx++; 732 count++; 733 if (xmit->head == xmit->tail) 734 break; 735 } 736 out_be16(&bdp->cbd_datlen, count); 737 setbits16(&bdp->cbd_sc, BD_SC_READY); 738 /* Get next BD. */ 739 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 740 bdp = pinfo->tx_bd_base; 741 else 742 bdp++; 743 } 744 pinfo->tx_cur = bdp; 745 746 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 747 uart_write_wakeup(port); 748 749 if (uart_circ_empty(xmit)) { 750 cpm_uart_stop_tx(port); 751 return 0; 752 } 753 754 return 1; 755} 756 757/* 758 * init buffer descriptors 759 */ 760static void cpm_uart_initbd(struct uart_cpm_port *pinfo) 761{ 762 int i; 763 u8 *mem_addr; 764 cbd_t __iomem *bdp; 765 766 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); 767 768 /* Set the physical address of the host memory 769 * buffers in the buffer descriptors, and the 770 * virtual address for us to work with. 771 */ 772 mem_addr = pinfo->mem_addr; 773 bdp = pinfo->rx_cur = pinfo->rx_bd_base; 774 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { 775 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 776 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 777 mem_addr += pinfo->rx_fifosize; 778 } 779 780 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 781 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 782 783 /* Set the physical address of the host memory 784 * buffers in the buffer descriptors, and the 785 * virtual address for us to work with. 786 */ 787 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); 788 bdp = pinfo->tx_cur = pinfo->tx_bd_base; 789 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { 790 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 791 out_be16(&bdp->cbd_sc, BD_SC_INTRPT); 792 mem_addr += pinfo->tx_fifosize; 793 } 794 795 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 796 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); 797} 798 799static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) 800{ 801 scc_t __iomem *scp; 802 scc_uart_t __iomem *sup; 803 804 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); 805 806 scp = pinfo->sccp; 807 sup = pinfo->sccup; 808 809 /* Store address */ 810 out_be16(&pinfo->sccup->scc_genscc.scc_rbase, 811 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 812 out_be16(&pinfo->sccup->scc_genscc.scc_tbase, 813 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 814 815 /* Set up the uart parameters in the 816 * parameter ram. 817 */ 818 819 cpm_set_scc_fcr(sup); 820 821 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 822 out_be16(&sup->scc_maxidl, 0x10); 823 out_be16(&sup->scc_brkcr, 1); 824 out_be16(&sup->scc_parec, 0); 825 out_be16(&sup->scc_frmec, 0); 826 out_be16(&sup->scc_nosec, 0); 827 out_be16(&sup->scc_brkec, 0); 828 out_be16(&sup->scc_uaddr1, 0); 829 out_be16(&sup->scc_uaddr2, 0); 830 out_be16(&sup->scc_toseq, 0); 831 out_be16(&sup->scc_char1, 0x8000); 832 out_be16(&sup->scc_char2, 0x8000); 833 out_be16(&sup->scc_char3, 0x8000); 834 out_be16(&sup->scc_char4, 0x8000); 835 out_be16(&sup->scc_char5, 0x8000); 836 out_be16(&sup->scc_char6, 0x8000); 837 out_be16(&sup->scc_char7, 0x8000); 838 out_be16(&sup->scc_char8, 0x8000); 839 out_be16(&sup->scc_rccm, 0xc0ff); 840 841 /* Send the CPM an initialize command. 842 */ 843 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 844 845 /* Set UART mode, 8 bit, no parity, one stop. 846 * Enable receive and transmit. 847 */ 848 out_be32(&scp->scc_gsmrh, 0); 849 out_be32(&scp->scc_gsmrl, 850 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); 851 852 /* Enable rx interrupts and clear all pending events. */ 853 out_be16(&scp->scc_sccm, 0); 854 out_be16(&scp->scc_scce, 0xffff); 855 out_be16(&scp->scc_dsr, 0x7e7e); 856 out_be16(&scp->scc_psmr, 0x3000); 857 858 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 859} 860 861static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) 862{ 863 smc_t __iomem *sp; 864 smc_uart_t __iomem *up; 865 866 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); 867 868 sp = pinfo->smcp; 869 up = pinfo->smcup; 870 871 /* Store address */ 872 out_be16(&pinfo->smcup->smc_rbase, 873 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 874 out_be16(&pinfo->smcup->smc_tbase, 875 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 876 877/* 878 * In case SMC1 is being relocated... 879 */ 880#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) 881 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); 882 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); 883 out_be32(&up->smc_rstate, 0); 884 out_be32(&up->smc_tstate, 0); 885 out_be16(&up->smc_brkcr, 1); /* number of break chars */ 886 out_be16(&up->smc_brkec, 0); 887#endif 888 889 /* Set up the uart parameters in the 890 * parameter ram. 891 */ 892 cpm_set_smc_fcr(up); 893 894 /* Using idle character time requires some additional tuning. */ 895 out_be16(&up->smc_mrblr, pinfo->rx_fifosize); 896 out_be16(&up->smc_maxidl, 0x10); 897 out_be16(&up->smc_brklen, 0); 898 out_be16(&up->smc_brkec, 0); 899 out_be16(&up->smc_brkcr, 1); 900 901 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 902 903 /* Set UART mode, 8 bit, no parity, one stop. 904 * Enable receive and transmit. 905 */ 906 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); 907 908 /* Enable only rx interrupts clear all pending events. */ 909 out_8(&sp->smc_smcm, 0); 910 out_8(&sp->smc_smce, 0xff); 911 912 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 913} 914 915/* 916 * Initialize port. This is called from early_console stuff 917 * so we have to be careful here ! 918 */ 919static int cpm_uart_request_port(struct uart_port *port) 920{ 921 struct uart_cpm_port *pinfo = 922 container_of(port, struct uart_cpm_port, port); 923 int ret; 924 925 pr_debug("CPM uart[%d]:request port\n", port->line); 926 927 if (pinfo->flags & FLAG_CONSOLE) 928 return 0; 929 930 if (IS_SMC(pinfo)) { 931 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 932 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 933 } else { 934 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 935 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 936 } 937 938 ret = cpm_uart_allocbuf(pinfo, 0); 939 940 if (ret) 941 return ret; 942 943 cpm_uart_initbd(pinfo); 944 if (IS_SMC(pinfo)) 945 cpm_uart_init_smc(pinfo); 946 else 947 cpm_uart_init_scc(pinfo); 948 949 return 0; 950} 951 952static void cpm_uart_release_port(struct uart_port *port) 953{ 954 struct uart_cpm_port *pinfo = 955 container_of(port, struct uart_cpm_port, port); 956 957 if (!(pinfo->flags & FLAG_CONSOLE)) 958 cpm_uart_freebuf(pinfo); 959} 960 961/* 962 * Configure/autoconfigure the port. 963 */ 964static void cpm_uart_config_port(struct uart_port *port, int flags) 965{ 966 pr_debug("CPM uart[%d]:config_port\n", port->line); 967 968 if (flags & UART_CONFIG_TYPE) { 969 port->type = PORT_CPM; 970 cpm_uart_request_port(port); 971 } 972} 973 974#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) 975/* 976 * Write a string to the serial port 977 * Note that this is called with interrupts already disabled 978 */ 979static void cpm_uart_early_write(struct uart_cpm_port *pinfo, 980 const char *string, u_int count, bool handle_linefeed) 981{ 982 unsigned int i; 983 cbd_t __iomem *bdp, *bdbase; 984 unsigned char *cpm_outp_addr; 985 986 /* Get the address of the host memory buffer. 987 */ 988 bdp = pinfo->tx_cur; 989 bdbase = pinfo->tx_bd_base; 990 991 /* 992 * Now, do each character. This is not as bad as it looks 993 * since this is a holding FIFO and not a transmitting FIFO. 994 * We could add the complexity of filling the entire transmit 995 * buffer, but we would just wait longer between accesses...... 996 */ 997 for (i = 0; i < count; i++, string++) { 998 /* Wait for transmitter fifo to empty. 999 * Ready indicates output is ready, and xmt is doing 1000 * that, not that it is ready for us to send. 1001 */ 1002 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1003 ; 1004 1005 /* Send the character out. 1006 * If the buffer address is in the CPM DPRAM, don't 1007 * convert it. 1008 */ 1009 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1010 pinfo); 1011 *cpm_outp_addr = *string; 1012 1013 out_be16(&bdp->cbd_datlen, 1); 1014 setbits16(&bdp->cbd_sc, BD_SC_READY); 1015 1016 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1017 bdp = bdbase; 1018 else 1019 bdp++; 1020 1021 /* if a LF, also do CR... */ 1022 if (handle_linefeed && *string == 10) { 1023 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1024 ; 1025 1026 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1027 pinfo); 1028 *cpm_outp_addr = 13; 1029 1030 out_be16(&bdp->cbd_datlen, 1); 1031 setbits16(&bdp->cbd_sc, BD_SC_READY); 1032 1033 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1034 bdp = bdbase; 1035 else 1036 bdp++; 1037 } 1038 } 1039 1040 /* 1041 * Finally, Wait for transmitter & holding register to empty 1042 * and restore the IER 1043 */ 1044 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1045 ; 1046 1047 pinfo->tx_cur = bdp; 1048} 1049#endif 1050 1051#ifdef CONFIG_CONSOLE_POLL 1052/* Serial polling routines for writing and reading from the uart while 1053 * in an interrupt or debug context. 1054 */ 1055 1056#define GDB_BUF_SIZE 512 /* power of 2, please */ 1057 1058static char poll_buf[GDB_BUF_SIZE]; 1059static char *pollp; 1060static int poll_chars; 1061 1062static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) 1063{ 1064 u_char c, *cp; 1065 volatile cbd_t *bdp; 1066 int i; 1067 1068 /* Get the address of the host memory buffer. 1069 */ 1070 bdp = pinfo->rx_cur; 1071 while (bdp->cbd_sc & BD_SC_EMPTY) 1072 ; 1073 1074 /* If the buffer address is in the CPM DPRAM, don't 1075 * convert it. 1076 */ 1077 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); 1078 1079 if (obuf) { 1080 i = c = bdp->cbd_datlen; 1081 while (i-- > 0) 1082 *obuf++ = *cp++; 1083 } else 1084 c = *cp; 1085 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); 1086 bdp->cbd_sc |= BD_SC_EMPTY; 1087 1088 if (bdp->cbd_sc & BD_SC_WRAP) 1089 bdp = pinfo->rx_bd_base; 1090 else 1091 bdp++; 1092 pinfo->rx_cur = (cbd_t *)bdp; 1093 1094 return (int)c; 1095} 1096 1097static int cpm_get_poll_char(struct uart_port *port) 1098{ 1099 struct uart_cpm_port *pinfo = 1100 container_of(port, struct uart_cpm_port, port); 1101 1102 if (!serial_polled) { 1103 serial_polled = 1; 1104 poll_chars = 0; 1105 } 1106 if (poll_chars <= 0) { 1107 poll_chars = poll_wait_key(poll_buf, pinfo); 1108 pollp = poll_buf; 1109 } 1110 poll_chars--; 1111 return *pollp++; 1112} 1113 1114static void cpm_put_poll_char(struct uart_port *port, 1115 unsigned char c) 1116{ 1117 struct uart_cpm_port *pinfo = 1118 container_of(port, struct uart_cpm_port, port); 1119 static char ch[2]; 1120 1121 ch[0] = (char)c; 1122 cpm_uart_early_write(pinfo, ch, 1, false); 1123} 1124#endif /* CONFIG_CONSOLE_POLL */ 1125 1126static struct uart_ops cpm_uart_pops = { 1127 .tx_empty = cpm_uart_tx_empty, 1128 .set_mctrl = cpm_uart_set_mctrl, 1129 .get_mctrl = cpm_uart_get_mctrl, 1130 .stop_tx = cpm_uart_stop_tx, 1131 .start_tx = cpm_uart_start_tx, 1132 .stop_rx = cpm_uart_stop_rx, 1133 .break_ctl = cpm_uart_break_ctl, 1134 .startup = cpm_uart_startup, 1135 .shutdown = cpm_uart_shutdown, 1136 .set_termios = cpm_uart_set_termios, 1137 .type = cpm_uart_type, 1138 .release_port = cpm_uart_release_port, 1139 .request_port = cpm_uart_request_port, 1140 .config_port = cpm_uart_config_port, 1141 .verify_port = cpm_uart_verify_port, 1142#ifdef CONFIG_CONSOLE_POLL 1143 .poll_get_char = cpm_get_poll_char, 1144 .poll_put_char = cpm_put_poll_char, 1145#endif 1146}; 1147 1148struct uart_cpm_port cpm_uart_ports[UART_NR]; 1149 1150static int cpm_uart_init_port(struct device_node *np, 1151 struct uart_cpm_port *pinfo) 1152{ 1153 const u32 *data; 1154 void __iomem *mem, *pram; 1155 int len; 1156 int ret; 1157 int i; 1158 1159 data = of_get_property(np, "clock", NULL); 1160 if (data) { 1161 struct clk *clk = clk_get(NULL, (const char*)data); 1162 if (!IS_ERR(clk)) 1163 pinfo->clk = clk; 1164 } 1165 if (!pinfo->clk) { 1166 data = of_get_property(np, "fsl,cpm-brg", &len); 1167 if (!data || len != 4) { 1168 printk(KERN_ERR "CPM UART %s has no/invalid " 1169 "fsl,cpm-brg property.\n", np->name); 1170 return -EINVAL; 1171 } 1172 pinfo->brg = *data; 1173 } 1174 1175 data = of_get_property(np, "fsl,cpm-command", &len); 1176 if (!data || len != 4) { 1177 printk(KERN_ERR "CPM UART %s has no/invalid " 1178 "fsl,cpm-command property.\n", np->name); 1179 return -EINVAL; 1180 } 1181 pinfo->command = *data; 1182 1183 mem = of_iomap(np, 0); 1184 if (!mem) 1185 return -ENOMEM; 1186 1187 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || 1188 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { 1189 pinfo->sccp = mem; 1190 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); 1191 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || 1192 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { 1193 pinfo->flags |= FLAG_SMC; 1194 pinfo->smcp = mem; 1195 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); 1196 } else { 1197 ret = -ENODEV; 1198 goto out_mem; 1199 } 1200 1201 if (!pram) { 1202 ret = -ENOMEM; 1203 goto out_mem; 1204 } 1205 1206 pinfo->tx_nrfifos = TX_NUM_FIFO; 1207 pinfo->tx_fifosize = TX_BUF_SIZE; 1208 pinfo->rx_nrfifos = RX_NUM_FIFO; 1209 pinfo->rx_fifosize = RX_BUF_SIZE; 1210 1211 pinfo->port.uartclk = ppc_proc_freq; 1212 pinfo->port.mapbase = (unsigned long)mem; 1213 pinfo->port.type = PORT_CPM; 1214 pinfo->port.ops = &cpm_uart_pops, 1215 pinfo->port.iotype = UPIO_MEM; 1216 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; 1217 spin_lock_init(&pinfo->port.lock); 1218 1219 pinfo->port.irq = irq_of_parse_and_map(np, 0); 1220 if (pinfo->port.irq == NO_IRQ) { 1221 ret = -EINVAL; 1222 goto out_pram; 1223 } 1224 1225 for (i = 0; i < NUM_GPIOS; i++) { 1226 int gpio; 1227 1228 pinfo->gpios[i] = -1; 1229 1230 gpio = of_get_gpio(np, i); 1231 1232 if (gpio_is_valid(gpio)) { 1233 ret = gpio_request(gpio, "cpm_uart"); 1234 if (ret) { 1235 pr_err("can't request gpio #%d: %d\n", i, ret); 1236 continue; 1237 } 1238 if (i == GPIO_RTS || i == GPIO_DTR) 1239 ret = gpio_direction_output(gpio, 0); 1240 else 1241 ret = gpio_direction_input(gpio); 1242 if (ret) { 1243 pr_err("can't set direction for gpio #%d: %d\n", 1244 i, ret); 1245 gpio_free(gpio); 1246 continue; 1247 } 1248 pinfo->gpios[i] = gpio; 1249 } 1250 } 1251 1252#ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1253 udbg_putc = NULL; 1254#endif 1255 1256 return cpm_uart_request_port(&pinfo->port); 1257 1258out_pram: 1259 cpm_uart_unmap_pram(pinfo, pram); 1260out_mem: 1261 iounmap(mem); 1262 return ret; 1263} 1264 1265#ifdef CONFIG_SERIAL_CPM_CONSOLE 1266/* 1267 * Print a string to the serial port trying not to disturb 1268 * any possible real use of the port... 1269 * 1270 * Note that this is called with interrupts already disabled 1271 */ 1272static void cpm_uart_console_write(struct console *co, const char *s, 1273 u_int count) 1274{ 1275 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; 1276 unsigned long flags; 1277 int nolock = oops_in_progress; 1278 1279 if (unlikely(nolock)) { 1280 local_irq_save(flags); 1281 } else { 1282 spin_lock_irqsave(&pinfo->port.lock, flags); 1283 } 1284 1285 cpm_uart_early_write(pinfo, s, count, true); 1286 1287 if (unlikely(nolock)) { 1288 local_irq_restore(flags); 1289 } else { 1290 spin_unlock_irqrestore(&pinfo->port.lock, flags); 1291 } 1292} 1293 1294 1295static int __init cpm_uart_console_setup(struct console *co, char *options) 1296{ 1297 int baud = 38400; 1298 int bits = 8; 1299 int parity = 'n'; 1300 int flow = 'n'; 1301 int ret; 1302 struct uart_cpm_port *pinfo; 1303 struct uart_port *port; 1304 1305 struct device_node *np = NULL; 1306 int i = 0; 1307 1308 if (co->index >= UART_NR) { 1309 printk(KERN_ERR "cpm_uart: console index %d too high\n", 1310 co->index); 1311 return -ENODEV; 1312 } 1313 1314 do { 1315 np = of_find_node_by_type(np, "serial"); 1316 if (!np) 1317 return -ENODEV; 1318 1319 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && 1320 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && 1321 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && 1322 !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) 1323 i--; 1324 } while (i++ != co->index); 1325 1326 pinfo = &cpm_uart_ports[co->index]; 1327 1328 pinfo->flags |= FLAG_CONSOLE; 1329 port = &pinfo->port; 1330 1331 ret = cpm_uart_init_port(np, pinfo); 1332 of_node_put(np); 1333 if (ret) 1334 return ret; 1335 1336 if (options) { 1337 uart_parse_options(options, &baud, &parity, &bits, &flow); 1338 } else { 1339 if ((baud = uart_baudrate()) == -1) 1340 baud = 9600; 1341 } 1342 1343 if (IS_SMC(pinfo)) { 1344 out_be16(&pinfo->smcup->smc_brkcr, 0); 1345 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1346 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 1347 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 1348 } else { 1349 out_be16(&pinfo->sccup->scc_brkcr, 0); 1350 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 1351 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 1352 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 1353 } 1354 1355 ret = cpm_uart_allocbuf(pinfo, 1); 1356 1357 if (ret) 1358 return ret; 1359 1360 cpm_uart_initbd(pinfo); 1361 1362 if (IS_SMC(pinfo)) 1363 cpm_uart_init_smc(pinfo); 1364 else 1365 cpm_uart_init_scc(pinfo); 1366 1367 uart_set_options(port, co, baud, parity, bits, flow); 1368 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 1369 1370 return 0; 1371} 1372 1373static struct uart_driver cpm_reg; 1374static struct console cpm_scc_uart_console = { 1375 .name = "ttyCPM", 1376 .write = cpm_uart_console_write, 1377 .device = uart_console_device, 1378 .setup = cpm_uart_console_setup, 1379 .flags = CON_PRINTBUFFER, 1380 .index = -1, 1381 .data = &cpm_reg, 1382}; 1383 1384static int __init cpm_uart_console_init(void) 1385{ 1386 register_console(&cpm_scc_uart_console); 1387 return 0; 1388} 1389 1390console_initcall(cpm_uart_console_init); 1391 1392#define CPM_UART_CONSOLE &cpm_scc_uart_console 1393#else 1394#define CPM_UART_CONSOLE NULL 1395#endif 1396 1397static struct uart_driver cpm_reg = { 1398 .owner = THIS_MODULE, 1399 .driver_name = "ttyCPM", 1400 .dev_name = "ttyCPM", 1401 .major = SERIAL_CPM_MAJOR, 1402 .minor = SERIAL_CPM_MINOR, 1403 .cons = CPM_UART_CONSOLE, 1404 .nr = UART_NR, 1405}; 1406 1407static int probe_index; 1408 1409static int cpm_uart_probe(struct platform_device *ofdev) 1410{ 1411 int index = probe_index++; 1412 struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; 1413 int ret; 1414 1415 pinfo->port.line = index; 1416 1417 if (index >= UART_NR) 1418 return -ENODEV; 1419 1420 platform_set_drvdata(ofdev, pinfo); 1421 1422 /* initialize the device pointer for the port */ 1423 pinfo->port.dev = &ofdev->dev; 1424 1425 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); 1426 if (ret) 1427 return ret; 1428 1429 return uart_add_one_port(&cpm_reg, &pinfo->port); 1430} 1431 1432static int cpm_uart_remove(struct platform_device *ofdev) 1433{ 1434 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); 1435 return uart_remove_one_port(&cpm_reg, &pinfo->port); 1436} 1437 1438static const struct of_device_id cpm_uart_match[] = { 1439 { 1440 .compatible = "fsl,cpm1-smc-uart", 1441 }, 1442 { 1443 .compatible = "fsl,cpm1-scc-uart", 1444 }, 1445 { 1446 .compatible = "fsl,cpm2-smc-uart", 1447 }, 1448 { 1449 .compatible = "fsl,cpm2-scc-uart", 1450 }, 1451 {} 1452}; 1453 1454static struct platform_driver cpm_uart_driver = { 1455 .driver = { 1456 .name = "cpm_uart", 1457 .of_match_table = cpm_uart_match, 1458 }, 1459 .probe = cpm_uart_probe, 1460 .remove = cpm_uart_remove, 1461 }; 1462 1463static int __init cpm_uart_init(void) 1464{ 1465 int ret = uart_register_driver(&cpm_reg); 1466 if (ret) 1467 return ret; 1468 1469 ret = platform_driver_register(&cpm_uart_driver); 1470 if (ret) 1471 uart_unregister_driver(&cpm_reg); 1472 1473 return ret; 1474} 1475 1476static void __exit cpm_uart_exit(void) 1477{ 1478 platform_driver_unregister(&cpm_uart_driver); 1479 uart_unregister_driver(&cpm_reg); 1480} 1481 1482module_init(cpm_uart_init); 1483module_exit(cpm_uart_exit); 1484 1485MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); 1486MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); 1487MODULE_LICENSE("GPL"); 1488MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); 1489