1/* 2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. 3 * 4 * FIXME According to the usermanual the status bits in the status register 5 * are only updated when the peripherals access the FIFO and not when the 6 * CPU access them. So since we use this bits to know when we stop writing 7 * and reading, they may not be updated in-time and a race condition may 8 * exists. But I haven't be able to prove this and I don't care. But if 9 * any problem arises, it might worth checking. The TX/RX FIFO Stats 10 * registers should be used in addition. 11 * Update: Actually, they seem updated ... At least the bits we use. 12 * 13 * 14 * Maintainer : Sylvain Munaut <tnt@246tNt.com> 15 * 16 * Some of the code has been inspired/copied from the 2.4 code written 17 * by Dale Farnsworth <dfarnsworth@mvista.com>. 18 * 19 * Copyright (C) 2008 Freescale Semiconductor Inc. 20 * John Rigby <jrigby@gmail.com> 21 * Added support for MPC5121 22 * Copyright (C) 2006 Secret Lab Technologies Ltd. 23 * Grant Likely <grant.likely@secretlab.ca> 24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> 25 * Copyright (C) 2003 MontaVista, Software, Inc. 26 * 27 * This file is licensed under the terms of the GNU General Public License 28 * version 2. This program is licensed "as is" without any warranty of any 29 * kind, whether express or implied. 30 */ 31 32#undef DEBUG 33 34#include <linux/device.h> 35#include <linux/module.h> 36#include <linux/tty.h> 37#include <linux/tty_flip.h> 38#include <linux/serial.h> 39#include <linux/sysrq.h> 40#include <linux/console.h> 41#include <linux/delay.h> 42#include <linux/io.h> 43#include <linux/of.h> 44#include <linux/of_platform.h> 45#include <linux/clk.h> 46 47#include <asm/mpc52xx.h> 48#include <asm/mpc52xx_psc.h> 49 50#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 51#define SUPPORT_SYSRQ 52#endif 53 54#include <linux/serial_core.h> 55 56 57/* We've been assigned a range on the "Low-density serial ports" major */ 58#define SERIAL_PSC_MAJOR 204 59#define SERIAL_PSC_MINOR 148 60 61 62#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ 63 64 65static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; 66 /* Rem: - We use the read_status_mask as a shadow of 67 * psc->mpc52xx_psc_imr 68 * - It's important that is array is all zero on start as we 69 * use it to know if it's initialized or not ! If it's not sure 70 * it's cleared, then a memset(...,0,...) should be added to 71 * the console_init 72 */ 73 74/* lookup table for matching device nodes to index numbers */ 75static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; 76 77static void mpc52xx_uart_of_enumerate(void); 78 79 80#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) 81 82 83/* Forward declaration of the interruption handling routine */ 84static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); 85static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); 86 87/* ======================================================================== */ 88/* PSC fifo operations for isolating differences between 52xx and 512x */ 89/* ======================================================================== */ 90 91struct psc_ops { 92 void (*fifo_init)(struct uart_port *port); 93 int (*raw_rx_rdy)(struct uart_port *port); 94 int (*raw_tx_rdy)(struct uart_port *port); 95 int (*rx_rdy)(struct uart_port *port); 96 int (*tx_rdy)(struct uart_port *port); 97 int (*tx_empty)(struct uart_port *port); 98 void (*stop_rx)(struct uart_port *port); 99 void (*start_tx)(struct uart_port *port); 100 void (*stop_tx)(struct uart_port *port); 101 void (*rx_clr_irq)(struct uart_port *port); 102 void (*tx_clr_irq)(struct uart_port *port); 103 void (*write_char)(struct uart_port *port, unsigned char c); 104 unsigned char (*read_char)(struct uart_port *port); 105 void (*cw_disable_ints)(struct uart_port *port); 106 void (*cw_restore_ints)(struct uart_port *port); 107 unsigned int (*set_baudrate)(struct uart_port *port, 108 struct ktermios *new, 109 struct ktermios *old); 110 int (*clock_alloc)(struct uart_port *port); 111 void (*clock_relse)(struct uart_port *port); 112 int (*clock)(struct uart_port *port, int enable); 113 int (*fifoc_init)(void); 114 void (*fifoc_uninit)(void); 115 void (*get_irq)(struct uart_port *, struct device_node *); 116 irqreturn_t (*handle_irq)(struct uart_port *port); 117 u16 (*get_status)(struct uart_port *port); 118 u8 (*get_ipcr)(struct uart_port *port); 119 void (*command)(struct uart_port *port, u8 cmd); 120 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2); 121 void (*set_rts)(struct uart_port *port, int state); 122 void (*enable_ms)(struct uart_port *port); 123 void (*set_sicr)(struct uart_port *port, u32 val); 124 void (*set_imr)(struct uart_port *port, u16 val); 125 u8 (*get_mr1)(struct uart_port *port); 126}; 127 128/* setting the prescaler and divisor reg is common for all chips */ 129static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, 130 u16 prescaler, unsigned int divisor) 131{ 132 /* select prescaler */ 133 out_be16(&psc->mpc52xx_psc_clock_select, prescaler); 134 out_8(&psc->ctur, divisor >> 8); 135 out_8(&psc->ctlr, divisor & 0xff); 136} 137 138static u16 mpc52xx_psc_get_status(struct uart_port *port) 139{ 140 return in_be16(&PSC(port)->mpc52xx_psc_status); 141} 142 143static u8 mpc52xx_psc_get_ipcr(struct uart_port *port) 144{ 145 return in_8(&PSC(port)->mpc52xx_psc_ipcr); 146} 147 148static void mpc52xx_psc_command(struct uart_port *port, u8 cmd) 149{ 150 out_8(&PSC(port)->command, cmd); 151} 152 153static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 154{ 155 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 156 out_8(&PSC(port)->mode, mr1); 157 out_8(&PSC(port)->mode, mr2); 158} 159 160static void mpc52xx_psc_set_rts(struct uart_port *port, int state) 161{ 162 if (state) 163 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); 164 else 165 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); 166} 167 168static void mpc52xx_psc_enable_ms(struct uart_port *port) 169{ 170 struct mpc52xx_psc __iomem *psc = PSC(port); 171 172 /* clear D_*-bits by reading them */ 173 in_8(&psc->mpc52xx_psc_ipcr); 174 /* enable CTS and DCD as IPC interrupts */ 175 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 176 177 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 178 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 179} 180 181static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) 182{ 183 out_be32(&PSC(port)->sicr, val); 184} 185 186static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) 187{ 188 out_be16(&PSC(port)->mpc52xx_psc_imr, val); 189} 190 191static u8 mpc52xx_psc_get_mr1(struct uart_port *port) 192{ 193 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); 194 return in_8(&PSC(port)->mode); 195} 196 197#ifdef CONFIG_PPC_MPC52xx 198#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) 199static void mpc52xx_psc_fifo_init(struct uart_port *port) 200{ 201 struct mpc52xx_psc __iomem *psc = PSC(port); 202 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); 203 204 out_8(&fifo->rfcntl, 0x00); 205 out_be16(&fifo->rfalarm, 0x1ff); 206 out_8(&fifo->tfcntl, 0x07); 207 out_be16(&fifo->tfalarm, 0x80); 208 209 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; 210 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 211} 212 213static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) 214{ 215 return in_be16(&PSC(port)->mpc52xx_psc_status) 216 & MPC52xx_PSC_SR_RXRDY; 217} 218 219static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) 220{ 221 return in_be16(&PSC(port)->mpc52xx_psc_status) 222 & MPC52xx_PSC_SR_TXRDY; 223} 224 225 226static int mpc52xx_psc_rx_rdy(struct uart_port *port) 227{ 228 return in_be16(&PSC(port)->mpc52xx_psc_isr) 229 & port->read_status_mask 230 & MPC52xx_PSC_IMR_RXRDY; 231} 232 233static int mpc52xx_psc_tx_rdy(struct uart_port *port) 234{ 235 return in_be16(&PSC(port)->mpc52xx_psc_isr) 236 & port->read_status_mask 237 & MPC52xx_PSC_IMR_TXRDY; 238} 239 240static int mpc52xx_psc_tx_empty(struct uart_port *port) 241{ 242 return in_be16(&PSC(port)->mpc52xx_psc_status) 243 & MPC52xx_PSC_SR_TXEMP; 244} 245 246static void mpc52xx_psc_start_tx(struct uart_port *port) 247{ 248 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; 249 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 250} 251 252static void mpc52xx_psc_stop_tx(struct uart_port *port) 253{ 254 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; 255 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 256} 257 258static void mpc52xx_psc_stop_rx(struct uart_port *port) 259{ 260 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; 261 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 262} 263 264static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) 265{ 266} 267 268static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) 269{ 270} 271 272static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) 273{ 274 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); 275} 276 277static unsigned char mpc52xx_psc_read_char(struct uart_port *port) 278{ 279 return in_8(&PSC(port)->mpc52xx_psc_buffer_8); 280} 281 282static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) 283{ 284 out_be16(&PSC(port)->mpc52xx_psc_imr, 0); 285} 286 287static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) 288{ 289 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); 290} 291 292static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, 293 struct ktermios *new, 294 struct ktermios *old) 295{ 296 unsigned int baud; 297 unsigned int divisor; 298 299 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ 300 baud = uart_get_baud_rate(port, new, old, 301 port->uartclk / (32 * 0xffff) + 1, 302 port->uartclk / 32); 303 divisor = (port->uartclk + 16 * baud) / (32 * baud); 304 305 /* enable the /32 prescaler and set the divisor */ 306 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 307 return baud; 308} 309 310static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, 311 struct ktermios *new, 312 struct ktermios *old) 313{ 314 unsigned int baud; 315 unsigned int divisor; 316 u16 prescaler; 317 318 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the 319 * ipb freq */ 320 baud = uart_get_baud_rate(port, new, old, 321 port->uartclk / (32 * 0xffff) + 1, 322 port->uartclk / 4); 323 divisor = (port->uartclk + 2 * baud) / (4 * baud); 324 325 /* select the proper prescaler and set the divisor 326 * prefer high prescaler for more tolerance on low baudrates */ 327 if (divisor > 0xffff || baud <= 115200) { 328 divisor = (divisor + 4) / 8; 329 prescaler = 0xdd00; /* /32 */ 330 } else 331 prescaler = 0xff00; /* /4 */ 332 mpc52xx_set_divisor(PSC(port), prescaler, divisor); 333 return baud; 334} 335 336static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) 337{ 338 port->irqflags = 0; 339 port->irq = irq_of_parse_and_map(np, 0); 340} 341 342/* 52xx specific interrupt handler. The caller holds the port lock */ 343static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) 344{ 345 return mpc5xxx_uart_process_int(port); 346} 347 348static struct psc_ops mpc52xx_psc_ops = { 349 .fifo_init = mpc52xx_psc_fifo_init, 350 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 351 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 352 .rx_rdy = mpc52xx_psc_rx_rdy, 353 .tx_rdy = mpc52xx_psc_tx_rdy, 354 .tx_empty = mpc52xx_psc_tx_empty, 355 .stop_rx = mpc52xx_psc_stop_rx, 356 .start_tx = mpc52xx_psc_start_tx, 357 .stop_tx = mpc52xx_psc_stop_tx, 358 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 359 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 360 .write_char = mpc52xx_psc_write_char, 361 .read_char = mpc52xx_psc_read_char, 362 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 363 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 364 .set_baudrate = mpc5200_psc_set_baudrate, 365 .get_irq = mpc52xx_psc_get_irq, 366 .handle_irq = mpc52xx_psc_handle_irq, 367 .get_status = mpc52xx_psc_get_status, 368 .get_ipcr = mpc52xx_psc_get_ipcr, 369 .command = mpc52xx_psc_command, 370 .set_mode = mpc52xx_psc_set_mode, 371 .set_rts = mpc52xx_psc_set_rts, 372 .enable_ms = mpc52xx_psc_enable_ms, 373 .set_sicr = mpc52xx_psc_set_sicr, 374 .set_imr = mpc52xx_psc_set_imr, 375 .get_mr1 = mpc52xx_psc_get_mr1, 376}; 377 378static struct psc_ops mpc5200b_psc_ops = { 379 .fifo_init = mpc52xx_psc_fifo_init, 380 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, 381 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, 382 .rx_rdy = mpc52xx_psc_rx_rdy, 383 .tx_rdy = mpc52xx_psc_tx_rdy, 384 .tx_empty = mpc52xx_psc_tx_empty, 385 .stop_rx = mpc52xx_psc_stop_rx, 386 .start_tx = mpc52xx_psc_start_tx, 387 .stop_tx = mpc52xx_psc_stop_tx, 388 .rx_clr_irq = mpc52xx_psc_rx_clr_irq, 389 .tx_clr_irq = mpc52xx_psc_tx_clr_irq, 390 .write_char = mpc52xx_psc_write_char, 391 .read_char = mpc52xx_psc_read_char, 392 .cw_disable_ints = mpc52xx_psc_cw_disable_ints, 393 .cw_restore_ints = mpc52xx_psc_cw_restore_ints, 394 .set_baudrate = mpc5200b_psc_set_baudrate, 395 .get_irq = mpc52xx_psc_get_irq, 396 .handle_irq = mpc52xx_psc_handle_irq, 397 .get_status = mpc52xx_psc_get_status, 398 .get_ipcr = mpc52xx_psc_get_ipcr, 399 .command = mpc52xx_psc_command, 400 .set_mode = mpc52xx_psc_set_mode, 401 .set_rts = mpc52xx_psc_set_rts, 402 .enable_ms = mpc52xx_psc_enable_ms, 403 .set_sicr = mpc52xx_psc_set_sicr, 404 .set_imr = mpc52xx_psc_set_imr, 405 .get_mr1 = mpc52xx_psc_get_mr1, 406}; 407 408#endif /* CONFIG_MPC52xx */ 409 410#ifdef CONFIG_PPC_MPC512x 411#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) 412 413/* PSC FIFO Controller for mpc512x */ 414struct psc_fifoc { 415 u32 fifoc_cmd; 416 u32 fifoc_int; 417 u32 fifoc_dma; 418 u32 fifoc_axe; 419 u32 fifoc_debug; 420}; 421 422static struct psc_fifoc __iomem *psc_fifoc; 423static unsigned int psc_fifoc_irq; 424static struct clk *psc_fifoc_clk; 425 426static void mpc512x_psc_fifo_init(struct uart_port *port) 427{ 428 /* /32 prescaler */ 429 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); 430 431 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 432 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 433 out_be32(&FIFO_512x(port)->txalarm, 1); 434 out_be32(&FIFO_512x(port)->tximr, 0); 435 436 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 437 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 438 out_be32(&FIFO_512x(port)->rxalarm, 1); 439 out_be32(&FIFO_512x(port)->rximr, 0); 440 441 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); 442 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); 443} 444 445static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) 446{ 447 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 448} 449 450static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) 451{ 452 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); 453} 454 455static int mpc512x_psc_rx_rdy(struct uart_port *port) 456{ 457 return in_be32(&FIFO_512x(port)->rxsr) 458 & in_be32(&FIFO_512x(port)->rximr) 459 & MPC512x_PSC_FIFO_ALARM; 460} 461 462static int mpc512x_psc_tx_rdy(struct uart_port *port) 463{ 464 return in_be32(&FIFO_512x(port)->txsr) 465 & in_be32(&FIFO_512x(port)->tximr) 466 & MPC512x_PSC_FIFO_ALARM; 467} 468 469static int mpc512x_psc_tx_empty(struct uart_port *port) 470{ 471 return in_be32(&FIFO_512x(port)->txsr) 472 & MPC512x_PSC_FIFO_EMPTY; 473} 474 475static void mpc512x_psc_stop_rx(struct uart_port *port) 476{ 477 unsigned long rx_fifo_imr; 478 479 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); 480 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 481 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); 482} 483 484static void mpc512x_psc_start_tx(struct uart_port *port) 485{ 486 unsigned long tx_fifo_imr; 487 488 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 489 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 490 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 491} 492 493static void mpc512x_psc_stop_tx(struct uart_port *port) 494{ 495 unsigned long tx_fifo_imr; 496 497 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); 498 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 499 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); 500} 501 502static void mpc512x_psc_rx_clr_irq(struct uart_port *port) 503{ 504 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); 505} 506 507static void mpc512x_psc_tx_clr_irq(struct uart_port *port) 508{ 509 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); 510} 511 512static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) 513{ 514 out_8(&FIFO_512x(port)->txdata_8, c); 515} 516 517static unsigned char mpc512x_psc_read_char(struct uart_port *port) 518{ 519 return in_8(&FIFO_512x(port)->rxdata_8); 520} 521 522static void mpc512x_psc_cw_disable_ints(struct uart_port *port) 523{ 524 port->read_status_mask = 525 in_be32(&FIFO_512x(port)->tximr) << 16 | 526 in_be32(&FIFO_512x(port)->rximr); 527 out_be32(&FIFO_512x(port)->tximr, 0); 528 out_be32(&FIFO_512x(port)->rximr, 0); 529} 530 531static void mpc512x_psc_cw_restore_ints(struct uart_port *port) 532{ 533 out_be32(&FIFO_512x(port)->tximr, 534 (port->read_status_mask >> 16) & 0x7f); 535 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); 536} 537 538static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, 539 struct ktermios *new, 540 struct ktermios *old) 541{ 542 unsigned int baud; 543 unsigned int divisor; 544 545 /* 546 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on 547 * pg. 30-10 that the chip supports a /32 and a /10 prescaler. 548 * Furthermore, it states that "After reset, the prescaler by 10 549 * for the UART mode is selected", but the reset register value is 550 * 0x0000 which means a /32 prescaler. This is wrong. 551 * 552 * In reality using /32 prescaler doesn't work, as it is not supported! 553 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", 554 * Chapter 4.1 PSC in UART Mode. 555 * Calculate with a /16 prescaler here. 556 */ 557 558 /* uartclk contains the ips freq */ 559 baud = uart_get_baud_rate(port, new, old, 560 port->uartclk / (16 * 0xffff) + 1, 561 port->uartclk / 16); 562 divisor = (port->uartclk + 8 * baud) / (16 * baud); 563 564 /* enable the /16 prescaler and set the divisor */ 565 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); 566 return baud; 567} 568 569/* Init PSC FIFO Controller */ 570static int __init mpc512x_psc_fifoc_init(void) 571{ 572 int err; 573 struct device_node *np; 574 struct clk *clk; 575 576 /* default error code, potentially overwritten by clock calls */ 577 err = -ENODEV; 578 579 np = of_find_compatible_node(NULL, NULL, 580 "fsl,mpc5121-psc-fifo"); 581 if (!np) { 582 pr_err("%s: Can't find FIFOC node\n", __func__); 583 goto out_err; 584 } 585 586 clk = of_clk_get(np, 0); 587 if (IS_ERR(clk)) { 588 /* backwards compat with device trees that lack clock specs */ 589 clk = clk_get_sys(np->name, "ipg"); 590 } 591 if (IS_ERR(clk)) { 592 pr_err("%s: Can't lookup FIFO clock\n", __func__); 593 err = PTR_ERR(clk); 594 goto out_ofnode_put; 595 } 596 if (clk_prepare_enable(clk)) { 597 pr_err("%s: Can't enable FIFO clock\n", __func__); 598 clk_put(clk); 599 goto out_ofnode_put; 600 } 601 psc_fifoc_clk = clk; 602 603 psc_fifoc = of_iomap(np, 0); 604 if (!psc_fifoc) { 605 pr_err("%s: Can't map FIFOC\n", __func__); 606 goto out_clk_disable; 607 } 608 609 psc_fifoc_irq = irq_of_parse_and_map(np, 0); 610 if (psc_fifoc_irq == 0) { 611 pr_err("%s: Can't get FIFOC irq\n", __func__); 612 goto out_unmap; 613 } 614 615 of_node_put(np); 616 return 0; 617 618out_unmap: 619 iounmap(psc_fifoc); 620out_clk_disable: 621 clk_disable_unprepare(psc_fifoc_clk); 622 clk_put(psc_fifoc_clk); 623out_ofnode_put: 624 of_node_put(np); 625out_err: 626 return err; 627} 628 629static void __exit mpc512x_psc_fifoc_uninit(void) 630{ 631 iounmap(psc_fifoc); 632 633 /* disable the clock, errors are not fatal */ 634 if (psc_fifoc_clk) { 635 clk_disable_unprepare(psc_fifoc_clk); 636 clk_put(psc_fifoc_clk); 637 psc_fifoc_clk = NULL; 638 } 639} 640 641/* 512x specific interrupt handler. The caller holds the port lock */ 642static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) 643{ 644 unsigned long fifoc_int; 645 int psc_num; 646 647 /* Read pending PSC FIFOC interrupts */ 648 fifoc_int = in_be32(&psc_fifoc->fifoc_int); 649 650 /* Check if it is an interrupt for this port */ 651 psc_num = (port->mapbase & 0xf00) >> 8; 652 if (test_bit(psc_num, &fifoc_int) || 653 test_bit(psc_num + 16, &fifoc_int)) 654 return mpc5xxx_uart_process_int(port); 655 656 return IRQ_NONE; 657} 658 659static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM]; 660static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM]; 661 662/* called from within the .request_port() callback (allocation) */ 663static int mpc512x_psc_alloc_clock(struct uart_port *port) 664{ 665 int psc_num; 666 struct clk *clk; 667 int err; 668 669 psc_num = (port->mapbase & 0xf00) >> 8; 670 671 clk = devm_clk_get(port->dev, "mclk"); 672 if (IS_ERR(clk)) { 673 dev_err(port->dev, "Failed to get MCLK!\n"); 674 err = PTR_ERR(clk); 675 goto out_err; 676 } 677 err = clk_prepare_enable(clk); 678 if (err) { 679 dev_err(port->dev, "Failed to enable MCLK!\n"); 680 goto out_err; 681 } 682 psc_mclk_clk[psc_num] = clk; 683 684 clk = devm_clk_get(port->dev, "ipg"); 685 if (IS_ERR(clk)) { 686 dev_err(port->dev, "Failed to get IPG clock!\n"); 687 err = PTR_ERR(clk); 688 goto out_err; 689 } 690 err = clk_prepare_enable(clk); 691 if (err) { 692 dev_err(port->dev, "Failed to enable IPG clock!\n"); 693 goto out_err; 694 } 695 psc_ipg_clk[psc_num] = clk; 696 697 return 0; 698 699out_err: 700 if (psc_mclk_clk[psc_num]) { 701 clk_disable_unprepare(psc_mclk_clk[psc_num]); 702 psc_mclk_clk[psc_num] = NULL; 703 } 704 if (psc_ipg_clk[psc_num]) { 705 clk_disable_unprepare(psc_ipg_clk[psc_num]); 706 psc_ipg_clk[psc_num] = NULL; 707 } 708 return err; 709} 710 711/* called from within the .release_port() callback (release) */ 712static void mpc512x_psc_relse_clock(struct uart_port *port) 713{ 714 int psc_num; 715 struct clk *clk; 716 717 psc_num = (port->mapbase & 0xf00) >> 8; 718 clk = psc_mclk_clk[psc_num]; 719 if (clk) { 720 clk_disable_unprepare(clk); 721 psc_mclk_clk[psc_num] = NULL; 722 } 723 if (psc_ipg_clk[psc_num]) { 724 clk_disable_unprepare(psc_ipg_clk[psc_num]); 725 psc_ipg_clk[psc_num] = NULL; 726 } 727} 728 729/* implementation of the .clock() callback (enable/disable) */ 730static int mpc512x_psc_endis_clock(struct uart_port *port, int enable) 731{ 732 int psc_num; 733 struct clk *psc_clk; 734 int ret; 735 736 if (uart_console(port)) 737 return 0; 738 739 psc_num = (port->mapbase & 0xf00) >> 8; 740 psc_clk = psc_mclk_clk[psc_num]; 741 if (!psc_clk) { 742 dev_err(port->dev, "Failed to get PSC clock entry!\n"); 743 return -ENODEV; 744 } 745 746 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis"); 747 if (enable) { 748 ret = clk_enable(psc_clk); 749 if (ret) 750 dev_err(port->dev, "Failed to enable MCLK!\n"); 751 return ret; 752 } else { 753 clk_disable(psc_clk); 754 return 0; 755 } 756} 757 758static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) 759{ 760 port->irqflags = IRQF_SHARED; 761 port->irq = psc_fifoc_irq; 762} 763#endif 764 765#ifdef CONFIG_PPC_MPC512x 766 767#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase)) 768#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1)) 769 770static void mpc5125_psc_fifo_init(struct uart_port *port) 771{ 772 /* /32 prescaler */ 773 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd); 774 775 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); 776 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 777 out_be32(&FIFO_5125(port)->txalarm, 1); 778 out_be32(&FIFO_5125(port)->tximr, 0); 779 780 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); 781 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); 782 out_be32(&FIFO_5125(port)->rxalarm, 1); 783 out_be32(&FIFO_5125(port)->rximr, 0); 784 785 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM); 786 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM); 787} 788 789static int mpc5125_psc_raw_rx_rdy(struct uart_port *port) 790{ 791 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); 792} 793 794static int mpc5125_psc_raw_tx_rdy(struct uart_port *port) 795{ 796 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); 797} 798 799static int mpc5125_psc_rx_rdy(struct uart_port *port) 800{ 801 return in_be32(&FIFO_5125(port)->rxsr) & 802 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM; 803} 804 805static int mpc5125_psc_tx_rdy(struct uart_port *port) 806{ 807 return in_be32(&FIFO_5125(port)->txsr) & 808 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM; 809} 810 811static int mpc5125_psc_tx_empty(struct uart_port *port) 812{ 813 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; 814} 815 816static void mpc5125_psc_stop_rx(struct uart_port *port) 817{ 818 unsigned long rx_fifo_imr; 819 820 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr); 821 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 822 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr); 823} 824 825static void mpc5125_psc_start_tx(struct uart_port *port) 826{ 827 unsigned long tx_fifo_imr; 828 829 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 830 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; 831 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 832} 833 834static void mpc5125_psc_stop_tx(struct uart_port *port) 835{ 836 unsigned long tx_fifo_imr; 837 838 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); 839 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; 840 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); 841} 842 843static void mpc5125_psc_rx_clr_irq(struct uart_port *port) 844{ 845 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr)); 846} 847 848static void mpc5125_psc_tx_clr_irq(struct uart_port *port) 849{ 850 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr)); 851} 852 853static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c) 854{ 855 out_8(&FIFO_5125(port)->txdata_8, c); 856} 857 858static unsigned char mpc5125_psc_read_char(struct uart_port *port) 859{ 860 return in_8(&FIFO_5125(port)->rxdata_8); 861} 862 863static void mpc5125_psc_cw_disable_ints(struct uart_port *port) 864{ 865 port->read_status_mask = 866 in_be32(&FIFO_5125(port)->tximr) << 16 | 867 in_be32(&FIFO_5125(port)->rximr); 868 out_be32(&FIFO_5125(port)->tximr, 0); 869 out_be32(&FIFO_5125(port)->rximr, 0); 870} 871 872static void mpc5125_psc_cw_restore_ints(struct uart_port *port) 873{ 874 out_be32(&FIFO_5125(port)->tximr, 875 (port->read_status_mask >> 16) & 0x7f); 876 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f); 877} 878 879static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, 880 u8 prescaler, unsigned int divisor) 881{ 882 /* select prescaler */ 883 out_8(&psc->mpc52xx_psc_clock_select, prescaler); 884 out_8(&psc->ctur, divisor >> 8); 885 out_8(&psc->ctlr, divisor & 0xff); 886} 887 888static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port, 889 struct ktermios *new, 890 struct ktermios *old) 891{ 892 unsigned int baud; 893 unsigned int divisor; 894 895 /* 896 * Calculate with a /16 prescaler here. 897 */ 898 899 /* uartclk contains the ips freq */ 900 baud = uart_get_baud_rate(port, new, old, 901 port->uartclk / (16 * 0xffff) + 1, 902 port->uartclk / 16); 903 divisor = (port->uartclk + 8 * baud) / (16 * baud); 904 905 /* enable the /16 prescaler and set the divisor */ 906 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); 907 return baud; 908} 909 910/* 911 * MPC5125 have compatible PSC FIFO Controller. 912 * Special init not needed. 913 */ 914static u16 mpc5125_psc_get_status(struct uart_port *port) 915{ 916 return in_be16(&PSC_5125(port)->mpc52xx_psc_status); 917} 918 919static u8 mpc5125_psc_get_ipcr(struct uart_port *port) 920{ 921 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr); 922} 923 924static void mpc5125_psc_command(struct uart_port *port, u8 cmd) 925{ 926 out_8(&PSC_5125(port)->command, cmd); 927} 928 929static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) 930{ 931 out_8(&PSC_5125(port)->mr1, mr1); 932 out_8(&PSC_5125(port)->mr2, mr2); 933} 934 935static void mpc5125_psc_set_rts(struct uart_port *port, int state) 936{ 937 if (state & TIOCM_RTS) 938 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); 939 else 940 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS); 941} 942 943static void mpc5125_psc_enable_ms(struct uart_port *port) 944{ 945 struct mpc5125_psc __iomem *psc = PSC_5125(port); 946 947 /* clear D_*-bits by reading them */ 948 in_8(&psc->mpc52xx_psc_ipcr); 949 /* enable CTS and DCD as IPC interrupts */ 950 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); 951 952 port->read_status_mask |= MPC52xx_PSC_IMR_IPC; 953 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); 954} 955 956static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) 957{ 958 out_be32(&PSC_5125(port)->sicr, val); 959} 960 961static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) 962{ 963 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); 964} 965 966static u8 mpc5125_psc_get_mr1(struct uart_port *port) 967{ 968 return in_8(&PSC_5125(port)->mr1); 969} 970 971static struct psc_ops mpc5125_psc_ops = { 972 .fifo_init = mpc5125_psc_fifo_init, 973 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy, 974 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy, 975 .rx_rdy = mpc5125_psc_rx_rdy, 976 .tx_rdy = mpc5125_psc_tx_rdy, 977 .tx_empty = mpc5125_psc_tx_empty, 978 .stop_rx = mpc5125_psc_stop_rx, 979 .start_tx = mpc5125_psc_start_tx, 980 .stop_tx = mpc5125_psc_stop_tx, 981 .rx_clr_irq = mpc5125_psc_rx_clr_irq, 982 .tx_clr_irq = mpc5125_psc_tx_clr_irq, 983 .write_char = mpc5125_psc_write_char, 984 .read_char = mpc5125_psc_read_char, 985 .cw_disable_ints = mpc5125_psc_cw_disable_ints, 986 .cw_restore_ints = mpc5125_psc_cw_restore_ints, 987 .set_baudrate = mpc5125_psc_set_baudrate, 988 .clock_alloc = mpc512x_psc_alloc_clock, 989 .clock_relse = mpc512x_psc_relse_clock, 990 .clock = mpc512x_psc_endis_clock, 991 .fifoc_init = mpc512x_psc_fifoc_init, 992 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 993 .get_irq = mpc512x_psc_get_irq, 994 .handle_irq = mpc512x_psc_handle_irq, 995 .get_status = mpc5125_psc_get_status, 996 .get_ipcr = mpc5125_psc_get_ipcr, 997 .command = mpc5125_psc_command, 998 .set_mode = mpc5125_psc_set_mode, 999 .set_rts = mpc5125_psc_set_rts, 1000 .enable_ms = mpc5125_psc_enable_ms, 1001 .set_sicr = mpc5125_psc_set_sicr, 1002 .set_imr = mpc5125_psc_set_imr, 1003 .get_mr1 = mpc5125_psc_get_mr1, 1004}; 1005 1006static struct psc_ops mpc512x_psc_ops = { 1007 .fifo_init = mpc512x_psc_fifo_init, 1008 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, 1009 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, 1010 .rx_rdy = mpc512x_psc_rx_rdy, 1011 .tx_rdy = mpc512x_psc_tx_rdy, 1012 .tx_empty = mpc512x_psc_tx_empty, 1013 .stop_rx = mpc512x_psc_stop_rx, 1014 .start_tx = mpc512x_psc_start_tx, 1015 .stop_tx = mpc512x_psc_stop_tx, 1016 .rx_clr_irq = mpc512x_psc_rx_clr_irq, 1017 .tx_clr_irq = mpc512x_psc_tx_clr_irq, 1018 .write_char = mpc512x_psc_write_char, 1019 .read_char = mpc512x_psc_read_char, 1020 .cw_disable_ints = mpc512x_psc_cw_disable_ints, 1021 .cw_restore_ints = mpc512x_psc_cw_restore_ints, 1022 .set_baudrate = mpc512x_psc_set_baudrate, 1023 .clock_alloc = mpc512x_psc_alloc_clock, 1024 .clock_relse = mpc512x_psc_relse_clock, 1025 .clock = mpc512x_psc_endis_clock, 1026 .fifoc_init = mpc512x_psc_fifoc_init, 1027 .fifoc_uninit = mpc512x_psc_fifoc_uninit, 1028 .get_irq = mpc512x_psc_get_irq, 1029 .handle_irq = mpc512x_psc_handle_irq, 1030 .get_status = mpc52xx_psc_get_status, 1031 .get_ipcr = mpc52xx_psc_get_ipcr, 1032 .command = mpc52xx_psc_command, 1033 .set_mode = mpc52xx_psc_set_mode, 1034 .set_rts = mpc52xx_psc_set_rts, 1035 .enable_ms = mpc52xx_psc_enable_ms, 1036 .set_sicr = mpc52xx_psc_set_sicr, 1037 .set_imr = mpc52xx_psc_set_imr, 1038 .get_mr1 = mpc52xx_psc_get_mr1, 1039}; 1040#endif /* CONFIG_PPC_MPC512x */ 1041 1042 1043static const struct psc_ops *psc_ops; 1044 1045/* ======================================================================== */ 1046/* UART operations */ 1047/* ======================================================================== */ 1048 1049static unsigned int 1050mpc52xx_uart_tx_empty(struct uart_port *port) 1051{ 1052 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; 1053} 1054 1055static void 1056mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1057{ 1058 psc_ops->set_rts(port, mctrl & TIOCM_RTS); 1059} 1060 1061static unsigned int 1062mpc52xx_uart_get_mctrl(struct uart_port *port) 1063{ 1064 unsigned int ret = TIOCM_DSR; 1065 u8 status = psc_ops->get_ipcr(port); 1066 1067 if (!(status & MPC52xx_PSC_CTS)) 1068 ret |= TIOCM_CTS; 1069 if (!(status & MPC52xx_PSC_DCD)) 1070 ret |= TIOCM_CAR; 1071 1072 return ret; 1073} 1074 1075static void 1076mpc52xx_uart_stop_tx(struct uart_port *port) 1077{ 1078 /* port->lock taken by caller */ 1079 psc_ops->stop_tx(port); 1080} 1081 1082static void 1083mpc52xx_uart_start_tx(struct uart_port *port) 1084{ 1085 /* port->lock taken by caller */ 1086 psc_ops->start_tx(port); 1087} 1088 1089static void 1090mpc52xx_uart_stop_rx(struct uart_port *port) 1091{ 1092 /* port->lock taken by caller */ 1093 psc_ops->stop_rx(port); 1094} 1095 1096static void 1097mpc52xx_uart_enable_ms(struct uart_port *port) 1098{ 1099 psc_ops->enable_ms(port); 1100} 1101 1102static void 1103mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) 1104{ 1105 unsigned long flags; 1106 spin_lock_irqsave(&port->lock, flags); 1107 1108 if (ctl == -1) 1109 psc_ops->command(port, MPC52xx_PSC_START_BRK); 1110 else 1111 psc_ops->command(port, MPC52xx_PSC_STOP_BRK); 1112 1113 spin_unlock_irqrestore(&port->lock, flags); 1114} 1115 1116static int 1117mpc52xx_uart_startup(struct uart_port *port) 1118{ 1119 int ret; 1120 1121 if (psc_ops->clock) { 1122 ret = psc_ops->clock(port, 1); 1123 if (ret) 1124 return ret; 1125 } 1126 1127 /* Request IRQ */ 1128 ret = request_irq(port->irq, mpc52xx_uart_int, 1129 port->irqflags, "mpc52xx_psc_uart", port); 1130 if (ret) 1131 return ret; 1132 1133 /* Reset/activate the port, clear and enable interrupts */ 1134 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1135 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1136 1137 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */ 1138 1139 psc_ops->fifo_init(port); 1140 1141 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1142 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1143 1144 return 0; 1145} 1146 1147static void 1148mpc52xx_uart_shutdown(struct uart_port *port) 1149{ 1150 /* Shut down the port. Leave TX active if on a console port */ 1151 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1152 if (!uart_console(port)) 1153 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1154 1155 port->read_status_mask = 0; 1156 psc_ops->set_imr(port, port->read_status_mask); 1157 1158 if (psc_ops->clock) 1159 psc_ops->clock(port, 0); 1160 1161 /* Disable interrupt */ 1162 psc_ops->cw_disable_ints(port); 1163 1164 /* Release interrupt */ 1165 free_irq(port->irq, port); 1166} 1167 1168static void 1169mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, 1170 struct ktermios *old) 1171{ 1172 unsigned long flags; 1173 unsigned char mr1, mr2; 1174 unsigned int j; 1175 unsigned int baud; 1176 1177 /* Prepare what we're gonna write */ 1178 mr1 = 0; 1179 1180 switch (new->c_cflag & CSIZE) { 1181 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; 1182 break; 1183 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; 1184 break; 1185 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; 1186 break; 1187 case CS8: 1188 default: mr1 |= MPC52xx_PSC_MODE_8_BITS; 1189 } 1190 1191 if (new->c_cflag & PARENB) { 1192 if (new->c_cflag & CMSPAR) 1193 mr1 |= MPC52xx_PSC_MODE_PARFORCE; 1194 1195 /* With CMSPAR, PARODD also means high parity (same as termios) */ 1196 mr1 |= (new->c_cflag & PARODD) ? 1197 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; 1198 } else { 1199 mr1 |= MPC52xx_PSC_MODE_PARNONE; 1200 } 1201 1202 mr2 = 0; 1203 1204 if (new->c_cflag & CSTOPB) 1205 mr2 |= MPC52xx_PSC_MODE_TWO_STOP; 1206 else 1207 mr2 |= ((new->c_cflag & CSIZE) == CS5) ? 1208 MPC52xx_PSC_MODE_ONE_STOP_5_BITS : 1209 MPC52xx_PSC_MODE_ONE_STOP; 1210 1211 if (new->c_cflag & CRTSCTS) { 1212 mr1 |= MPC52xx_PSC_MODE_RXRTS; 1213 mr2 |= MPC52xx_PSC_MODE_TXCTS; 1214 } 1215 1216 /* Get the lock */ 1217 spin_lock_irqsave(&port->lock, flags); 1218 1219 /* Do our best to flush TX & RX, so we don't lose anything */ 1220 /* But we don't wait indefinitely ! */ 1221 j = 5000000; /* Maximum wait */ 1222 /* FIXME Can't receive chars since set_termios might be called at early 1223 * boot for the console, all stuff is not yet ready to receive at that 1224 * time and that just makes the kernel oops */ 1225 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ 1226 while (!mpc52xx_uart_tx_empty(port) && --j) 1227 udelay(1); 1228 1229 if (!j) 1230 printk(KERN_ERR "mpc52xx_uart.c: " 1231 "Unable to flush RX & TX fifos in-time in set_termios." 1232 "Some chars may have been lost.\n"); 1233 1234 /* Reset the TX & RX */ 1235 psc_ops->command(port, MPC52xx_PSC_RST_RX); 1236 psc_ops->command(port, MPC52xx_PSC_RST_TX); 1237 1238 /* Send new mode settings */ 1239 psc_ops->set_mode(port, mr1, mr2); 1240 baud = psc_ops->set_baudrate(port, new, old); 1241 1242 /* Update the per-port timeout */ 1243 uart_update_timeout(port, new->c_cflag, baud); 1244 1245 if (UART_ENABLE_MS(port, new->c_cflag)) 1246 mpc52xx_uart_enable_ms(port); 1247 1248 /* Reenable TX & RX */ 1249 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); 1250 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1251 1252 /* We're all set, release the lock */ 1253 spin_unlock_irqrestore(&port->lock, flags); 1254} 1255 1256static const char * 1257mpc52xx_uart_type(struct uart_port *port) 1258{ 1259 /* 1260 * We keep using PORT_MPC52xx for historic reasons although it applies 1261 * for MPC512x, too, but print "MPC5xxx" to not irritate users 1262 */ 1263 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; 1264} 1265 1266static void 1267mpc52xx_uart_release_port(struct uart_port *port) 1268{ 1269 if (psc_ops->clock_relse) 1270 psc_ops->clock_relse(port); 1271 1272 /* remapped by us ? */ 1273 if (port->flags & UPF_IOREMAP) { 1274 iounmap(port->membase); 1275 port->membase = NULL; 1276 } 1277 1278 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1279} 1280 1281static int 1282mpc52xx_uart_request_port(struct uart_port *port) 1283{ 1284 int err; 1285 1286 if (port->flags & UPF_IOREMAP) /* Need to remap ? */ 1287 port->membase = ioremap(port->mapbase, 1288 sizeof(struct mpc52xx_psc)); 1289 1290 if (!port->membase) 1291 return -EINVAL; 1292 1293 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), 1294 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; 1295 1296 if (err) 1297 goto out_membase; 1298 1299 if (psc_ops->clock_alloc) { 1300 err = psc_ops->clock_alloc(port); 1301 if (err) 1302 goto out_mapregion; 1303 } 1304 1305 return 0; 1306 1307out_mapregion: 1308 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); 1309out_membase: 1310 if (port->flags & UPF_IOREMAP) { 1311 iounmap(port->membase); 1312 port->membase = NULL; 1313 } 1314 return err; 1315} 1316 1317static void 1318mpc52xx_uart_config_port(struct uart_port *port, int flags) 1319{ 1320 if ((flags & UART_CONFIG_TYPE) 1321 && (mpc52xx_uart_request_port(port) == 0)) 1322 port->type = PORT_MPC52xx; 1323} 1324 1325static int 1326mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1327{ 1328 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) 1329 return -EINVAL; 1330 1331 if ((ser->irq != port->irq) || 1332 (ser->io_type != UPIO_MEM) || 1333 (ser->baud_base != port->uartclk) || 1334 (ser->iomem_base != (void *)port->mapbase) || 1335 (ser->hub6 != 0)) 1336 return -EINVAL; 1337 1338 return 0; 1339} 1340 1341 1342static struct uart_ops mpc52xx_uart_ops = { 1343 .tx_empty = mpc52xx_uart_tx_empty, 1344 .set_mctrl = mpc52xx_uart_set_mctrl, 1345 .get_mctrl = mpc52xx_uart_get_mctrl, 1346 .stop_tx = mpc52xx_uart_stop_tx, 1347 .start_tx = mpc52xx_uart_start_tx, 1348 .stop_rx = mpc52xx_uart_stop_rx, 1349 .enable_ms = mpc52xx_uart_enable_ms, 1350 .break_ctl = mpc52xx_uart_break_ctl, 1351 .startup = mpc52xx_uart_startup, 1352 .shutdown = mpc52xx_uart_shutdown, 1353 .set_termios = mpc52xx_uart_set_termios, 1354/* .pm = mpc52xx_uart_pm, Not supported yet */ 1355 .type = mpc52xx_uart_type, 1356 .release_port = mpc52xx_uart_release_port, 1357 .request_port = mpc52xx_uart_request_port, 1358 .config_port = mpc52xx_uart_config_port, 1359 .verify_port = mpc52xx_uart_verify_port 1360}; 1361 1362 1363/* ======================================================================== */ 1364/* Interrupt handling */ 1365/* ======================================================================== */ 1366 1367static inline int 1368mpc52xx_uart_int_rx_chars(struct uart_port *port) 1369{ 1370 struct tty_port *tport = &port->state->port; 1371 unsigned char ch, flag; 1372 unsigned short status; 1373 1374 /* While we can read, do so ! */ 1375 while (psc_ops->raw_rx_rdy(port)) { 1376 /* Get the char */ 1377 ch = psc_ops->read_char(port); 1378 1379 /* Handle sysreq char */ 1380#ifdef SUPPORT_SYSRQ 1381 if (uart_handle_sysrq_char(port, ch)) { 1382 port->sysrq = 0; 1383 continue; 1384 } 1385#endif 1386 1387 /* Store it */ 1388 1389 flag = TTY_NORMAL; 1390 port->icount.rx++; 1391 1392 status = psc_ops->get_status(port); 1393 1394 if (status & (MPC52xx_PSC_SR_PE | 1395 MPC52xx_PSC_SR_FE | 1396 MPC52xx_PSC_SR_RB)) { 1397 1398 if (status & MPC52xx_PSC_SR_RB) { 1399 flag = TTY_BREAK; 1400 uart_handle_break(port); 1401 port->icount.brk++; 1402 } else if (status & MPC52xx_PSC_SR_PE) { 1403 flag = TTY_PARITY; 1404 port->icount.parity++; 1405 } 1406 else if (status & MPC52xx_PSC_SR_FE) { 1407 flag = TTY_FRAME; 1408 port->icount.frame++; 1409 } 1410 1411 /* Clear error condition */ 1412 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT); 1413 1414 } 1415 tty_insert_flip_char(tport, ch, flag); 1416 if (status & MPC52xx_PSC_SR_OE) { 1417 /* 1418 * Overrun is special, since it's 1419 * reported immediately, and doesn't 1420 * affect the current character 1421 */ 1422 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1423 port->icount.overrun++; 1424 } 1425 } 1426 1427 spin_unlock(&port->lock); 1428 tty_flip_buffer_push(tport); 1429 spin_lock(&port->lock); 1430 1431 return psc_ops->raw_rx_rdy(port); 1432} 1433 1434static inline int 1435mpc52xx_uart_int_tx_chars(struct uart_port *port) 1436{ 1437 struct circ_buf *xmit = &port->state->xmit; 1438 1439 /* Process out of band chars */ 1440 if (port->x_char) { 1441 psc_ops->write_char(port, port->x_char); 1442 port->icount.tx++; 1443 port->x_char = 0; 1444 return 1; 1445 } 1446 1447 /* Nothing to do ? */ 1448 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 1449 mpc52xx_uart_stop_tx(port); 1450 return 0; 1451 } 1452 1453 /* Send chars */ 1454 while (psc_ops->raw_tx_rdy(port)) { 1455 psc_ops->write_char(port, xmit->buf[xmit->tail]); 1456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1457 port->icount.tx++; 1458 if (uart_circ_empty(xmit)) 1459 break; 1460 } 1461 1462 /* Wake up */ 1463 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1464 uart_write_wakeup(port); 1465 1466 /* Maybe we're done after all */ 1467 if (uart_circ_empty(xmit)) { 1468 mpc52xx_uart_stop_tx(port); 1469 return 0; 1470 } 1471 1472 return 1; 1473} 1474 1475static irqreturn_t 1476mpc5xxx_uart_process_int(struct uart_port *port) 1477{ 1478 unsigned long pass = ISR_PASS_LIMIT; 1479 unsigned int keepgoing; 1480 u8 status; 1481 1482 /* While we have stuff to do, we continue */ 1483 do { 1484 /* If we don't find anything to do, we stop */ 1485 keepgoing = 0; 1486 1487 psc_ops->rx_clr_irq(port); 1488 if (psc_ops->rx_rdy(port)) 1489 keepgoing |= mpc52xx_uart_int_rx_chars(port); 1490 1491 psc_ops->tx_clr_irq(port); 1492 if (psc_ops->tx_rdy(port)) 1493 keepgoing |= mpc52xx_uart_int_tx_chars(port); 1494 1495 status = psc_ops->get_ipcr(port); 1496 if (status & MPC52xx_PSC_D_DCD) 1497 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); 1498 1499 if (status & MPC52xx_PSC_D_CTS) 1500 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); 1501 1502 /* Limit number of iteration */ 1503 if (!(--pass)) 1504 keepgoing = 0; 1505 1506 } while (keepgoing); 1507 1508 return IRQ_HANDLED; 1509} 1510 1511static irqreturn_t 1512mpc52xx_uart_int(int irq, void *dev_id) 1513{ 1514 struct uart_port *port = dev_id; 1515 irqreturn_t ret; 1516 1517 spin_lock(&port->lock); 1518 1519 ret = psc_ops->handle_irq(port); 1520 1521 spin_unlock(&port->lock); 1522 1523 return ret; 1524} 1525 1526/* ======================================================================== */ 1527/* Console ( if applicable ) */ 1528/* ======================================================================== */ 1529 1530#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE 1531 1532static void __init 1533mpc52xx_console_get_options(struct uart_port *port, 1534 int *baud, int *parity, int *bits, int *flow) 1535{ 1536 unsigned char mr1; 1537 1538 pr_debug("mpc52xx_console_get_options(port=%p)\n", port); 1539 1540 /* Read the mode registers */ 1541 mr1 = psc_ops->get_mr1(port); 1542 1543 /* CT{U,L}R are write-only ! */ 1544 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1545 1546 /* Parse them */ 1547 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { 1548 case MPC52xx_PSC_MODE_5_BITS: 1549 *bits = 5; 1550 break; 1551 case MPC52xx_PSC_MODE_6_BITS: 1552 *bits = 6; 1553 break; 1554 case MPC52xx_PSC_MODE_7_BITS: 1555 *bits = 7; 1556 break; 1557 case MPC52xx_PSC_MODE_8_BITS: 1558 default: 1559 *bits = 8; 1560 } 1561 1562 if (mr1 & MPC52xx_PSC_MODE_PARNONE) 1563 *parity = 'n'; 1564 else 1565 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; 1566} 1567 1568static void 1569mpc52xx_console_write(struct console *co, const char *s, unsigned int count) 1570{ 1571 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1572 unsigned int i, j; 1573 1574 /* Disable interrupts */ 1575 psc_ops->cw_disable_ints(port); 1576 1577 /* Wait the TX buffer to be empty */ 1578 j = 5000000; /* Maximum wait */ 1579 while (!mpc52xx_uart_tx_empty(port) && --j) 1580 udelay(1); 1581 1582 /* Write all the chars */ 1583 for (i = 0; i < count; i++, s++) { 1584 /* Line return handling */ 1585 if (*s == '\n') 1586 psc_ops->write_char(port, '\r'); 1587 1588 /* Send the char */ 1589 psc_ops->write_char(port, *s); 1590 1591 /* Wait the TX buffer to be empty */ 1592 j = 20000; /* Maximum wait */ 1593 while (!mpc52xx_uart_tx_empty(port) && --j) 1594 udelay(1); 1595 } 1596 1597 /* Restore interrupt state */ 1598 psc_ops->cw_restore_ints(port); 1599} 1600 1601 1602static int __init 1603mpc52xx_console_setup(struct console *co, char *options) 1604{ 1605 struct uart_port *port = &mpc52xx_uart_ports[co->index]; 1606 struct device_node *np = mpc52xx_uart_nodes[co->index]; 1607 unsigned int uartclk; 1608 struct resource res; 1609 int ret; 1610 1611 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; 1612 int bits = 8; 1613 int parity = 'n'; 1614 int flow = 'n'; 1615 1616 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", 1617 co, co->index, options); 1618 1619 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { 1620 pr_debug("PSC%x out of range\n", co->index); 1621 return -EINVAL; 1622 } 1623 1624 if (!np) { 1625 pr_debug("PSC%x not found in device tree\n", co->index); 1626 return -EINVAL; 1627 } 1628 1629 pr_debug("Console on ttyPSC%x is %s\n", 1630 co->index, mpc52xx_uart_nodes[co->index]->full_name); 1631 1632 /* Fetch register locations */ 1633 ret = of_address_to_resource(np, 0, &res); 1634 if (ret) { 1635 pr_debug("Could not get resources for PSC%x\n", co->index); 1636 return ret; 1637 } 1638 1639 uartclk = mpc5xxx_get_bus_frequency(np); 1640 if (uartclk == 0) { 1641 pr_debug("Could not find uart clock frequency!\n"); 1642 return -EINVAL; 1643 } 1644 1645 /* Basic port init. Needed since we use some uart_??? func before 1646 * real init for early access */ 1647 spin_lock_init(&port->lock); 1648 port->uartclk = uartclk; 1649 port->ops = &mpc52xx_uart_ops; 1650 port->mapbase = res.start; 1651 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); 1652 port->irq = irq_of_parse_and_map(np, 0); 1653 1654 if (port->membase == NULL) 1655 return -EINVAL; 1656 1657 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", 1658 (void *)port->mapbase, port->membase, 1659 port->irq, port->uartclk); 1660 1661 /* Setup the port parameters accoding to options */ 1662 if (options) 1663 uart_parse_options(options, &baud, &parity, &bits, &flow); 1664 else 1665 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); 1666 1667 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", 1668 baud, bits, parity, flow); 1669 1670 return uart_set_options(port, co, baud, parity, bits, flow); 1671} 1672 1673 1674static struct uart_driver mpc52xx_uart_driver; 1675 1676static struct console mpc52xx_console = { 1677 .name = "ttyPSC", 1678 .write = mpc52xx_console_write, 1679 .device = uart_console_device, 1680 .setup = mpc52xx_console_setup, 1681 .flags = CON_PRINTBUFFER, 1682 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ 1683 .data = &mpc52xx_uart_driver, 1684}; 1685 1686 1687static int __init 1688mpc52xx_console_init(void) 1689{ 1690 mpc52xx_uart_of_enumerate(); 1691 register_console(&mpc52xx_console); 1692 return 0; 1693} 1694 1695console_initcall(mpc52xx_console_init); 1696 1697#define MPC52xx_PSC_CONSOLE &mpc52xx_console 1698#else 1699#define MPC52xx_PSC_CONSOLE NULL 1700#endif 1701 1702 1703/* ======================================================================== */ 1704/* UART Driver */ 1705/* ======================================================================== */ 1706 1707static struct uart_driver mpc52xx_uart_driver = { 1708 .driver_name = "mpc52xx_psc_uart", 1709 .dev_name = "ttyPSC", 1710 .major = SERIAL_PSC_MAJOR, 1711 .minor = SERIAL_PSC_MINOR, 1712 .nr = MPC52xx_PSC_MAXNUM, 1713 .cons = MPC52xx_PSC_CONSOLE, 1714}; 1715 1716/* ======================================================================== */ 1717/* OF Platform Driver */ 1718/* ======================================================================== */ 1719 1720static const struct of_device_id mpc52xx_uart_of_match[] = { 1721#ifdef CONFIG_PPC_MPC52xx 1722 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, 1723 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1724 /* binding used by old lite5200 device trees: */ 1725 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, 1726 /* binding used by efika: */ 1727 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, 1728#endif 1729#ifdef CONFIG_PPC_MPC512x 1730 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, 1731 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, }, 1732#endif 1733 {}, 1734}; 1735 1736static int mpc52xx_uart_of_probe(struct platform_device *op) 1737{ 1738 int idx = -1; 1739 unsigned int uartclk; 1740 struct uart_port *port = NULL; 1741 struct resource res; 1742 int ret; 1743 1744 /* Check validity & presence */ 1745 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) 1746 if (mpc52xx_uart_nodes[idx] == op->dev.of_node) 1747 break; 1748 if (idx >= MPC52xx_PSC_MAXNUM) 1749 return -EINVAL; 1750 pr_debug("Found %s assigned to ttyPSC%x\n", 1751 mpc52xx_uart_nodes[idx]->full_name, idx); 1752 1753 /* set the uart clock to the input clock of the psc, the different 1754 * prescalers are taken into account in the set_baudrate() methods 1755 * of the respective chip */ 1756 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node); 1757 if (uartclk == 0) { 1758 dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); 1759 return -EINVAL; 1760 } 1761 1762 /* Init the port structure */ 1763 port = &mpc52xx_uart_ports[idx]; 1764 1765 spin_lock_init(&port->lock); 1766 port->uartclk = uartclk; 1767 port->fifosize = 512; 1768 port->iotype = UPIO_MEM; 1769 port->flags = UPF_BOOT_AUTOCONF | 1770 (uart_console(port) ? 0 : UPF_IOREMAP); 1771 port->line = idx; 1772 port->ops = &mpc52xx_uart_ops; 1773 port->dev = &op->dev; 1774 1775 /* Search for IRQ and mapbase */ 1776 ret = of_address_to_resource(op->dev.of_node, 0, &res); 1777 if (ret) 1778 return ret; 1779 1780 port->mapbase = res.start; 1781 if (!port->mapbase) { 1782 dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); 1783 return -EINVAL; 1784 } 1785 1786 psc_ops->get_irq(port, op->dev.of_node); 1787 if (port->irq == 0) { 1788 dev_dbg(&op->dev, "Could not get irq\n"); 1789 return -EINVAL; 1790 } 1791 1792 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", 1793 (void *)port->mapbase, port->irq, port->uartclk); 1794 1795 /* Add the port to the uart sub-system */ 1796 ret = uart_add_one_port(&mpc52xx_uart_driver, port); 1797 if (ret) 1798 return ret; 1799 1800 platform_set_drvdata(op, (void *)port); 1801 return 0; 1802} 1803 1804static int 1805mpc52xx_uart_of_remove(struct platform_device *op) 1806{ 1807 struct uart_port *port = platform_get_drvdata(op); 1808 1809 if (port) 1810 uart_remove_one_port(&mpc52xx_uart_driver, port); 1811 1812 return 0; 1813} 1814 1815#ifdef CONFIG_PM 1816static int 1817mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) 1818{ 1819 struct uart_port *port = platform_get_drvdata(op); 1820 1821 if (port) 1822 uart_suspend_port(&mpc52xx_uart_driver, port); 1823 1824 return 0; 1825} 1826 1827static int 1828mpc52xx_uart_of_resume(struct platform_device *op) 1829{ 1830 struct uart_port *port = platform_get_drvdata(op); 1831 1832 if (port) 1833 uart_resume_port(&mpc52xx_uart_driver, port); 1834 1835 return 0; 1836} 1837#endif 1838 1839static void 1840mpc52xx_uart_of_assign(struct device_node *np) 1841{ 1842 int i; 1843 1844 /* Find the first free PSC number */ 1845 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1846 if (mpc52xx_uart_nodes[i] == NULL) { 1847 of_node_get(np); 1848 mpc52xx_uart_nodes[i] = np; 1849 return; 1850 } 1851 } 1852} 1853 1854static void 1855mpc52xx_uart_of_enumerate(void) 1856{ 1857 static int enum_done; 1858 struct device_node *np; 1859 const struct of_device_id *match; 1860 int i; 1861 1862 if (enum_done) 1863 return; 1864 1865 /* Assign index to each PSC in device tree */ 1866 for_each_matching_node(np, mpc52xx_uart_of_match) { 1867 match = of_match_node(mpc52xx_uart_of_match, np); 1868 psc_ops = match->data; 1869 mpc52xx_uart_of_assign(np); 1870 } 1871 1872 enum_done = 1; 1873 1874 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1875 if (mpc52xx_uart_nodes[i]) 1876 pr_debug("%s assigned to ttyPSC%x\n", 1877 mpc52xx_uart_nodes[i]->full_name, i); 1878 } 1879} 1880 1881MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); 1882 1883static struct platform_driver mpc52xx_uart_of_driver = { 1884 .probe = mpc52xx_uart_of_probe, 1885 .remove = mpc52xx_uart_of_remove, 1886#ifdef CONFIG_PM 1887 .suspend = mpc52xx_uart_of_suspend, 1888 .resume = mpc52xx_uart_of_resume, 1889#endif 1890 .driver = { 1891 .name = "mpc52xx-psc-uart", 1892 .of_match_table = mpc52xx_uart_of_match, 1893 }, 1894}; 1895 1896 1897/* ======================================================================== */ 1898/* Module */ 1899/* ======================================================================== */ 1900 1901static int __init 1902mpc52xx_uart_init(void) 1903{ 1904 int ret; 1905 1906 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); 1907 1908 ret = uart_register_driver(&mpc52xx_uart_driver); 1909 if (ret) { 1910 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", 1911 __FILE__, ret); 1912 return ret; 1913 } 1914 1915 mpc52xx_uart_of_enumerate(); 1916 1917 /* 1918 * Map the PSC FIFO Controller and init if on MPC512x. 1919 */ 1920 if (psc_ops && psc_ops->fifoc_init) { 1921 ret = psc_ops->fifoc_init(); 1922 if (ret) 1923 goto err_init; 1924 } 1925 1926 ret = platform_driver_register(&mpc52xx_uart_of_driver); 1927 if (ret) { 1928 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", 1929 __FILE__, ret); 1930 goto err_reg; 1931 } 1932 1933 return 0; 1934err_reg: 1935 if (psc_ops && psc_ops->fifoc_uninit) 1936 psc_ops->fifoc_uninit(); 1937err_init: 1938 uart_unregister_driver(&mpc52xx_uart_driver); 1939 return ret; 1940} 1941 1942static void __exit 1943mpc52xx_uart_exit(void) 1944{ 1945 if (psc_ops->fifoc_uninit) 1946 psc_ops->fifoc_uninit(); 1947 1948 platform_driver_unregister(&mpc52xx_uart_of_driver); 1949 uart_unregister_driver(&mpc52xx_uart_driver); 1950} 1951 1952 1953module_init(mpc52xx_uart_init); 1954module_exit(mpc52xx_uart_exit); 1955 1956MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); 1957MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); 1958MODULE_LICENSE("GPL"); 1959