1/* 2 * Driver for msm7k serial device and console 3 * 4 * Copyright (C) 2007 Google, Inc. 5 * Author: Robert Love <rlove@google.com> 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19# define SUPPORT_SYSRQ 20#endif 21 22#include <linux/atomic.h> 23#include <linux/hrtimer.h> 24#include <linux/module.h> 25#include <linux/io.h> 26#include <linux/ioport.h> 27#include <linux/irq.h> 28#include <linux/init.h> 29#include <linux/console.h> 30#include <linux/tty.h> 31#include <linux/tty_flip.h> 32#include <linux/serial_core.h> 33#include <linux/serial.h> 34#include <linux/clk.h> 35#include <linux/platform_device.h> 36#include <linux/delay.h> 37#include <linux/of.h> 38#include <linux/of_device.h> 39 40#include "msm_serial.h" 41 42enum { 43 UARTDM_1P1 = 1, 44 UARTDM_1P2, 45 UARTDM_1P3, 46 UARTDM_1P4, 47}; 48 49struct msm_port { 50 struct uart_port uart; 51 char name[16]; 52 struct clk *clk; 53 struct clk *pclk; 54 unsigned int imr; 55 int is_uartdm; 56 unsigned int old_snap_state; 57 bool break_detected; 58}; 59 60static inline void wait_for_xmitr(struct uart_port *port) 61{ 62 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { 63 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) 64 break; 65 udelay(1); 66 } 67 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); 68} 69 70static void msm_stop_tx(struct uart_port *port) 71{ 72 struct msm_port *msm_port = UART_TO_MSM(port); 73 74 msm_port->imr &= ~UART_IMR_TXLEV; 75 msm_write(port, msm_port->imr, UART_IMR); 76} 77 78static void msm_start_tx(struct uart_port *port) 79{ 80 struct msm_port *msm_port = UART_TO_MSM(port); 81 82 msm_port->imr |= UART_IMR_TXLEV; 83 msm_write(port, msm_port->imr, UART_IMR); 84} 85 86static void msm_stop_rx(struct uart_port *port) 87{ 88 struct msm_port *msm_port = UART_TO_MSM(port); 89 90 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 91 msm_write(port, msm_port->imr, UART_IMR); 92} 93 94static void msm_enable_ms(struct uart_port *port) 95{ 96 struct msm_port *msm_port = UART_TO_MSM(port); 97 98 msm_port->imr |= UART_IMR_DELTA_CTS; 99 msm_write(port, msm_port->imr, UART_IMR); 100} 101 102static void handle_rx_dm(struct uart_port *port, unsigned int misr) 103{ 104 struct tty_port *tport = &port->state->port; 105 unsigned int sr; 106 int count = 0; 107 struct msm_port *msm_port = UART_TO_MSM(port); 108 109 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 110 port->icount.overrun++; 111 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 112 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 113 } 114 115 if (misr & UART_IMR_RXSTALE) { 116 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 117 msm_port->old_snap_state; 118 msm_port->old_snap_state = 0; 119 } else { 120 count = 4 * (msm_read(port, UART_RFWR)); 121 msm_port->old_snap_state += count; 122 } 123 124 /* TODO: Precise error reporting */ 125 126 port->icount.rx += count; 127 128 while (count > 0) { 129 unsigned char buf[4]; 130 int sysrq, r_count, i; 131 132 sr = msm_read(port, UART_SR); 133 if ((sr & UART_SR_RX_READY) == 0) { 134 msm_port->old_snap_state -= count; 135 break; 136 } 137 138 ioread32_rep(port->membase + UARTDM_RF, buf, 1); 139 r_count = min_t(int, count, sizeof(buf)); 140 141 for (i = 0; i < r_count; i++) { 142 char flag = TTY_NORMAL; 143 144 if (msm_port->break_detected && buf[i] == 0) { 145 port->icount.brk++; 146 flag = TTY_BREAK; 147 msm_port->break_detected = false; 148 if (uart_handle_break(port)) 149 continue; 150 } 151 152 if (!(port->read_status_mask & UART_SR_RX_BREAK)) 153 flag = TTY_NORMAL; 154 155 spin_unlock(&port->lock); 156 sysrq = uart_handle_sysrq_char(port, buf[i]); 157 spin_lock(&port->lock); 158 if (!sysrq) 159 tty_insert_flip_char(tport, buf[i], flag); 160 } 161 count -= r_count; 162 } 163 164 spin_unlock(&port->lock); 165 tty_flip_buffer_push(tport); 166 spin_lock(&port->lock); 167 168 if (misr & (UART_IMR_RXSTALE)) 169 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 170 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 171 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 172} 173 174static void handle_rx(struct uart_port *port) 175{ 176 struct tty_port *tport = &port->state->port; 177 unsigned int sr; 178 179 /* 180 * Handle overrun. My understanding of the hardware is that overrun 181 * is not tied to the RX buffer, so we handle the case out of band. 182 */ 183 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 184 port->icount.overrun++; 185 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 186 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 187 } 188 189 /* and now the main RX loop */ 190 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 191 unsigned int c; 192 char flag = TTY_NORMAL; 193 int sysrq; 194 195 c = msm_read(port, UART_RF); 196 197 if (sr & UART_SR_RX_BREAK) { 198 port->icount.brk++; 199 if (uart_handle_break(port)) 200 continue; 201 } else if (sr & UART_SR_PAR_FRAME_ERR) { 202 port->icount.frame++; 203 } else { 204 port->icount.rx++; 205 } 206 207 /* Mask conditions we're ignorning. */ 208 sr &= port->read_status_mask; 209 210 if (sr & UART_SR_RX_BREAK) 211 flag = TTY_BREAK; 212 else if (sr & UART_SR_PAR_FRAME_ERR) 213 flag = TTY_FRAME; 214 215 spin_unlock(&port->lock); 216 sysrq = uart_handle_sysrq_char(port, c); 217 spin_lock(&port->lock); 218 if (!sysrq) 219 tty_insert_flip_char(tport, c, flag); 220 } 221 222 spin_unlock(&port->lock); 223 tty_flip_buffer_push(tport); 224 spin_lock(&port->lock); 225} 226 227static void reset_dm_count(struct uart_port *port, int count) 228{ 229 wait_for_xmitr(port); 230 msm_write(port, count, UARTDM_NCF_TX); 231 msm_read(port, UARTDM_NCF_TX); 232} 233 234static void handle_tx(struct uart_port *port) 235{ 236 struct circ_buf *xmit = &port->state->xmit; 237 struct msm_port *msm_port = UART_TO_MSM(port); 238 unsigned int tx_count, num_chars; 239 unsigned int tf_pointer = 0; 240 void __iomem *tf; 241 242 if (msm_port->is_uartdm) 243 tf = port->membase + UARTDM_TF; 244 else 245 tf = port->membase + UART_TF; 246 247 tx_count = uart_circ_chars_pending(xmit); 248 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail, 249 port->fifosize); 250 251 if (port->x_char) { 252 if (msm_port->is_uartdm) 253 reset_dm_count(port, tx_count + 1); 254 255 iowrite8_rep(tf, &port->x_char, 1); 256 port->icount.tx++; 257 port->x_char = 0; 258 } else if (tx_count && msm_port->is_uartdm) { 259 reset_dm_count(port, tx_count); 260 } 261 262 while (tf_pointer < tx_count) { 263 int i; 264 char buf[4] = { 0 }; 265 266 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 267 break; 268 269 if (msm_port->is_uartdm) 270 num_chars = min(tx_count - tf_pointer, 271 (unsigned int)sizeof(buf)); 272 else 273 num_chars = 1; 274 275 for (i = 0; i < num_chars; i++) { 276 buf[i] = xmit->buf[xmit->tail + i]; 277 port->icount.tx++; 278 } 279 280 iowrite32_rep(tf, buf, 1); 281 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 282 tf_pointer += num_chars; 283 } 284 285 /* disable tx interrupts if nothing more to send */ 286 if (uart_circ_empty(xmit)) 287 msm_stop_tx(port); 288 289 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 290 uart_write_wakeup(port); 291} 292 293static void handle_delta_cts(struct uart_port *port) 294{ 295 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 296 port->icount.cts++; 297 wake_up_interruptible(&port->state->port.delta_msr_wait); 298} 299 300static irqreturn_t msm_irq(int irq, void *dev_id) 301{ 302 struct uart_port *port = dev_id; 303 struct msm_port *msm_port = UART_TO_MSM(port); 304 unsigned int misr; 305 306 spin_lock(&port->lock); 307 misr = msm_read(port, UART_MISR); 308 msm_write(port, 0, UART_IMR); /* disable interrupt */ 309 310 if (misr & UART_IMR_RXBREAK_START) { 311 msm_port->break_detected = true; 312 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR); 313 } 314 315 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 316 if (msm_port->is_uartdm) 317 handle_rx_dm(port, misr); 318 else 319 handle_rx(port); 320 } 321 if (misr & UART_IMR_TXLEV) 322 handle_tx(port); 323 if (misr & UART_IMR_DELTA_CTS) 324 handle_delta_cts(port); 325 326 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 327 spin_unlock(&port->lock); 328 329 return IRQ_HANDLED; 330} 331 332static unsigned int msm_tx_empty(struct uart_port *port) 333{ 334 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 335} 336 337static unsigned int msm_get_mctrl(struct uart_port *port) 338{ 339 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 340} 341 342static void msm_reset(struct uart_port *port) 343{ 344 struct msm_port *msm_port = UART_TO_MSM(port); 345 346 /* reset everything */ 347 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 348 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 349 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 350 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 351 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 352 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); 353 354 /* Disable DM modes */ 355 if (msm_port->is_uartdm) 356 msm_write(port, 0, UARTDM_DMEN); 357} 358 359static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 360{ 361 unsigned int mr; 362 363 mr = msm_read(port, UART_MR1); 364 365 if (!(mctrl & TIOCM_RTS)) { 366 mr &= ~UART_MR1_RX_RDY_CTL; 367 msm_write(port, mr, UART_MR1); 368 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 369 } else { 370 mr |= UART_MR1_RX_RDY_CTL; 371 msm_write(port, mr, UART_MR1); 372 } 373} 374 375static void msm_break_ctl(struct uart_port *port, int break_ctl) 376{ 377 if (break_ctl) 378 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 379 else 380 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 381} 382 383struct msm_baud_map { 384 u16 divisor; 385 u8 code; 386 u8 rxstale; 387}; 388 389static const struct msm_baud_map * 390msm_find_best_baud(struct uart_port *port, unsigned int baud) 391{ 392 unsigned int i, divisor; 393 const struct msm_baud_map *entry; 394 static const struct msm_baud_map table[] = { 395 { 1536, 0x00, 1 }, 396 { 768, 0x11, 1 }, 397 { 384, 0x22, 1 }, 398 { 192, 0x33, 1 }, 399 { 96, 0x44, 1 }, 400 { 48, 0x55, 1 }, 401 { 32, 0x66, 1 }, 402 { 24, 0x77, 1 }, 403 { 16, 0x88, 1 }, 404 { 12, 0x99, 6 }, 405 { 8, 0xaa, 6 }, 406 { 6, 0xbb, 6 }, 407 { 4, 0xcc, 6 }, 408 { 3, 0xdd, 8 }, 409 { 2, 0xee, 16 }, 410 { 1, 0xff, 31 }, 411 }; 412 413 divisor = uart_get_divisor(port, baud); 414 415 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++) 416 if (entry->divisor <= divisor) 417 break; 418 419 return entry; /* Default to smallest divider */ 420} 421 422static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) 423{ 424 unsigned int rxstale, watermark; 425 struct msm_port *msm_port = UART_TO_MSM(port); 426 const struct msm_baud_map *entry; 427 428 entry = msm_find_best_baud(port, baud); 429 430 msm_write(port, entry->code, UART_CSR); 431 432 /* RX stale watermark */ 433 rxstale = entry->rxstale; 434 watermark = UART_IPR_STALE_LSB & rxstale; 435 watermark |= UART_IPR_RXSTALE_LAST; 436 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); 437 msm_write(port, watermark, UART_IPR); 438 439 /* set RX watermark */ 440 watermark = (port->fifosize * 3) / 4; 441 msm_write(port, watermark, UART_RFWR); 442 443 /* set TX watermark */ 444 msm_write(port, 10, UART_TFWR); 445 446 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 447 msm_reset(port); 448 449 /* Enable RX and TX */ 450 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR); 451 452 /* turn on RX and CTS interrupts */ 453 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 454 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START; 455 456 msm_write(port, msm_port->imr, UART_IMR); 457 458 if (msm_port->is_uartdm) { 459 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 460 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 461 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 462 } 463 464 return baud; 465} 466 467static void msm_init_clock(struct uart_port *port) 468{ 469 struct msm_port *msm_port = UART_TO_MSM(port); 470 471 clk_prepare_enable(msm_port->clk); 472 clk_prepare_enable(msm_port->pclk); 473 msm_serial_set_mnd_regs(port); 474} 475 476static int msm_startup(struct uart_port *port) 477{ 478 struct msm_port *msm_port = UART_TO_MSM(port); 479 unsigned int data, rfr_level; 480 int ret; 481 482 snprintf(msm_port->name, sizeof(msm_port->name), 483 "msm_serial%d", port->line); 484 485 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, 486 msm_port->name, port); 487 if (unlikely(ret)) 488 return ret; 489 490 msm_init_clock(port); 491 492 if (likely(port->fifosize > 12)) 493 rfr_level = port->fifosize - 12; 494 else 495 rfr_level = port->fifosize; 496 497 /* set automatic RFR level */ 498 data = msm_read(port, UART_MR1); 499 data &= ~UART_MR1_AUTO_RFR_LEVEL1; 500 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 501 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); 502 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 503 msm_write(port, data, UART_MR1); 504 return 0; 505} 506 507static void msm_shutdown(struct uart_port *port) 508{ 509 struct msm_port *msm_port = UART_TO_MSM(port); 510 511 msm_port->imr = 0; 512 msm_write(port, 0, UART_IMR); /* disable interrupts */ 513 514 clk_disable_unprepare(msm_port->clk); 515 516 free_irq(port->irq, port); 517} 518 519static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 520 struct ktermios *old) 521{ 522 unsigned long flags; 523 unsigned int baud, mr; 524 525 spin_lock_irqsave(&port->lock, flags); 526 527 /* calculate and set baud rate */ 528 baud = uart_get_baud_rate(port, termios, old, 300, 115200); 529 baud = msm_set_baud_rate(port, baud); 530 if (tty_termios_baud_rate(termios)) 531 tty_termios_encode_baud_rate(termios, baud, baud); 532 533 /* calculate parity */ 534 mr = msm_read(port, UART_MR2); 535 mr &= ~UART_MR2_PARITY_MODE; 536 if (termios->c_cflag & PARENB) { 537 if (termios->c_cflag & PARODD) 538 mr |= UART_MR2_PARITY_MODE_ODD; 539 else if (termios->c_cflag & CMSPAR) 540 mr |= UART_MR2_PARITY_MODE_SPACE; 541 else 542 mr |= UART_MR2_PARITY_MODE_EVEN; 543 } 544 545 /* calculate bits per char */ 546 mr &= ~UART_MR2_BITS_PER_CHAR; 547 switch (termios->c_cflag & CSIZE) { 548 case CS5: 549 mr |= UART_MR2_BITS_PER_CHAR_5; 550 break; 551 case CS6: 552 mr |= UART_MR2_BITS_PER_CHAR_6; 553 break; 554 case CS7: 555 mr |= UART_MR2_BITS_PER_CHAR_7; 556 break; 557 case CS8: 558 default: 559 mr |= UART_MR2_BITS_PER_CHAR_8; 560 break; 561 } 562 563 /* calculate stop bits */ 564 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 565 if (termios->c_cflag & CSTOPB) 566 mr |= UART_MR2_STOP_BIT_LEN_TWO; 567 else 568 mr |= UART_MR2_STOP_BIT_LEN_ONE; 569 570 /* set parity, bits per char, and stop bit */ 571 msm_write(port, mr, UART_MR2); 572 573 /* calculate and set hardware flow control */ 574 mr = msm_read(port, UART_MR1); 575 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 576 if (termios->c_cflag & CRTSCTS) { 577 mr |= UART_MR1_CTS_CTL; 578 mr |= UART_MR1_RX_RDY_CTL; 579 } 580 msm_write(port, mr, UART_MR1); 581 582 /* Configure status bits to ignore based on termio flags. */ 583 port->read_status_mask = 0; 584 if (termios->c_iflag & INPCK) 585 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 586 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 587 port->read_status_mask |= UART_SR_RX_BREAK; 588 589 uart_update_timeout(port, termios->c_cflag, baud); 590 591 spin_unlock_irqrestore(&port->lock, flags); 592} 593 594static const char *msm_type(struct uart_port *port) 595{ 596 return "MSM"; 597} 598 599static void msm_release_port(struct uart_port *port) 600{ 601 struct platform_device *pdev = to_platform_device(port->dev); 602 struct resource *uart_resource; 603 resource_size_t size; 604 605 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 606 if (unlikely(!uart_resource)) 607 return; 608 size = resource_size(uart_resource); 609 610 release_mem_region(port->mapbase, size); 611 iounmap(port->membase); 612 port->membase = NULL; 613} 614 615static int msm_request_port(struct uart_port *port) 616{ 617 struct platform_device *pdev = to_platform_device(port->dev); 618 struct resource *uart_resource; 619 resource_size_t size; 620 int ret; 621 622 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 623 if (unlikely(!uart_resource)) 624 return -ENXIO; 625 626 size = resource_size(uart_resource); 627 628 if (!request_mem_region(port->mapbase, size, "msm_serial")) 629 return -EBUSY; 630 631 port->membase = ioremap(port->mapbase, size); 632 if (!port->membase) { 633 ret = -EBUSY; 634 goto fail_release_port; 635 } 636 637 return 0; 638 639fail_release_port: 640 release_mem_region(port->mapbase, size); 641 return ret; 642} 643 644static void msm_config_port(struct uart_port *port, int flags) 645{ 646 int ret; 647 648 if (flags & UART_CONFIG_TYPE) { 649 port->type = PORT_MSM; 650 ret = msm_request_port(port); 651 if (ret) 652 return; 653 } 654} 655 656static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 657{ 658 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 659 return -EINVAL; 660 if (unlikely(port->irq != ser->irq)) 661 return -EINVAL; 662 return 0; 663} 664 665static void msm_power(struct uart_port *port, unsigned int state, 666 unsigned int oldstate) 667{ 668 struct msm_port *msm_port = UART_TO_MSM(port); 669 670 switch (state) { 671 case 0: 672 clk_prepare_enable(msm_port->clk); 673 clk_prepare_enable(msm_port->pclk); 674 break; 675 case 3: 676 clk_disable_unprepare(msm_port->clk); 677 clk_disable_unprepare(msm_port->pclk); 678 break; 679 default: 680 pr_err("msm_serial: Unknown PM state %d\n", state); 681 } 682} 683 684#ifdef CONFIG_CONSOLE_POLL 685static int msm_poll_get_char_single(struct uart_port *port) 686{ 687 struct msm_port *msm_port = UART_TO_MSM(port); 688 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF; 689 690 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) 691 return NO_POLL_CHAR; 692 693 return msm_read(port, rf_reg) & 0xff; 694} 695 696static int msm_poll_get_char_dm(struct uart_port *port) 697{ 698 int c; 699 static u32 slop; 700 static int count; 701 unsigned char *sp = (unsigned char *)&slop; 702 703 /* Check if a previous read had more than one char */ 704 if (count) { 705 c = sp[sizeof(slop) - count]; 706 count--; 707 /* Or if FIFO is empty */ 708 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) { 709 /* 710 * If RX packing buffer has less than a word, force stale to 711 * push contents into RX FIFO 712 */ 713 count = msm_read(port, UARTDM_RXFS); 714 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 715 if (count) { 716 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); 717 slop = msm_read(port, UARTDM_RF); 718 c = sp[0]; 719 count--; 720 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 721 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 722 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, 723 UART_CR); 724 } else { 725 c = NO_POLL_CHAR; 726 } 727 /* FIFO has a word */ 728 } else { 729 slop = msm_read(port, UARTDM_RF); 730 c = sp[0]; 731 count = sizeof(slop) - 1; 732 } 733 734 return c; 735} 736 737static int msm_poll_get_char(struct uart_port *port) 738{ 739 u32 imr; 740 int c; 741 struct msm_port *msm_port = UART_TO_MSM(port); 742 743 /* Disable all interrupts */ 744 imr = msm_read(port, UART_IMR); 745 msm_write(port, 0, UART_IMR); 746 747 if (msm_port->is_uartdm) 748 c = msm_poll_get_char_dm(port); 749 else 750 c = msm_poll_get_char_single(port); 751 752 /* Enable interrupts */ 753 msm_write(port, imr, UART_IMR); 754 755 return c; 756} 757 758static void msm_poll_put_char(struct uart_port *port, unsigned char c) 759{ 760 u32 imr; 761 struct msm_port *msm_port = UART_TO_MSM(port); 762 763 /* Disable all interrupts */ 764 imr = msm_read(port, UART_IMR); 765 msm_write(port, 0, UART_IMR); 766 767 if (msm_port->is_uartdm) 768 reset_dm_count(port, 1); 769 770 /* Wait until FIFO is empty */ 771 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 772 cpu_relax(); 773 774 /* Write a character */ 775 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 776 777 /* Wait until FIFO is empty */ 778 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 779 cpu_relax(); 780 781 /* Enable interrupts */ 782 msm_write(port, imr, UART_IMR); 783} 784#endif 785 786static struct uart_ops msm_uart_pops = { 787 .tx_empty = msm_tx_empty, 788 .set_mctrl = msm_set_mctrl, 789 .get_mctrl = msm_get_mctrl, 790 .stop_tx = msm_stop_tx, 791 .start_tx = msm_start_tx, 792 .stop_rx = msm_stop_rx, 793 .enable_ms = msm_enable_ms, 794 .break_ctl = msm_break_ctl, 795 .startup = msm_startup, 796 .shutdown = msm_shutdown, 797 .set_termios = msm_set_termios, 798 .type = msm_type, 799 .release_port = msm_release_port, 800 .request_port = msm_request_port, 801 .config_port = msm_config_port, 802 .verify_port = msm_verify_port, 803 .pm = msm_power, 804#ifdef CONFIG_CONSOLE_POLL 805 .poll_get_char = msm_poll_get_char, 806 .poll_put_char = msm_poll_put_char, 807#endif 808}; 809 810static struct msm_port msm_uart_ports[] = { 811 { 812 .uart = { 813 .iotype = UPIO_MEM, 814 .ops = &msm_uart_pops, 815 .flags = UPF_BOOT_AUTOCONF, 816 .fifosize = 64, 817 .line = 0, 818 }, 819 }, 820 { 821 .uart = { 822 .iotype = UPIO_MEM, 823 .ops = &msm_uart_pops, 824 .flags = UPF_BOOT_AUTOCONF, 825 .fifosize = 64, 826 .line = 1, 827 }, 828 }, 829 { 830 .uart = { 831 .iotype = UPIO_MEM, 832 .ops = &msm_uart_pops, 833 .flags = UPF_BOOT_AUTOCONF, 834 .fifosize = 64, 835 .line = 2, 836 }, 837 }, 838}; 839 840#define UART_NR ARRAY_SIZE(msm_uart_ports) 841 842static inline struct uart_port *get_port_from_line(unsigned int line) 843{ 844 return &msm_uart_ports[line].uart; 845} 846 847#ifdef CONFIG_SERIAL_MSM_CONSOLE 848static void __msm_console_write(struct uart_port *port, const char *s, 849 unsigned int count, bool is_uartdm) 850{ 851 int i; 852 int num_newlines = 0; 853 bool replaced = false; 854 void __iomem *tf; 855 856 if (is_uartdm) 857 tf = port->membase + UARTDM_TF; 858 else 859 tf = port->membase + UART_TF; 860 861 /* Account for newlines that will get a carriage return added */ 862 for (i = 0; i < count; i++) 863 if (s[i] == '\n') 864 num_newlines++; 865 count += num_newlines; 866 867 spin_lock(&port->lock); 868 if (is_uartdm) 869 reset_dm_count(port, count); 870 871 i = 0; 872 while (i < count) { 873 int j; 874 unsigned int num_chars; 875 char buf[4] = { 0 }; 876 877 if (is_uartdm) 878 num_chars = min(count - i, (unsigned int)sizeof(buf)); 879 else 880 num_chars = 1; 881 882 for (j = 0; j < num_chars; j++) { 883 char c = *s; 884 885 if (c == '\n' && !replaced) { 886 buf[j] = '\r'; 887 j++; 888 replaced = true; 889 } 890 if (j < num_chars) { 891 buf[j] = c; 892 s++; 893 replaced = false; 894 } 895 } 896 897 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 898 cpu_relax(); 899 900 iowrite32_rep(tf, buf, 1); 901 i += num_chars; 902 } 903 spin_unlock(&port->lock); 904} 905 906static void msm_console_write(struct console *co, const char *s, 907 unsigned int count) 908{ 909 struct uart_port *port; 910 struct msm_port *msm_port; 911 912 BUG_ON(co->index < 0 || co->index >= UART_NR); 913 914 port = get_port_from_line(co->index); 915 msm_port = UART_TO_MSM(port); 916 917 __msm_console_write(port, s, count, msm_port->is_uartdm); 918} 919 920static int __init msm_console_setup(struct console *co, char *options) 921{ 922 struct uart_port *port; 923 int baud = 115200; 924 int bits = 8; 925 int parity = 'n'; 926 int flow = 'n'; 927 928 if (unlikely(co->index >= UART_NR || co->index < 0)) 929 return -ENXIO; 930 931 port = get_port_from_line(co->index); 932 933 if (unlikely(!port->membase)) 934 return -ENXIO; 935 936 msm_init_clock(port); 937 938 if (options) 939 uart_parse_options(options, &baud, &parity, &bits, &flow); 940 941 pr_info("msm_serial: console setup on port #%d\n", port->line); 942 943 return uart_set_options(port, co, baud, parity, bits, flow); 944} 945 946static void 947msm_serial_early_write(struct console *con, const char *s, unsigned n) 948{ 949 struct earlycon_device *dev = con->data; 950 951 __msm_console_write(&dev->port, s, n, false); 952} 953 954static int __init 955msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) 956{ 957 if (!device->port.membase) 958 return -ENODEV; 959 960 device->con->write = msm_serial_early_write; 961 return 0; 962} 963EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup); 964OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", 965 msm_serial_early_console_setup); 966 967static void 968msm_serial_early_write_dm(struct console *con, const char *s, unsigned n) 969{ 970 struct earlycon_device *dev = con->data; 971 972 __msm_console_write(&dev->port, s, n, true); 973} 974 975static int __init 976msm_serial_early_console_setup_dm(struct earlycon_device *device, 977 const char *opt) 978{ 979 if (!device->port.membase) 980 return -ENODEV; 981 982 device->con->write = msm_serial_early_write_dm; 983 return 0; 984} 985EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm); 986OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", 987 msm_serial_early_console_setup_dm); 988 989static struct uart_driver msm_uart_driver; 990 991static struct console msm_console = { 992 .name = "ttyMSM", 993 .write = msm_console_write, 994 .device = uart_console_device, 995 .setup = msm_console_setup, 996 .flags = CON_PRINTBUFFER, 997 .index = -1, 998 .data = &msm_uart_driver, 999}; 1000 1001#define MSM_CONSOLE (&msm_console) 1002 1003#else 1004#define MSM_CONSOLE NULL 1005#endif 1006 1007static struct uart_driver msm_uart_driver = { 1008 .owner = THIS_MODULE, 1009 .driver_name = "msm_serial", 1010 .dev_name = "ttyMSM", 1011 .nr = UART_NR, 1012 .cons = MSM_CONSOLE, 1013}; 1014 1015static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 1016 1017static const struct of_device_id msm_uartdm_table[] = { 1018 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, 1019 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, 1020 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, 1021 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, 1022 { } 1023}; 1024 1025static int msm_serial_probe(struct platform_device *pdev) 1026{ 1027 struct msm_port *msm_port; 1028 struct resource *resource; 1029 struct uart_port *port; 1030 const struct of_device_id *id; 1031 int irq, line; 1032 1033 if (pdev->dev.of_node) 1034 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1035 else 1036 line = pdev->id; 1037 1038 if (line < 0) 1039 line = atomic_inc_return(&msm_uart_next_id) - 1; 1040 1041 if (unlikely(line < 0 || line >= UART_NR)) 1042 return -ENXIO; 1043 1044 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line); 1045 1046 port = get_port_from_line(line); 1047 port->dev = &pdev->dev; 1048 msm_port = UART_TO_MSM(port); 1049 1050 id = of_match_device(msm_uartdm_table, &pdev->dev); 1051 if (id) 1052 msm_port->is_uartdm = (unsigned long)id->data; 1053 else 1054 msm_port->is_uartdm = 0; 1055 1056 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 1057 if (IS_ERR(msm_port->clk)) 1058 return PTR_ERR(msm_port->clk); 1059 1060 if (msm_port->is_uartdm) { 1061 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 1062 if (IS_ERR(msm_port->pclk)) 1063 return PTR_ERR(msm_port->pclk); 1064 1065 clk_set_rate(msm_port->clk, 1843200); 1066 } 1067 1068 port->uartclk = clk_get_rate(msm_port->clk); 1069 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk); 1070 1071 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1072 if (unlikely(!resource)) 1073 return -ENXIO; 1074 port->mapbase = resource->start; 1075 1076 irq = platform_get_irq(pdev, 0); 1077 if (unlikely(irq < 0)) 1078 return -ENXIO; 1079 port->irq = irq; 1080 1081 platform_set_drvdata(pdev, port); 1082 1083 return uart_add_one_port(&msm_uart_driver, port); 1084} 1085 1086static int msm_serial_remove(struct platform_device *pdev) 1087{ 1088 struct uart_port *port = platform_get_drvdata(pdev); 1089 1090 uart_remove_one_port(&msm_uart_driver, port); 1091 1092 return 0; 1093} 1094 1095static const struct of_device_id msm_match_table[] = { 1096 { .compatible = "qcom,msm-uart" }, 1097 { .compatible = "qcom,msm-uartdm" }, 1098 {} 1099}; 1100 1101static struct platform_driver msm_platform_driver = { 1102 .remove = msm_serial_remove, 1103 .probe = msm_serial_probe, 1104 .driver = { 1105 .name = "msm_serial", 1106 .of_match_table = msm_match_table, 1107 }, 1108}; 1109 1110static int __init msm_serial_init(void) 1111{ 1112 int ret; 1113 1114 ret = uart_register_driver(&msm_uart_driver); 1115 if (unlikely(ret)) 1116 return ret; 1117 1118 ret = platform_driver_register(&msm_platform_driver); 1119 if (unlikely(ret)) 1120 uart_unregister_driver(&msm_uart_driver); 1121 1122 pr_info("msm_serial: driver initialized\n"); 1123 1124 return ret; 1125} 1126 1127static void __exit msm_serial_exit(void) 1128{ 1129 platform_driver_unregister(&msm_platform_driver); 1130 uart_unregister_driver(&msm_uart_driver); 1131} 1132 1133module_init(msm_serial_init); 1134module_exit(msm_serial_exit); 1135 1136MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1137MODULE_DESCRIPTION("Driver for msm7x serial device"); 1138MODULE_LICENSE("GPL"); 1139