1/** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22#include <linux/version.h> 23#include <linux/module.h> 24#include <linux/kernel.h> 25#include <linux/slab.h> 26#include <linux/spinlock.h> 27#include <linux/platform_device.h> 28#include <linux/pm_runtime.h> 29#include <linux/interrupt.h> 30#include <linux/ioport.h> 31#include <linux/io.h> 32#include <linux/list.h> 33#include <linux/delay.h> 34#include <linux/dma-mapping.h> 35#include <linux/of.h> 36#include <linux/acpi.h> 37 38#include <linux/usb/ch9.h> 39#include <linux/usb/gadget.h> 40#include <linux/usb/of.h> 41#include <linux/usb/otg.h> 42 43#include "platform_data.h" 44#include "core.h" 45#include "gadget.h" 46#include "io.h" 47 48#include "debug.h" 49 50/* -------------------------------------------------------------------------- */ 51 52void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 53{ 54 u32 reg; 55 56 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 58 reg |= DWC3_GCTL_PRTCAPDIR(mode); 59 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 60} 61 62/** 63 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 64 * @dwc: pointer to our context structure 65 */ 66static int dwc3_core_soft_reset(struct dwc3 *dwc) 67{ 68 u32 reg; 69 int ret; 70 71 /* Before Resetting PHY, put Core in Reset */ 72 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 73 reg |= DWC3_GCTL_CORESOFTRESET; 74 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 75 76 /* Assert USB3 PHY reset */ 77 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 78 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 79 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 80 81 /* Assert USB2 PHY reset */ 82 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 83 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 85 86 usb_phy_init(dwc->usb2_phy); 87 usb_phy_init(dwc->usb3_phy); 88 ret = phy_init(dwc->usb2_generic_phy); 89 if (ret < 0) 90 return ret; 91 92 ret = phy_init(dwc->usb3_generic_phy); 93 if (ret < 0) { 94 phy_exit(dwc->usb2_generic_phy); 95 return ret; 96 } 97 mdelay(100); 98 99 /* Clear USB3 PHY reset */ 100 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 101 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 102 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 103 104 /* Clear USB2 PHY reset */ 105 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 106 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 107 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 108 109 mdelay(100); 110 111 /* After PHYs are stable we can take Core out of reset state */ 112 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 113 reg &= ~DWC3_GCTL_CORESOFTRESET; 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 return 0; 117} 118 119/** 120 * dwc3_free_one_event_buffer - Frees one event buffer 121 * @dwc: Pointer to our controller context structure 122 * @evt: Pointer to event buffer to be freed 123 */ 124static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 125 struct dwc3_event_buffer *evt) 126{ 127 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); 128} 129 130/** 131 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 132 * @dwc: Pointer to our controller context structure 133 * @length: size of the event buffer 134 * 135 * Returns a pointer to the allocated event buffer structure on success 136 * otherwise ERR_PTR(errno). 137 */ 138static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 139 unsigned length) 140{ 141 struct dwc3_event_buffer *evt; 142 143 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 144 if (!evt) 145 return ERR_PTR(-ENOMEM); 146 147 evt->dwc = dwc; 148 evt->length = length; 149 evt->buf = dma_alloc_coherent(dwc->dev, length, 150 &evt->dma, GFP_KERNEL); 151 if (!evt->buf) 152 return ERR_PTR(-ENOMEM); 153 154 return evt; 155} 156 157/** 158 * dwc3_free_event_buffers - frees all allocated event buffers 159 * @dwc: Pointer to our controller context structure 160 */ 161static void dwc3_free_event_buffers(struct dwc3 *dwc) 162{ 163 struct dwc3_event_buffer *evt; 164 int i; 165 166 for (i = 0; i < dwc->num_event_buffers; i++) { 167 evt = dwc->ev_buffs[i]; 168 if (evt) 169 dwc3_free_one_event_buffer(dwc, evt); 170 } 171} 172 173/** 174 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 175 * @dwc: pointer to our controller context structure 176 * @length: size of event buffer 177 * 178 * Returns 0 on success otherwise negative errno. In the error case, dwc 179 * may contain some buffers allocated but not all which were requested. 180 */ 181static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 182{ 183 int num; 184 int i; 185 186 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 187 dwc->num_event_buffers = num; 188 189 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, 190 GFP_KERNEL); 191 if (!dwc->ev_buffs) 192 return -ENOMEM; 193 194 for (i = 0; i < num; i++) { 195 struct dwc3_event_buffer *evt; 196 197 evt = dwc3_alloc_one_event_buffer(dwc, length); 198 if (IS_ERR(evt)) { 199 dev_err(dwc->dev, "can't allocate event buffer\n"); 200 return PTR_ERR(evt); 201 } 202 dwc->ev_buffs[i] = evt; 203 } 204 205 return 0; 206} 207 208/** 209 * dwc3_event_buffers_setup - setup our allocated event buffers 210 * @dwc: pointer to our controller context structure 211 * 212 * Returns 0 on success otherwise negative errno. 213 */ 214static int dwc3_event_buffers_setup(struct dwc3 *dwc) 215{ 216 struct dwc3_event_buffer *evt; 217 int n; 218 219 for (n = 0; n < dwc->num_event_buffers; n++) { 220 evt = dwc->ev_buffs[n]; 221 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 222 evt->buf, (unsigned long long) evt->dma, 223 evt->length); 224 225 evt->lpos = 0; 226 227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 228 lower_32_bits(evt->dma)); 229 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 230 upper_32_bits(evt->dma)); 231 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 232 DWC3_GEVNTSIZ_SIZE(evt->length)); 233 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 234 } 235 236 return 0; 237} 238 239static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 240{ 241 struct dwc3_event_buffer *evt; 242 int n; 243 244 for (n = 0; n < dwc->num_event_buffers; n++) { 245 evt = dwc->ev_buffs[n]; 246 247 evt->lpos = 0; 248 249 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 250 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 251 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 252 | DWC3_GEVNTSIZ_SIZE(0)); 253 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 254 } 255} 256 257static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 258{ 259 if (!dwc->has_hibernation) 260 return 0; 261 262 if (!dwc->nr_scratch) 263 return 0; 264 265 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 266 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 267 if (!dwc->scratchbuf) 268 return -ENOMEM; 269 270 return 0; 271} 272 273static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 274{ 275 dma_addr_t scratch_addr; 276 u32 param; 277 int ret; 278 279 if (!dwc->has_hibernation) 280 return 0; 281 282 if (!dwc->nr_scratch) 283 return 0; 284 285 /* should never fall here */ 286 if (!WARN_ON(dwc->scratchbuf)) 287 return 0; 288 289 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, 290 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 291 DMA_BIDIRECTIONAL); 292 if (dma_mapping_error(dwc->dev, scratch_addr)) { 293 dev_err(dwc->dev, "failed to map scratch buffer\n"); 294 ret = -EFAULT; 295 goto err0; 296 } 297 298 dwc->scratch_addr = scratch_addr; 299 300 param = lower_32_bits(scratch_addr); 301 302 ret = dwc3_send_gadget_generic_command(dwc, 303 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 304 if (ret < 0) 305 goto err1; 306 307 param = upper_32_bits(scratch_addr); 308 309 ret = dwc3_send_gadget_generic_command(dwc, 310 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 311 if (ret < 0) 312 goto err1; 313 314 return 0; 315 316err1: 317 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 318 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 319 320err0: 321 return ret; 322} 323 324static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 325{ 326 if (!dwc->has_hibernation) 327 return; 328 329 if (!dwc->nr_scratch) 330 return; 331 332 /* should never fall here */ 333 if (!WARN_ON(dwc->scratchbuf)) 334 return; 335 336 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 337 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 338 kfree(dwc->scratchbuf); 339} 340 341static void dwc3_core_num_eps(struct dwc3 *dwc) 342{ 343 struct dwc3_hwparams *parms = &dwc->hwparams; 344 345 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 346 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 347 348 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", 349 dwc->num_in_eps, dwc->num_out_eps); 350} 351 352static void dwc3_cache_hwparams(struct dwc3 *dwc) 353{ 354 struct dwc3_hwparams *parms = &dwc->hwparams; 355 356 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 357 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 358 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 359 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 360 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 361 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 362 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 363 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 364 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 365} 366 367/** 368 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 369 * @dwc: Pointer to our controller context structure 370 */ 371static void dwc3_phy_setup(struct dwc3 *dwc) 372{ 373 u32 reg; 374 375 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 376 377 /* 378 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 379 * to '0' during coreConsultant configuration. So default value 380 * will be '0' when the core is reset. Application needs to set it 381 * to '1' after the core initialization is completed. 382 */ 383 if (dwc->revision > DWC3_REVISION_194A) 384 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 385 386 if (dwc->u2ss_inp3_quirk) 387 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 388 389 if (dwc->req_p1p2p3_quirk) 390 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 391 392 if (dwc->del_p1p2p3_quirk) 393 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 394 395 if (dwc->del_phy_power_chg_quirk) 396 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 397 398 if (dwc->lfps_filter_quirk) 399 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 400 401 if (dwc->rx_detect_poll_quirk) 402 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 403 404 if (dwc->tx_de_emphasis_quirk) 405 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 406 407 if (dwc->dis_u3_susphy_quirk) 408 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 409 410 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 411 412 mdelay(100); 413 414 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 415 416 /* 417 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 418 * '0' during coreConsultant configuration. So default value will 419 * be '0' when the core is reset. Application needs to set it to 420 * '1' after the core initialization is completed. 421 */ 422 if (dwc->revision > DWC3_REVISION_194A) 423 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 424 425 if (dwc->dis_u2_susphy_quirk) 426 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 427 428 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 429 430 mdelay(100); 431} 432 433/** 434 * dwc3_core_init - Low-level initialization of DWC3 Core 435 * @dwc: Pointer to our controller context structure 436 * 437 * Returns 0 on success otherwise negative errno. 438 */ 439static int dwc3_core_init(struct dwc3 *dwc) 440{ 441 unsigned long timeout; 442 u32 hwparams4 = dwc->hwparams.hwparams4; 443 u32 reg; 444 int ret; 445 446 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 447 /* This should read as U3 followed by revision number */ 448 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 449 /* Detected DWC_usb3 IP */ 450 dwc->revision = reg; 451 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 452 /* Detected DWC_usb31 IP */ 453 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 454 dwc->revision |= DWC3_REVISION_IS_DWC31; 455 } else { 456 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 457 ret = -ENODEV; 458 goto err0; 459 } 460 461 /* 462 * Write Linux Version Code to our GUID register so it's easy to figure 463 * out which kernel version a bug was found. 464 */ 465 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 466 467 /* Handle USB2.0-only core configuration */ 468 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 469 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 470 if (dwc->maximum_speed == USB_SPEED_SUPER) 471 dwc->maximum_speed = USB_SPEED_HIGH; 472 } 473 474 /* issue device SoftReset too */ 475 timeout = jiffies + msecs_to_jiffies(500); 476 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 477 do { 478 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 479 if (!(reg & DWC3_DCTL_CSFTRST)) 480 break; 481 482 if (time_after(jiffies, timeout)) { 483 dev_err(dwc->dev, "Reset Timed Out\n"); 484 ret = -ETIMEDOUT; 485 goto err0; 486 } 487 488 cpu_relax(); 489 } while (true); 490 491 ret = dwc3_core_soft_reset(dwc); 492 if (ret) 493 goto err0; 494 495 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 496 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 497 498 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 499 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 500 /** 501 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 502 * issue which would cause xHCI compliance tests to fail. 503 * 504 * Because of that we cannot enable clock gating on such 505 * configurations. 506 * 507 * Refers to: 508 * 509 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 510 * SOF/ITP Mode Used 511 */ 512 if ((dwc->dr_mode == USB_DR_MODE_HOST || 513 dwc->dr_mode == USB_DR_MODE_OTG) && 514 (dwc->revision >= DWC3_REVISION_210A && 515 dwc->revision <= DWC3_REVISION_250A)) 516 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 517 else 518 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 519 break; 520 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 521 /* enable hibernation here */ 522 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 523 524 /* 525 * REVISIT Enabling this bit so that host-mode hibernation 526 * will work. Device-mode hibernation is not yet implemented. 527 */ 528 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 529 break; 530 default: 531 dev_dbg(dwc->dev, "No power optimization available\n"); 532 } 533 534 /* check if current dwc3 is on simulation board */ 535 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 536 dev_dbg(dwc->dev, "it is on FPGA board\n"); 537 dwc->is_fpga = true; 538 } 539 540 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 541 "disable_scramble cannot be used on non-FPGA builds\n"); 542 543 if (dwc->disable_scramble_quirk && dwc->is_fpga) 544 reg |= DWC3_GCTL_DISSCRAMBLE; 545 else 546 reg &= ~DWC3_GCTL_DISSCRAMBLE; 547 548 if (dwc->u2exit_lfps_quirk) 549 reg |= DWC3_GCTL_U2EXIT_LFPS; 550 551 /* 552 * WORKAROUND: DWC3 revisions <1.90a have a bug 553 * where the device can fail to connect at SuperSpeed 554 * and falls back to high-speed mode which causes 555 * the device to enter a Connect/Disconnect loop 556 */ 557 if (dwc->revision < DWC3_REVISION_190A) 558 reg |= DWC3_GCTL_U2RSTECN; 559 560 dwc3_core_num_eps(dwc); 561 562 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 563 564 dwc3_phy_setup(dwc); 565 566 ret = dwc3_alloc_scratch_buffers(dwc); 567 if (ret) 568 goto err1; 569 570 ret = dwc3_setup_scratch_buffers(dwc); 571 if (ret) 572 goto err2; 573 574 return 0; 575 576err2: 577 dwc3_free_scratch_buffers(dwc); 578 579err1: 580 usb_phy_shutdown(dwc->usb2_phy); 581 usb_phy_shutdown(dwc->usb3_phy); 582 phy_exit(dwc->usb2_generic_phy); 583 phy_exit(dwc->usb3_generic_phy); 584 585err0: 586 return ret; 587} 588 589static void dwc3_core_exit(struct dwc3 *dwc) 590{ 591 dwc3_free_scratch_buffers(dwc); 592 usb_phy_shutdown(dwc->usb2_phy); 593 usb_phy_shutdown(dwc->usb3_phy); 594 phy_exit(dwc->usb2_generic_phy); 595 phy_exit(dwc->usb3_generic_phy); 596} 597 598static int dwc3_core_get_phy(struct dwc3 *dwc) 599{ 600 struct device *dev = dwc->dev; 601 struct device_node *node = dev->of_node; 602 int ret; 603 604 if (node) { 605 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 606 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 607 } else { 608 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 609 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 610 } 611 612 if (IS_ERR(dwc->usb2_phy)) { 613 ret = PTR_ERR(dwc->usb2_phy); 614 if (ret == -ENXIO || ret == -ENODEV) { 615 dwc->usb2_phy = NULL; 616 } else if (ret == -EPROBE_DEFER) { 617 return ret; 618 } else { 619 dev_err(dev, "no usb2 phy configured\n"); 620 return ret; 621 } 622 } 623 624 if (IS_ERR(dwc->usb3_phy)) { 625 ret = PTR_ERR(dwc->usb3_phy); 626 if (ret == -ENXIO || ret == -ENODEV) { 627 dwc->usb3_phy = NULL; 628 } else if (ret == -EPROBE_DEFER) { 629 return ret; 630 } else { 631 dev_err(dev, "no usb3 phy configured\n"); 632 return ret; 633 } 634 } 635 636 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 637 if (IS_ERR(dwc->usb2_generic_phy)) { 638 ret = PTR_ERR(dwc->usb2_generic_phy); 639 if (ret == -ENOSYS || ret == -ENODEV) { 640 dwc->usb2_generic_phy = NULL; 641 } else if (ret == -EPROBE_DEFER) { 642 return ret; 643 } else { 644 dev_err(dev, "no usb2 phy configured\n"); 645 return ret; 646 } 647 } 648 649 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 650 if (IS_ERR(dwc->usb3_generic_phy)) { 651 ret = PTR_ERR(dwc->usb3_generic_phy); 652 if (ret == -ENOSYS || ret == -ENODEV) { 653 dwc->usb3_generic_phy = NULL; 654 } else if (ret == -EPROBE_DEFER) { 655 return ret; 656 } else { 657 dev_err(dev, "no usb3 phy configured\n"); 658 return ret; 659 } 660 } 661 662 return 0; 663} 664 665static int dwc3_core_init_mode(struct dwc3 *dwc) 666{ 667 struct device *dev = dwc->dev; 668 int ret; 669 670 switch (dwc->dr_mode) { 671 case USB_DR_MODE_PERIPHERAL: 672 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 673 ret = dwc3_gadget_init(dwc); 674 if (ret) { 675 dev_err(dev, "failed to initialize gadget\n"); 676 return ret; 677 } 678 break; 679 case USB_DR_MODE_HOST: 680 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 681 ret = dwc3_host_init(dwc); 682 if (ret) { 683 dev_err(dev, "failed to initialize host\n"); 684 return ret; 685 } 686 break; 687 case USB_DR_MODE_OTG: 688 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 689 ret = dwc3_host_init(dwc); 690 if (ret) { 691 dev_err(dev, "failed to initialize host\n"); 692 return ret; 693 } 694 695 ret = dwc3_gadget_init(dwc); 696 if (ret) { 697 dev_err(dev, "failed to initialize gadget\n"); 698 return ret; 699 } 700 break; 701 default: 702 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 703 return -EINVAL; 704 } 705 706 return 0; 707} 708 709static void dwc3_core_exit_mode(struct dwc3 *dwc) 710{ 711 switch (dwc->dr_mode) { 712 case USB_DR_MODE_PERIPHERAL: 713 dwc3_gadget_exit(dwc); 714 break; 715 case USB_DR_MODE_HOST: 716 dwc3_host_exit(dwc); 717 break; 718 case USB_DR_MODE_OTG: 719 dwc3_host_exit(dwc); 720 dwc3_gadget_exit(dwc); 721 break; 722 default: 723 /* do nothing */ 724 break; 725 } 726} 727 728#define DWC3_ALIGN_MASK (16 - 1) 729 730static int dwc3_probe(struct platform_device *pdev) 731{ 732 struct device *dev = &pdev->dev; 733 struct dwc3_platform_data *pdata = dev_get_platdata(dev); 734 struct device_node *node = dev->of_node; 735 struct resource *res; 736 struct dwc3 *dwc; 737 u8 lpm_nyet_threshold; 738 u8 tx_de_emphasis; 739 u8 hird_threshold; 740 741 int ret; 742 743 void __iomem *regs; 744 void *mem; 745 746 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 747 if (!mem) 748 return -ENOMEM; 749 750 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 751 dwc->mem = mem; 752 dwc->dev = dev; 753 754 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 755 if (!res) { 756 dev_err(dev, "missing IRQ\n"); 757 return -ENODEV; 758 } 759 dwc->xhci_resources[1].start = res->start; 760 dwc->xhci_resources[1].end = res->end; 761 dwc->xhci_resources[1].flags = res->flags; 762 dwc->xhci_resources[1].name = res->name; 763 764 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 765 if (!res) { 766 dev_err(dev, "missing memory resource\n"); 767 return -ENODEV; 768 } 769 770 dwc->xhci_resources[0].start = res->start; 771 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 772 DWC3_XHCI_REGS_END; 773 dwc->xhci_resources[0].flags = res->flags; 774 dwc->xhci_resources[0].name = res->name; 775 776 res->start += DWC3_GLOBALS_REGS_START; 777 778 /* 779 * Request memory region but exclude xHCI regs, 780 * since it will be requested by the xhci-plat driver. 781 */ 782 regs = devm_ioremap_resource(dev, res); 783 if (IS_ERR(regs)) { 784 ret = PTR_ERR(regs); 785 goto err0; 786 } 787 788 dwc->regs = regs; 789 dwc->regs_size = resource_size(res); 790 791 /* default to highest possible threshold */ 792 lpm_nyet_threshold = 0xff; 793 794 /* default to -3.5dB de-emphasis */ 795 tx_de_emphasis = 1; 796 797 /* 798 * default to assert utmi_sleep_n and use maximum allowed HIRD 799 * threshold value of 0b1100 800 */ 801 hird_threshold = 12; 802 803 if (node) { 804 dwc->maximum_speed = of_usb_get_maximum_speed(node); 805 dwc->has_lpm_erratum = of_property_read_bool(node, 806 "snps,has-lpm-erratum"); 807 of_property_read_u8(node, "snps,lpm-nyet-threshold", 808 &lpm_nyet_threshold); 809 dwc->is_utmi_l1_suspend = of_property_read_bool(node, 810 "snps,is-utmi-l1-suspend"); 811 of_property_read_u8(node, "snps,hird-threshold", 812 &hird_threshold); 813 dwc->usb3_lpm_capable = of_property_read_bool(node, 814 "snps,usb3_lpm_capable"); 815 816 dwc->needs_fifo_resize = of_property_read_bool(node, 817 "tx-fifo-resize"); 818 dwc->dr_mode = of_usb_get_dr_mode(node); 819 820 dwc->disable_scramble_quirk = of_property_read_bool(node, 821 "snps,disable_scramble_quirk"); 822 dwc->u2exit_lfps_quirk = of_property_read_bool(node, 823 "snps,u2exit_lfps_quirk"); 824 dwc->u2ss_inp3_quirk = of_property_read_bool(node, 825 "snps,u2ss_inp3_quirk"); 826 dwc->req_p1p2p3_quirk = of_property_read_bool(node, 827 "snps,req_p1p2p3_quirk"); 828 dwc->del_p1p2p3_quirk = of_property_read_bool(node, 829 "snps,del_p1p2p3_quirk"); 830 dwc->del_phy_power_chg_quirk = of_property_read_bool(node, 831 "snps,del_phy_power_chg_quirk"); 832 dwc->lfps_filter_quirk = of_property_read_bool(node, 833 "snps,lfps_filter_quirk"); 834 dwc->rx_detect_poll_quirk = of_property_read_bool(node, 835 "snps,rx_detect_poll_quirk"); 836 dwc->dis_u3_susphy_quirk = of_property_read_bool(node, 837 "snps,dis_u3_susphy_quirk"); 838 dwc->dis_u2_susphy_quirk = of_property_read_bool(node, 839 "snps,dis_u2_susphy_quirk"); 840 841 dwc->tx_de_emphasis_quirk = of_property_read_bool(node, 842 "snps,tx_de_emphasis_quirk"); 843 of_property_read_u8(node, "snps,tx_de_emphasis", 844 &tx_de_emphasis); 845 } else if (pdata) { 846 dwc->maximum_speed = pdata->maximum_speed; 847 dwc->has_lpm_erratum = pdata->has_lpm_erratum; 848 if (pdata->lpm_nyet_threshold) 849 lpm_nyet_threshold = pdata->lpm_nyet_threshold; 850 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; 851 if (pdata->hird_threshold) 852 hird_threshold = pdata->hird_threshold; 853 854 dwc->needs_fifo_resize = pdata->tx_fifo_resize; 855 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable; 856 dwc->dr_mode = pdata->dr_mode; 857 858 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; 859 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; 860 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; 861 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; 862 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; 863 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; 864 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; 865 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; 866 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; 867 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; 868 869 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; 870 if (pdata->tx_de_emphasis) 871 tx_de_emphasis = pdata->tx_de_emphasis; 872 } 873 874 /* default to superspeed if no maximum_speed passed */ 875 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 876 dwc->maximum_speed = USB_SPEED_SUPER; 877 878 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 879 dwc->tx_de_emphasis = tx_de_emphasis; 880 881 dwc->hird_threshold = hird_threshold 882 | (dwc->is_utmi_l1_suspend << 4); 883 884 ret = dwc3_core_get_phy(dwc); 885 if (ret) 886 goto err0; 887 888 spin_lock_init(&dwc->lock); 889 platform_set_drvdata(pdev, dwc); 890 891 if (!dev->dma_mask) { 892 dev->dma_mask = dev->parent->dma_mask; 893 dev->dma_parms = dev->parent->dma_parms; 894 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); 895 } 896 897 pm_runtime_enable(dev); 898 pm_runtime_get_sync(dev); 899 pm_runtime_forbid(dev); 900 901 dwc3_cache_hwparams(dwc); 902 903 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 904 if (ret) { 905 dev_err(dwc->dev, "failed to allocate event buffers\n"); 906 ret = -ENOMEM; 907 goto err1; 908 } 909 910 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 911 dwc->dr_mode = USB_DR_MODE_HOST; 912 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 913 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 914 915 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 916 dwc->dr_mode = USB_DR_MODE_OTG; 917 918 ret = dwc3_core_init(dwc); 919 if (ret) { 920 dev_err(dev, "failed to initialize core\n"); 921 goto err1; 922 } 923 924 usb_phy_set_suspend(dwc->usb2_phy, 0); 925 usb_phy_set_suspend(dwc->usb3_phy, 0); 926 ret = phy_power_on(dwc->usb2_generic_phy); 927 if (ret < 0) 928 goto err2; 929 930 ret = phy_power_on(dwc->usb3_generic_phy); 931 if (ret < 0) 932 goto err3; 933 934 ret = dwc3_event_buffers_setup(dwc); 935 if (ret) { 936 dev_err(dwc->dev, "failed to setup event buffers\n"); 937 goto err4; 938 } 939 940 ret = dwc3_core_init_mode(dwc); 941 if (ret) 942 goto err5; 943 944 ret = dwc3_debugfs_init(dwc); 945 if (ret) { 946 dev_err(dev, "failed to initialize debugfs\n"); 947 goto err6; 948 } 949 950 pm_runtime_allow(dev); 951 952 return 0; 953 954err6: 955 dwc3_core_exit_mode(dwc); 956 957err5: 958 dwc3_event_buffers_cleanup(dwc); 959 960err4: 961 phy_power_off(dwc->usb3_generic_phy); 962 963err3: 964 phy_power_off(dwc->usb2_generic_phy); 965 966err2: 967 usb_phy_set_suspend(dwc->usb2_phy, 1); 968 usb_phy_set_suspend(dwc->usb3_phy, 1); 969 dwc3_core_exit(dwc); 970 971err1: 972 dwc3_free_event_buffers(dwc); 973 974err0: 975 /* 976 * restore res->start back to its original value so that, in case the 977 * probe is deferred, we don't end up getting error in request the 978 * memory region the next time probe is called. 979 */ 980 res->start -= DWC3_GLOBALS_REGS_START; 981 982 return ret; 983} 984 985static int dwc3_remove(struct platform_device *pdev) 986{ 987 struct dwc3 *dwc = platform_get_drvdata(pdev); 988 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 989 990 /* 991 * restore res->start back to its original value so that, in case the 992 * probe is deferred, we don't end up getting error in request the 993 * memory region the next time probe is called. 994 */ 995 res->start -= DWC3_GLOBALS_REGS_START; 996 997 dwc3_debugfs_exit(dwc); 998 dwc3_core_exit_mode(dwc); 999 dwc3_event_buffers_cleanup(dwc); 1000 dwc3_free_event_buffers(dwc); 1001 1002 usb_phy_set_suspend(dwc->usb2_phy, 1); 1003 usb_phy_set_suspend(dwc->usb3_phy, 1); 1004 phy_power_off(dwc->usb2_generic_phy); 1005 phy_power_off(dwc->usb3_generic_phy); 1006 1007 dwc3_core_exit(dwc); 1008 1009 pm_runtime_put_sync(&pdev->dev); 1010 pm_runtime_disable(&pdev->dev); 1011 1012 return 0; 1013} 1014 1015#ifdef CONFIG_PM_SLEEP 1016static int dwc3_suspend(struct device *dev) 1017{ 1018 struct dwc3 *dwc = dev_get_drvdata(dev); 1019 unsigned long flags; 1020 1021 spin_lock_irqsave(&dwc->lock, flags); 1022 1023 switch (dwc->dr_mode) { 1024 case USB_DR_MODE_PERIPHERAL: 1025 case USB_DR_MODE_OTG: 1026 dwc3_gadget_suspend(dwc); 1027 /* FALLTHROUGH */ 1028 case USB_DR_MODE_HOST: 1029 default: 1030 dwc3_event_buffers_cleanup(dwc); 1031 break; 1032 } 1033 1034 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); 1035 spin_unlock_irqrestore(&dwc->lock, flags); 1036 1037 usb_phy_shutdown(dwc->usb3_phy); 1038 usb_phy_shutdown(dwc->usb2_phy); 1039 phy_exit(dwc->usb2_generic_phy); 1040 phy_exit(dwc->usb3_generic_phy); 1041 1042 return 0; 1043} 1044 1045static int dwc3_resume(struct device *dev) 1046{ 1047 struct dwc3 *dwc = dev_get_drvdata(dev); 1048 unsigned long flags; 1049 int ret; 1050 1051 usb_phy_init(dwc->usb3_phy); 1052 usb_phy_init(dwc->usb2_phy); 1053 ret = phy_init(dwc->usb2_generic_phy); 1054 if (ret < 0) 1055 return ret; 1056 1057 ret = phy_init(dwc->usb3_generic_phy); 1058 if (ret < 0) 1059 goto err_usb2phy_init; 1060 1061 spin_lock_irqsave(&dwc->lock, flags); 1062 1063 dwc3_event_buffers_setup(dwc); 1064 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); 1065 1066 switch (dwc->dr_mode) { 1067 case USB_DR_MODE_PERIPHERAL: 1068 case USB_DR_MODE_OTG: 1069 dwc3_gadget_resume(dwc); 1070 /* FALLTHROUGH */ 1071 case USB_DR_MODE_HOST: 1072 default: 1073 /* do nothing */ 1074 break; 1075 } 1076 1077 spin_unlock_irqrestore(&dwc->lock, flags); 1078 1079 pm_runtime_disable(dev); 1080 pm_runtime_set_active(dev); 1081 pm_runtime_enable(dev); 1082 1083 return 0; 1084 1085err_usb2phy_init: 1086 phy_exit(dwc->usb2_generic_phy); 1087 1088 return ret; 1089} 1090 1091static const struct dev_pm_ops dwc3_dev_pm_ops = { 1092 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1093}; 1094 1095#define DWC3_PM_OPS &(dwc3_dev_pm_ops) 1096#else 1097#define DWC3_PM_OPS NULL 1098#endif 1099 1100#ifdef CONFIG_OF 1101static const struct of_device_id of_dwc3_match[] = { 1102 { 1103 .compatible = "snps,dwc3" 1104 }, 1105 { 1106 .compatible = "synopsys,dwc3" 1107 }, 1108 { }, 1109}; 1110MODULE_DEVICE_TABLE(of, of_dwc3_match); 1111#endif 1112 1113#ifdef CONFIG_ACPI 1114 1115#define ACPI_ID_INTEL_BSW "808622B7" 1116 1117static const struct acpi_device_id dwc3_acpi_match[] = { 1118 { ACPI_ID_INTEL_BSW, 0 }, 1119 { }, 1120}; 1121MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1122#endif 1123 1124static struct platform_driver dwc3_driver = { 1125 .probe = dwc3_probe, 1126 .remove = dwc3_remove, 1127 .driver = { 1128 .name = "dwc3", 1129 .of_match_table = of_match_ptr(of_dwc3_match), 1130 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1131 .pm = DWC3_PM_OPS, 1132 }, 1133}; 1134 1135module_platform_driver(dwc3_driver); 1136 1137MODULE_ALIAS("platform:dwc3"); 1138MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1139MODULE_LICENSE("GPL v2"); 1140MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1141