1/* 2 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Author: Li Yang <leoli@freescale.com> 6 * Jiang Bo <tanya.jiang@freescale.com> 7 * 8 * Description: 9 * Freescale high-speed USB SOC DR module device controller driver. 10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus. 11 * The driver is previously named as mpc_udc. Based on bare board 12 * code from Dave Liu and Shlomi Gridish. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 */ 19 20#undef VERBOSE 21 22#include <linux/module.h> 23#include <linux/kernel.h> 24#include <linux/ioport.h> 25#include <linux/types.h> 26#include <linux/errno.h> 27#include <linux/err.h> 28#include <linux/slab.h> 29#include <linux/init.h> 30#include <linux/list.h> 31#include <linux/interrupt.h> 32#include <linux/proc_fs.h> 33#include <linux/mm.h> 34#include <linux/moduleparam.h> 35#include <linux/device.h> 36#include <linux/usb/ch9.h> 37#include <linux/usb/gadget.h> 38#include <linux/usb/otg.h> 39#include <linux/dma-mapping.h> 40#include <linux/platform_device.h> 41#include <linux/fsl_devices.h> 42#include <linux/dmapool.h> 43#include <linux/delay.h> 44#include <linux/of_device.h> 45 46#include <asm/byteorder.h> 47#include <asm/io.h> 48#include <asm/unaligned.h> 49#include <asm/dma.h> 50 51#include "fsl_usb2_udc.h" 52 53#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver" 54#define DRIVER_AUTHOR "Li Yang/Jiang Bo" 55#define DRIVER_VERSION "Apr 20, 2007" 56 57#define DMA_ADDR_INVALID (~(dma_addr_t)0) 58 59static const char driver_name[] = "fsl-usb2-udc"; 60static const char driver_desc[] = DRIVER_DESC; 61 62static struct usb_dr_device __iomem *dr_regs; 63 64static struct usb_sys_interface __iomem *usb_sys_regs; 65 66/* it is initialized in probe() */ 67static struct fsl_udc *udc_controller = NULL; 68 69static const struct usb_endpoint_descriptor 70fsl_ep0_desc = { 71 .bLength = USB_DT_ENDPOINT_SIZE, 72 .bDescriptorType = USB_DT_ENDPOINT, 73 .bEndpointAddress = 0, 74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD, 76}; 77 78static void fsl_ep_fifo_flush(struct usb_ep *_ep); 79 80#ifdef CONFIG_PPC32 81/* 82 * On some SoCs, the USB controller registers can be big or little endian, 83 * depending on the version of the chip. In order to be able to run the 84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision 85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the 86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel() 87 * call through those pointers. Platform code for SoCs that have BE USB 88 * registers should set pdata->big_endian_mmio flag. 89 * 90 * This also applies to controller-to-cpu accessors for the USB descriptors, 91 * since their endianness is also SoC dependant. Platform code for SoCs that 92 * have BE USB descriptors should set pdata->big_endian_desc flag. 93 */ 94static u32 _fsl_readl_be(const unsigned __iomem *p) 95{ 96 return in_be32(p); 97} 98 99static u32 _fsl_readl_le(const unsigned __iomem *p) 100{ 101 return in_le32(p); 102} 103 104static void _fsl_writel_be(u32 v, unsigned __iomem *p) 105{ 106 out_be32(p, v); 107} 108 109static void _fsl_writel_le(u32 v, unsigned __iomem *p) 110{ 111 out_le32(p, v); 112} 113 114static u32 (*_fsl_readl)(const unsigned __iomem *p); 115static void (*_fsl_writel)(u32 v, unsigned __iomem *p); 116 117#define fsl_readl(p) (*_fsl_readl)((p)) 118#define fsl_writel(v, p) (*_fsl_writel)((v), (p)) 119 120static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) 121{ 122 if (pdata->big_endian_mmio) { 123 _fsl_readl = _fsl_readl_be; 124 _fsl_writel = _fsl_writel_be; 125 } else { 126 _fsl_readl = _fsl_readl_le; 127 _fsl_writel = _fsl_writel_le; 128 } 129} 130 131static inline u32 cpu_to_hc32(const u32 x) 132{ 133 return udc_controller->pdata->big_endian_desc 134 ? (__force u32)cpu_to_be32(x) 135 : (__force u32)cpu_to_le32(x); 136} 137 138static inline u32 hc32_to_cpu(const u32 x) 139{ 140 return udc_controller->pdata->big_endian_desc 141 ? be32_to_cpu((__force __be32)x) 142 : le32_to_cpu((__force __le32)x); 143} 144#else /* !CONFIG_PPC32 */ 145static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {} 146 147#define fsl_readl(addr) readl(addr) 148#define fsl_writel(val32, addr) writel(val32, addr) 149#define cpu_to_hc32(x) cpu_to_le32(x) 150#define hc32_to_cpu(x) le32_to_cpu(x) 151#endif /* CONFIG_PPC32 */ 152 153/******************************************************************** 154 * Internal Used Function 155********************************************************************/ 156/*----------------------------------------------------------------- 157 * done() - retire a request; caller blocked irqs 158 * @status : request status to be set, only works when 159 * request is still in progress. 160 *--------------------------------------------------------------*/ 161static void done(struct fsl_ep *ep, struct fsl_req *req, int status) 162__releases(ep->udc->lock) 163__acquires(ep->udc->lock) 164{ 165 struct fsl_udc *udc = NULL; 166 unsigned char stopped = ep->stopped; 167 struct ep_td_struct *curr_td, *next_td; 168 int j; 169 170 udc = (struct fsl_udc *)ep->udc; 171 /* Removed the req from fsl_ep->queue */ 172 list_del_init(&req->queue); 173 174 /* req.status should be set as -EINPROGRESS in ep_queue() */ 175 if (req->req.status == -EINPROGRESS) 176 req->req.status = status; 177 else 178 status = req->req.status; 179 180 /* Free dtd for the request */ 181 next_td = req->head; 182 for (j = 0; j < req->dtd_count; j++) { 183 curr_td = next_td; 184 if (j != req->dtd_count - 1) { 185 next_td = curr_td->next_td_virt; 186 } 187 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma); 188 } 189 190 usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep)); 191 192 if (status && (status != -ESHUTDOWN)) 193 VDBG("complete %s req %p stat %d len %u/%u", 194 ep->ep.name, &req->req, status, 195 req->req.actual, req->req.length); 196 197 ep->stopped = 1; 198 199 spin_unlock(&ep->udc->lock); 200 201 usb_gadget_giveback_request(&ep->ep, &req->req); 202 203 spin_lock(&ep->udc->lock); 204 ep->stopped = stopped; 205} 206 207/*----------------------------------------------------------------- 208 * nuke(): delete all requests related to this ep 209 * called with spinlock held 210 *--------------------------------------------------------------*/ 211static void nuke(struct fsl_ep *ep, int status) 212{ 213 ep->stopped = 1; 214 215 /* Flush fifo */ 216 fsl_ep_fifo_flush(&ep->ep); 217 218 /* Whether this eq has request linked */ 219 while (!list_empty(&ep->queue)) { 220 struct fsl_req *req = NULL; 221 222 req = list_entry(ep->queue.next, struct fsl_req, queue); 223 done(ep, req, status); 224 } 225} 226 227/*------------------------------------------------------------------ 228 Internal Hardware related function 229 ------------------------------------------------------------------*/ 230 231static int dr_controller_setup(struct fsl_udc *udc) 232{ 233 unsigned int tmp, portctrl, ep_num; 234 unsigned int max_no_of_ep; 235 unsigned int ctrl; 236 unsigned long timeout; 237 238#define FSL_UDC_RESET_TIMEOUT 1000 239 240 /* Config PHY interface */ 241 portctrl = fsl_readl(&dr_regs->portsc1); 242 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH); 243 switch (udc->phy_mode) { 244 case FSL_USB2_PHY_ULPI: 245 if (udc->pdata->have_sysif_regs) { 246 if (udc->pdata->controller_ver) { 247 /* controller version 1.6 or above */ 248 ctrl = __raw_readl(&usb_sys_regs->control); 249 ctrl &= ~USB_CTRL_UTMI_PHY_EN; 250 ctrl |= USB_CTRL_USB_EN; 251 __raw_writel(ctrl, &usb_sys_regs->control); 252 } 253 } 254 portctrl |= PORTSCX_PTS_ULPI; 255 break; 256 case FSL_USB2_PHY_UTMI_WIDE: 257 portctrl |= PORTSCX_PTW_16BIT; 258 /* fall through */ 259 case FSL_USB2_PHY_UTMI: 260 if (udc->pdata->have_sysif_regs) { 261 if (udc->pdata->controller_ver) { 262 /* controller version 1.6 or above */ 263 ctrl = __raw_readl(&usb_sys_regs->control); 264 ctrl |= (USB_CTRL_UTMI_PHY_EN | 265 USB_CTRL_USB_EN); 266 __raw_writel(ctrl, &usb_sys_regs->control); 267 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI 268 PHY CLK to become stable - 10ms*/ 269 } 270 } 271 portctrl |= PORTSCX_PTS_UTMI; 272 break; 273 case FSL_USB2_PHY_SERIAL: 274 portctrl |= PORTSCX_PTS_FSLS; 275 break; 276 default: 277 return -EINVAL; 278 } 279 fsl_writel(portctrl, &dr_regs->portsc1); 280 281 /* Stop and reset the usb controller */ 282 tmp = fsl_readl(&dr_regs->usbcmd); 283 tmp &= ~USB_CMD_RUN_STOP; 284 fsl_writel(tmp, &dr_regs->usbcmd); 285 286 tmp = fsl_readl(&dr_regs->usbcmd); 287 tmp |= USB_CMD_CTRL_RESET; 288 fsl_writel(tmp, &dr_regs->usbcmd); 289 290 /* Wait for reset to complete */ 291 timeout = jiffies + FSL_UDC_RESET_TIMEOUT; 292 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) { 293 if (time_after(jiffies, timeout)) { 294 ERR("udc reset timeout!\n"); 295 return -ETIMEDOUT; 296 } 297 cpu_relax(); 298 } 299 300 /* Set the controller as device mode */ 301 tmp = fsl_readl(&dr_regs->usbmode); 302 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */ 303 tmp |= USB_MODE_CTRL_MODE_DEVICE; 304 /* Disable Setup Lockout */ 305 tmp |= USB_MODE_SETUP_LOCK_OFF; 306 if (udc->pdata->es) 307 tmp |= USB_MODE_ES; 308 fsl_writel(tmp, &dr_regs->usbmode); 309 310 /* Clear the setup status */ 311 fsl_writel(0, &dr_regs->usbsts); 312 313 tmp = udc->ep_qh_dma; 314 tmp &= USB_EP_LIST_ADDRESS_MASK; 315 fsl_writel(tmp, &dr_regs->endpointlistaddr); 316 317 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x", 318 udc->ep_qh, (int)tmp, 319 fsl_readl(&dr_regs->endpointlistaddr)); 320 321 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams)); 322 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) { 323 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]); 324 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE); 325 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT) 326 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT); 327 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]); 328 } 329 /* Config control enable i/o output, cpu endian register */ 330#ifndef CONFIG_ARCH_MXC 331 if (udc->pdata->have_sysif_regs) { 332 ctrl = __raw_readl(&usb_sys_regs->control); 333 ctrl |= USB_CTRL_IOENB; 334 __raw_writel(ctrl, &usb_sys_regs->control); 335 } 336#endif 337 338#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 339 /* Turn on cache snooping hardware, since some PowerPC platforms 340 * wholly rely on hardware to deal with cache coherent. */ 341 342 if (udc->pdata->have_sysif_regs) { 343 /* Setup Snooping for all the 4GB space */ 344 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ 345 __raw_writel(tmp, &usb_sys_regs->snoop1); 346 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ 347 __raw_writel(tmp, &usb_sys_regs->snoop2); 348 } 349#endif 350 351 return 0; 352} 353 354/* Enable DR irq and set controller to run state */ 355static void dr_controller_run(struct fsl_udc *udc) 356{ 357 u32 temp; 358 359 /* Enable DR irq reg */ 360 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN 361 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN 362 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN; 363 364 fsl_writel(temp, &dr_regs->usbintr); 365 366 /* Clear stopped bit */ 367 udc->stopped = 0; 368 369 /* Set the controller as device mode */ 370 temp = fsl_readl(&dr_regs->usbmode); 371 temp |= USB_MODE_CTRL_MODE_DEVICE; 372 fsl_writel(temp, &dr_regs->usbmode); 373 374 /* Set controller to Run */ 375 temp = fsl_readl(&dr_regs->usbcmd); 376 temp |= USB_CMD_RUN_STOP; 377 fsl_writel(temp, &dr_regs->usbcmd); 378} 379 380static void dr_controller_stop(struct fsl_udc *udc) 381{ 382 unsigned int tmp; 383 384 pr_debug("%s\n", __func__); 385 386 /* if we're in OTG mode, and the Host is currently using the port, 387 * stop now and don't rip the controller out from under the 388 * ehci driver 389 */ 390 if (udc->gadget.is_otg) { 391 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) { 392 pr_debug("udc: Leaving early\n"); 393 return; 394 } 395 } 396 397 /* disable all INTR */ 398 fsl_writel(0, &dr_regs->usbintr); 399 400 /* Set stopped bit for isr */ 401 udc->stopped = 1; 402 403 /* disable IO output */ 404/* usb_sys_regs->control = 0; */ 405 406 /* set controller to Stop */ 407 tmp = fsl_readl(&dr_regs->usbcmd); 408 tmp &= ~USB_CMD_RUN_STOP; 409 fsl_writel(tmp, &dr_regs->usbcmd); 410} 411 412static void dr_ep_setup(unsigned char ep_num, unsigned char dir, 413 unsigned char ep_type) 414{ 415 unsigned int tmp_epctrl = 0; 416 417 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 418 if (dir) { 419 if (ep_num) 420 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; 421 tmp_epctrl |= EPCTRL_TX_ENABLE; 422 tmp_epctrl &= ~EPCTRL_TX_TYPE; 423 tmp_epctrl |= ((unsigned int)(ep_type) 424 << EPCTRL_TX_EP_TYPE_SHIFT); 425 } else { 426 if (ep_num) 427 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; 428 tmp_epctrl |= EPCTRL_RX_ENABLE; 429 tmp_epctrl &= ~EPCTRL_RX_TYPE; 430 tmp_epctrl |= ((unsigned int)(ep_type) 431 << EPCTRL_RX_EP_TYPE_SHIFT); 432 } 433 434 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); 435} 436 437static void 438dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value) 439{ 440 u32 tmp_epctrl = 0; 441 442 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 443 444 if (value) { 445 /* set the stall bit */ 446 if (dir) 447 tmp_epctrl |= EPCTRL_TX_EP_STALL; 448 else 449 tmp_epctrl |= EPCTRL_RX_EP_STALL; 450 } else { 451 /* clear the stall bit and reset data toggle */ 452 if (dir) { 453 tmp_epctrl &= ~EPCTRL_TX_EP_STALL; 454 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST; 455 } else { 456 tmp_epctrl &= ~EPCTRL_RX_EP_STALL; 457 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST; 458 } 459 } 460 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]); 461} 462 463/* Get stall status of a specific ep 464 Return: 0: not stalled; 1:stalled */ 465static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir) 466{ 467 u32 epctrl; 468 469 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 470 if (dir) 471 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0; 472 else 473 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0; 474} 475 476/******************************************************************** 477 Internal Structure Build up functions 478********************************************************************/ 479 480/*------------------------------------------------------------------ 481* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH 482 * @zlt: Zero Length Termination Select (1: disable; 0: enable) 483 * @mult: Mult field 484 ------------------------------------------------------------------*/ 485static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num, 486 unsigned char dir, unsigned char ep_type, 487 unsigned int max_pkt_len, 488 unsigned int zlt, unsigned char mult) 489{ 490 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir]; 491 unsigned int tmp = 0; 492 493 /* set the Endpoint Capabilites in QH */ 494 switch (ep_type) { 495 case USB_ENDPOINT_XFER_CONTROL: 496 /* Interrupt On Setup (IOS). for control ep */ 497 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) 498 | EP_QUEUE_HEAD_IOS; 499 break; 500 case USB_ENDPOINT_XFER_ISOC: 501 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS) 502 | (mult << EP_QUEUE_HEAD_MULT_POS); 503 break; 504 case USB_ENDPOINT_XFER_BULK: 505 case USB_ENDPOINT_XFER_INT: 506 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS; 507 break; 508 default: 509 VDBG("error ep type is %d", ep_type); 510 return; 511 } 512 if (zlt) 513 tmp |= EP_QUEUE_HEAD_ZLT_SEL; 514 515 p_QH->max_pkt_length = cpu_to_hc32(tmp); 516 p_QH->next_dtd_ptr = 1; 517 p_QH->size_ioc_int_sts = 0; 518} 519 520/* Setup qh structure and ep register for ep0. */ 521static void ep0_setup(struct fsl_udc *udc) 522{ 523 /* the intialization of an ep includes: fields in QH, Regs, 524 * fsl_ep struct */ 525 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL, 526 USB_MAX_CTRL_PAYLOAD, 0, 0); 527 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL, 528 USB_MAX_CTRL_PAYLOAD, 0, 0); 529 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL); 530 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL); 531 532 return; 533 534} 535 536/*********************************************************************** 537 Endpoint Management Functions 538***********************************************************************/ 539 540/*------------------------------------------------------------------------- 541 * when configurations are set, or when interface settings change 542 * for example the do_set_interface() in gadget layer, 543 * the driver will enable or disable the relevant endpoints 544 * ep0 doesn't use this routine. It is always enabled. 545-------------------------------------------------------------------------*/ 546static int fsl_ep_enable(struct usb_ep *_ep, 547 const struct usb_endpoint_descriptor *desc) 548{ 549 struct fsl_udc *udc = NULL; 550 struct fsl_ep *ep = NULL; 551 unsigned short max = 0; 552 unsigned char mult = 0, zlt; 553 int retval = -EINVAL; 554 unsigned long flags = 0; 555 556 ep = container_of(_ep, struct fsl_ep, ep); 557 558 /* catch various bogus parameters */ 559 if (!_ep || !desc 560 || (desc->bDescriptorType != USB_DT_ENDPOINT)) 561 return -EINVAL; 562 563 udc = ep->udc; 564 565 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN)) 566 return -ESHUTDOWN; 567 568 max = usb_endpoint_maxp(desc); 569 570 /* Disable automatic zlp generation. Driver is responsible to indicate 571 * explicitly through req->req.zero. This is needed to enable multi-td 572 * request. */ 573 zlt = 1; 574 575 /* Assume the max packet size from gadget is always correct */ 576 switch (desc->bmAttributes & 0x03) { 577 case USB_ENDPOINT_XFER_CONTROL: 578 case USB_ENDPOINT_XFER_BULK: 579 case USB_ENDPOINT_XFER_INT: 580 /* mult = 0. Execute N Transactions as demonstrated by 581 * the USB variable length packet protocol where N is 582 * computed using the Maximum Packet Length (dQH) and 583 * the Total Bytes field (dTD) */ 584 mult = 0; 585 break; 586 case USB_ENDPOINT_XFER_ISOC: 587 /* Calculate transactions needed for high bandwidth iso */ 588 mult = (unsigned char)(1 + ((max >> 11) & 0x03)); 589 max = max & 0x7ff; /* bit 0~10 */ 590 /* 3 transactions at most */ 591 if (mult > 3) 592 goto en_done; 593 break; 594 default: 595 goto en_done; 596 } 597 598 spin_lock_irqsave(&udc->lock, flags); 599 ep->ep.maxpacket = max; 600 ep->ep.desc = desc; 601 ep->stopped = 0; 602 603 /* Controller related setup */ 604 /* Init EPx Queue Head (Ep Capabilites field in QH 605 * according to max, zlt, mult) */ 606 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep), 607 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) 608 ? USB_SEND : USB_RECV), 609 (unsigned char) (desc->bmAttributes 610 & USB_ENDPOINT_XFERTYPE_MASK), 611 max, zlt, mult); 612 613 /* Init endpoint ctrl register */ 614 dr_ep_setup((unsigned char) ep_index(ep), 615 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN) 616 ? USB_SEND : USB_RECV), 617 (unsigned char) (desc->bmAttributes 618 & USB_ENDPOINT_XFERTYPE_MASK)); 619 620 spin_unlock_irqrestore(&udc->lock, flags); 621 retval = 0; 622 623 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name, 624 ep->ep.desc->bEndpointAddress & 0x0f, 625 (desc->bEndpointAddress & USB_DIR_IN) 626 ? "in" : "out", max); 627en_done: 628 return retval; 629} 630 631/*--------------------------------------------------------------------- 632 * @ep : the ep being unconfigured. May not be ep0 633 * Any pending and uncomplete req will complete with status (-ESHUTDOWN) 634*---------------------------------------------------------------------*/ 635static int fsl_ep_disable(struct usb_ep *_ep) 636{ 637 struct fsl_udc *udc = NULL; 638 struct fsl_ep *ep = NULL; 639 unsigned long flags = 0; 640 u32 epctrl; 641 int ep_num; 642 643 ep = container_of(_ep, struct fsl_ep, ep); 644 if (!_ep || !ep->ep.desc) { 645 VDBG("%s not enabled", _ep ? ep->ep.name : NULL); 646 return -EINVAL; 647 } 648 649 /* disable ep on controller */ 650 ep_num = ep_index(ep); 651 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 652 if (ep_is_in(ep)) { 653 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE); 654 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT; 655 } else { 656 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE); 657 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT; 658 } 659 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 660 661 udc = (struct fsl_udc *)ep->udc; 662 spin_lock_irqsave(&udc->lock, flags); 663 664 /* nuke all pending requests (does flush) */ 665 nuke(ep, -ESHUTDOWN); 666 667 ep->ep.desc = NULL; 668 ep->stopped = 1; 669 spin_unlock_irqrestore(&udc->lock, flags); 670 671 VDBG("disabled %s OK", _ep->name); 672 return 0; 673} 674 675/*--------------------------------------------------------------------- 676 * allocate a request object used by this endpoint 677 * the main operation is to insert the req->queue to the eq->queue 678 * Returns the request, or null if one could not be allocated 679*---------------------------------------------------------------------*/ 680static struct usb_request * 681fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 682{ 683 struct fsl_req *req = NULL; 684 685 req = kzalloc(sizeof *req, gfp_flags); 686 if (!req) 687 return NULL; 688 689 req->req.dma = DMA_ADDR_INVALID; 690 INIT_LIST_HEAD(&req->queue); 691 692 return &req->req; 693} 694 695static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req) 696{ 697 struct fsl_req *req = NULL; 698 699 req = container_of(_req, struct fsl_req, req); 700 701 if (_req) 702 kfree(req); 703} 704 705/* Actually add a dTD chain to an empty dQH and let go */ 706static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td) 707{ 708 struct ep_queue_head *qh = get_qh_by_ep(ep); 709 710 /* Write dQH next pointer and terminate bit to 0 */ 711 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma 712 & EP_QUEUE_HEAD_NEXT_POINTER_MASK); 713 714 /* Clear active and halt bit */ 715 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE 716 | EP_QUEUE_HEAD_STATUS_HALT)); 717 718 /* Ensure that updates to the QH will occur before priming. */ 719 wmb(); 720 721 /* Prime endpoint by writing correct bit to ENDPTPRIME */ 722 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16)) 723 : (1 << (ep_index(ep))), &dr_regs->endpointprime); 724} 725 726/* Add dTD chain to the dQH of an EP */ 727static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) 728{ 729 u32 temp, bitmask, tmp_stat; 730 731 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr); 732 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */ 733 734 bitmask = ep_is_in(ep) 735 ? (1 << (ep_index(ep) + 16)) 736 : (1 << (ep_index(ep))); 737 738 /* check if the pipe is empty */ 739 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) { 740 /* Add td to the end */ 741 struct fsl_req *lastreq; 742 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); 743 lastreq->tail->next_td_ptr = 744 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK); 745 /* Ensure dTD's next dtd pointer to be updated */ 746 wmb(); 747 /* Read prime bit, if 1 goto done */ 748 if (fsl_readl(&dr_regs->endpointprime) & bitmask) 749 return; 750 751 do { 752 /* Set ATDTW bit in USBCMD */ 753 temp = fsl_readl(&dr_regs->usbcmd); 754 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd); 755 756 /* Read correct status bit */ 757 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask; 758 759 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW)); 760 761 /* Write ATDTW bit to 0 */ 762 temp = fsl_readl(&dr_regs->usbcmd); 763 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd); 764 765 if (tmp_stat) 766 return; 767 } 768 769 fsl_prime_ep(ep, req->head); 770} 771 772/* Fill in the dTD structure 773 * @req: request that the transfer belongs to 774 * @length: return actually data length of the dTD 775 * @dma: return dma address of the dTD 776 * @is_last: return flag if it is the last dTD of the request 777 * return: pointer to the built dTD */ 778static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length, 779 dma_addr_t *dma, int *is_last, gfp_t gfp_flags) 780{ 781 u32 swap_temp; 782 struct ep_td_struct *dtd; 783 784 /* how big will this transfer be? */ 785 *length = min(req->req.length - req->req.actual, 786 (unsigned)EP_MAX_LENGTH_TRANSFER); 787 788 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma); 789 if (dtd == NULL) 790 return dtd; 791 792 dtd->td_dma = *dma; 793 /* Clear reserved field */ 794 swap_temp = hc32_to_cpu(dtd->size_ioc_sts); 795 swap_temp &= ~DTD_RESERVED_FIELDS; 796 dtd->size_ioc_sts = cpu_to_hc32(swap_temp); 797 798 /* Init all of buffer page pointers */ 799 swap_temp = (u32) (req->req.dma + req->req.actual); 800 dtd->buff_ptr0 = cpu_to_hc32(swap_temp); 801 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000); 802 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000); 803 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000); 804 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000); 805 806 req->req.actual += *length; 807 808 /* zlp is needed if req->req.zero is set */ 809 if (req->req.zero) { 810 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) 811 *is_last = 1; 812 else 813 *is_last = 0; 814 } else if (req->req.length == req->req.actual) 815 *is_last = 1; 816 else 817 *is_last = 0; 818 819 if ((*is_last) == 0) 820 VDBG("multi-dtd request!"); 821 /* Fill in the transfer size; set active bit */ 822 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE); 823 824 /* Enable interrupt for the last dtd of a request */ 825 if (*is_last && !req->req.no_interrupt) 826 swap_temp |= DTD_IOC; 827 828 dtd->size_ioc_sts = cpu_to_hc32(swap_temp); 829 830 mb(); 831 832 VDBG("length = %d address= 0x%x", *length, (int)*dma); 833 834 return dtd; 835} 836 837/* Generate dtd chain for a request */ 838static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags) 839{ 840 unsigned count; 841 int is_last; 842 int is_first =1; 843 struct ep_td_struct *last_dtd = NULL, *dtd; 844 dma_addr_t dma; 845 846 do { 847 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags); 848 if (dtd == NULL) 849 return -ENOMEM; 850 851 if (is_first) { 852 is_first = 0; 853 req->head = dtd; 854 } else { 855 last_dtd->next_td_ptr = cpu_to_hc32(dma); 856 last_dtd->next_td_virt = dtd; 857 } 858 last_dtd = dtd; 859 860 req->dtd_count++; 861 } while (!is_last); 862 863 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE); 864 865 req->tail = dtd; 866 867 return 0; 868} 869 870/* queues (submits) an I/O request to an endpoint */ 871static int 872fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 873{ 874 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); 875 struct fsl_req *req = container_of(_req, struct fsl_req, req); 876 struct fsl_udc *udc; 877 unsigned long flags; 878 int ret; 879 880 /* catch various bogus parameters */ 881 if (!_req || !req->req.complete || !req->req.buf 882 || !list_empty(&req->queue)) { 883 VDBG("%s, bad params", __func__); 884 return -EINVAL; 885 } 886 if (unlikely(!_ep || !ep->ep.desc)) { 887 VDBG("%s, bad ep", __func__); 888 return -EINVAL; 889 } 890 if (usb_endpoint_xfer_isoc(ep->ep.desc)) { 891 if (req->req.length > ep->ep.maxpacket) 892 return -EMSGSIZE; 893 } 894 895 udc = ep->udc; 896 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 897 return -ESHUTDOWN; 898 899 req->ep = ep; 900 901 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep)); 902 if (ret) 903 return ret; 904 905 req->req.status = -EINPROGRESS; 906 req->req.actual = 0; 907 req->dtd_count = 0; 908 909 /* build dtds and push them to device queue */ 910 if (!fsl_req_to_dtd(req, gfp_flags)) { 911 spin_lock_irqsave(&udc->lock, flags); 912 fsl_queue_td(ep, req); 913 } else { 914 return -ENOMEM; 915 } 916 917 /* irq handler advances the queue */ 918 if (req != NULL) 919 list_add_tail(&req->queue, &ep->queue); 920 spin_unlock_irqrestore(&udc->lock, flags); 921 922 return 0; 923} 924 925/* dequeues (cancels, unlinks) an I/O request from an endpoint */ 926static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 927{ 928 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); 929 struct fsl_req *req; 930 unsigned long flags; 931 int ep_num, stopped, ret = 0; 932 u32 epctrl; 933 934 if (!_ep || !_req) 935 return -EINVAL; 936 937 spin_lock_irqsave(&ep->udc->lock, flags); 938 stopped = ep->stopped; 939 940 /* Stop the ep before we deal with the queue */ 941 ep->stopped = 1; 942 ep_num = ep_index(ep); 943 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 944 if (ep_is_in(ep)) 945 epctrl &= ~EPCTRL_TX_ENABLE; 946 else 947 epctrl &= ~EPCTRL_RX_ENABLE; 948 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 949 950 /* make sure it's actually queued on this endpoint */ 951 list_for_each_entry(req, &ep->queue, queue) { 952 if (&req->req == _req) 953 break; 954 } 955 if (&req->req != _req) { 956 ret = -EINVAL; 957 goto out; 958 } 959 960 /* The request is in progress, or completed but not dequeued */ 961 if (ep->queue.next == &req->queue) { 962 _req->status = -ECONNRESET; 963 fsl_ep_fifo_flush(_ep); /* flush current transfer */ 964 965 /* The request isn't the last request in this ep queue */ 966 if (req->queue.next != &ep->queue) { 967 struct fsl_req *next_req; 968 969 next_req = list_entry(req->queue.next, struct fsl_req, 970 queue); 971 972 /* prime with dTD of next request */ 973 fsl_prime_ep(ep, next_req->head); 974 } 975 /* The request hasn't been processed, patch up the TD chain */ 976 } else { 977 struct fsl_req *prev_req; 978 979 prev_req = list_entry(req->queue.prev, struct fsl_req, queue); 980 prev_req->tail->next_td_ptr = req->tail->next_td_ptr; 981 } 982 983 done(ep, req, -ECONNRESET); 984 985 /* Enable EP */ 986out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]); 987 if (ep_is_in(ep)) 988 epctrl |= EPCTRL_TX_ENABLE; 989 else 990 epctrl |= EPCTRL_RX_ENABLE; 991 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); 992 ep->stopped = stopped; 993 994 spin_unlock_irqrestore(&ep->udc->lock, flags); 995 return ret; 996} 997 998/*-------------------------------------------------------------------------*/ 999 1000/*----------------------------------------------------------------- 1001 * modify the endpoint halt feature 1002 * @ep: the non-isochronous endpoint being stalled 1003 * @value: 1--set halt 0--clear halt 1004 * Returns zero, or a negative error code. 1005*----------------------------------------------------------------*/ 1006static int fsl_ep_set_halt(struct usb_ep *_ep, int value) 1007{ 1008 struct fsl_ep *ep = NULL; 1009 unsigned long flags = 0; 1010 int status = -EOPNOTSUPP; /* operation not supported */ 1011 unsigned char ep_dir = 0, ep_num = 0; 1012 struct fsl_udc *udc = NULL; 1013 1014 ep = container_of(_ep, struct fsl_ep, ep); 1015 udc = ep->udc; 1016 if (!_ep || !ep->ep.desc) { 1017 status = -EINVAL; 1018 goto out; 1019 } 1020 1021 if (usb_endpoint_xfer_isoc(ep->ep.desc)) { 1022 status = -EOPNOTSUPP; 1023 goto out; 1024 } 1025 1026 /* Attempt to halt IN ep will fail if any transfer requests 1027 * are still queue */ 1028 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { 1029 status = -EAGAIN; 1030 goto out; 1031 } 1032 1033 status = 0; 1034 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; 1035 ep_num = (unsigned char)(ep_index(ep)); 1036 spin_lock_irqsave(&ep->udc->lock, flags); 1037 dr_ep_change_stall(ep_num, ep_dir, value); 1038 spin_unlock_irqrestore(&ep->udc->lock, flags); 1039 1040 if (ep_index(ep) == 0) { 1041 udc->ep0_state = WAIT_FOR_SETUP; 1042 udc->ep0_dir = 0; 1043 } 1044out: 1045 VDBG(" %s %s halt stat %d", ep->ep.name, 1046 value ? "set" : "clear", status); 1047 1048 return status; 1049} 1050 1051static int fsl_ep_fifo_status(struct usb_ep *_ep) 1052{ 1053 struct fsl_ep *ep; 1054 struct fsl_udc *udc; 1055 int size = 0; 1056 u32 bitmask; 1057 struct ep_queue_head *qh; 1058 1059 ep = container_of(_ep, struct fsl_ep, ep); 1060 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0)) 1061 return -ENODEV; 1062 1063 udc = (struct fsl_udc *)ep->udc; 1064 1065 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) 1066 return -ESHUTDOWN; 1067 1068 qh = get_qh_by_ep(ep); 1069 1070 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) : 1071 (1 << (ep_index(ep))); 1072 1073 if (fsl_readl(&dr_regs->endptstatus) & bitmask) 1074 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE) 1075 >> DTD_LENGTH_BIT_POS; 1076 1077 pr_debug("%s %u\n", __func__, size); 1078 return size; 1079} 1080 1081static void fsl_ep_fifo_flush(struct usb_ep *_ep) 1082{ 1083 struct fsl_ep *ep; 1084 int ep_num, ep_dir; 1085 u32 bits; 1086 unsigned long timeout; 1087#define FSL_UDC_FLUSH_TIMEOUT 1000 1088 1089 if (!_ep) { 1090 return; 1091 } else { 1092 ep = container_of(_ep, struct fsl_ep, ep); 1093 if (!ep->ep.desc) 1094 return; 1095 } 1096 ep_num = ep_index(ep); 1097 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV; 1098 1099 if (ep_num == 0) 1100 bits = (1 << 16) | 1; 1101 else if (ep_dir == USB_SEND) 1102 bits = 1 << (16 + ep_num); 1103 else 1104 bits = 1 << ep_num; 1105 1106 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT; 1107 do { 1108 fsl_writel(bits, &dr_regs->endptflush); 1109 1110 /* Wait until flush complete */ 1111 while (fsl_readl(&dr_regs->endptflush)) { 1112 if (time_after(jiffies, timeout)) { 1113 ERR("ep flush timeout\n"); 1114 return; 1115 } 1116 cpu_relax(); 1117 } 1118 /* See if we need to flush again */ 1119 } while (fsl_readl(&dr_regs->endptstatus) & bits); 1120} 1121 1122static struct usb_ep_ops fsl_ep_ops = { 1123 .enable = fsl_ep_enable, 1124 .disable = fsl_ep_disable, 1125 1126 .alloc_request = fsl_alloc_request, 1127 .free_request = fsl_free_request, 1128 1129 .queue = fsl_ep_queue, 1130 .dequeue = fsl_ep_dequeue, 1131 1132 .set_halt = fsl_ep_set_halt, 1133 .fifo_status = fsl_ep_fifo_status, 1134 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */ 1135}; 1136 1137/*------------------------------------------------------------------------- 1138 Gadget Driver Layer Operations 1139-------------------------------------------------------------------------*/ 1140 1141/*---------------------------------------------------------------------- 1142 * Get the current frame number (from DR frame_index Reg ) 1143 *----------------------------------------------------------------------*/ 1144static int fsl_get_frame(struct usb_gadget *gadget) 1145{ 1146 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS); 1147} 1148 1149/*----------------------------------------------------------------------- 1150 * Tries to wake up the host connected to this gadget 1151 -----------------------------------------------------------------------*/ 1152static int fsl_wakeup(struct usb_gadget *gadget) 1153{ 1154 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget); 1155 u32 portsc; 1156 1157 /* Remote wakeup feature not enabled by host */ 1158 if (!udc->remote_wakeup) 1159 return -ENOTSUPP; 1160 1161 portsc = fsl_readl(&dr_regs->portsc1); 1162 /* not suspended? */ 1163 if (!(portsc & PORTSCX_PORT_SUSPEND)) 1164 return 0; 1165 /* trigger force resume */ 1166 portsc |= PORTSCX_PORT_FORCE_RESUME; 1167 fsl_writel(portsc, &dr_regs->portsc1); 1168 return 0; 1169} 1170 1171static int can_pullup(struct fsl_udc *udc) 1172{ 1173 return udc->driver && udc->softconnect && udc->vbus_active; 1174} 1175 1176/* Notify controller that VBUS is powered, Called by whatever 1177 detects VBUS sessions */ 1178static int fsl_vbus_session(struct usb_gadget *gadget, int is_active) 1179{ 1180 struct fsl_udc *udc; 1181 unsigned long flags; 1182 1183 udc = container_of(gadget, struct fsl_udc, gadget); 1184 spin_lock_irqsave(&udc->lock, flags); 1185 VDBG("VBUS %s", is_active ? "on" : "off"); 1186 udc->vbus_active = (is_active != 0); 1187 if (can_pullup(udc)) 1188 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), 1189 &dr_regs->usbcmd); 1190 else 1191 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), 1192 &dr_regs->usbcmd); 1193 spin_unlock_irqrestore(&udc->lock, flags); 1194 return 0; 1195} 1196 1197/* constrain controller's VBUS power usage 1198 * This call is used by gadget drivers during SET_CONFIGURATION calls, 1199 * reporting how much power the device may consume. For example, this 1200 * could affect how quickly batteries are recharged. 1201 * 1202 * Returns zero on success, else negative errno. 1203 */ 1204static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1205{ 1206 struct fsl_udc *udc; 1207 1208 udc = container_of(gadget, struct fsl_udc, gadget); 1209 if (!IS_ERR_OR_NULL(udc->transceiver)) 1210 return usb_phy_set_power(udc->transceiver, mA); 1211 return -ENOTSUPP; 1212} 1213 1214/* Change Data+ pullup status 1215 * this func is used by usb_gadget_connect/disconnet 1216 */ 1217static int fsl_pullup(struct usb_gadget *gadget, int is_on) 1218{ 1219 struct fsl_udc *udc; 1220 1221 udc = container_of(gadget, struct fsl_udc, gadget); 1222 1223 if (!udc->vbus_active) 1224 return -EOPNOTSUPP; 1225 1226 udc->softconnect = (is_on != 0); 1227 if (can_pullup(udc)) 1228 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP), 1229 &dr_regs->usbcmd); 1230 else 1231 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP), 1232 &dr_regs->usbcmd); 1233 1234 return 0; 1235} 1236 1237static int fsl_udc_start(struct usb_gadget *g, 1238 struct usb_gadget_driver *driver); 1239static int fsl_udc_stop(struct usb_gadget *g); 1240 1241static const struct usb_gadget_ops fsl_gadget_ops = { 1242 .get_frame = fsl_get_frame, 1243 .wakeup = fsl_wakeup, 1244/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */ 1245 .vbus_session = fsl_vbus_session, 1246 .vbus_draw = fsl_vbus_draw, 1247 .pullup = fsl_pullup, 1248 .udc_start = fsl_udc_start, 1249 .udc_stop = fsl_udc_stop, 1250}; 1251 1252/* Set protocol stall on ep0, protocol stall will automatically be cleared 1253 on new transaction */ 1254static void ep0stall(struct fsl_udc *udc) 1255{ 1256 u32 tmp; 1257 1258 /* must set tx and rx to stall at the same time */ 1259 tmp = fsl_readl(&dr_regs->endptctrl[0]); 1260 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL; 1261 fsl_writel(tmp, &dr_regs->endptctrl[0]); 1262 udc->ep0_state = WAIT_FOR_SETUP; 1263 udc->ep0_dir = 0; 1264} 1265 1266/* Prime a status phase for ep0 */ 1267static int ep0_prime_status(struct fsl_udc *udc, int direction) 1268{ 1269 struct fsl_req *req = udc->status_req; 1270 struct fsl_ep *ep; 1271 int ret; 1272 1273 if (direction == EP_DIR_IN) 1274 udc->ep0_dir = USB_DIR_IN; 1275 else 1276 udc->ep0_dir = USB_DIR_OUT; 1277 1278 ep = &udc->eps[0]; 1279 if (udc->ep0_state != DATA_STATE_XMIT) 1280 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1281 1282 req->ep = ep; 1283 req->req.length = 0; 1284 req->req.status = -EINPROGRESS; 1285 req->req.actual = 0; 1286 req->req.complete = NULL; 1287 req->dtd_count = 0; 1288 1289 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep)); 1290 if (ret) 1291 return ret; 1292 1293 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0) 1294 fsl_queue_td(ep, req); 1295 else 1296 return -ENOMEM; 1297 1298 list_add_tail(&req->queue, &ep->queue); 1299 1300 return 0; 1301} 1302 1303static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe) 1304{ 1305 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe); 1306 1307 if (ep->name) 1308 nuke(ep, -ESHUTDOWN); 1309} 1310 1311/* 1312 * ch9 Set address 1313 */ 1314static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length) 1315{ 1316 /* Save the new address to device struct */ 1317 udc->device_address = (u8) value; 1318 /* Update usb state */ 1319 udc->usb_state = USB_STATE_ADDRESS; 1320 /* Status phase */ 1321 if (ep0_prime_status(udc, EP_DIR_IN)) 1322 ep0stall(udc); 1323} 1324 1325/* 1326 * ch9 Get status 1327 */ 1328static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, 1329 u16 index, u16 length) 1330{ 1331 u16 tmp = 0; /* Status, cpu endian */ 1332 struct fsl_req *req; 1333 struct fsl_ep *ep; 1334 int ret; 1335 1336 ep = &udc->eps[0]; 1337 1338 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) { 1339 /* Get device status */ 1340 tmp = udc->gadget.is_selfpowered; 1341 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP; 1342 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) { 1343 /* Get interface status */ 1344 /* We don't have interface information in udc driver */ 1345 tmp = 0; 1346 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { 1347 /* Get endpoint status */ 1348 struct fsl_ep *target_ep; 1349 1350 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index)); 1351 1352 /* stall if endpoint doesn't exist */ 1353 if (!target_ep->ep.desc) 1354 goto stall; 1355 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep)) 1356 << USB_ENDPOINT_HALT; 1357 } 1358 1359 udc->ep0_dir = USB_DIR_IN; 1360 /* Borrow the per device status_req */ 1361 req = udc->status_req; 1362 /* Fill in the reqest structure */ 1363 *((u16 *) req->req.buf) = cpu_to_le16(tmp); 1364 1365 req->ep = ep; 1366 req->req.length = 2; 1367 req->req.status = -EINPROGRESS; 1368 req->req.actual = 0; 1369 req->req.complete = NULL; 1370 req->dtd_count = 0; 1371 1372 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep)); 1373 if (ret) 1374 goto stall; 1375 1376 /* prime the data phase */ 1377 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0)) 1378 fsl_queue_td(ep, req); 1379 else /* no mem */ 1380 goto stall; 1381 1382 list_add_tail(&req->queue, &ep->queue); 1383 udc->ep0_state = DATA_STATE_XMIT; 1384 if (ep0_prime_status(udc, EP_DIR_OUT)) 1385 ep0stall(udc); 1386 1387 return; 1388stall: 1389 ep0stall(udc); 1390} 1391 1392static void setup_received_irq(struct fsl_udc *udc, 1393 struct usb_ctrlrequest *setup) 1394__releases(udc->lock) 1395__acquires(udc->lock) 1396{ 1397 u16 wValue = le16_to_cpu(setup->wValue); 1398 u16 wIndex = le16_to_cpu(setup->wIndex); 1399 u16 wLength = le16_to_cpu(setup->wLength); 1400 1401 udc_reset_ep_queue(udc, 0); 1402 1403 /* We process some stardard setup requests here */ 1404 switch (setup->bRequest) { 1405 case USB_REQ_GET_STATUS: 1406 /* Data+Status phase from udc */ 1407 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK)) 1408 != (USB_DIR_IN | USB_TYPE_STANDARD)) 1409 break; 1410 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength); 1411 return; 1412 1413 case USB_REQ_SET_ADDRESS: 1414 /* Status phase from udc */ 1415 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD 1416 | USB_RECIP_DEVICE)) 1417 break; 1418 ch9setaddress(udc, wValue, wIndex, wLength); 1419 return; 1420 1421 case USB_REQ_CLEAR_FEATURE: 1422 case USB_REQ_SET_FEATURE: 1423 /* Status phase from udc */ 1424 { 1425 int rc = -EOPNOTSUPP; 1426 u16 ptc = 0; 1427 1428 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) 1429 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) { 1430 int pipe = get_pipe_by_windex(wIndex); 1431 struct fsl_ep *ep; 1432 1433 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep) 1434 break; 1435 ep = get_ep_by_pipe(udc, pipe); 1436 1437 spin_unlock(&udc->lock); 1438 rc = fsl_ep_set_halt(&ep->ep, 1439 (setup->bRequest == USB_REQ_SET_FEATURE) 1440 ? 1 : 0); 1441 spin_lock(&udc->lock); 1442 1443 } else if ((setup->bRequestType & (USB_RECIP_MASK 1444 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE 1445 | USB_TYPE_STANDARD)) { 1446 /* Note: The driver has not include OTG support yet. 1447 * This will be set when OTG support is added */ 1448 if (wValue == USB_DEVICE_TEST_MODE) 1449 ptc = wIndex >> 8; 1450 else if (gadget_is_otg(&udc->gadget)) { 1451 if (setup->bRequest == 1452 USB_DEVICE_B_HNP_ENABLE) 1453 udc->gadget.b_hnp_enable = 1; 1454 else if (setup->bRequest == 1455 USB_DEVICE_A_HNP_SUPPORT) 1456 udc->gadget.a_hnp_support = 1; 1457 else if (setup->bRequest == 1458 USB_DEVICE_A_ALT_HNP_SUPPORT) 1459 udc->gadget.a_alt_hnp_support = 1; 1460 } 1461 rc = 0; 1462 } else 1463 break; 1464 1465 if (rc == 0) { 1466 if (ep0_prime_status(udc, EP_DIR_IN)) 1467 ep0stall(udc); 1468 } 1469 if (ptc) { 1470 u32 tmp; 1471 1472 mdelay(10); 1473 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16); 1474 fsl_writel(tmp, &dr_regs->portsc1); 1475 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc); 1476 } 1477 1478 return; 1479 } 1480 1481 default: 1482 break; 1483 } 1484 1485 /* Requests handled by gadget */ 1486 if (wLength) { 1487 /* Data phase from gadget, status phase from udc */ 1488 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN) 1489 ? USB_DIR_IN : USB_DIR_OUT; 1490 spin_unlock(&udc->lock); 1491 if (udc->driver->setup(&udc->gadget, 1492 &udc->local_setup_buff) < 0) 1493 ep0stall(udc); 1494 spin_lock(&udc->lock); 1495 udc->ep0_state = (setup->bRequestType & USB_DIR_IN) 1496 ? DATA_STATE_XMIT : DATA_STATE_RECV; 1497 /* 1498 * If the data stage is IN, send status prime immediately. 1499 * See 2.0 Spec chapter 8.5.3.3 for detail. 1500 */ 1501 if (udc->ep0_state == DATA_STATE_XMIT) 1502 if (ep0_prime_status(udc, EP_DIR_OUT)) 1503 ep0stall(udc); 1504 1505 } else { 1506 /* No data phase, IN status from gadget */ 1507 udc->ep0_dir = USB_DIR_IN; 1508 spin_unlock(&udc->lock); 1509 if (udc->driver->setup(&udc->gadget, 1510 &udc->local_setup_buff) < 0) 1511 ep0stall(udc); 1512 spin_lock(&udc->lock); 1513 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1514 } 1515} 1516 1517/* Process request for Data or Status phase of ep0 1518 * prime status phase if needed */ 1519static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, 1520 struct fsl_req *req) 1521{ 1522 if (udc->usb_state == USB_STATE_ADDRESS) { 1523 /* Set the new address */ 1524 u32 new_address = (u32) udc->device_address; 1525 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS, 1526 &dr_regs->deviceaddr); 1527 } 1528 1529 done(ep0, req, 0); 1530 1531 switch (udc->ep0_state) { 1532 case DATA_STATE_XMIT: 1533 /* already primed at setup_received_irq */ 1534 udc->ep0_state = WAIT_FOR_OUT_STATUS; 1535 break; 1536 case DATA_STATE_RECV: 1537 /* send status phase */ 1538 if (ep0_prime_status(udc, EP_DIR_IN)) 1539 ep0stall(udc); 1540 break; 1541 case WAIT_FOR_OUT_STATUS: 1542 udc->ep0_state = WAIT_FOR_SETUP; 1543 break; 1544 case WAIT_FOR_SETUP: 1545 ERR("Unexpect ep0 packets\n"); 1546 break; 1547 default: 1548 ep0stall(udc); 1549 break; 1550 } 1551} 1552 1553/* Tripwire mechanism to ensure a setup packet payload is extracted without 1554 * being corrupted by another incoming setup packet */ 1555static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr) 1556{ 1557 u32 temp; 1558 struct ep_queue_head *qh; 1559 struct fsl_usb2_platform_data *pdata = udc->pdata; 1560 1561 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT]; 1562 1563 /* Clear bit in ENDPTSETUPSTAT */ 1564 temp = fsl_readl(&dr_regs->endptsetupstat); 1565 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat); 1566 1567 /* while a hazard exists when setup package arrives */ 1568 do { 1569 /* Set Setup Tripwire */ 1570 temp = fsl_readl(&dr_regs->usbcmd); 1571 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd); 1572 1573 /* Copy the setup packet to local buffer */ 1574 if (pdata->le_setup_buf) { 1575 u32 *p = (u32 *)buffer_ptr; 1576 u32 *s = (u32 *)qh->setup_buffer; 1577 1578 /* Convert little endian setup buffer to CPU endian */ 1579 *p++ = le32_to_cpu(*s++); 1580 *p = le32_to_cpu(*s); 1581 } else { 1582 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8); 1583 } 1584 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW)); 1585 1586 /* Clear Setup Tripwire */ 1587 temp = fsl_readl(&dr_regs->usbcmd); 1588 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd); 1589} 1590 1591/* process-ep_req(): free the completed Tds for this req */ 1592static int process_ep_req(struct fsl_udc *udc, int pipe, 1593 struct fsl_req *curr_req) 1594{ 1595 struct ep_td_struct *curr_td; 1596 int td_complete, actual, remaining_length, j, tmp; 1597 int status = 0; 1598 int errors = 0; 1599 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe]; 1600 int direction = pipe % 2; 1601 1602 curr_td = curr_req->head; 1603 td_complete = 0; 1604 actual = curr_req->req.length; 1605 1606 for (j = 0; j < curr_req->dtd_count; j++) { 1607 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts) 1608 & DTD_PACKET_SIZE) 1609 >> DTD_LENGTH_BIT_POS; 1610 actual -= remaining_length; 1611 1612 errors = hc32_to_cpu(curr_td->size_ioc_sts); 1613 if (errors & DTD_ERROR_MASK) { 1614 if (errors & DTD_STATUS_HALTED) { 1615 ERR("dTD error %08x QH=%d\n", errors, pipe); 1616 /* Clear the errors and Halt condition */ 1617 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts); 1618 tmp &= ~errors; 1619 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp); 1620 status = -EPIPE; 1621 /* FIXME: continue with next queued TD? */ 1622 1623 break; 1624 } 1625 if (errors & DTD_STATUS_DATA_BUFF_ERR) { 1626 VDBG("Transfer overflow"); 1627 status = -EPROTO; 1628 break; 1629 } else if (errors & DTD_STATUS_TRANSACTION_ERR) { 1630 VDBG("ISO error"); 1631 status = -EILSEQ; 1632 break; 1633 } else 1634 ERR("Unknown error has occurred (0x%x)!\n", 1635 errors); 1636 1637 } else if (hc32_to_cpu(curr_td->size_ioc_sts) 1638 & DTD_STATUS_ACTIVE) { 1639 VDBG("Request not complete"); 1640 status = REQ_UNCOMPLETE; 1641 return status; 1642 } else if (remaining_length) { 1643 if (direction) { 1644 VDBG("Transmit dTD remaining length not zero"); 1645 status = -EPROTO; 1646 break; 1647 } else { 1648 td_complete++; 1649 break; 1650 } 1651 } else { 1652 td_complete++; 1653 VDBG("dTD transmitted successful"); 1654 } 1655 1656 if (j != curr_req->dtd_count - 1) 1657 curr_td = (struct ep_td_struct *)curr_td->next_td_virt; 1658 } 1659 1660 if (status) 1661 return status; 1662 1663 curr_req->req.actual = actual; 1664 1665 return 0; 1666} 1667 1668/* Process a DTD completion interrupt */ 1669static void dtd_complete_irq(struct fsl_udc *udc) 1670{ 1671 u32 bit_pos; 1672 int i, ep_num, direction, bit_mask, status; 1673 struct fsl_ep *curr_ep; 1674 struct fsl_req *curr_req, *temp_req; 1675 1676 /* Clear the bits in the register */ 1677 bit_pos = fsl_readl(&dr_regs->endptcomplete); 1678 fsl_writel(bit_pos, &dr_regs->endptcomplete); 1679 1680 if (!bit_pos) 1681 return; 1682 1683 for (i = 0; i < udc->max_ep; i++) { 1684 ep_num = i >> 1; 1685 direction = i % 2; 1686 1687 bit_mask = 1 << (ep_num + 16 * direction); 1688 1689 if (!(bit_pos & bit_mask)) 1690 continue; 1691 1692 curr_ep = get_ep_by_pipe(udc, i); 1693 1694 /* If the ep is configured */ 1695 if (curr_ep->name == NULL) { 1696 WARNING("Invalid EP?"); 1697 continue; 1698 } 1699 1700 /* process the req queue until an uncomplete request */ 1701 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue, 1702 queue) { 1703 status = process_ep_req(udc, i, curr_req); 1704 1705 VDBG("status of process_ep_req= %d, ep = %d", 1706 status, ep_num); 1707 if (status == REQ_UNCOMPLETE) 1708 break; 1709 /* write back status to req */ 1710 curr_req->req.status = status; 1711 1712 if (ep_num == 0) { 1713 ep0_req_complete(udc, curr_ep, curr_req); 1714 break; 1715 } else 1716 done(curr_ep, curr_req, status); 1717 } 1718 } 1719} 1720 1721static inline enum usb_device_speed portscx_device_speed(u32 reg) 1722{ 1723 switch (reg & PORTSCX_PORT_SPEED_MASK) { 1724 case PORTSCX_PORT_SPEED_HIGH: 1725 return USB_SPEED_HIGH; 1726 case PORTSCX_PORT_SPEED_FULL: 1727 return USB_SPEED_FULL; 1728 case PORTSCX_PORT_SPEED_LOW: 1729 return USB_SPEED_LOW; 1730 default: 1731 return USB_SPEED_UNKNOWN; 1732 } 1733} 1734 1735/* Process a port change interrupt */ 1736static void port_change_irq(struct fsl_udc *udc) 1737{ 1738 if (udc->bus_reset) 1739 udc->bus_reset = 0; 1740 1741 /* Bus resetting is finished */ 1742 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) 1743 /* Get the speed */ 1744 udc->gadget.speed = 1745 portscx_device_speed(fsl_readl(&dr_regs->portsc1)); 1746 1747 /* Update USB state */ 1748 if (!udc->resume_state) 1749 udc->usb_state = USB_STATE_DEFAULT; 1750} 1751 1752/* Process suspend interrupt */ 1753static void suspend_irq(struct fsl_udc *udc) 1754{ 1755 udc->resume_state = udc->usb_state; 1756 udc->usb_state = USB_STATE_SUSPENDED; 1757 1758 /* report suspend to the driver, serial.c does not support this */ 1759 if (udc->driver->suspend) 1760 udc->driver->suspend(&udc->gadget); 1761} 1762 1763static void bus_resume(struct fsl_udc *udc) 1764{ 1765 udc->usb_state = udc->resume_state; 1766 udc->resume_state = 0; 1767 1768 /* report resume to the driver, serial.c does not support this */ 1769 if (udc->driver->resume) 1770 udc->driver->resume(&udc->gadget); 1771} 1772 1773/* Clear up all ep queues */ 1774static int reset_queues(struct fsl_udc *udc, bool bus_reset) 1775{ 1776 u8 pipe; 1777 1778 for (pipe = 0; pipe < udc->max_pipes; pipe++) 1779 udc_reset_ep_queue(udc, pipe); 1780 1781 /* report disconnect; the driver is already quiesced */ 1782 spin_unlock(&udc->lock); 1783 if (bus_reset) 1784 usb_gadget_udc_reset(&udc->gadget, udc->driver); 1785 else 1786 udc->driver->disconnect(&udc->gadget); 1787 spin_lock(&udc->lock); 1788 1789 return 0; 1790} 1791 1792/* Process reset interrupt */ 1793static void reset_irq(struct fsl_udc *udc) 1794{ 1795 u32 temp; 1796 unsigned long timeout; 1797 1798 /* Clear the device address */ 1799 temp = fsl_readl(&dr_regs->deviceaddr); 1800 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr); 1801 1802 udc->device_address = 0; 1803 1804 /* Clear usb state */ 1805 udc->resume_state = 0; 1806 udc->ep0_dir = 0; 1807 udc->ep0_state = WAIT_FOR_SETUP; 1808 udc->remote_wakeup = 0; /* default to 0 on reset */ 1809 udc->gadget.b_hnp_enable = 0; 1810 udc->gadget.a_hnp_support = 0; 1811 udc->gadget.a_alt_hnp_support = 0; 1812 1813 /* Clear all the setup token semaphores */ 1814 temp = fsl_readl(&dr_regs->endptsetupstat); 1815 fsl_writel(temp, &dr_regs->endptsetupstat); 1816 1817 /* Clear all the endpoint complete status bits */ 1818 temp = fsl_readl(&dr_regs->endptcomplete); 1819 fsl_writel(temp, &dr_regs->endptcomplete); 1820 1821 timeout = jiffies + 100; 1822 while (fsl_readl(&dr_regs->endpointprime)) { 1823 /* Wait until all endptprime bits cleared */ 1824 if (time_after(jiffies, timeout)) { 1825 ERR("Timeout for reset\n"); 1826 break; 1827 } 1828 cpu_relax(); 1829 } 1830 1831 /* Write 1s to the flush register */ 1832 fsl_writel(0xffffffff, &dr_regs->endptflush); 1833 1834 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) { 1835 VDBG("Bus reset"); 1836 /* Bus is reseting */ 1837 udc->bus_reset = 1; 1838 /* Reset all the queues, include XD, dTD, EP queue 1839 * head and TR Queue */ 1840 reset_queues(udc, true); 1841 udc->usb_state = USB_STATE_DEFAULT; 1842 } else { 1843 VDBG("Controller reset"); 1844 /* initialize usb hw reg except for regs for EP, not 1845 * touch usbintr reg */ 1846 dr_controller_setup(udc); 1847 1848 /* Reset all internal used Queues */ 1849 reset_queues(udc, false); 1850 1851 ep0_setup(udc); 1852 1853 /* Enable DR IRQ reg, Set Run bit, change udc state */ 1854 dr_controller_run(udc); 1855 udc->usb_state = USB_STATE_ATTACHED; 1856 } 1857} 1858 1859/* 1860 * USB device controller interrupt handler 1861 */ 1862static irqreturn_t fsl_udc_irq(int irq, void *_udc) 1863{ 1864 struct fsl_udc *udc = _udc; 1865 u32 irq_src; 1866 irqreturn_t status = IRQ_NONE; 1867 unsigned long flags; 1868 1869 /* Disable ISR for OTG host mode */ 1870 if (udc->stopped) 1871 return IRQ_NONE; 1872 spin_lock_irqsave(&udc->lock, flags); 1873 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr); 1874 /* Clear notification bits */ 1875 fsl_writel(irq_src, &dr_regs->usbsts); 1876 1877 /* VDBG("irq_src [0x%8x]", irq_src); */ 1878 1879 /* Need to resume? */ 1880 if (udc->usb_state == USB_STATE_SUSPENDED) 1881 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0) 1882 bus_resume(udc); 1883 1884 /* USB Interrupt */ 1885 if (irq_src & USB_STS_INT) { 1886 VDBG("Packet int"); 1887 /* Setup package, we only support ep0 as control ep */ 1888 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) { 1889 tripwire_handler(udc, 0, 1890 (u8 *) (&udc->local_setup_buff)); 1891 setup_received_irq(udc, &udc->local_setup_buff); 1892 status = IRQ_HANDLED; 1893 } 1894 1895 /* completion of dtd */ 1896 if (fsl_readl(&dr_regs->endptcomplete)) { 1897 dtd_complete_irq(udc); 1898 status = IRQ_HANDLED; 1899 } 1900 } 1901 1902 /* SOF (for ISO transfer) */ 1903 if (irq_src & USB_STS_SOF) { 1904 status = IRQ_HANDLED; 1905 } 1906 1907 /* Port Change */ 1908 if (irq_src & USB_STS_PORT_CHANGE) { 1909 port_change_irq(udc); 1910 status = IRQ_HANDLED; 1911 } 1912 1913 /* Reset Received */ 1914 if (irq_src & USB_STS_RESET) { 1915 VDBG("reset int"); 1916 reset_irq(udc); 1917 status = IRQ_HANDLED; 1918 } 1919 1920 /* Sleep Enable (Suspend) */ 1921 if (irq_src & USB_STS_SUSPEND) { 1922 suspend_irq(udc); 1923 status = IRQ_HANDLED; 1924 } 1925 1926 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) { 1927 VDBG("Error IRQ %x", irq_src); 1928 } 1929 1930 spin_unlock_irqrestore(&udc->lock, flags); 1931 return status; 1932} 1933 1934/*----------------------------------------------------------------* 1935 * Hook to gadget drivers 1936 * Called by initialization code of gadget drivers 1937*----------------------------------------------------------------*/ 1938static int fsl_udc_start(struct usb_gadget *g, 1939 struct usb_gadget_driver *driver) 1940{ 1941 int retval = 0; 1942 unsigned long flags = 0; 1943 1944 /* lock is needed but whether should use this lock or another */ 1945 spin_lock_irqsave(&udc_controller->lock, flags); 1946 1947 driver->driver.bus = NULL; 1948 /* hook up the driver */ 1949 udc_controller->driver = driver; 1950 spin_unlock_irqrestore(&udc_controller->lock, flags); 1951 g->is_selfpowered = 1; 1952 1953 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) { 1954 /* Suspend the controller until OTG enable it */ 1955 udc_controller->stopped = 1; 1956 printk(KERN_INFO "Suspend udc for OTG auto detect\n"); 1957 1958 /* connect to bus through transceiver */ 1959 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) { 1960 retval = otg_set_peripheral( 1961 udc_controller->transceiver->otg, 1962 &udc_controller->gadget); 1963 if (retval < 0) { 1964 ERR("can't bind to transceiver\n"); 1965 udc_controller->driver = NULL; 1966 return retval; 1967 } 1968 } 1969 } else { 1970 /* Enable DR IRQ reg and set USBCMD reg Run bit */ 1971 dr_controller_run(udc_controller); 1972 udc_controller->usb_state = USB_STATE_ATTACHED; 1973 udc_controller->ep0_state = WAIT_FOR_SETUP; 1974 udc_controller->ep0_dir = 0; 1975 } 1976 1977 return retval; 1978} 1979 1980/* Disconnect from gadget driver */ 1981static int fsl_udc_stop(struct usb_gadget *g) 1982{ 1983 struct fsl_ep *loop_ep; 1984 unsigned long flags; 1985 1986 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) 1987 otg_set_peripheral(udc_controller->transceiver->otg, NULL); 1988 1989 /* stop DR, disable intr */ 1990 dr_controller_stop(udc_controller); 1991 1992 /* in fact, no needed */ 1993 udc_controller->usb_state = USB_STATE_ATTACHED; 1994 udc_controller->ep0_state = WAIT_FOR_SETUP; 1995 udc_controller->ep0_dir = 0; 1996 1997 /* stand operation */ 1998 spin_lock_irqsave(&udc_controller->lock, flags); 1999 udc_controller->gadget.speed = USB_SPEED_UNKNOWN; 2000 nuke(&udc_controller->eps[0], -ESHUTDOWN); 2001 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list, 2002 ep.ep_list) 2003 nuke(loop_ep, -ESHUTDOWN); 2004 spin_unlock_irqrestore(&udc_controller->lock, flags); 2005 2006 udc_controller->driver = NULL; 2007 2008 return 0; 2009} 2010 2011/*------------------------------------------------------------------------- 2012 PROC File System Support 2013-------------------------------------------------------------------------*/ 2014#ifdef CONFIG_USB_GADGET_DEBUG_FILES 2015 2016#include <linux/seq_file.h> 2017 2018static const char proc_filename[] = "driver/fsl_usb2_udc"; 2019 2020static int fsl_proc_read(struct seq_file *m, void *v) 2021{ 2022 unsigned long flags; 2023 int i; 2024 u32 tmp_reg; 2025 struct fsl_ep *ep = NULL; 2026 struct fsl_req *req; 2027 2028 struct fsl_udc *udc = udc_controller; 2029 2030 spin_lock_irqsave(&udc->lock, flags); 2031 2032 /* ------basic driver information ---- */ 2033 seq_printf(m, 2034 DRIVER_DESC "\n" 2035 "%s version: %s\n" 2036 "Gadget driver: %s\n\n", 2037 driver_name, DRIVER_VERSION, 2038 udc->driver ? udc->driver->driver.name : "(none)"); 2039 2040 /* ------ DR Registers ----- */ 2041 tmp_reg = fsl_readl(&dr_regs->usbcmd); 2042 seq_printf(m, 2043 "USBCMD reg:\n" 2044 "SetupTW: %d\n" 2045 "Run/Stop: %s\n\n", 2046 (tmp_reg & USB_CMD_SUTW) ? 1 : 0, 2047 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop"); 2048 2049 tmp_reg = fsl_readl(&dr_regs->usbsts); 2050 seq_printf(m, 2051 "USB Status Reg:\n" 2052 "Dr Suspend: %d Reset Received: %d System Error: %s " 2053 "USB Error Interrupt: %s\n\n", 2054 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0, 2055 (tmp_reg & USB_STS_RESET) ? 1 : 0, 2056 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal", 2057 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err"); 2058 2059 tmp_reg = fsl_readl(&dr_regs->usbintr); 2060 seq_printf(m, 2061 "USB Interrupt Enable Reg:\n" 2062 "Sleep Enable: %d SOF Received Enable: %d " 2063 "Reset Enable: %d\n" 2064 "System Error Enable: %d " 2065 "Port Change Dectected Enable: %d\n" 2066 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n", 2067 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0, 2068 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0, 2069 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0, 2070 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0, 2071 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0, 2072 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0, 2073 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0); 2074 2075 tmp_reg = fsl_readl(&dr_regs->frindex); 2076 seq_printf(m, 2077 "USB Frame Index Reg: Frame Number is 0x%x\n\n", 2078 (tmp_reg & USB_FRINDEX_MASKS)); 2079 2080 tmp_reg = fsl_readl(&dr_regs->deviceaddr); 2081 seq_printf(m, 2082 "USB Device Address Reg: Device Addr is 0x%x\n\n", 2083 (tmp_reg & USB_DEVICE_ADDRESS_MASK)); 2084 2085 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr); 2086 seq_printf(m, 2087 "USB Endpoint List Address Reg: " 2088 "Device Addr is 0x%x\n\n", 2089 (tmp_reg & USB_EP_LIST_ADDRESS_MASK)); 2090 2091 tmp_reg = fsl_readl(&dr_regs->portsc1); 2092 seq_printf(m, 2093 "USB Port Status&Control Reg:\n" 2094 "Port Transceiver Type : %s Port Speed: %s\n" 2095 "PHY Low Power Suspend: %s Port Reset: %s " 2096 "Port Suspend Mode: %s\n" 2097 "Over-current Change: %s " 2098 "Port Enable/Disable Change: %s\n" 2099 "Port Enabled/Disabled: %s " 2100 "Current Connect Status: %s\n\n", ( { 2101 const char *s; 2102 switch (tmp_reg & PORTSCX_PTS_FSLS) { 2103 case PORTSCX_PTS_UTMI: 2104 s = "UTMI"; break; 2105 case PORTSCX_PTS_ULPI: 2106 s = "ULPI "; break; 2107 case PORTSCX_PTS_FSLS: 2108 s = "FS/LS Serial"; break; 2109 default: 2110 s = "None"; break; 2111 } 2112 s;} ), 2113 usb_speed_string(portscx_device_speed(tmp_reg)), 2114 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ? 2115 "Normal PHY mode" : "Low power mode", 2116 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" : 2117 "Not in Reset", 2118 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in", 2119 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" : 2120 "No", 2121 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" : 2122 "Not change", 2123 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" : 2124 "Not correct", 2125 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ? 2126 "Attached" : "Not-Att"); 2127 2128 tmp_reg = fsl_readl(&dr_regs->usbmode); 2129 seq_printf(m, 2130 "USB Mode Reg: Controller Mode is: %s\n\n", ( { 2131 const char *s; 2132 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) { 2133 case USB_MODE_CTRL_MODE_IDLE: 2134 s = "Idle"; break; 2135 case USB_MODE_CTRL_MODE_DEVICE: 2136 s = "Device Controller"; break; 2137 case USB_MODE_CTRL_MODE_HOST: 2138 s = "Host Controller"; break; 2139 default: 2140 s = "None"; break; 2141 } 2142 s; 2143 } )); 2144 2145 tmp_reg = fsl_readl(&dr_regs->endptsetupstat); 2146 seq_printf(m, 2147 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n", 2148 (tmp_reg & EP_SETUP_STATUS_MASK)); 2149 2150 for (i = 0; i < udc->max_ep / 2; i++) { 2151 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]); 2152 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg); 2153 } 2154 tmp_reg = fsl_readl(&dr_regs->endpointprime); 2155 seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg); 2156 2157#ifndef CONFIG_ARCH_MXC 2158 if (udc->pdata->have_sysif_regs) { 2159 tmp_reg = usb_sys_regs->snoop1; 2160 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg); 2161 2162 tmp_reg = usb_sys_regs->control; 2163 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg); 2164 } 2165#endif 2166 2167 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */ 2168 ep = &udc->eps[0]; 2169 seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n", 2170 ep->ep.name, ep_maxpacket(ep), ep_index(ep)); 2171 2172 if (list_empty(&ep->queue)) { 2173 seq_puts(m, "its req queue is empty\n\n"); 2174 } else { 2175 list_for_each_entry(req, &ep->queue, queue) { 2176 seq_printf(m, 2177 "req %p actual 0x%x length 0x%x buf %p\n", 2178 &req->req, req->req.actual, 2179 req->req.length, req->req.buf); 2180 } 2181 } 2182 /* other gadget->eplist ep */ 2183 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2184 if (ep->ep.desc) { 2185 seq_printf(m, 2186 "\nFor %s Maxpkt is 0x%x " 2187 "index is 0x%x\n", 2188 ep->ep.name, ep_maxpacket(ep), 2189 ep_index(ep)); 2190 2191 if (list_empty(&ep->queue)) { 2192 seq_puts(m, "its req queue is empty\n\n"); 2193 } else { 2194 list_for_each_entry(req, &ep->queue, queue) { 2195 seq_printf(m, 2196 "req %p actual 0x%x length " 2197 "0x%x buf %p\n", 2198 &req->req, req->req.actual, 2199 req->req.length, req->req.buf); 2200 } /* end for each_entry of ep req */ 2201 } /* end for else */ 2202 } /* end for if(ep->queue) */ 2203 } /* end (ep->desc) */ 2204 2205 spin_unlock_irqrestore(&udc->lock, flags); 2206 return 0; 2207} 2208 2209/* 2210 * seq_file wrappers for procfile show routines. 2211 */ 2212static int fsl_proc_open(struct inode *inode, struct file *file) 2213{ 2214 return single_open(file, fsl_proc_read, NULL); 2215} 2216 2217static const struct file_operations fsl_proc_fops = { 2218 .open = fsl_proc_open, 2219 .read = seq_read, 2220 .llseek = seq_lseek, 2221 .release = single_release, 2222}; 2223 2224#define create_proc_file() proc_create(proc_filename, 0, NULL, &fsl_proc_fops) 2225#define remove_proc_file() remove_proc_entry(proc_filename, NULL) 2226 2227#else /* !CONFIG_USB_GADGET_DEBUG_FILES */ 2228 2229#define create_proc_file() do {} while (0) 2230#define remove_proc_file() do {} while (0) 2231 2232#endif /* CONFIG_USB_GADGET_DEBUG_FILES */ 2233 2234/*-------------------------------------------------------------------------*/ 2235 2236/* Release udc structures */ 2237static void fsl_udc_release(struct device *dev) 2238{ 2239 complete(udc_controller->done); 2240 dma_free_coherent(dev->parent, udc_controller->ep_qh_size, 2241 udc_controller->ep_qh, udc_controller->ep_qh_dma); 2242 kfree(udc_controller); 2243} 2244 2245/****************************************************************** 2246 Internal structure setup functions 2247*******************************************************************/ 2248/*------------------------------------------------------------------ 2249 * init resource for globle controller 2250 * Return the udc handle on success or NULL on failure 2251 ------------------------------------------------------------------*/ 2252static int struct_udc_setup(struct fsl_udc *udc, 2253 struct platform_device *pdev) 2254{ 2255 struct fsl_usb2_platform_data *pdata; 2256 size_t size; 2257 2258 pdata = dev_get_platdata(&pdev->dev); 2259 udc->phy_mode = pdata->phy_mode; 2260 2261 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL); 2262 if (!udc->eps) 2263 return -1; 2264 2265 /* initialized QHs, take care of alignment */ 2266 size = udc->max_ep * sizeof(struct ep_queue_head); 2267 if (size < QH_ALIGNMENT) 2268 size = QH_ALIGNMENT; 2269 else if ((size % QH_ALIGNMENT) != 0) { 2270 size += QH_ALIGNMENT + 1; 2271 size &= ~(QH_ALIGNMENT - 1); 2272 } 2273 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size, 2274 &udc->ep_qh_dma, GFP_KERNEL); 2275 if (!udc->ep_qh) { 2276 ERR("malloc QHs for udc failed\n"); 2277 kfree(udc->eps); 2278 return -1; 2279 } 2280 2281 udc->ep_qh_size = size; 2282 2283 /* Initialize ep0 status request structure */ 2284 /* FIXME: fsl_alloc_request() ignores ep argument */ 2285 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL), 2286 struct fsl_req, req); 2287 /* allocate a small amount of memory to get valid address */ 2288 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL); 2289 2290 udc->resume_state = USB_STATE_NOTATTACHED; 2291 udc->usb_state = USB_STATE_POWERED; 2292 udc->ep0_dir = 0; 2293 udc->remote_wakeup = 0; /* default to 0 on reset */ 2294 2295 return 0; 2296} 2297 2298/*---------------------------------------------------------------- 2299 * Setup the fsl_ep struct for eps 2300 * Link fsl_ep->ep to gadget->ep_list 2301 * ep0out is not used so do nothing here 2302 * ep0in should be taken care 2303 *--------------------------------------------------------------*/ 2304static int struct_ep_setup(struct fsl_udc *udc, unsigned char index, 2305 char *name, int link) 2306{ 2307 struct fsl_ep *ep = &udc->eps[index]; 2308 2309 ep->udc = udc; 2310 strcpy(ep->name, name); 2311 ep->ep.name = ep->name; 2312 2313 ep->ep.ops = &fsl_ep_ops; 2314 ep->stopped = 0; 2315 2316 /* for ep0: maxP defined in desc 2317 * for other eps, maxP is set by epautoconfig() called by gadget layer 2318 */ 2319 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0); 2320 2321 /* the queue lists any req for this ep */ 2322 INIT_LIST_HEAD(&ep->queue); 2323 2324 /* gagdet.ep_list used for ep_autoconfig so no ep0 */ 2325 if (link) 2326 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 2327 ep->gadget = &udc->gadget; 2328 ep->qh = &udc->ep_qh[index]; 2329 2330 return 0; 2331} 2332 2333/* Driver probe function 2334 * all intialization operations implemented here except enabling usb_intr reg 2335 * board setup should have been done in the platform code 2336 */ 2337static int fsl_udc_probe(struct platform_device *pdev) 2338{ 2339 struct fsl_usb2_platform_data *pdata; 2340 struct resource *res; 2341 int ret = -ENODEV; 2342 unsigned int i; 2343 u32 dccparams; 2344 2345 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL); 2346 if (udc_controller == NULL) 2347 return -ENOMEM; 2348 2349 pdata = dev_get_platdata(&pdev->dev); 2350 udc_controller->pdata = pdata; 2351 spin_lock_init(&udc_controller->lock); 2352 udc_controller->stopped = 1; 2353 2354#ifdef CONFIG_USB_OTG 2355 if (pdata->operating_mode == FSL_USB2_DR_OTG) { 2356 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); 2357 if (IS_ERR_OR_NULL(udc_controller->transceiver)) { 2358 ERR("Can't find OTG driver!\n"); 2359 ret = -ENODEV; 2360 goto err_kfree; 2361 } 2362 } 2363#endif 2364 2365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2366 if (!res) { 2367 ret = -ENXIO; 2368 goto err_kfree; 2369 } 2370 2371 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) { 2372 if (!request_mem_region(res->start, resource_size(res), 2373 driver_name)) { 2374 ERR("request mem region for %s failed\n", pdev->name); 2375 ret = -EBUSY; 2376 goto err_kfree; 2377 } 2378 } 2379 2380 dr_regs = ioremap(res->start, resource_size(res)); 2381 if (!dr_regs) { 2382 ret = -ENOMEM; 2383 goto err_release_mem_region; 2384 } 2385 2386 pdata->regs = (void __iomem *)dr_regs; 2387 2388 /* 2389 * do platform specific init: check the clock, grab/config pins, etc. 2390 */ 2391 if (pdata->init && pdata->init(pdev)) { 2392 ret = -ENODEV; 2393 goto err_iounmap_noclk; 2394 } 2395 2396 /* Set accessors only after pdata->init() ! */ 2397 fsl_set_accessors(pdata); 2398 2399#ifndef CONFIG_ARCH_MXC 2400 if (pdata->have_sysif_regs) 2401 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET; 2402#endif 2403 2404 /* Initialize USB clocks */ 2405 ret = fsl_udc_clk_init(pdev); 2406 if (ret < 0) 2407 goto err_iounmap_noclk; 2408 2409 /* Read Device Controller Capability Parameters register */ 2410 dccparams = fsl_readl(&dr_regs->dccparams); 2411 if (!(dccparams & DCCPARAMS_DC)) { 2412 ERR("This SOC doesn't support device role\n"); 2413 ret = -ENODEV; 2414 goto err_iounmap; 2415 } 2416 /* Get max device endpoints */ 2417 /* DEN is bidirectional ep number, max_ep doubles the number */ 2418 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2; 2419 2420 udc_controller->irq = platform_get_irq(pdev, 0); 2421 if (!udc_controller->irq) { 2422 ret = -ENODEV; 2423 goto err_iounmap; 2424 } 2425 2426 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED, 2427 driver_name, udc_controller); 2428 if (ret != 0) { 2429 ERR("cannot request irq %d err %d\n", 2430 udc_controller->irq, ret); 2431 goto err_iounmap; 2432 } 2433 2434 /* Initialize the udc structure including QH member and other member */ 2435 if (struct_udc_setup(udc_controller, pdev)) { 2436 ERR("Can't initialize udc data structure\n"); 2437 ret = -ENOMEM; 2438 goto err_free_irq; 2439 } 2440 2441 if (IS_ERR_OR_NULL(udc_controller->transceiver)) { 2442 /* initialize usb hw reg except for regs for EP, 2443 * leave usbintr reg untouched */ 2444 dr_controller_setup(udc_controller); 2445 } 2446 2447 ret = fsl_udc_clk_finalize(pdev); 2448 if (ret) 2449 goto err_free_irq; 2450 2451 /* Setup gadget structure */ 2452 udc_controller->gadget.ops = &fsl_gadget_ops; 2453 udc_controller->gadget.max_speed = USB_SPEED_HIGH; 2454 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep; 2455 INIT_LIST_HEAD(&udc_controller->gadget.ep_list); 2456 udc_controller->gadget.speed = USB_SPEED_UNKNOWN; 2457 udc_controller->gadget.name = driver_name; 2458 2459 /* Setup gadget.dev and register with kernel */ 2460 dev_set_name(&udc_controller->gadget.dev, "gadget"); 2461 udc_controller->gadget.dev.of_node = pdev->dev.of_node; 2462 2463 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) 2464 udc_controller->gadget.is_otg = 1; 2465 2466 /* setup QH and epctrl for ep0 */ 2467 ep0_setup(udc_controller); 2468 2469 /* setup udc->eps[] for ep0 */ 2470 struct_ep_setup(udc_controller, 0, "ep0", 0); 2471 /* for ep0: the desc defined here; 2472 * for other eps, gadget layer called ep_enable with defined desc 2473 */ 2474 udc_controller->eps[0].ep.desc = &fsl_ep0_desc; 2475 usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep, 2476 USB_MAX_CTRL_PAYLOAD); 2477 2478 /* setup the udc->eps[] for non-control endpoints and link 2479 * to gadget.ep_list */ 2480 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) { 2481 char name[14]; 2482 2483 sprintf(name, "ep%dout", i); 2484 struct_ep_setup(udc_controller, i * 2, name, 1); 2485 sprintf(name, "ep%din", i); 2486 struct_ep_setup(udc_controller, i * 2 + 1, name, 1); 2487 } 2488 2489 /* use dma_pool for TD management */ 2490 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev, 2491 sizeof(struct ep_td_struct), 2492 DTD_ALIGNMENT, UDC_DMA_BOUNDARY); 2493 if (udc_controller->td_pool == NULL) { 2494 ret = -ENOMEM; 2495 goto err_free_irq; 2496 } 2497 2498 ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget, 2499 fsl_udc_release); 2500 if (ret) 2501 goto err_del_udc; 2502 2503 create_proc_file(); 2504 return 0; 2505 2506err_del_udc: 2507 dma_pool_destroy(udc_controller->td_pool); 2508err_free_irq: 2509 free_irq(udc_controller->irq, udc_controller); 2510err_iounmap: 2511 if (pdata->exit) 2512 pdata->exit(pdev); 2513 fsl_udc_clk_release(); 2514err_iounmap_noclk: 2515 iounmap(dr_regs); 2516err_release_mem_region: 2517 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) 2518 release_mem_region(res->start, resource_size(res)); 2519err_kfree: 2520 kfree(udc_controller); 2521 udc_controller = NULL; 2522 return ret; 2523} 2524 2525/* Driver removal function 2526 * Free resources and finish pending transactions 2527 */ 2528static int fsl_udc_remove(struct platform_device *pdev) 2529{ 2530 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2531 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); 2532 2533 DECLARE_COMPLETION_ONSTACK(done); 2534 2535 if (!udc_controller) 2536 return -ENODEV; 2537 2538 udc_controller->done = &done; 2539 usb_del_gadget_udc(&udc_controller->gadget); 2540 2541 fsl_udc_clk_release(); 2542 2543 /* DR has been stopped in usb_gadget_unregister_driver() */ 2544 remove_proc_file(); 2545 2546 /* Free allocated memory */ 2547 kfree(udc_controller->status_req->req.buf); 2548 kfree(udc_controller->status_req); 2549 kfree(udc_controller->eps); 2550 2551 dma_pool_destroy(udc_controller->td_pool); 2552 free_irq(udc_controller->irq, udc_controller); 2553 iounmap(dr_regs); 2554 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) 2555 release_mem_region(res->start, resource_size(res)); 2556 2557 /* free udc --wait for the release() finished */ 2558 wait_for_completion(&done); 2559 2560 /* 2561 * do platform specific un-initialization: 2562 * release iomux pins, etc. 2563 */ 2564 if (pdata->exit) 2565 pdata->exit(pdev); 2566 2567 return 0; 2568} 2569 2570/*----------------------------------------------------------------- 2571 * Modify Power management attributes 2572 * Used by OTG statemachine to disable gadget temporarily 2573 -----------------------------------------------------------------*/ 2574static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state) 2575{ 2576 dr_controller_stop(udc_controller); 2577 return 0; 2578} 2579 2580/*----------------------------------------------------------------- 2581 * Invoked on USB resume. May be called in_interrupt. 2582 * Here we start the DR controller and enable the irq 2583 *-----------------------------------------------------------------*/ 2584static int fsl_udc_resume(struct platform_device *pdev) 2585{ 2586 /* Enable DR irq reg and set controller Run */ 2587 if (udc_controller->stopped) { 2588 dr_controller_setup(udc_controller); 2589 dr_controller_run(udc_controller); 2590 } 2591 udc_controller->usb_state = USB_STATE_ATTACHED; 2592 udc_controller->ep0_state = WAIT_FOR_SETUP; 2593 udc_controller->ep0_dir = 0; 2594 return 0; 2595} 2596 2597static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state) 2598{ 2599 struct fsl_udc *udc = udc_controller; 2600 u32 mode, usbcmd; 2601 2602 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK; 2603 2604 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped); 2605 2606 /* 2607 * If the controller is already stopped, then this must be a 2608 * PM suspend. Remember this fact, so that we will leave the 2609 * controller stopped at PM resume time. 2610 */ 2611 if (udc->stopped) { 2612 pr_debug("gadget already stopped, leaving early\n"); 2613 udc->already_stopped = 1; 2614 return 0; 2615 } 2616 2617 if (mode != USB_MODE_CTRL_MODE_DEVICE) { 2618 pr_debug("gadget not in device mode, leaving early\n"); 2619 return 0; 2620 } 2621 2622 /* stop the controller */ 2623 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP; 2624 fsl_writel(usbcmd, &dr_regs->usbcmd); 2625 2626 udc->stopped = 1; 2627 2628 pr_info("USB Gadget suspended\n"); 2629 2630 return 0; 2631} 2632 2633static int fsl_udc_otg_resume(struct device *dev) 2634{ 2635 pr_debug("%s(): stopped %d already_stopped %d\n", __func__, 2636 udc_controller->stopped, udc_controller->already_stopped); 2637 2638 /* 2639 * If the controller was stopped at suspend time, then 2640 * don't resume it now. 2641 */ 2642 if (udc_controller->already_stopped) { 2643 udc_controller->already_stopped = 0; 2644 pr_debug("gadget was already stopped, leaving early\n"); 2645 return 0; 2646 } 2647 2648 pr_info("USB Gadget resume\n"); 2649 2650 return fsl_udc_resume(NULL); 2651} 2652/*------------------------------------------------------------------------- 2653 Register entry point for the peripheral controller driver 2654--------------------------------------------------------------------------*/ 2655static const struct platform_device_id fsl_udc_devtype[] = { 2656 { 2657 .name = "imx-udc-mx27", 2658 }, { 2659 .name = "imx-udc-mx51", 2660 }, { 2661 /* sentinel */ 2662 } 2663}; 2664MODULE_DEVICE_TABLE(platform, fsl_udc_devtype); 2665static struct platform_driver udc_driver = { 2666 .remove = fsl_udc_remove, 2667 /* Just for FSL i.mx SoC currently */ 2668 .id_table = fsl_udc_devtype, 2669 /* these suspend and resume are not usb suspend and resume */ 2670 .suspend = fsl_udc_suspend, 2671 .resume = fsl_udc_resume, 2672 .driver = { 2673 .name = driver_name, 2674 /* udc suspend/resume called from OTG driver */ 2675 .suspend = fsl_udc_otg_suspend, 2676 .resume = fsl_udc_otg_resume, 2677 }, 2678}; 2679 2680module_platform_driver_probe(udc_driver, fsl_udc_probe); 2681 2682MODULE_DESCRIPTION(DRIVER_DESC); 2683MODULE_AUTHOR(DRIVER_AUTHOR); 2684MODULE_LICENSE("GPL"); 2685MODULE_ALIAS("platform:fsl-usb2-udc"); 2686