1 2/* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software Foundation, 21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24#ifndef __LINUX_XHCI_HCD_H 25#define __LINUX_XHCI_HCD_H 26 27#include <linux/usb.h> 28#include <linux/timer.h> 29#include <linux/kernel.h> 30#include <linux/usb/hcd.h> 31 32/* Code sharing between pci-quirks and xhci hcd */ 33#include "xhci-ext-caps.h" 34#include "pci-quirks.h" 35 36/* xHCI PCI Configuration Registers */ 37#define XHCI_SBRN_OFFSET (0x60) 38 39/* Max number of USB devices for any host controller - limit in section 6.1 */ 40#define MAX_HC_SLOTS 256 41/* Section 5.3.3 - MaxPorts */ 42#define MAX_HC_PORTS 127 43 44/* 45 * xHCI register interface. 46 * This corresponds to the eXtensible Host Controller Interface (xHCI) 47 * Revision 0.95 specification 48 */ 49 50/** 51 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 52 * @hc_capbase: length of the capabilities register and HC version number 53 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 54 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 55 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 56 * @hcc_params: HCCPARAMS - Capability Parameters 57 * @db_off: DBOFF - Doorbell array offset 58 * @run_regs_off: RTSOFF - Runtime register space offset 59 */ 60struct xhci_cap_regs { 61 __le32 hc_capbase; 62 __le32 hcs_params1; 63 __le32 hcs_params2; 64 __le32 hcs_params3; 65 __le32 hcc_params; 66 __le32 db_off; 67 __le32 run_regs_off; 68 /* Reserved up to (CAPLENGTH - 0x1C) */ 69}; 70 71/* hc_capbase bitmasks */ 72/* bits 7:0 - how long is the Capabilities register */ 73#define HC_LENGTH(p) XHCI_HC_LENGTH(p) 74/* bits 31:16 */ 75#define HC_VERSION(p) (((p) >> 16) & 0xffff) 76 77/* HCSPARAMS1 - hcs_params1 - bitmasks */ 78/* bits 0:7, Max Device Slots */ 79#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 80#define HCS_SLOTS_MASK 0xff 81/* bits 8:18, Max Interrupters */ 82#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 83/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 84#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 85 86/* HCSPARAMS2 - hcs_params2 - bitmasks */ 87/* bits 0:3, frames or uframes that SW needs to queue transactions 88 * ahead of the HW to meet periodic deadlines */ 89#define HCS_IST(p) (((p) >> 0) & 0xf) 90/* bits 4:7, max number of Event Ring segments */ 91#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 92/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 93/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 94/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 95#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 96 97/* HCSPARAMS3 - hcs_params3 - bitmasks */ 98/* bits 0:7, Max U1 to U0 latency for the roothub ports */ 99#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 100/* bits 16:31, Max U2 to U0 latency for the roothub ports */ 101#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 102 103/* HCCPARAMS - hcc_params - bitmasks */ 104/* true: HC can use 64-bit address pointers */ 105#define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 106/* true: HC can do bandwidth negotiation */ 107#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 108/* true: HC uses 64-byte Device Context structures 109 * FIXME 64-byte context structures aren't supported yet. 110 */ 111#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 112/* true: HC has port power switches */ 113#define HCC_PPC(p) ((p) & (1 << 3)) 114/* true: HC has port indicators */ 115#define HCS_INDICATOR(p) ((p) & (1 << 4)) 116/* true: HC has Light HC Reset Capability */ 117#define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 118/* true: HC supports latency tolerance messaging */ 119#define HCC_LTC(p) ((p) & (1 << 6)) 120/* true: no secondary Stream ID Support */ 121#define HCC_NSS(p) ((p) & (1 << 7)) 122/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 123#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 124/* Extended Capabilities pointer from PCI base - section 5.3.6 */ 125#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 126 127/* db_off bitmask - bits 0:1 reserved */ 128#define DBOFF_MASK (~0x3) 129 130/* run_regs_off bitmask - bits 0:4 reserved */ 131#define RTSOFF_MASK (~0x1f) 132 133 134/* Number of registers per port */ 135#define NUM_PORT_REGS 4 136 137#define PORTSC 0 138#define PORTPMSC 1 139#define PORTLI 2 140#define PORTHLPMC 3 141 142/** 143 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 144 * @command: USBCMD - xHC command register 145 * @status: USBSTS - xHC status register 146 * @page_size: This indicates the page size that the host controller 147 * supports. If bit n is set, the HC supports a page size 148 * of 2^(n+12), up to a 128MB page size. 149 * 4K is the minimum page size. 150 * @cmd_ring: CRP - 64-bit Command Ring Pointer 151 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 152 * @config_reg: CONFIG - Configure Register 153 * @port_status_base: PORTSCn - base address for Port Status and Control 154 * Each port has a Port Status and Control register, 155 * followed by a Port Power Management Status and Control 156 * register, a Port Link Info register, and a reserved 157 * register. 158 * @port_power_base: PORTPMSCn - base address for 159 * Port Power Management Status and Control 160 * @port_link_base: PORTLIn - base address for Port Link Info (current 161 * Link PM state and control) for USB 2.1 and USB 3.0 162 * devices. 163 */ 164struct xhci_op_regs { 165 __le32 command; 166 __le32 status; 167 __le32 page_size; 168 __le32 reserved1; 169 __le32 reserved2; 170 __le32 dev_notification; 171 __le64 cmd_ring; 172 /* rsvd: offset 0x20-2F */ 173 __le32 reserved3[4]; 174 __le64 dcbaa_ptr; 175 __le32 config_reg; 176 /* rsvd: offset 0x3C-3FF */ 177 __le32 reserved4[241]; 178 /* port 1 registers, which serve as a base address for other ports */ 179 __le32 port_status_base; 180 __le32 port_power_base; 181 __le32 port_link_base; 182 __le32 reserved5; 183 /* registers for ports 2-255 */ 184 __le32 reserved6[NUM_PORT_REGS*254]; 185}; 186 187/* USBCMD - USB command - command bitmasks */ 188/* start/stop HC execution - do not write unless HC is halted*/ 189#define CMD_RUN XHCI_CMD_RUN 190/* Reset HC - resets internal HC state machine and all registers (except 191 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 192 * The xHCI driver must reinitialize the xHC after setting this bit. 193 */ 194#define CMD_RESET (1 << 1) 195/* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 196#define CMD_EIE XHCI_CMD_EIE 197/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 198#define CMD_HSEIE XHCI_CMD_HSEIE 199/* bits 4:6 are reserved (and should be preserved on writes). */ 200/* light reset (port status stays unchanged) - reset completed when this is 0 */ 201#define CMD_LRESET (1 << 7) 202/* host controller save/restore state. */ 203#define CMD_CSS (1 << 8) 204#define CMD_CRS (1 << 9) 205/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 206#define CMD_EWE XHCI_CMD_EWE 207/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 208 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 209 * '0' means the xHC can power it off if all ports are in the disconnect, 210 * disabled, or powered-off state. 211 */ 212#define CMD_PM_INDEX (1 << 11) 213/* bits 12:31 are reserved (and should be preserved on writes). */ 214 215/* IMAN - Interrupt Management Register */ 216#define IMAN_IE (1 << 1) 217#define IMAN_IP (1 << 0) 218 219/* USBSTS - USB status - status bitmasks */ 220/* HC not running - set to 1 when run/stop bit is cleared. */ 221#define STS_HALT XHCI_STS_HALT 222/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 223#define STS_FATAL (1 << 2) 224/* event interrupt - clear this prior to clearing any IP flags in IR set*/ 225#define STS_EINT (1 << 3) 226/* port change detect */ 227#define STS_PORT (1 << 4) 228/* bits 5:7 reserved and zeroed */ 229/* save state status - '1' means xHC is saving state */ 230#define STS_SAVE (1 << 8) 231/* restore state status - '1' means xHC is restoring state */ 232#define STS_RESTORE (1 << 9) 233/* true: save or restore error */ 234#define STS_SRE (1 << 10) 235/* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 236#define STS_CNR XHCI_STS_CNR 237/* true: internal Host Controller Error - SW needs to reset and reinitialize */ 238#define STS_HCE (1 << 12) 239/* bits 13:31 reserved and should be preserved */ 240 241/* 242 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 243 * Generate a device notification event when the HC sees a transaction with a 244 * notification type that matches a bit set in this bit field. 245 */ 246#define DEV_NOTE_MASK (0xffff) 247#define ENABLE_DEV_NOTE(x) (1 << (x)) 248/* Most of the device notification types should only be used for debug. 249 * SW does need to pay attention to function wake notifications. 250 */ 251#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 252 253/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 254/* bit 0 is the command ring cycle state */ 255/* stop ring operation after completion of the currently executing command */ 256#define CMD_RING_PAUSE (1 << 1) 257/* stop ring immediately - abort the currently executing command */ 258#define CMD_RING_ABORT (1 << 2) 259/* true: command ring is running */ 260#define CMD_RING_RUNNING (1 << 3) 261/* bits 4:5 reserved and should be preserved */ 262/* Command Ring pointer - bit mask for the lower 32 bits. */ 263#define CMD_RING_RSVD_BITS (0x3f) 264 265/* CONFIG - Configure Register - config_reg bitmasks */ 266/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 267#define MAX_DEVS(p) ((p) & 0xff) 268/* bits 8:31 - reserved and should be preserved */ 269 270/* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 271/* true: device connected */ 272#define PORT_CONNECT (1 << 0) 273/* true: port enabled */ 274#define PORT_PE (1 << 1) 275/* bit 2 reserved and zeroed */ 276/* true: port has an over-current condition */ 277#define PORT_OC (1 << 3) 278/* true: port reset signaling asserted */ 279#define PORT_RESET (1 << 4) 280/* Port Link State - bits 5:8 281 * A read gives the current link PM state of the port, 282 * a write with Link State Write Strobe set sets the link state. 283 */ 284#define PORT_PLS_MASK (0xf << 5) 285#define XDEV_U0 (0x0 << 5) 286#define XDEV_U2 (0x2 << 5) 287#define XDEV_U3 (0x3 << 5) 288#define XDEV_INACTIVE (0x6 << 5) 289#define XDEV_RESUME (0xf << 5) 290/* true: port has power (see HCC_PPC) */ 291#define PORT_POWER (1 << 9) 292/* bits 10:13 indicate device speed: 293 * 0 - undefined speed - port hasn't be initialized by a reset yet 294 * 1 - full speed 295 * 2 - low speed 296 * 3 - high speed 297 * 4 - super speed 298 * 5-15 reserved 299 */ 300#define DEV_SPEED_MASK (0xf << 10) 301#define XDEV_FS (0x1 << 10) 302#define XDEV_LS (0x2 << 10) 303#define XDEV_HS (0x3 << 10) 304#define XDEV_SS (0x4 << 10) 305#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 306#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 307#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 308#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 309#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 310/* Bits 20:23 in the Slot Context are the speed for the device */ 311#define SLOT_SPEED_FS (XDEV_FS << 10) 312#define SLOT_SPEED_LS (XDEV_LS << 10) 313#define SLOT_SPEED_HS (XDEV_HS << 10) 314#define SLOT_SPEED_SS (XDEV_SS << 10) 315/* Port Indicator Control */ 316#define PORT_LED_OFF (0 << 14) 317#define PORT_LED_AMBER (1 << 14) 318#define PORT_LED_GREEN (2 << 14) 319#define PORT_LED_MASK (3 << 14) 320/* Port Link State Write Strobe - set this when changing link state */ 321#define PORT_LINK_STROBE (1 << 16) 322/* true: connect status change */ 323#define PORT_CSC (1 << 17) 324/* true: port enable change */ 325#define PORT_PEC (1 << 18) 326/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 327 * into an enabled state, and the device into the default state. A "warm" reset 328 * also resets the link, forcing the device through the link training sequence. 329 * SW can also look at the Port Reset register to see when warm reset is done. 330 */ 331#define PORT_WRC (1 << 19) 332/* true: over-current change */ 333#define PORT_OCC (1 << 20) 334/* true: reset change - 1 to 0 transition of PORT_RESET */ 335#define PORT_RC (1 << 21) 336/* port link status change - set on some port link state transitions: 337 * Transition Reason 338 * ------------------------------------------------------------------------------ 339 * - U3 to Resume Wakeup signaling from a device 340 * - Resume to Recovery to U0 USB 3.0 device resume 341 * - Resume to U0 USB 2.0 device resume 342 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 343 * - U3 to U0 Software resume of USB 2.0 device complete 344 * - U2 to U0 L1 resume of USB 2.1 device complete 345 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 346 * - U0 to disabled L1 entry error with USB 2.1 device 347 * - Any state to inactive Error on USB 3.0 port 348 */ 349#define PORT_PLC (1 << 22) 350/* port configure error change - port failed to configure its link partner */ 351#define PORT_CEC (1 << 23) 352/* Cold Attach Status - xHC can set this bit to report device attached during 353 * Sx state. Warm port reset should be perfomed to clear this bit and move port 354 * to connected state. 355 */ 356#define PORT_CAS (1 << 24) 357/* wake on connect (enable) */ 358#define PORT_WKCONN_E (1 << 25) 359/* wake on disconnect (enable) */ 360#define PORT_WKDISC_E (1 << 26) 361/* wake on over-current (enable) */ 362#define PORT_WKOC_E (1 << 27) 363/* bits 28:29 reserved */ 364/* true: device is non-removable - for USB 3.0 roothub emulation */ 365#define PORT_DEV_REMOVE (1 << 30) 366/* Initiate a warm port reset - complete when PORT_WRC is '1' */ 367#define PORT_WR (1 << 31) 368 369/* We mark duplicate entries with -1 */ 370#define DUPLICATE_ENTRY ((u8)(-1)) 371 372/* Port Power Management Status and Control - port_power_base bitmasks */ 373/* Inactivity timer value for transitions into U1, in microseconds. 374 * Timeout can be up to 127us. 0xFF means an infinite timeout. 375 */ 376#define PORT_U1_TIMEOUT(p) ((p) & 0xff) 377#define PORT_U1_TIMEOUT_MASK 0xff 378/* Inactivity timer value for transitions into U2 */ 379#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 380#define PORT_U2_TIMEOUT_MASK (0xff << 8) 381/* Bits 24:31 for port testing */ 382 383/* USB2 Protocol PORTSPMSC */ 384#define PORT_L1S_MASK 7 385#define PORT_L1S_SUCCESS 1 386#define PORT_RWE (1 << 3) 387#define PORT_HIRD(p) (((p) & 0xf) << 4) 388#define PORT_HIRD_MASK (0xf << 4) 389#define PORT_L1DS_MASK (0xff << 8) 390#define PORT_L1DS(p) (((p) & 0xff) << 8) 391#define PORT_HLE (1 << 16) 392 393 394/* USB2 Protocol PORTHLPMC */ 395#define PORT_HIRDM(p)((p) & 3) 396#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 397#define PORT_BESLD(p)(((p) & 0xf) << 10) 398 399/* use 512 microseconds as USB2 LPM L1 default timeout. */ 400#define XHCI_L1_TIMEOUT 512 401 402/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 403 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 404 * by other operating systems. 405 * 406 * XHCI 1.0 errata 8/14/12 Table 13 notes: 407 * "Software should choose xHC BESL/BESLD field values that do not violate a 408 * device's resume latency requirements, 409 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 410 * or not program values < '4' if BLC = '0' and a BESL device is attached. 411 */ 412#define XHCI_DEFAULT_BESL 4 413 414/** 415 * struct xhci_intr_reg - Interrupt Register Set 416 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 417 * interrupts and check for pending interrupts. 418 * @irq_control: IMOD - Interrupt Moderation Register. 419 * Used to throttle interrupts. 420 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 421 * @erst_base: ERST base address. 422 * @erst_dequeue: Event ring dequeue pointer. 423 * 424 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 425 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 426 * multiple segments of the same size. The HC places events on the ring and 427 * "updates the Cycle bit in the TRBs to indicate to software the current 428 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 429 * updates the dequeue pointer. 430 */ 431struct xhci_intr_reg { 432 __le32 irq_pending; 433 __le32 irq_control; 434 __le32 erst_size; 435 __le32 rsvd; 436 __le64 erst_base; 437 __le64 erst_dequeue; 438}; 439 440/* irq_pending bitmasks */ 441#define ER_IRQ_PENDING(p) ((p) & 0x1) 442/* bits 2:31 need to be preserved */ 443/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 444#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 445#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 446#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 447 448/* irq_control bitmasks */ 449/* Minimum interval between interrupts (in 250ns intervals). The interval 450 * between interrupts will be longer if there are no events on the event ring. 451 * Default is 4000 (1 ms). 452 */ 453#define ER_IRQ_INTERVAL_MASK (0xffff) 454/* Counter used to count down the time to the next interrupt - HW use only */ 455#define ER_IRQ_COUNTER_MASK (0xffff << 16) 456 457/* erst_size bitmasks */ 458/* Preserve bits 16:31 of erst_size */ 459#define ERST_SIZE_MASK (0xffff << 16) 460 461/* erst_dequeue bitmasks */ 462/* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 463 * where the current dequeue pointer lies. This is an optional HW hint. 464 */ 465#define ERST_DESI_MASK (0x7) 466/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 467 * a work queue (or delayed service routine)? 468 */ 469#define ERST_EHB (1 << 3) 470#define ERST_PTR_MASK (0xf) 471 472/** 473 * struct xhci_run_regs 474 * @microframe_index: 475 * MFINDEX - current microframe number 476 * 477 * Section 5.5 Host Controller Runtime Registers: 478 * "Software should read and write these registers using only Dword (32 bit) 479 * or larger accesses" 480 */ 481struct xhci_run_regs { 482 __le32 microframe_index; 483 __le32 rsvd[7]; 484 struct xhci_intr_reg ir_set[128]; 485}; 486 487/** 488 * struct doorbell_array 489 * 490 * Bits 0 - 7: Endpoint target 491 * Bits 8 - 15: RsvdZ 492 * Bits 16 - 31: Stream ID 493 * 494 * Section 5.6 495 */ 496struct xhci_doorbell_array { 497 __le32 doorbell[256]; 498}; 499 500#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 501#define DB_VALUE_HOST 0x00000000 502 503/** 504 * struct xhci_protocol_caps 505 * @revision: major revision, minor revision, capability ID, 506 * and next capability pointer. 507 * @name_string: Four ASCII characters to say which spec this xHC 508 * follows, typically "USB ". 509 * @port_info: Port offset, count, and protocol-defined information. 510 */ 511struct xhci_protocol_caps { 512 u32 revision; 513 u32 name_string; 514 u32 port_info; 515}; 516 517#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 518#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 519#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 520 521/** 522 * struct xhci_container_ctx 523 * @type: Type of context. Used to calculated offsets to contained contexts. 524 * @size: Size of the context data 525 * @bytes: The raw context data given to HW 526 * @dma: dma address of the bytes 527 * 528 * Represents either a Device or Input context. Holds a pointer to the raw 529 * memory used for the context (bytes) and dma address of it (dma). 530 */ 531struct xhci_container_ctx { 532 unsigned type; 533#define XHCI_CTX_TYPE_DEVICE 0x1 534#define XHCI_CTX_TYPE_INPUT 0x2 535 536 int size; 537 538 u8 *bytes; 539 dma_addr_t dma; 540}; 541 542/** 543 * struct xhci_slot_ctx 544 * @dev_info: Route string, device speed, hub info, and last valid endpoint 545 * @dev_info2: Max exit latency for device number, root hub port number 546 * @tt_info: tt_info is used to construct split transaction tokens 547 * @dev_state: slot state and device address 548 * 549 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 550 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 551 * reserved at the end of the slot context for HC internal use. 552 */ 553struct xhci_slot_ctx { 554 __le32 dev_info; 555 __le32 dev_info2; 556 __le32 tt_info; 557 __le32 dev_state; 558 /* offset 0x10 to 0x1f reserved for HC internal use */ 559 __le32 reserved[4]; 560}; 561 562/* dev_info bitmasks */ 563/* Route String - 0:19 */ 564#define ROUTE_STRING_MASK (0xfffff) 565/* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 566#define DEV_SPEED (0xf << 20) 567/* bit 24 reserved */ 568/* Is this LS/FS device connected through a HS hub? - bit 25 */ 569#define DEV_MTT (0x1 << 25) 570/* Set if the device is a hub - bit 26 */ 571#define DEV_HUB (0x1 << 26) 572/* Index of the last valid endpoint context in this device context - 27:31 */ 573#define LAST_CTX_MASK (0x1f << 27) 574#define LAST_CTX(p) ((p) << 27) 575#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 576#define SLOT_FLAG (1 << 0) 577#define EP0_FLAG (1 << 1) 578 579/* dev_info2 bitmasks */ 580/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 581#define MAX_EXIT (0xffff) 582/* Root hub port number that is needed to access the USB device */ 583#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 584#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 585/* Maximum number of ports under a hub device */ 586#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 587 588/* tt_info bitmasks */ 589/* 590 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 591 * The Slot ID of the hub that isolates the high speed signaling from 592 * this low or full-speed device. '0' if attached to root hub port. 593 */ 594#define TT_SLOT (0xff) 595/* 596 * The number of the downstream facing port of the high-speed hub 597 * '0' if the device is not low or full speed. 598 */ 599#define TT_PORT (0xff << 8) 600#define TT_THINK_TIME(p) (((p) & 0x3) << 16) 601 602/* dev_state bitmasks */ 603/* USB device address - assigned by the HC */ 604#define DEV_ADDR_MASK (0xff) 605/* bits 8:26 reserved */ 606/* Slot state */ 607#define SLOT_STATE (0x1f << 27) 608#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 609 610#define SLOT_STATE_DISABLED 0 611#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 612#define SLOT_STATE_DEFAULT 1 613#define SLOT_STATE_ADDRESSED 2 614#define SLOT_STATE_CONFIGURED 3 615 616/** 617 * struct xhci_ep_ctx 618 * @ep_info: endpoint state, streams, mult, and interval information. 619 * @ep_info2: information on endpoint type, max packet size, max burst size, 620 * error count, and whether the HC will force an event for all 621 * transactions. 622 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 623 * defines one stream, this points to the endpoint transfer ring. 624 * Otherwise, it points to a stream context array, which has a 625 * ring pointer for each flow. 626 * @tx_info: 627 * Average TRB lengths for the endpoint ring and 628 * max payload within an Endpoint Service Interval Time (ESIT). 629 * 630 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 631 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 632 * reserved at the end of the endpoint context for HC internal use. 633 */ 634struct xhci_ep_ctx { 635 __le32 ep_info; 636 __le32 ep_info2; 637 __le64 deq; 638 __le32 tx_info; 639 /* offset 0x14 - 0x1f reserved for HC internal use */ 640 __le32 reserved[3]; 641}; 642 643/* ep_info bitmasks */ 644/* 645 * Endpoint State - bits 0:2 646 * 0 - disabled 647 * 1 - running 648 * 2 - halted due to halt condition - ok to manipulate endpoint ring 649 * 3 - stopped 650 * 4 - TRB error 651 * 5-7 - reserved 652 */ 653#define EP_STATE_MASK (0xf) 654#define EP_STATE_DISABLED 0 655#define EP_STATE_RUNNING 1 656#define EP_STATE_HALTED 2 657#define EP_STATE_STOPPED 3 658#define EP_STATE_ERROR 4 659/* Mult - Max number of burtst within an interval, in EP companion desc. */ 660#define EP_MULT(p) (((p) & 0x3) << 8) 661#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 662/* bits 10:14 are Max Primary Streams */ 663/* bit 15 is Linear Stream Array */ 664/* Interval - period between requests to an endpoint - 125u increments. */ 665#define EP_INTERVAL(p) (((p) & 0xff) << 16) 666#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 667#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 668#define EP_MAXPSTREAMS_MASK (0x1f << 10) 669#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 670/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 671#define EP_HAS_LSA (1 << 15) 672 673/* ep_info2 bitmasks */ 674/* 675 * Force Event - generate transfer events for all TRBs for this endpoint 676 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 677 */ 678#define FORCE_EVENT (0x1) 679#define ERROR_COUNT(p) (((p) & 0x3) << 1) 680#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 681#define EP_TYPE(p) ((p) << 3) 682#define ISOC_OUT_EP 1 683#define BULK_OUT_EP 2 684#define INT_OUT_EP 3 685#define CTRL_EP 4 686#define ISOC_IN_EP 5 687#define BULK_IN_EP 6 688#define INT_IN_EP 7 689/* bit 6 reserved */ 690/* bit 7 is Host Initiate Disable - for disabling stream selection */ 691#define MAX_BURST(p) (((p)&0xff) << 8) 692#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 693#define MAX_PACKET(p) (((p)&0xffff) << 16) 694#define MAX_PACKET_MASK (0xffff << 16) 695#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 696 697/* Get max packet size from ep desc. Bit 10..0 specify the max packet size. 698 * USB2.0 spec 9.6.6. 699 */ 700#define GET_MAX_PACKET(p) ((p) & 0x7ff) 701 702/* tx_info bitmasks */ 703#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) 704#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) 705#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 706 707/* deq bitmasks */ 708#define EP_CTX_CYCLE_MASK (1 << 0) 709#define SCTX_DEQ_MASK (~0xfL) 710 711 712/** 713 * struct xhci_input_control_context 714 * Input control context; see section 6.2.5. 715 * 716 * @drop_context: set the bit of the endpoint context you want to disable 717 * @add_context: set the bit of the endpoint context you want to enable 718 */ 719struct xhci_input_control_ctx { 720 __le32 drop_flags; 721 __le32 add_flags; 722 __le32 rsvd2[6]; 723}; 724 725#define EP_IS_ADDED(ctrl_ctx, i) \ 726 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 727#define EP_IS_DROPPED(ctrl_ctx, i) \ 728 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 729 730/* Represents everything that is needed to issue a command on the command ring. 731 * It's useful to pre-allocate these for commands that cannot fail due to 732 * out-of-memory errors, like freeing streams. 733 */ 734struct xhci_command { 735 /* Input context for changing device state */ 736 struct xhci_container_ctx *in_ctx; 737 u32 status; 738 /* If completion is null, no one is waiting on this command 739 * and the structure can be freed after the command completes. 740 */ 741 struct completion *completion; 742 union xhci_trb *command_trb; 743 struct list_head cmd_list; 744}; 745 746/* drop context bitmasks */ 747#define DROP_EP(x) (0x1 << x) 748/* add context bitmasks */ 749#define ADD_EP(x) (0x1 << x) 750 751struct xhci_stream_ctx { 752 /* 64-bit stream ring address, cycle state, and stream type */ 753 __le64 stream_ring; 754 /* offset 0x14 - 0x1f reserved for HC internal use */ 755 __le32 reserved[2]; 756}; 757 758/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 759#define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 760/* Secondary stream array type, dequeue pointer is to a transfer ring */ 761#define SCT_SEC_TR 0 762/* Primary stream array type, dequeue pointer is to a transfer ring */ 763#define SCT_PRI_TR 1 764/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 765#define SCT_SSA_8 2 766#define SCT_SSA_16 3 767#define SCT_SSA_32 4 768#define SCT_SSA_64 5 769#define SCT_SSA_128 6 770#define SCT_SSA_256 7 771 772/* Assume no secondary streams for now */ 773struct xhci_stream_info { 774 struct xhci_ring **stream_rings; 775 /* Number of streams, including stream 0 (which drivers can't use) */ 776 unsigned int num_streams; 777 /* The stream context array may be bigger than 778 * the number of streams the driver asked for 779 */ 780 struct xhci_stream_ctx *stream_ctx_array; 781 unsigned int num_stream_ctxs; 782 dma_addr_t ctx_array_dma; 783 /* For mapping physical TRB addresses to segments in stream rings */ 784 struct radix_tree_root trb_address_map; 785 struct xhci_command *free_streams_command; 786}; 787 788#define SMALL_STREAM_ARRAY_SIZE 256 789#define MEDIUM_STREAM_ARRAY_SIZE 1024 790 791/* Some Intel xHCI host controllers need software to keep track of the bus 792 * bandwidth. Keep track of endpoint info here. Each root port is allocated 793 * the full bus bandwidth. We must also treat TTs (including each port under a 794 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 795 * (DMI) also limits the total bandwidth (across all domains) that can be used. 796 */ 797struct xhci_bw_info { 798 /* ep_interval is zero-based */ 799 unsigned int ep_interval; 800 /* mult and num_packets are one-based */ 801 unsigned int mult; 802 unsigned int num_packets; 803 unsigned int max_packet_size; 804 unsigned int max_esit_payload; 805 unsigned int type; 806}; 807 808/* "Block" sizes in bytes the hardware uses for different device speeds. 809 * The logic in this part of the hardware limits the number of bits the hardware 810 * can use, so must represent bandwidth in a less precise manner to mimic what 811 * the scheduler hardware computes. 812 */ 813#define FS_BLOCK 1 814#define HS_BLOCK 4 815#define SS_BLOCK 16 816#define DMI_BLOCK 32 817 818/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 819 * with each byte transferred. SuperSpeed devices have an initial overhead to 820 * set up bursts. These are in blocks, see above. LS overhead has already been 821 * translated into FS blocks. 822 */ 823#define DMI_OVERHEAD 8 824#define DMI_OVERHEAD_BURST 4 825#define SS_OVERHEAD 8 826#define SS_OVERHEAD_BURST 32 827#define HS_OVERHEAD 26 828#define FS_OVERHEAD 20 829#define LS_OVERHEAD 128 830/* The TTs need to claim roughly twice as much bandwidth (94 bytes per 831 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 832 * of overhead associated with split transfers crossing microframe boundaries. 833 * 31 blocks is pure protocol overhead. 834 */ 835#define TT_HS_OVERHEAD (31 + 94) 836#define TT_DMI_OVERHEAD (25 + 12) 837 838/* Bandwidth limits in blocks */ 839#define FS_BW_LIMIT 1285 840#define TT_BW_LIMIT 1320 841#define HS_BW_LIMIT 1607 842#define SS_BW_LIMIT_IN 3906 843#define DMI_BW_LIMIT_IN 3906 844#define SS_BW_LIMIT_OUT 3906 845#define DMI_BW_LIMIT_OUT 3906 846 847/* Percentage of bus bandwidth reserved for non-periodic transfers */ 848#define FS_BW_RESERVED 10 849#define HS_BW_RESERVED 20 850#define SS_BW_RESERVED 10 851 852struct xhci_virt_ep { 853 struct xhci_ring *ring; 854 /* Related to endpoints that are configured to use stream IDs only */ 855 struct xhci_stream_info *stream_info; 856 /* Temporary storage in case the configure endpoint command fails and we 857 * have to restore the device state to the previous state 858 */ 859 struct xhci_ring *new_ring; 860 unsigned int ep_state; 861#define SET_DEQ_PENDING (1 << 0) 862#define EP_HALTED (1 << 1) /* For stall handling */ 863#define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ 864/* Transitioning the endpoint to using streams, don't enqueue URBs */ 865#define EP_GETTING_STREAMS (1 << 3) 866#define EP_HAS_STREAMS (1 << 4) 867/* Transitioning the endpoint to not using streams, don't enqueue URBs */ 868#define EP_GETTING_NO_STREAMS (1 << 5) 869 /* ---- Related to URB cancellation ---- */ 870 struct list_head cancelled_td_list; 871 struct xhci_td *stopped_td; 872 unsigned int stopped_stream; 873 /* Watchdog timer for stop endpoint command to cancel URBs */ 874 struct timer_list stop_cmd_timer; 875 int stop_cmds_pending; 876 struct xhci_hcd *xhci; 877 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 878 * command. We'll need to update the ring's dequeue segment and dequeue 879 * pointer after the command completes. 880 */ 881 struct xhci_segment *queued_deq_seg; 882 union xhci_trb *queued_deq_ptr; 883 /* 884 * Sometimes the xHC can not process isochronous endpoint ring quickly 885 * enough, and it will miss some isoc tds on the ring and generate 886 * a Missed Service Error Event. 887 * Set skip flag when receive a Missed Service Error Event and 888 * process the missed tds on the endpoint ring. 889 */ 890 bool skip; 891 /* Bandwidth checking storage */ 892 struct xhci_bw_info bw_info; 893 struct list_head bw_endpoint_list; 894}; 895 896enum xhci_overhead_type { 897 LS_OVERHEAD_TYPE = 0, 898 FS_OVERHEAD_TYPE, 899 HS_OVERHEAD_TYPE, 900}; 901 902struct xhci_interval_bw { 903 unsigned int num_packets; 904 /* Sorted by max packet size. 905 * Head of the list is the greatest max packet size. 906 */ 907 struct list_head endpoints; 908 /* How many endpoints of each speed are present. */ 909 unsigned int overhead[3]; 910}; 911 912#define XHCI_MAX_INTERVAL 16 913 914struct xhci_interval_bw_table { 915 unsigned int interval0_esit_payload; 916 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 917 /* Includes reserved bandwidth for async endpoints */ 918 unsigned int bw_used; 919 unsigned int ss_bw_in; 920 unsigned int ss_bw_out; 921}; 922 923 924struct xhci_virt_device { 925 struct usb_device *udev; 926 /* 927 * Commands to the hardware are passed an "input context" that 928 * tells the hardware what to change in its data structures. 929 * The hardware will return changes in an "output context" that 930 * software must allocate for the hardware. We need to keep 931 * track of input and output contexts separately because 932 * these commands might fail and we don't trust the hardware. 933 */ 934 struct xhci_container_ctx *out_ctx; 935 /* Used for addressing devices and configuration changes */ 936 struct xhci_container_ctx *in_ctx; 937 /* Rings saved to ensure old alt settings can be re-instated */ 938 struct xhci_ring **ring_cache; 939 int num_rings_cached; 940#define XHCI_MAX_RINGS_CACHED 31 941 struct xhci_virt_ep eps[31]; 942 struct completion cmd_completion; 943 u8 fake_port; 944 u8 real_port; 945 struct xhci_interval_bw_table *bw_table; 946 struct xhci_tt_bw_info *tt_info; 947 /* The current max exit latency for the enabled USB3 link states. */ 948 u16 current_mel; 949}; 950 951/* 952 * For each roothub, keep track of the bandwidth information for each periodic 953 * interval. 954 * 955 * If a high speed hub is attached to the roothub, each TT associated with that 956 * hub is a separate bandwidth domain. The interval information for the 957 * endpoints on the devices under that TT will appear in the TT structure. 958 */ 959struct xhci_root_port_bw_info { 960 struct list_head tts; 961 unsigned int num_active_tts; 962 struct xhci_interval_bw_table bw_table; 963}; 964 965struct xhci_tt_bw_info { 966 struct list_head tt_list; 967 int slot_id; 968 int ttport; 969 struct xhci_interval_bw_table bw_table; 970 int active_eps; 971}; 972 973 974/** 975 * struct xhci_device_context_array 976 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 977 */ 978struct xhci_device_context_array { 979 /* 64-bit device addresses; we only write 32-bit addresses */ 980 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 981 /* private xHCD pointers */ 982 dma_addr_t dma; 983}; 984/* TODO: write function to set the 64-bit device DMA address */ 985/* 986 * TODO: change this to be dynamically sized at HC mem init time since the HC 987 * might not be able to handle the maximum number of devices possible. 988 */ 989 990 991struct xhci_transfer_event { 992 /* 64-bit buffer address, or immediate data */ 993 __le64 buffer; 994 __le32 transfer_len; 995 /* This field is interpreted differently based on the type of TRB */ 996 __le32 flags; 997}; 998 999/* Transfer event TRB length bit mask */ 1000/* bits 0:23 */ 1001#define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1002 1003/** Transfer Event bit fields **/ 1004#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1005 1006/* Completion Code - only applicable for some types of TRBs */ 1007#define COMP_CODE_MASK (0xff << 24) 1008#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1009#define COMP_SUCCESS 1 1010/* Data Buffer Error */ 1011#define COMP_DB_ERR 2 1012/* Babble Detected Error */ 1013#define COMP_BABBLE 3 1014/* USB Transaction Error */ 1015#define COMP_TX_ERR 4 1016/* TRB Error - some TRB field is invalid */ 1017#define COMP_TRB_ERR 5 1018/* Stall Error - USB device is stalled */ 1019#define COMP_STALL 6 1020/* Resource Error - HC doesn't have memory for that device configuration */ 1021#define COMP_ENOMEM 7 1022/* Bandwidth Error - not enough room in schedule for this dev config */ 1023#define COMP_BW_ERR 8 1024/* No Slots Available Error - HC ran out of device slots */ 1025#define COMP_ENOSLOTS 9 1026/* Invalid Stream Type Error */ 1027#define COMP_STREAM_ERR 10 1028/* Slot Not Enabled Error - doorbell rung for disabled device slot */ 1029#define COMP_EBADSLT 11 1030/* Endpoint Not Enabled Error */ 1031#define COMP_EBADEP 12 1032/* Short Packet */ 1033#define COMP_SHORT_TX 13 1034/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ 1035#define COMP_UNDERRUN 14 1036/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ 1037#define COMP_OVERRUN 15 1038/* Virtual Function Event Ring Full Error */ 1039#define COMP_VF_FULL 16 1040/* Parameter Error - Context parameter is invalid */ 1041#define COMP_EINVAL 17 1042/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ 1043#define COMP_BW_OVER 18 1044/* Context State Error - illegal context state transition requested */ 1045#define COMP_CTX_STATE 19 1046/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ 1047#define COMP_PING_ERR 20 1048/* Event Ring is full */ 1049#define COMP_ER_FULL 21 1050/* Incompatible Device Error */ 1051#define COMP_DEV_ERR 22 1052/* Missed Service Error - HC couldn't service an isoc ep within interval */ 1053#define COMP_MISSED_INT 23 1054/* Successfully stopped command ring */ 1055#define COMP_CMD_STOP 24 1056/* Successfully aborted current command and stopped command ring */ 1057#define COMP_CMD_ABORT 25 1058/* Stopped - transfer was terminated by a stop endpoint command */ 1059#define COMP_STOP 26 1060/* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ 1061#define COMP_STOP_INVAL 27 1062/* Control Abort Error - Debug Capability - control pipe aborted */ 1063#define COMP_DBG_ABORT 28 1064/* Max Exit Latency Too Large Error */ 1065#define COMP_MEL_ERR 29 1066/* TRB type 30 reserved */ 1067/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ 1068#define COMP_BUFF_OVER 31 1069/* Event Lost Error - xHC has an "internal event overrun condition" */ 1070#define COMP_ISSUES 32 1071/* Undefined Error - reported when other error codes don't apply */ 1072#define COMP_UNKNOWN 33 1073/* Invalid Stream ID Error */ 1074#define COMP_STRID_ERR 34 1075/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ 1076#define COMP_2ND_BW_ERR 35 1077/* Split Transaction Error */ 1078#define COMP_SPLIT_ERR 36 1079 1080struct xhci_link_trb { 1081 /* 64-bit segment pointer*/ 1082 __le64 segment_ptr; 1083 __le32 intr_target; 1084 __le32 control; 1085}; 1086 1087/* control bitfields */ 1088#define LINK_TOGGLE (0x1<<1) 1089 1090/* Command completion event TRB */ 1091struct xhci_event_cmd { 1092 /* Pointer to command TRB, or the value passed by the event data trb */ 1093 __le64 cmd_trb; 1094 __le32 status; 1095 __le32 flags; 1096}; 1097 1098/* flags bitmasks */ 1099 1100/* Address device - disable SetAddress */ 1101#define TRB_BSR (1<<9) 1102enum xhci_setup_dev { 1103 SETUP_CONTEXT_ONLY, 1104 SETUP_CONTEXT_ADDRESS, 1105}; 1106 1107/* bits 16:23 are the virtual function ID */ 1108/* bits 24:31 are the slot ID */ 1109#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1110#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1111 1112/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1113#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1114#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1115 1116#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1117#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1118#define LAST_EP_INDEX 30 1119 1120/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1121#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1122#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1123#define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1124 1125 1126/* Port Status Change Event TRB fields */ 1127/* Port ID - bits 31:24 */ 1128#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1129 1130/* Normal TRB fields */ 1131/* transfer_len bitmasks - bits 0:16 */ 1132#define TRB_LEN(p) ((p) & 0x1ffff) 1133/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1134#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1135/* Interrupter Target - which MSI-X vector to target the completion event at */ 1136#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1137#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1138#define TRB_TBC(p) (((p) & 0x3) << 7) 1139#define TRB_TLBPC(p) (((p) & 0xf) << 16) 1140 1141/* Cycle bit - indicates TRB ownership by HC or HCD */ 1142#define TRB_CYCLE (1<<0) 1143/* 1144 * Force next event data TRB to be evaluated before task switch. 1145 * Used to pass OS data back after a TD completes. 1146 */ 1147#define TRB_ENT (1<<1) 1148/* Interrupt on short packet */ 1149#define TRB_ISP (1<<2) 1150/* Set PCIe no snoop attribute */ 1151#define TRB_NO_SNOOP (1<<3) 1152/* Chain multiple TRBs into a TD */ 1153#define TRB_CHAIN (1<<4) 1154/* Interrupt on completion */ 1155#define TRB_IOC (1<<5) 1156/* The buffer pointer contains immediate data */ 1157#define TRB_IDT (1<<6) 1158 1159/* Block Event Interrupt */ 1160#define TRB_BEI (1<<9) 1161 1162/* Control transfer TRB specific fields */ 1163#define TRB_DIR_IN (1<<16) 1164#define TRB_TX_TYPE(p) ((p) << 16) 1165#define TRB_DATA_OUT 2 1166#define TRB_DATA_IN 3 1167 1168/* Isochronous TRB specific fields */ 1169#define TRB_SIA (1<<31) 1170 1171struct xhci_generic_trb { 1172 __le32 field[4]; 1173}; 1174 1175union xhci_trb { 1176 struct xhci_link_trb link; 1177 struct xhci_transfer_event trans_event; 1178 struct xhci_event_cmd event_cmd; 1179 struct xhci_generic_trb generic; 1180}; 1181 1182/* TRB bit mask */ 1183#define TRB_TYPE_BITMASK (0xfc00) 1184#define TRB_TYPE(p) ((p) << 10) 1185#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1186/* TRB type IDs */ 1187/* bulk, interrupt, isoc scatter/gather, and control data stage */ 1188#define TRB_NORMAL 1 1189/* setup stage for control transfers */ 1190#define TRB_SETUP 2 1191/* data stage for control transfers */ 1192#define TRB_DATA 3 1193/* status stage for control transfers */ 1194#define TRB_STATUS 4 1195/* isoc transfers */ 1196#define TRB_ISOC 5 1197/* TRB for linking ring segments */ 1198#define TRB_LINK 6 1199#define TRB_EVENT_DATA 7 1200/* Transfer Ring No-op (not for the command ring) */ 1201#define TRB_TR_NOOP 8 1202/* Command TRBs */ 1203/* Enable Slot Command */ 1204#define TRB_ENABLE_SLOT 9 1205/* Disable Slot Command */ 1206#define TRB_DISABLE_SLOT 10 1207/* Address Device Command */ 1208#define TRB_ADDR_DEV 11 1209/* Configure Endpoint Command */ 1210#define TRB_CONFIG_EP 12 1211/* Evaluate Context Command */ 1212#define TRB_EVAL_CONTEXT 13 1213/* Reset Endpoint Command */ 1214#define TRB_RESET_EP 14 1215/* Stop Transfer Ring Command */ 1216#define TRB_STOP_RING 15 1217/* Set Transfer Ring Dequeue Pointer Command */ 1218#define TRB_SET_DEQ 16 1219/* Reset Device Command */ 1220#define TRB_RESET_DEV 17 1221/* Force Event Command (opt) */ 1222#define TRB_FORCE_EVENT 18 1223/* Negotiate Bandwidth Command (opt) */ 1224#define TRB_NEG_BANDWIDTH 19 1225/* Set Latency Tolerance Value Command (opt) */ 1226#define TRB_SET_LT 20 1227/* Get port bandwidth Command */ 1228#define TRB_GET_BW 21 1229/* Force Header Command - generate a transaction or link management packet */ 1230#define TRB_FORCE_HEADER 22 1231/* No-op Command - not for transfer rings */ 1232#define TRB_CMD_NOOP 23 1233/* TRB IDs 24-31 reserved */ 1234/* Event TRBS */ 1235/* Transfer Event */ 1236#define TRB_TRANSFER 32 1237/* Command Completion Event */ 1238#define TRB_COMPLETION 33 1239/* Port Status Change Event */ 1240#define TRB_PORT_STATUS 34 1241/* Bandwidth Request Event (opt) */ 1242#define TRB_BANDWIDTH_EVENT 35 1243/* Doorbell Event (opt) */ 1244#define TRB_DOORBELL 36 1245/* Host Controller Event */ 1246#define TRB_HC_EVENT 37 1247/* Device Notification Event - device sent function wake notification */ 1248#define TRB_DEV_NOTE 38 1249/* MFINDEX Wrap Event - microframe counter wrapped */ 1250#define TRB_MFINDEX_WRAP 39 1251/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1252 1253/* Nec vendor-specific command completion event. */ 1254#define TRB_NEC_CMD_COMP 48 1255/* Get NEC firmware revision. */ 1256#define TRB_NEC_GET_FW 49 1257 1258#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1259/* Above, but for __le32 types -- can avoid work by swapping constants: */ 1260#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1261 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1262#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1263 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1264 1265#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1266#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1267 1268/* 1269 * TRBS_PER_SEGMENT must be a multiple of 4, 1270 * since the command ring is 64-byte aligned. 1271 * It must also be greater than 16. 1272 */ 1273#define TRBS_PER_SEGMENT 256 1274/* Allow two commands + a link TRB, along with any reserved command TRBs */ 1275#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1276#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1277#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1278/* TRB buffer pointers can't cross 64KB boundaries */ 1279#define TRB_MAX_BUFF_SHIFT 16 1280#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1281 1282struct xhci_segment { 1283 union xhci_trb *trbs; 1284 /* private to HCD */ 1285 struct xhci_segment *next; 1286 dma_addr_t dma; 1287}; 1288 1289struct xhci_td { 1290 struct list_head td_list; 1291 struct list_head cancelled_td_list; 1292 struct urb *urb; 1293 struct xhci_segment *start_seg; 1294 union xhci_trb *first_trb; 1295 union xhci_trb *last_trb; 1296 /* actual_length of the URB has already been set */ 1297 bool urb_length_set; 1298}; 1299 1300/* xHCI command default timeout value */ 1301#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1302 1303/* command descriptor */ 1304struct xhci_cd { 1305 struct xhci_command *command; 1306 union xhci_trb *cmd_trb; 1307}; 1308 1309struct xhci_dequeue_state { 1310 struct xhci_segment *new_deq_seg; 1311 union xhci_trb *new_deq_ptr; 1312 int new_cycle_state; 1313}; 1314 1315enum xhci_ring_type { 1316 TYPE_CTRL = 0, 1317 TYPE_ISOC, 1318 TYPE_BULK, 1319 TYPE_INTR, 1320 TYPE_STREAM, 1321 TYPE_COMMAND, 1322 TYPE_EVENT, 1323}; 1324 1325struct xhci_ring { 1326 struct xhci_segment *first_seg; 1327 struct xhci_segment *last_seg; 1328 union xhci_trb *enqueue; 1329 struct xhci_segment *enq_seg; 1330 unsigned int enq_updates; 1331 union xhci_trb *dequeue; 1332 struct xhci_segment *deq_seg; 1333 unsigned int deq_updates; 1334 struct list_head td_list; 1335 /* 1336 * Write the cycle state into the TRB cycle field to give ownership of 1337 * the TRB to the host controller (if we are the producer), or to check 1338 * if we own the TRB (if we are the consumer). See section 4.9.1. 1339 */ 1340 u32 cycle_state; 1341 unsigned int stream_id; 1342 unsigned int num_segs; 1343 unsigned int num_trbs_free; 1344 unsigned int num_trbs_free_temp; 1345 enum xhci_ring_type type; 1346 bool last_td_was_short; 1347 struct radix_tree_root *trb_address_map; 1348}; 1349 1350struct xhci_erst_entry { 1351 /* 64-bit event ring segment address */ 1352 __le64 seg_addr; 1353 __le32 seg_size; 1354 /* Set to zero */ 1355 __le32 rsvd; 1356}; 1357 1358struct xhci_erst { 1359 struct xhci_erst_entry *entries; 1360 unsigned int num_entries; 1361 /* xhci->event_ring keeps track of segment dma addresses */ 1362 dma_addr_t erst_dma_addr; 1363 /* Num entries the ERST can contain */ 1364 unsigned int erst_size; 1365}; 1366 1367struct xhci_scratchpad { 1368 u64 *sp_array; 1369 dma_addr_t sp_dma; 1370 void **sp_buffers; 1371 dma_addr_t *sp_dma_buffers; 1372}; 1373 1374struct urb_priv { 1375 int length; 1376 int td_cnt; 1377 struct xhci_td *td[0]; 1378}; 1379 1380/* 1381 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1382 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1383 * meaning 64 ring segments. 1384 * Initial allocated size of the ERST, in number of entries */ 1385#define ERST_NUM_SEGS 1 1386/* Initial allocated size of the ERST, in number of entries */ 1387#define ERST_SIZE 64 1388/* Initial number of event segment rings allocated */ 1389#define ERST_ENTRIES 1 1390/* Poll every 60 seconds */ 1391#define POLL_TIMEOUT 60 1392/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1393#define XHCI_STOP_EP_CMD_TIMEOUT 5 1394/* XXX: Make these module parameters */ 1395 1396struct s3_save { 1397 u32 command; 1398 u32 dev_nt; 1399 u64 dcbaa_ptr; 1400 u32 config_reg; 1401 u32 irq_pending; 1402 u32 irq_control; 1403 u32 erst_size; 1404 u64 erst_base; 1405 u64 erst_dequeue; 1406}; 1407 1408/* Use for lpm */ 1409struct dev_info { 1410 u32 dev_id; 1411 struct list_head list; 1412}; 1413 1414struct xhci_bus_state { 1415 unsigned long bus_suspended; 1416 unsigned long next_statechange; 1417 1418 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1419 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1420 u32 port_c_suspend; 1421 u32 suspended_ports; 1422 u32 port_remote_wakeup; 1423 unsigned long resume_done[USB_MAXCHILDREN]; 1424 /* which ports have started to resume */ 1425 unsigned long resuming_ports; 1426 /* Which ports are waiting on RExit to U0 transition. */ 1427 unsigned long rexit_ports; 1428 struct completion rexit_done[USB_MAXCHILDREN]; 1429}; 1430 1431 1432/* 1433 * It can take up to 20 ms to transition from RExit to U0 on the 1434 * Intel Lynx Point LP xHCI host. 1435 */ 1436#define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1437 1438static inline unsigned int hcd_index(struct usb_hcd *hcd) 1439{ 1440 if (hcd->speed == HCD_USB3) 1441 return 0; 1442 else 1443 return 1; 1444} 1445 1446/* There is one xhci_hcd structure per controller */ 1447struct xhci_hcd { 1448 struct usb_hcd *main_hcd; 1449 struct usb_hcd *shared_hcd; 1450 /* glue to PCI and HCD framework */ 1451 struct xhci_cap_regs __iomem *cap_regs; 1452 struct xhci_op_regs __iomem *op_regs; 1453 struct xhci_run_regs __iomem *run_regs; 1454 struct xhci_doorbell_array __iomem *dba; 1455 /* Our HCD's current interrupter register set */ 1456 struct xhci_intr_reg __iomem *ir_set; 1457 1458 /* Cached register copies of read-only HC data */ 1459 __u32 hcs_params1; 1460 __u32 hcs_params2; 1461 __u32 hcs_params3; 1462 __u32 hcc_params; 1463 1464 spinlock_t lock; 1465 1466 /* packed release number */ 1467 u8 sbrn; 1468 u16 hci_version; 1469 u8 max_slots; 1470 u8 max_interrupters; 1471 u8 max_ports; 1472 u8 isoc_threshold; 1473 int event_ring_max; 1474 int addr_64; 1475 /* 4KB min, 128MB max */ 1476 int page_size; 1477 /* Valid values are 12 to 20, inclusive */ 1478 int page_shift; 1479 /* msi-x vectors */ 1480 int msix_count; 1481 struct msix_entry *msix_entries; 1482 /* optional clock */ 1483 struct clk *clk; 1484 /* data structures */ 1485 struct xhci_device_context_array *dcbaa; 1486 struct xhci_ring *cmd_ring; 1487 unsigned int cmd_ring_state; 1488#define CMD_RING_STATE_RUNNING (1 << 0) 1489#define CMD_RING_STATE_ABORTED (1 << 1) 1490#define CMD_RING_STATE_STOPPED (1 << 2) 1491 struct list_head cmd_list; 1492 unsigned int cmd_ring_reserved_trbs; 1493 struct timer_list cmd_timer; 1494 struct xhci_command *current_cmd; 1495 struct xhci_ring *event_ring; 1496 struct xhci_erst erst; 1497 /* Scratchpad */ 1498 struct xhci_scratchpad *scratchpad; 1499 /* Store LPM test failed devices' information */ 1500 struct list_head lpm_failed_devs; 1501 1502 /* slot enabling and address device helpers */ 1503 /* these are not thread safe so use mutex */ 1504 struct mutex mutex; 1505 struct completion addr_dev; 1506 int slot_id; 1507 /* For USB 3.0 LPM enable/disable. */ 1508 struct xhci_command *lpm_command; 1509 /* Internal mirror of the HW's dcbaa */ 1510 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1511 /* For keeping track of bandwidth domains per roothub. */ 1512 struct xhci_root_port_bw_info *rh_bw; 1513 1514 /* DMA pools */ 1515 struct dma_pool *device_pool; 1516 struct dma_pool *segment_pool; 1517 struct dma_pool *small_streams_pool; 1518 struct dma_pool *medium_streams_pool; 1519 1520 /* Host controller watchdog timer structures */ 1521 unsigned int xhc_state; 1522 1523 u32 command; 1524 struct s3_save s3; 1525/* Host controller is dying - not responding to commands. "I'm not dead yet!" 1526 * 1527 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1528 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1529 * that sees this status (other than the timer that set it) should stop touching 1530 * hardware immediately. Interrupt handlers should return immediately when 1531 * they see this status (any time they drop and re-acquire xhci->lock). 1532 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1533 * putting the TD on the canceled list, etc. 1534 * 1535 * There are no reports of xHCI host controllers that display this issue. 1536 */ 1537#define XHCI_STATE_DYING (1 << 0) 1538#define XHCI_STATE_HALTED (1 << 1) 1539#define XHCI_STATE_REMOVING (1 << 2) 1540 /* Statistics */ 1541 int error_bitmask; 1542 unsigned int quirks; 1543#define XHCI_LINK_TRB_QUIRK (1 << 0) 1544#define XHCI_RESET_EP_QUIRK (1 << 1) 1545#define XHCI_NEC_HOST (1 << 2) 1546#define XHCI_AMD_PLL_FIX (1 << 3) 1547#define XHCI_SPURIOUS_SUCCESS (1 << 4) 1548/* 1549 * Certain Intel host controllers have a limit to the number of endpoint 1550 * contexts they can handle. Ideally, they would signal that they can't handle 1551 * anymore endpoint contexts by returning a Resource Error for the Configure 1552 * Endpoint command, but they don't. Instead they expect software to keep track 1553 * of the number of active endpoints for them, across configure endpoint 1554 * commands, reset device commands, disable slot commands, and address device 1555 * commands. 1556 */ 1557#define XHCI_EP_LIMIT_QUIRK (1 << 5) 1558#define XHCI_BROKEN_MSI (1 << 6) 1559#define XHCI_RESET_ON_RESUME (1 << 7) 1560#define XHCI_SW_BW_CHECKING (1 << 8) 1561#define XHCI_AMD_0x96_HOST (1 << 9) 1562#define XHCI_TRUST_TX_LENGTH (1 << 10) 1563#define XHCI_LPM_SUPPORT (1 << 11) 1564#define XHCI_INTEL_HOST (1 << 12) 1565#define XHCI_SPURIOUS_REBOOT (1 << 13) 1566#define XHCI_COMP_MODE_QUIRK (1 << 14) 1567#define XHCI_AVOID_BEI (1 << 15) 1568#define XHCI_PLAT (1 << 16) 1569#define XHCI_SLOW_SUSPEND (1 << 17) 1570#define XHCI_SPURIOUS_WAKEUP (1 << 18) 1571/* For controllers with a broken beyond repair streams implementation */ 1572#define XHCI_BROKEN_STREAMS (1 << 19) 1573#define XHCI_PME_STUCK_QUIRK (1 << 20) 1574#define XHCI_SSIC_PORT_UNUSED (1 << 22) 1575#define XHCI_NO_64BIT_SUPPORT (1 << 23) 1576 unsigned int num_active_eps; 1577 unsigned int limit_active_eps; 1578 /* There are two roothubs to keep track of bus suspend info for */ 1579 struct xhci_bus_state bus_state[2]; 1580 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1581 u8 *port_array; 1582 /* Array of pointers to USB 3.0 PORTSC registers */ 1583 __le32 __iomem **usb3_ports; 1584 unsigned int num_usb3_ports; 1585 /* Array of pointers to USB 2.0 PORTSC registers */ 1586 __le32 __iomem **usb2_ports; 1587 unsigned int num_usb2_ports; 1588 /* support xHCI 0.96 spec USB2 software LPM */ 1589 unsigned sw_lpm_support:1; 1590 /* support xHCI 1.0 spec USB2 hardware LPM */ 1591 unsigned hw_lpm_support:1; 1592 /* cached usb2 extened protocol capabilites */ 1593 u32 *ext_caps; 1594 unsigned int num_ext_caps; 1595 /* Compliance Mode Recovery Data */ 1596 struct timer_list comp_mode_recovery_timer; 1597 u32 port_status_u0; 1598/* Compliance Mode Timer Triggered every 2 seconds */ 1599#define COMP_MODE_RCVRY_MSECS 2000 1600}; 1601 1602/* convert between an HCD pointer and the corresponding EHCI_HCD */ 1603static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1604{ 1605 return *((struct xhci_hcd **) (hcd->hcd_priv)); 1606} 1607 1608static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1609{ 1610 return xhci->main_hcd; 1611} 1612 1613#define xhci_dbg(xhci, fmt, args...) \ 1614 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1615#define xhci_err(xhci, fmt, args...) \ 1616 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1617#define xhci_warn(xhci, fmt, args...) \ 1618 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1619#define xhci_warn_ratelimited(xhci, fmt, args...) \ 1620 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1621#define xhci_info(xhci, fmt, args...) \ 1622 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1623 1624/* 1625 * Registers should always be accessed with double word or quad word accesses. 1626 * 1627 * Some xHCI implementations may support 64-bit address pointers. Registers 1628 * with 64-bit address pointers should be written to with dword accesses by 1629 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1630 * xHCI implementations that do not support 64-bit address pointers will ignore 1631 * the high dword, and write order is irrelevant. 1632 */ 1633static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1634 __le64 __iomem *regs) 1635{ 1636 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1637 u64 val_lo = readl(ptr); 1638 u64 val_hi = readl(ptr + 1); 1639 return val_lo + (val_hi << 32); 1640} 1641static inline void xhci_write_64(struct xhci_hcd *xhci, 1642 const u64 val, __le64 __iomem *regs) 1643{ 1644 __u32 __iomem *ptr = (__u32 __iomem *) regs; 1645 u32 val_lo = lower_32_bits(val); 1646 u32 val_hi = upper_32_bits(val); 1647 1648 writel(val_lo, ptr); 1649 writel(val_hi, ptr + 1); 1650} 1651 1652static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1653{ 1654 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1655} 1656 1657/* xHCI debugging */ 1658void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); 1659void xhci_print_registers(struct xhci_hcd *xhci); 1660void xhci_dbg_regs(struct xhci_hcd *xhci); 1661void xhci_print_run_regs(struct xhci_hcd *xhci); 1662void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); 1663void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); 1664void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); 1665void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); 1666void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1667void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); 1668void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); 1669void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); 1670char *xhci_get_slot_state(struct xhci_hcd *xhci, 1671 struct xhci_container_ctx *ctx); 1672void xhci_dbg_ep_rings(struct xhci_hcd *xhci, 1673 unsigned int slot_id, unsigned int ep_index, 1674 struct xhci_virt_ep *ep); 1675void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1676 const char *fmt, ...); 1677 1678/* xHCI memory management */ 1679void xhci_mem_cleanup(struct xhci_hcd *xhci); 1680int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1681void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1682int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1683int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1684void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1685 struct usb_device *udev); 1686unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1687unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1688unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); 1689unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); 1690unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1691void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1692void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, 1693 struct xhci_bw_info *ep_bw, 1694 struct xhci_interval_bw_table *bw_table, 1695 struct usb_device *udev, 1696 struct xhci_virt_ep *virt_ep, 1697 struct xhci_tt_bw_info *tt_info); 1698void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1699 struct xhci_virt_device *virt_dev, 1700 int old_active_eps); 1701void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1702void xhci_update_bw_info(struct xhci_hcd *xhci, 1703 struct xhci_container_ctx *in_ctx, 1704 struct xhci_input_control_ctx *ctrl_ctx, 1705 struct xhci_virt_device *virt_dev); 1706void xhci_endpoint_copy(struct xhci_hcd *xhci, 1707 struct xhci_container_ctx *in_ctx, 1708 struct xhci_container_ctx *out_ctx, 1709 unsigned int ep_index); 1710void xhci_slot_copy(struct xhci_hcd *xhci, 1711 struct xhci_container_ctx *in_ctx, 1712 struct xhci_container_ctx *out_ctx); 1713int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1714 struct usb_device *udev, struct usb_host_endpoint *ep, 1715 gfp_t mem_flags); 1716void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1717int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1718 unsigned int num_trbs, gfp_t flags); 1719void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, 1720 struct xhci_virt_device *virt_dev, 1721 unsigned int ep_index); 1722struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1723 unsigned int num_stream_ctxs, 1724 unsigned int num_streams, gfp_t flags); 1725void xhci_free_stream_info(struct xhci_hcd *xhci, 1726 struct xhci_stream_info *stream_info); 1727void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1728 struct xhci_ep_ctx *ep_ctx, 1729 struct xhci_stream_info *stream_info); 1730void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1731 struct xhci_virt_ep *ep); 1732void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1733 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1734struct xhci_ring *xhci_dma_to_transfer_ring( 1735 struct xhci_virt_ep *ep, 1736 u64 address); 1737struct xhci_ring *xhci_stream_id_to_ring( 1738 struct xhci_virt_device *dev, 1739 unsigned int ep_index, 1740 unsigned int stream_id); 1741struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 1742 bool allocate_in_ctx, bool allocate_completion, 1743 gfp_t mem_flags); 1744void xhci_urb_free_priv(struct urb_priv *urb_priv); 1745void xhci_free_command(struct xhci_hcd *xhci, 1746 struct xhci_command *command); 1747 1748/* xHCI host controller glue */ 1749typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 1750int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 1751void xhci_quiesce(struct xhci_hcd *xhci); 1752int xhci_halt(struct xhci_hcd *xhci); 1753int xhci_reset(struct xhci_hcd *xhci); 1754int xhci_init(struct usb_hcd *hcd); 1755int xhci_run(struct usb_hcd *hcd); 1756void xhci_stop(struct usb_hcd *hcd); 1757void xhci_shutdown(struct usb_hcd *hcd); 1758int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 1759void xhci_init_driver(struct hc_driver *drv, int (*setup_fn)(struct usb_hcd *)); 1760 1761#ifdef CONFIG_PM 1762int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 1763int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 1764#else 1765#define xhci_suspend NULL 1766#define xhci_resume NULL 1767#endif 1768 1769int xhci_get_frame(struct usb_hcd *hcd); 1770irqreturn_t xhci_irq(struct usb_hcd *hcd); 1771irqreturn_t xhci_msi_irq(int irq, void *hcd); 1772int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 1773void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); 1774int xhci_alloc_tt_info(struct xhci_hcd *xhci, 1775 struct xhci_virt_device *virt_dev, 1776 struct usb_device *hdev, 1777 struct usb_tt *tt, gfp_t mem_flags); 1778int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, 1779 struct usb_host_endpoint **eps, unsigned int num_eps, 1780 unsigned int num_streams, gfp_t mem_flags); 1781int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, 1782 struct usb_host_endpoint **eps, unsigned int num_eps, 1783 gfp_t mem_flags); 1784int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); 1785int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); 1786int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); 1787int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, 1788 struct usb_device *udev, int enable); 1789int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, 1790 struct usb_tt *tt, gfp_t mem_flags); 1791int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); 1792int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); 1793int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1794int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); 1795void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); 1796int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); 1797int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1798void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); 1799 1800/* xHCI ring, segment, TRB, and TD functions */ 1801dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 1802struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1803 struct xhci_segment *start_seg, union xhci_trb *start_trb, 1804 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 1805int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 1806void xhci_ring_cmd_db(struct xhci_hcd *xhci); 1807int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 1808 u32 trb_type, u32 slot_id); 1809int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1810 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 1811int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 1812 u32 field1, u32 field2, u32 field3, u32 field4); 1813int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 1814 int slot_id, unsigned int ep_index, int suspend); 1815int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1816 int slot_id, unsigned int ep_index); 1817int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1818 int slot_id, unsigned int ep_index); 1819int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 1820 int slot_id, unsigned int ep_index); 1821int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 1822 struct urb *urb, int slot_id, unsigned int ep_index); 1823int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 1824 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 1825 bool command_must_succeed); 1826int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 1827 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 1828int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 1829 int slot_id, unsigned int ep_index); 1830int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 1831 u32 slot_id); 1832void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 1833 unsigned int slot_id, unsigned int ep_index, 1834 unsigned int stream_id, struct xhci_td *cur_td, 1835 struct xhci_dequeue_state *state); 1836void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 1837 unsigned int slot_id, unsigned int ep_index, 1838 unsigned int stream_id, 1839 struct xhci_dequeue_state *deq_state); 1840void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, 1841 unsigned int ep_index, struct xhci_td *td); 1842void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, 1843 unsigned int slot_id, unsigned int ep_index, 1844 struct xhci_dequeue_state *deq_state); 1845void xhci_stop_endpoint_command_watchdog(unsigned long arg); 1846void xhci_handle_command_timeout(unsigned long data); 1847 1848void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 1849 unsigned int ep_index, unsigned int stream_id); 1850void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 1851 1852/* xHCI roothub code */ 1853void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1854 int port_id, u32 link_state); 1855int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, 1856 struct usb_device *udev, enum usb3_link_state state); 1857int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, 1858 struct usb_device *udev, enum usb3_link_state state); 1859void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 1860 int port_id, u32 port_bit); 1861int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 1862 char *buf, u16 wLength); 1863int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 1864int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 1865 1866#ifdef CONFIG_PM 1867int xhci_bus_suspend(struct usb_hcd *hcd); 1868int xhci_bus_resume(struct usb_hcd *hcd); 1869#else 1870#define xhci_bus_suspend NULL 1871#define xhci_bus_resume NULL 1872#endif /* CONFIG_PM */ 1873 1874u32 xhci_port_state_to_neutral(u32 state); 1875int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 1876 u16 port); 1877void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 1878 1879/* xHCI contexts */ 1880struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 1881struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 1882struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 1883 1884#endif /* __LINUX_XHCI_HCD_H */ 1885