1/* 2 * VFIO PCI config space virtualization 3 * 4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved. 5 * Author: Alex Williamson <alex.williamson@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Derived from original vfio: 12 * Copyright 2010 Cisco Systems, Inc. All rights reserved. 13 * Author: Tom Lyon, pugs@cisco.com 14 */ 15 16/* 17 * This code handles reading and writing of PCI configuration registers. 18 * This is hairy because we want to allow a lot of flexibility to the 19 * user driver, but cannot trust it with all of the config fields. 20 * Tables determine which fields can be read and written, as well as 21 * which fields are 'virtualized' - special actions and translations to 22 * make it appear to the user that he has control, when in fact things 23 * must be negotiated with the underlying OS. 24 */ 25 26#include <linux/fs.h> 27#include <linux/pci.h> 28#include <linux/uaccess.h> 29#include <linux/vfio.h> 30#include <linux/slab.h> 31 32#include "vfio_pci_private.h" 33 34#define PCI_CFG_SPACE_SIZE 256 35 36/* Useful "pseudo" capabilities */ 37#define PCI_CAP_ID_BASIC 0 38#define PCI_CAP_ID_INVALID 0xFF 39 40#define is_bar(offset) \ 41 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \ 42 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4)) 43 44/* 45 * Lengths of PCI Config Capabilities 46 * 0: Removed from the user visible capability list 47 * FF: Variable length 48 */ 49static u8 pci_cap_length[] = { 50 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */ 51 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF, 52 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF, 53 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF, 54 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */ 55 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */ 56 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */ 57 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */ 58 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */ 59 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */ 60 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */ 61 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */ 62 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */ 63 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */ 64 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */ 65 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */ 66 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */ 67 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF, 68 [PCI_CAP_ID_SATA] = 0xFF, 69 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF, 70}; 71 72/* 73 * Lengths of PCIe/PCI-X Extended Config Capabilities 74 * 0: Removed or masked from the user visible capabilty list 75 * FF: Variable length 76 */ 77static u16 pci_ext_cap_length[] = { 78 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND, 79 [PCI_EXT_CAP_ID_VC] = 0xFF, 80 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF, 81 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF, 82 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */ 83 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */ 84 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */ 85 [PCI_EXT_CAP_ID_MFVC] = 0xFF, 86 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */ 87 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */ 88 [PCI_EXT_CAP_ID_VNDR] = 0xFF, 89 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */ 90 [PCI_EXT_CAP_ID_ACS] = 0xFF, 91 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF, 92 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF, 93 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF, 94 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */ 95 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF, 96 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF, 97 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */ 98 [PCI_EXT_CAP_ID_REBAR] = 0xFF, 99 [PCI_EXT_CAP_ID_DPA] = 0xFF, 100 [PCI_EXT_CAP_ID_TPH] = 0xFF, 101 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, 102 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ 103 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ 104 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ 105}; 106 107/* 108 * Read/Write Permission Bits - one bit for each bit in capability 109 * Any field can be read if it exists, but what is read depends on 110 * whether the field is 'virtualized', or just pass thru to the 111 * hardware. Any virtualized field is also virtualized for writes. 112 * Writes are only permitted if they have a 1 bit here. 113 */ 114struct perm_bits { 115 u8 *virt; /* read/write virtual data, not hw */ 116 u8 *write; /* writeable bits */ 117 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count, 118 struct perm_bits *perm, int offset, __le32 *val); 119 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count, 120 struct perm_bits *perm, int offset, __le32 val); 121}; 122 123#define NO_VIRT 0 124#define ALL_VIRT 0xFFFFFFFFU 125#define NO_WRITE 0 126#define ALL_WRITE 0xFFFFFFFFU 127 128static int vfio_user_config_read(struct pci_dev *pdev, int offset, 129 __le32 *val, int count) 130{ 131 int ret = -EINVAL; 132 u32 tmp_val = 0; 133 134 switch (count) { 135 case 1: 136 { 137 u8 tmp; 138 ret = pci_user_read_config_byte(pdev, offset, &tmp); 139 tmp_val = tmp; 140 break; 141 } 142 case 2: 143 { 144 u16 tmp; 145 ret = pci_user_read_config_word(pdev, offset, &tmp); 146 tmp_val = tmp; 147 break; 148 } 149 case 4: 150 ret = pci_user_read_config_dword(pdev, offset, &tmp_val); 151 break; 152 } 153 154 *val = cpu_to_le32(tmp_val); 155 156 return pcibios_err_to_errno(ret); 157} 158 159static int vfio_user_config_write(struct pci_dev *pdev, int offset, 160 __le32 val, int count) 161{ 162 int ret = -EINVAL; 163 u32 tmp_val = le32_to_cpu(val); 164 165 switch (count) { 166 case 1: 167 ret = pci_user_write_config_byte(pdev, offset, tmp_val); 168 break; 169 case 2: 170 ret = pci_user_write_config_word(pdev, offset, tmp_val); 171 break; 172 case 4: 173 ret = pci_user_write_config_dword(pdev, offset, tmp_val); 174 break; 175 } 176 177 return pcibios_err_to_errno(ret); 178} 179 180static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, 181 int count, struct perm_bits *perm, 182 int offset, __le32 *val) 183{ 184 __le32 virt = 0; 185 186 memcpy(val, vdev->vconfig + pos, count); 187 188 memcpy(&virt, perm->virt + offset, count); 189 190 /* Any non-virtualized bits? */ 191 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { 192 struct pci_dev *pdev = vdev->pdev; 193 __le32 phys_val = 0; 194 int ret; 195 196 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 197 if (ret) 198 return ret; 199 200 *val = (phys_val & ~virt) | (*val & virt); 201 } 202 203 return count; 204} 205 206static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, 207 int count, struct perm_bits *perm, 208 int offset, __le32 val) 209{ 210 __le32 virt = 0, write = 0; 211 212 memcpy(&write, perm->write + offset, count); 213 214 if (!write) 215 return count; /* drop, no writable bits */ 216 217 memcpy(&virt, perm->virt + offset, count); 218 219 /* Virtualized and writable bits go to vconfig */ 220 if (write & virt) { 221 __le32 virt_val = 0; 222 223 memcpy(&virt_val, vdev->vconfig + pos, count); 224 225 virt_val &= ~(write & virt); 226 virt_val |= (val & (write & virt)); 227 228 memcpy(vdev->vconfig + pos, &virt_val, count); 229 } 230 231 /* Non-virtualzed and writable bits go to hardware */ 232 if (write & ~virt) { 233 struct pci_dev *pdev = vdev->pdev; 234 __le32 phys_val = 0; 235 int ret; 236 237 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 238 if (ret) 239 return ret; 240 241 phys_val &= ~(write & ~virt); 242 phys_val |= (val & (write & ~virt)); 243 244 ret = vfio_user_config_write(pdev, pos, phys_val, count); 245 if (ret) 246 return ret; 247 } 248 249 return count; 250} 251 252/* Allow direct read from hardware, except for capability next pointer */ 253static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, 254 int count, struct perm_bits *perm, 255 int offset, __le32 *val) 256{ 257 int ret; 258 259 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 260 if (ret) 261 return pcibios_err_to_errno(ret); 262 263 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ 264 if (offset < 4) 265 memcpy(val, vdev->vconfig + pos, count); 266 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ 267 if (offset == PCI_CAP_LIST_ID && count > 1) 268 memcpy(val, vdev->vconfig + pos, 269 min(PCI_CAP_FLAGS, count)); 270 else if (offset == PCI_CAP_LIST_NEXT) 271 memcpy(val, vdev->vconfig + pos, 1); 272 } 273 274 return count; 275} 276 277/* Raw access skips any kind of virtualization */ 278static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos, 279 int count, struct perm_bits *perm, 280 int offset, __le32 val) 281{ 282 int ret; 283 284 ret = vfio_user_config_write(vdev->pdev, pos, val, count); 285 if (ret) 286 return ret; 287 288 return count; 289} 290 291static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos, 292 int count, struct perm_bits *perm, 293 int offset, __le32 *val) 294{ 295 int ret; 296 297 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 298 if (ret) 299 return pcibios_err_to_errno(ret); 300 301 return count; 302} 303 304/* Default capability regions to read-only, no-virtualization */ 305static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { 306 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 307}; 308static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { 309 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 310}; 311/* 312 * Default unassigned regions to raw read-write access. Some devices 313 * require this to function as they hide registers between the gaps in 314 * config space (be2net). Like MMIO and I/O port registers, we have 315 * to trust the hardware isolation. 316 */ 317static struct perm_bits unassigned_perms = { 318 .readfn = vfio_raw_config_read, 319 .writefn = vfio_raw_config_write 320}; 321 322static void free_perm_bits(struct perm_bits *perm) 323{ 324 kfree(perm->virt); 325 kfree(perm->write); 326 perm->virt = NULL; 327 perm->write = NULL; 328} 329 330static int alloc_perm_bits(struct perm_bits *perm, int size) 331{ 332 /* 333 * Round up all permission bits to the next dword, this lets us 334 * ignore whether a read/write exceeds the defined capability 335 * structure. We can do this because: 336 * - Standard config space is already dword aligned 337 * - Capabilities are all dword alinged (bits 0:1 of next reserved) 338 * - Express capabilities defined as dword aligned 339 */ 340 size = round_up(size, 4); 341 342 /* 343 * Zero state is 344 * - All Readable, None Writeable, None Virtualized 345 */ 346 perm->virt = kzalloc(size, GFP_KERNEL); 347 perm->write = kzalloc(size, GFP_KERNEL); 348 if (!perm->virt || !perm->write) { 349 free_perm_bits(perm); 350 return -ENOMEM; 351 } 352 353 perm->readfn = vfio_default_config_read; 354 perm->writefn = vfio_default_config_write; 355 356 return 0; 357} 358 359/* 360 * Helper functions for filling in permission tables 361 */ 362static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) 363{ 364 p->virt[off] = virt; 365 p->write[off] = write; 366} 367 368/* Handle endian-ness - pci and tables are little-endian */ 369static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) 370{ 371 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); 372 *(__le16 *)(&p->write[off]) = cpu_to_le16(write); 373} 374 375/* Handle endian-ness - pci and tables are little-endian */ 376static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) 377{ 378 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); 379 *(__le32 *)(&p->write[off]) = cpu_to_le32(write); 380} 381 382/* 383 * Restore the *real* BARs after we detect a FLR or backdoor reset. 384 * (backdoor = some device specific technique that we didn't catch) 385 */ 386static void vfio_bar_restore(struct vfio_pci_device *vdev) 387{ 388 struct pci_dev *pdev = vdev->pdev; 389 u32 *rbar = vdev->rbar; 390 int i; 391 392 if (pdev->is_virtfn) 393 return; 394 395 pr_info("%s: %s reset recovery - restoring bars\n", 396 __func__, dev_name(&pdev->dev)); 397 398 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) 399 pci_user_write_config_dword(pdev, i, *rbar); 400 401 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); 402} 403 404static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) 405{ 406 unsigned long flags = pci_resource_flags(pdev, bar); 407 u32 val; 408 409 if (flags & IORESOURCE_IO) 410 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); 411 412 val = PCI_BASE_ADDRESS_SPACE_MEMORY; 413 414 if (flags & IORESOURCE_PREFETCH) 415 val |= PCI_BASE_ADDRESS_MEM_PREFETCH; 416 417 if (flags & IORESOURCE_MEM_64) 418 val |= PCI_BASE_ADDRESS_MEM_TYPE_64; 419 420 return cpu_to_le32(val); 421} 422 423/* 424 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs 425 * to reflect the hardware capabilities. This implements BAR sizing. 426 */ 427static void vfio_bar_fixup(struct vfio_pci_device *vdev) 428{ 429 struct pci_dev *pdev = vdev->pdev; 430 int i; 431 __le32 *bar; 432 u64 mask; 433 434 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; 435 436 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) { 437 if (!pci_resource_start(pdev, i)) { 438 *bar = 0; /* Unmapped by host = unimplemented to user */ 439 continue; 440 } 441 442 mask = ~(pci_resource_len(pdev, i) - 1); 443 444 *bar &= cpu_to_le32((u32)mask); 445 *bar |= vfio_generate_bar_flags(pdev, i); 446 447 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { 448 bar++; 449 *bar &= cpu_to_le32((u32)(mask >> 32)); 450 i++; 451 } 452 } 453 454 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; 455 456 /* 457 * NB. we expose the actual BAR size here, regardless of whether 458 * we can read it. When we report the REGION_INFO for the ROM 459 * we report what PCI tells us is the actual ROM size. 460 */ 461 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { 462 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); 463 mask |= PCI_ROM_ADDRESS_ENABLE; 464 *bar &= cpu_to_le32((u32)mask); 465 } else 466 *bar = 0; 467 468 vdev->bardirty = false; 469} 470 471static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, 472 int count, struct perm_bits *perm, 473 int offset, __le32 *val) 474{ 475 if (is_bar(offset)) /* pos == offset for basic config */ 476 vfio_bar_fixup(vdev); 477 478 count = vfio_default_config_read(vdev, pos, count, perm, offset, val); 479 480 /* Mask in virtual memory enable for SR-IOV devices */ 481 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { 482 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 483 u32 tmp_val = le32_to_cpu(*val); 484 485 tmp_val |= cmd & PCI_COMMAND_MEMORY; 486 *val = cpu_to_le32(tmp_val); 487 } 488 489 return count; 490} 491 492static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, 493 int count, struct perm_bits *perm, 494 int offset, __le32 val) 495{ 496 struct pci_dev *pdev = vdev->pdev; 497 __le16 *virt_cmd; 498 u16 new_cmd = 0; 499 int ret; 500 501 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; 502 503 if (offset == PCI_COMMAND) { 504 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; 505 u16 phys_cmd; 506 507 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); 508 if (ret) 509 return ret; 510 511 new_cmd = le32_to_cpu(val); 512 513 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); 514 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); 515 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); 516 517 phys_io = !!(phys_cmd & PCI_COMMAND_IO); 518 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); 519 new_io = !!(new_cmd & PCI_COMMAND_IO); 520 521 /* 522 * If the user is writing mem/io enable (new_mem/io) and we 523 * think it's already enabled (virt_mem/io), but the hardware 524 * shows it disabled (phys_mem/io, then the device has 525 * undergone some kind of backdoor reset and needs to be 526 * restored before we allow it to enable the bars. 527 * SR-IOV devices will trigger this, but we catch them later 528 */ 529 if ((new_mem && virt_mem && !phys_mem) || 530 (new_io && virt_io && !phys_io)) 531 vfio_bar_restore(vdev); 532 } 533 534 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 535 if (count < 0) 536 return count; 537 538 /* 539 * Save current memory/io enable bits in vconfig to allow for 540 * the test above next time. 541 */ 542 if (offset == PCI_COMMAND) { 543 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 544 545 *virt_cmd &= cpu_to_le16(~mask); 546 *virt_cmd |= cpu_to_le16(new_cmd & mask); 547 } 548 549 /* Emulate INTx disable */ 550 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { 551 bool virt_intx_disable; 552 553 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & 554 PCI_COMMAND_INTX_DISABLE); 555 556 if (virt_intx_disable && !vdev->virq_disabled) { 557 vdev->virq_disabled = true; 558 vfio_pci_intx_mask(vdev); 559 } else if (!virt_intx_disable && vdev->virq_disabled) { 560 vdev->virq_disabled = false; 561 vfio_pci_intx_unmask(vdev); 562 } 563 } 564 565 if (is_bar(offset)) 566 vdev->bardirty = true; 567 568 return count; 569} 570 571/* Permissions for the Basic PCI Header */ 572static int __init init_pci_cap_basic_perm(struct perm_bits *perm) 573{ 574 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) 575 return -ENOMEM; 576 577 perm->readfn = vfio_basic_config_read; 578 perm->writefn = vfio_basic_config_write; 579 580 /* Virtualized for SR-IOV functions, which just have FFFF */ 581 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); 582 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); 583 584 /* 585 * Virtualize INTx disable, we use it internally for interrupt 586 * control and can emulate it for non-PCI 2.3 devices. 587 */ 588 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); 589 590 /* Virtualize capability list, we might want to skip/disable */ 591 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); 592 593 /* No harm to write */ 594 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); 595 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); 596 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); 597 598 /* Virtualize all bars, can't touch the real ones */ 599 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); 600 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); 601 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); 602 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); 603 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); 604 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); 605 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); 606 607 /* Allow us to adjust capability chain */ 608 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); 609 610 /* Sometimes used by sw, just virtualize */ 611 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); 612 613 /* Virtualize interrupt pin to allow hiding INTx */ 614 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE); 615 616 return 0; 617} 618 619static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, 620 int count, struct perm_bits *perm, 621 int offset, __le32 val) 622{ 623 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 624 if (count < 0) 625 return count; 626 627 if (offset == PCI_PM_CTRL) { 628 pci_power_t state; 629 630 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { 631 case 0: 632 state = PCI_D0; 633 break; 634 case 1: 635 state = PCI_D1; 636 break; 637 case 2: 638 state = PCI_D2; 639 break; 640 case 3: 641 state = PCI_D3hot; 642 break; 643 } 644 645 pci_set_power_state(vdev->pdev, state); 646 } 647 648 return count; 649} 650 651/* Permissions for the Power Management capability */ 652static int __init init_pci_cap_pm_perm(struct perm_bits *perm) 653{ 654 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM])) 655 return -ENOMEM; 656 657 perm->writefn = vfio_pm_config_write; 658 659 /* 660 * We always virtualize the next field so we can remove 661 * capabilities from the chain if we want to. 662 */ 663 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 664 665 /* 666 * Power management is defined *per function*, so we can let 667 * the user change power state, but we trap and initiate the 668 * change ourselves, so the state bits are read-only. 669 */ 670 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); 671 return 0; 672} 673 674/* Permissions for PCI-X capability */ 675static int __init init_pci_cap_pcix_perm(struct perm_bits *perm) 676{ 677 /* Alloc 24, but only 8 are used in v0 */ 678 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2)) 679 return -ENOMEM; 680 681 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 682 683 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); 684 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); 685 return 0; 686} 687 688/* Permissions for PCI Express capability */ 689static int __init init_pci_cap_exp_perm(struct perm_bits *perm) 690{ 691 /* Alloc larger of two possible sizes */ 692 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2)) 693 return -ENOMEM; 694 695 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 696 697 /* 698 * Allow writes to device control fields (includes FLR!) 699 * but not to devctl_phantom which could confuse IOMMU 700 * or to the ARI bit in devctl2 which is set at probe time 701 */ 702 p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM); 703 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); 704 return 0; 705} 706 707/* Permissions for Advanced Function capability */ 708static int __init init_pci_cap_af_perm(struct perm_bits *perm) 709{ 710 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF])) 711 return -ENOMEM; 712 713 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 714 p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR); 715 return 0; 716} 717 718/* Permissions for Advanced Error Reporting extended capability */ 719static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 720{ 721 u32 mask; 722 723 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR])) 724 return -ENOMEM; 725 726 /* 727 * Virtualize the first dword of all express capabilities 728 * because it includes the next pointer. This lets us later 729 * remove capabilities from the chain if we need to. 730 */ 731 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 732 733 /* Writable bits mask */ 734 mask = PCI_ERR_UNC_UND | /* Undefined */ 735 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 736 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 737 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 738 PCI_ERR_UNC_FCP | /* Flow Control Protocol */ 739 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */ 740 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */ 741 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */ 742 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */ 743 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */ 744 PCI_ERR_UNC_ECRC | /* ECRC Error Status */ 745 PCI_ERR_UNC_UNSUP | /* Unsupported Request */ 746 PCI_ERR_UNC_ACSV | /* ACS Violation */ 747 PCI_ERR_UNC_INTN | /* internal error */ 748 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */ 749 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */ 750 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */ 751 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); 752 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); 753 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); 754 755 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ 756 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */ 757 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */ 758 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */ 759 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */ 760 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */ 761 PCI_ERR_COR_INTERNAL | /* Corrected Internal */ 762 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */ 763 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); 764 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); 765 766 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ 767 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */ 768 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); 769 return 0; 770} 771 772/* Permissions for Power Budgeting extended capability */ 773static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm) 774{ 775 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR])) 776 return -ENOMEM; 777 778 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 779 780 /* Writing the data selector is OK, the info is still read-only */ 781 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); 782 return 0; 783} 784 785/* 786 * Initialize the shared permission tables 787 */ 788void vfio_pci_uninit_perm_bits(void) 789{ 790 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]); 791 792 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]); 793 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]); 794 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]); 795 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]); 796 797 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 798 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 799} 800 801int __init vfio_pci_init_perm_bits(void) 802{ 803 int ret; 804 805 /* Basic config space */ 806 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]); 807 808 /* Capabilities */ 809 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]); 810 cap_perms[PCI_CAP_ID_VPD].writefn = vfio_raw_config_write; 811 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]); 812 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write; 813 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]); 814 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]); 815 816 /* Extended capabilities */ 817 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 818 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 819 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write; 820 821 if (ret) 822 vfio_pci_uninit_perm_bits(); 823 824 return ret; 825} 826 827static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos) 828{ 829 u8 cap; 830 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : 831 PCI_STD_HEADER_SIZEOF; 832 cap = vdev->pci_config_map[pos]; 833 834 if (cap == PCI_CAP_ID_BASIC) 835 return 0; 836 837 /* XXX Can we have to abutting capabilities of the same type? */ 838 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) 839 pos--; 840 841 return pos; 842} 843 844static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos, 845 int count, struct perm_bits *perm, 846 int offset, __le32 *val) 847{ 848 /* Update max available queue size from msi_qmax */ 849 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 850 __le16 *flags; 851 int start; 852 853 start = vfio_find_cap_start(vdev, pos); 854 855 flags = (__le16 *)&vdev->vconfig[start]; 856 857 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK); 858 *flags |= cpu_to_le16(vdev->msi_qmax << 1); 859 } 860 861 return vfio_default_config_read(vdev, pos, count, perm, offset, val); 862} 863 864static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos, 865 int count, struct perm_bits *perm, 866 int offset, __le32 val) 867{ 868 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 869 if (count < 0) 870 return count; 871 872 /* Fixup and write configured queue size and enable to hardware */ 873 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 874 __le16 *pflags; 875 u16 flags; 876 int start, ret; 877 878 start = vfio_find_cap_start(vdev, pos); 879 880 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS]; 881 882 flags = le16_to_cpu(*pflags); 883 884 /* MSI is enabled via ioctl */ 885 if (!is_msi(vdev)) 886 flags &= ~PCI_MSI_FLAGS_ENABLE; 887 888 /* Check queue size */ 889 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) { 890 flags &= ~PCI_MSI_FLAGS_QSIZE; 891 flags |= vdev->msi_qmax << 4; 892 } 893 894 /* Write back to virt and to hardware */ 895 *pflags = cpu_to_le16(flags); 896 ret = pci_user_write_config_word(vdev->pdev, 897 start + PCI_MSI_FLAGS, 898 flags); 899 if (ret) 900 return pcibios_err_to_errno(ret); 901 } 902 903 return count; 904} 905 906/* 907 * MSI determination is per-device, so this routine gets used beyond 908 * initialization time. Don't add __init 909 */ 910static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags) 911{ 912 if (alloc_perm_bits(perm, len)) 913 return -ENOMEM; 914 915 perm->readfn = vfio_msi_config_read; 916 perm->writefn = vfio_msi_config_write; 917 918 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 919 920 /* 921 * The upper byte of the control register is reserved, 922 * just setup the lower byte. 923 */ 924 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE); 925 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE); 926 if (flags & PCI_MSI_FLAGS_64BIT) { 927 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE); 928 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE); 929 if (flags & PCI_MSI_FLAGS_MASKBIT) { 930 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); 931 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); 932 } 933 } else { 934 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE); 935 if (flags & PCI_MSI_FLAGS_MASKBIT) { 936 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); 937 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); 938 } 939 } 940 return 0; 941} 942 943/* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */ 944static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos) 945{ 946 struct pci_dev *pdev = vdev->pdev; 947 int len, ret; 948 u16 flags; 949 950 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags); 951 if (ret) 952 return pcibios_err_to_errno(ret); 953 954 len = 10; /* Minimum size */ 955 if (flags & PCI_MSI_FLAGS_64BIT) 956 len += 4; 957 if (flags & PCI_MSI_FLAGS_MASKBIT) 958 len += 10; 959 960 if (vdev->msi_perm) 961 return len; 962 963 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL); 964 if (!vdev->msi_perm) 965 return -ENOMEM; 966 967 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags); 968 if (ret) 969 return ret; 970 971 return len; 972} 973 974/* Determine extended capability length for VC (2 & 9) and MFVC */ 975static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) 976{ 977 struct pci_dev *pdev = vdev->pdev; 978 u32 tmp; 979 int ret, evcc, phases, vc_arb; 980 int len = PCI_CAP_VC_BASE_SIZEOF; 981 982 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp); 983 if (ret) 984 return pcibios_err_to_errno(ret); 985 986 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */ 987 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp); 988 if (ret) 989 return pcibios_err_to_errno(ret); 990 991 if (tmp & PCI_VC_CAP2_128_PHASE) 992 phases = 128; 993 else if (tmp & PCI_VC_CAP2_64_PHASE) 994 phases = 64; 995 else if (tmp & PCI_VC_CAP2_32_PHASE) 996 phases = 32; 997 else 998 phases = 0; 999 1000 vc_arb = phases * 4; 1001 1002 /* 1003 * Port arbitration tables are root & switch only; 1004 * function arbitration tables are function 0 only. 1005 * In either case, we'll never let user write them so 1006 * we don't care how big they are 1007 */ 1008 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF; 1009 if (vc_arb) { 1010 len = round_up(len, 16); 1011 len += vc_arb / 8; 1012 } 1013 return len; 1014} 1015 1016static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) 1017{ 1018 struct pci_dev *pdev = vdev->pdev; 1019 u32 dword; 1020 u16 word; 1021 u8 byte; 1022 int ret; 1023 1024 switch (cap) { 1025 case PCI_CAP_ID_MSI: 1026 return vfio_msi_cap_len(vdev, pos); 1027 case PCI_CAP_ID_PCIX: 1028 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word); 1029 if (ret) 1030 return pcibios_err_to_errno(ret); 1031 1032 if (PCI_X_CMD_VERSION(word)) { 1033 /* Test for extended capabilities */ 1034 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1035 vdev->extended_caps = (dword != 0); 1036 return PCI_CAP_PCIX_SIZEOF_V2; 1037 } else 1038 return PCI_CAP_PCIX_SIZEOF_V0; 1039 case PCI_CAP_ID_VNDR: 1040 /* length follows next field */ 1041 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte); 1042 if (ret) 1043 return pcibios_err_to_errno(ret); 1044 1045 return byte; 1046 case PCI_CAP_ID_EXP: 1047 /* Test for extended capabilities */ 1048 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1049 vdev->extended_caps = (dword != 0); 1050 1051 /* length based on version */ 1052 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) 1053 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1; 1054 else 1055 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2; 1056 case PCI_CAP_ID_HT: 1057 ret = pci_read_config_byte(pdev, pos + 3, &byte); 1058 if (ret) 1059 return pcibios_err_to_errno(ret); 1060 1061 return (byte & HT_3BIT_CAP_MASK) ? 1062 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG; 1063 case PCI_CAP_ID_SATA: 1064 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte); 1065 if (ret) 1066 return pcibios_err_to_errno(ret); 1067 1068 byte &= PCI_SATA_REGS_MASK; 1069 if (byte == PCI_SATA_REGS_INLINE) 1070 return PCI_SATA_SIZEOF_LONG; 1071 else 1072 return PCI_SATA_SIZEOF_SHORT; 1073 default: 1074 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n", 1075 dev_name(&pdev->dev), __func__, cap, pos); 1076 } 1077 1078 return 0; 1079} 1080 1081static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos) 1082{ 1083 struct pci_dev *pdev = vdev->pdev; 1084 u8 byte; 1085 u32 dword; 1086 int ret; 1087 1088 switch (ecap) { 1089 case PCI_EXT_CAP_ID_VNDR: 1090 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword); 1091 if (ret) 1092 return pcibios_err_to_errno(ret); 1093 1094 return dword >> PCI_VSEC_HDR_LEN_SHIFT; 1095 case PCI_EXT_CAP_ID_VC: 1096 case PCI_EXT_CAP_ID_VC9: 1097 case PCI_EXT_CAP_ID_MFVC: 1098 return vfio_vc_cap_len(vdev, epos); 1099 case PCI_EXT_CAP_ID_ACS: 1100 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte); 1101 if (ret) 1102 return pcibios_err_to_errno(ret); 1103 1104 if (byte & PCI_ACS_EC) { 1105 int bits; 1106 1107 ret = pci_read_config_byte(pdev, 1108 epos + PCI_ACS_EGRESS_BITS, 1109 &byte); 1110 if (ret) 1111 return pcibios_err_to_errno(ret); 1112 1113 bits = byte ? round_up(byte, 32) : 256; 1114 return 8 + (bits / 8); 1115 } 1116 return 8; 1117 1118 case PCI_EXT_CAP_ID_REBAR: 1119 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte); 1120 if (ret) 1121 return pcibios_err_to_errno(ret); 1122 1123 byte &= PCI_REBAR_CTRL_NBAR_MASK; 1124 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT; 1125 1126 return 4 + (byte * 8); 1127 case PCI_EXT_CAP_ID_DPA: 1128 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte); 1129 if (ret) 1130 return pcibios_err_to_errno(ret); 1131 1132 byte &= PCI_DPA_CAP_SUBSTATE_MASK; 1133 return PCI_DPA_BASE_SIZEOF + byte + 1; 1134 case PCI_EXT_CAP_ID_TPH: 1135 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword); 1136 if (ret) 1137 return pcibios_err_to_errno(ret); 1138 1139 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) { 1140 int sts; 1141 1142 sts = dword & PCI_TPH_CAP_ST_MASK; 1143 sts >>= PCI_TPH_CAP_ST_SHIFT; 1144 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2; 1145 } 1146 return PCI_TPH_BASE_SIZEOF; 1147 default: 1148 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n", 1149 dev_name(&pdev->dev), __func__, ecap, epos); 1150 } 1151 1152 return 0; 1153} 1154 1155static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev, 1156 int offset, int size) 1157{ 1158 struct pci_dev *pdev = vdev->pdev; 1159 int ret = 0; 1160 1161 /* 1162 * We try to read physical config space in the largest chunks 1163 * we can, assuming that all of the fields support dword access. 1164 * pci_save_state() makes this same assumption and seems to do ok. 1165 */ 1166 while (size) { 1167 int filled; 1168 1169 if (size >= 4 && !(offset % 4)) { 1170 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset]; 1171 u32 dword; 1172 1173 ret = pci_read_config_dword(pdev, offset, &dword); 1174 if (ret) 1175 return ret; 1176 *dwordp = cpu_to_le32(dword); 1177 filled = 4; 1178 } else if (size >= 2 && !(offset % 2)) { 1179 __le16 *wordp = (__le16 *)&vdev->vconfig[offset]; 1180 u16 word; 1181 1182 ret = pci_read_config_word(pdev, offset, &word); 1183 if (ret) 1184 return ret; 1185 *wordp = cpu_to_le16(word); 1186 filled = 2; 1187 } else { 1188 u8 *byte = &vdev->vconfig[offset]; 1189 ret = pci_read_config_byte(pdev, offset, byte); 1190 if (ret) 1191 return ret; 1192 filled = 1; 1193 } 1194 1195 offset += filled; 1196 size -= filled; 1197 } 1198 1199 return ret; 1200} 1201 1202static int vfio_cap_init(struct vfio_pci_device *vdev) 1203{ 1204 struct pci_dev *pdev = vdev->pdev; 1205 u8 *map = vdev->pci_config_map; 1206 u16 status; 1207 u8 pos, *prev, cap; 1208 int loops, ret, caps = 0; 1209 1210 /* Any capabilities? */ 1211 ret = pci_read_config_word(pdev, PCI_STATUS, &status); 1212 if (ret) 1213 return ret; 1214 1215 if (!(status & PCI_STATUS_CAP_LIST)) 1216 return 0; /* Done */ 1217 1218 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos); 1219 if (ret) 1220 return ret; 1221 1222 /* Mark the previous position in case we want to skip a capability */ 1223 prev = &vdev->vconfig[PCI_CAPABILITY_LIST]; 1224 1225 /* We can bound our loop, capabilities are dword aligned */ 1226 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF; 1227 while (pos && loops--) { 1228 u8 next; 1229 int i, len = 0; 1230 1231 ret = pci_read_config_byte(pdev, pos, &cap); 1232 if (ret) 1233 return ret; 1234 1235 ret = pci_read_config_byte(pdev, 1236 pos + PCI_CAP_LIST_NEXT, &next); 1237 if (ret) 1238 return ret; 1239 1240 if (cap <= PCI_CAP_ID_MAX) { 1241 len = pci_cap_length[cap]; 1242 if (len == 0xFF) { /* Variable length */ 1243 len = vfio_cap_len(vdev, cap, pos); 1244 if (len < 0) 1245 return len; 1246 } 1247 } 1248 1249 if (!len) { 1250 pr_info("%s: %s hiding cap 0x%x\n", 1251 __func__, dev_name(&pdev->dev), cap); 1252 *prev = next; 1253 pos = next; 1254 continue; 1255 } 1256 1257 /* Sanity check, do we overlap other capabilities? */ 1258 for (i = 0; i < len; i++) { 1259 if (likely(map[pos + i] == PCI_CAP_ID_INVALID)) 1260 continue; 1261 1262 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n", 1263 __func__, dev_name(&pdev->dev), 1264 pos + i, map[pos + i], cap); 1265 } 1266 1267 memset(map + pos, cap, len); 1268 ret = vfio_fill_vconfig_bytes(vdev, pos, len); 1269 if (ret) 1270 return ret; 1271 1272 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT]; 1273 pos = next; 1274 caps++; 1275 } 1276 1277 /* If we didn't fill any capabilities, clear the status flag */ 1278 if (!caps) { 1279 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS]; 1280 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST); 1281 } 1282 1283 return 0; 1284} 1285 1286static int vfio_ecap_init(struct vfio_pci_device *vdev) 1287{ 1288 struct pci_dev *pdev = vdev->pdev; 1289 u8 *map = vdev->pci_config_map; 1290 u16 epos; 1291 __le32 *prev = NULL; 1292 int loops, ret, ecaps = 0; 1293 1294 if (!vdev->extended_caps) 1295 return 0; 1296 1297 epos = PCI_CFG_SPACE_SIZE; 1298 1299 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF; 1300 1301 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) { 1302 u32 header; 1303 u16 ecap; 1304 int i, len = 0; 1305 bool hidden = false; 1306 1307 ret = pci_read_config_dword(pdev, epos, &header); 1308 if (ret) 1309 return ret; 1310 1311 ecap = PCI_EXT_CAP_ID(header); 1312 1313 if (ecap <= PCI_EXT_CAP_ID_MAX) { 1314 len = pci_ext_cap_length[ecap]; 1315 if (len == 0xFF) { 1316 len = vfio_ext_cap_len(vdev, ecap, epos); 1317 if (len < 0) 1318 return ret; 1319 } 1320 } 1321 1322 if (!len) { 1323 pr_info("%s: %s hiding ecap 0x%x@0x%x\n", 1324 __func__, dev_name(&pdev->dev), ecap, epos); 1325 1326 /* If not the first in the chain, we can skip over it */ 1327 if (prev) { 1328 u32 val = epos = PCI_EXT_CAP_NEXT(header); 1329 *prev &= cpu_to_le32(~(0xffcU << 20)); 1330 *prev |= cpu_to_le32(val << 20); 1331 continue; 1332 } 1333 1334 /* 1335 * Otherwise, fill in a placeholder, the direct 1336 * readfn will virtualize this automatically 1337 */ 1338 len = PCI_CAP_SIZEOF; 1339 hidden = true; 1340 } 1341 1342 for (i = 0; i < len; i++) { 1343 if (likely(map[epos + i] == PCI_CAP_ID_INVALID)) 1344 continue; 1345 1346 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n", 1347 __func__, dev_name(&pdev->dev), 1348 epos + i, map[epos + i], ecap); 1349 } 1350 1351 /* 1352 * Even though ecap is 2 bytes, we're currently a long way 1353 * from exceeding 1 byte capabilities. If we ever make it 1354 * up to 0xFF we'll need to up this to a two-byte, byte map. 1355 */ 1356 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID); 1357 1358 memset(map + epos, ecap, len); 1359 ret = vfio_fill_vconfig_bytes(vdev, epos, len); 1360 if (ret) 1361 return ret; 1362 1363 /* 1364 * If we're just using this capability to anchor the list, 1365 * hide the real ID. Only count real ecaps. XXX PCI spec 1366 * indicates to use cap id = 0, version = 0, next = 0 if 1367 * ecaps are absent, hope users check all the way to next. 1368 */ 1369 if (hidden) 1370 *(__le32 *)&vdev->vconfig[epos] &= 1371 cpu_to_le32((0xffcU << 20)); 1372 else 1373 ecaps++; 1374 1375 prev = (__le32 *)&vdev->vconfig[epos]; 1376 epos = PCI_EXT_CAP_NEXT(header); 1377 } 1378 1379 if (!ecaps) 1380 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0; 1381 1382 return 0; 1383} 1384 1385/* 1386 * For each device we allocate a pci_config_map that indicates the 1387 * capability occupying each dword and thus the struct perm_bits we 1388 * use for read and write. We also allocate a virtualized config 1389 * space which tracks reads and writes to bits that we emulate for 1390 * the user. Initial values filled from device. 1391 * 1392 * Using shared stuct perm_bits between all vfio-pci devices saves 1393 * us from allocating cfg_size buffers for virt and write for every 1394 * device. We could remove vconfig and allocate individual buffers 1395 * for each area requring emulated bits, but the array of pointers 1396 * would be comparable in size (at least for standard config space). 1397 */ 1398int vfio_config_init(struct vfio_pci_device *vdev) 1399{ 1400 struct pci_dev *pdev = vdev->pdev; 1401 u8 *map, *vconfig; 1402 int ret; 1403 1404 /* 1405 * Config space, caps and ecaps are all dword aligned, so we could 1406 * use one byte per dword to record the type. However, there are 1407 * no requiremenst on the length of a capability, so the gap between 1408 * capabilities needs byte granularity. 1409 */ 1410 map = kmalloc(pdev->cfg_size, GFP_KERNEL); 1411 if (!map) 1412 return -ENOMEM; 1413 1414 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL); 1415 if (!vconfig) { 1416 kfree(map); 1417 return -ENOMEM; 1418 } 1419 1420 vdev->pci_config_map = map; 1421 vdev->vconfig = vconfig; 1422 1423 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF); 1424 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID, 1425 pdev->cfg_size - PCI_STD_HEADER_SIZEOF); 1426 1427 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF); 1428 if (ret) 1429 goto out; 1430 1431 vdev->bardirty = true; 1432 1433 /* 1434 * XXX can we just pci_load_saved_state/pci_restore_state? 1435 * may need to rebuild vconfig after that 1436 */ 1437 1438 /* For restore after reset */ 1439 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); 1440 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); 1441 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); 1442 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); 1443 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]); 1444 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]); 1445 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]); 1446 1447 if (pdev->is_virtfn) { 1448 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor); 1449 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); 1450 } 1451 1452 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX)) 1453 vconfig[PCI_INTERRUPT_PIN] = 0; 1454 1455 ret = vfio_cap_init(vdev); 1456 if (ret) 1457 goto out; 1458 1459 ret = vfio_ecap_init(vdev); 1460 if (ret) 1461 goto out; 1462 1463 return 0; 1464 1465out: 1466 kfree(map); 1467 vdev->pci_config_map = NULL; 1468 kfree(vconfig); 1469 vdev->vconfig = NULL; 1470 return pcibios_err_to_errno(ret); 1471} 1472 1473void vfio_config_free(struct vfio_pci_device *vdev) 1474{ 1475 kfree(vdev->vconfig); 1476 vdev->vconfig = NULL; 1477 kfree(vdev->pci_config_map); 1478 vdev->pci_config_map = NULL; 1479 kfree(vdev->msi_perm); 1480 vdev->msi_perm = NULL; 1481} 1482 1483/* 1484 * Find the remaining number of bytes in a dword that match the given 1485 * position. Stop at either the end of the capability or the dword boundary. 1486 */ 1487static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev, 1488 loff_t pos) 1489{ 1490 u8 cap = vdev->pci_config_map[pos]; 1491 size_t i; 1492 1493 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++) 1494 /* nop */; 1495 1496 return i; 1497} 1498 1499static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, 1500 size_t count, loff_t *ppos, bool iswrite) 1501{ 1502 struct pci_dev *pdev = vdev->pdev; 1503 struct perm_bits *perm; 1504 __le32 val = 0; 1505 int cap_start = 0, offset; 1506 u8 cap_id; 1507 ssize_t ret; 1508 1509 if (*ppos < 0 || *ppos >= pdev->cfg_size || 1510 *ppos + count > pdev->cfg_size) 1511 return -EFAULT; 1512 1513 /* 1514 * Chop accesses into aligned chunks containing no more than a 1515 * single capability. Caller increments to the next chunk. 1516 */ 1517 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos)); 1518 if (count >= 4 && !(*ppos % 4)) 1519 count = 4; 1520 else if (count >= 2 && !(*ppos % 2)) 1521 count = 2; 1522 else 1523 count = 1; 1524 1525 ret = count; 1526 1527 cap_id = vdev->pci_config_map[*ppos]; 1528 1529 if (cap_id == PCI_CAP_ID_INVALID) { 1530 perm = &unassigned_perms; 1531 cap_start = *ppos; 1532 } else { 1533 if (*ppos >= PCI_CFG_SPACE_SIZE) { 1534 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX); 1535 1536 perm = &ecap_perms[cap_id]; 1537 cap_start = vfio_find_cap_start(vdev, *ppos); 1538 } else { 1539 WARN_ON(cap_id > PCI_CAP_ID_MAX); 1540 1541 perm = &cap_perms[cap_id]; 1542 1543 if (cap_id == PCI_CAP_ID_MSI) 1544 perm = vdev->msi_perm; 1545 1546 if (cap_id > PCI_CAP_ID_BASIC) 1547 cap_start = vfio_find_cap_start(vdev, *ppos); 1548 } 1549 } 1550 1551 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC); 1552 WARN_ON(cap_start > *ppos); 1553 1554 offset = *ppos - cap_start; 1555 1556 if (iswrite) { 1557 if (!perm->writefn) 1558 return ret; 1559 1560 if (copy_from_user(&val, buf, count)) 1561 return -EFAULT; 1562 1563 ret = perm->writefn(vdev, *ppos, count, perm, offset, val); 1564 } else { 1565 if (perm->readfn) { 1566 ret = perm->readfn(vdev, *ppos, count, 1567 perm, offset, &val); 1568 if (ret < 0) 1569 return ret; 1570 } 1571 1572 if (copy_to_user(buf, &val, count)) 1573 return -EFAULT; 1574 } 1575 1576 return ret; 1577} 1578 1579ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf, 1580 size_t count, loff_t *ppos, bool iswrite) 1581{ 1582 size_t done = 0; 1583 int ret = 0; 1584 loff_t pos = *ppos; 1585 1586 pos &= VFIO_PCI_OFFSET_MASK; 1587 1588 while (count) { 1589 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite); 1590 if (ret < 0) 1591 return ret; 1592 1593 count -= ret; 1594 done += ret; 1595 buf += ret; 1596 pos += ret; 1597 } 1598 1599 *ppos += done; 1600 1601 return done; 1602} 1603