1/* 2 * ti_hdmi_4xxx_ip.c 3 * 4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 6 * Authors: Yong Zhi 7 * Mythri pk <mythripk@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published by 11 * the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22#define DSS_SUBSYS_NAME "HDMICORE" 23 24#include <linux/kernel.h> 25#include <linux/module.h> 26#include <linux/err.h> 27#include <linux/io.h> 28#include <linux/interrupt.h> 29#include <linux/mutex.h> 30#include <linux/delay.h> 31#include <linux/platform_device.h> 32#include <linux/string.h> 33#include <linux/seq_file.h> 34#include <sound/asound.h> 35#include <sound/asoundef.h> 36 37#include "hdmi4_core.h" 38#include "dss_features.h" 39 40#define HDMI_CORE_AV 0x500 41 42static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) 43{ 44 return core->base + HDMI_CORE_AV; 45} 46 47static int hdmi_core_ddc_init(struct hdmi_core_data *core) 48{ 49 void __iomem *base = core->base; 50 51 /* Turn on CLK for DDC */ 52 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); 53 54 /* IN_PROG */ 55 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { 56 /* Abort transaction */ 57 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); 58 /* IN_PROG */ 59 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 60 4, 4, 0) != 0) { 61 DSSERR("Timeout aborting DDC transaction\n"); 62 return -ETIMEDOUT; 63 } 64 } 65 66 /* Clk SCL Devices */ 67 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); 68 69 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 70 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 71 4, 4, 0) != 0) { 72 DSSERR("Timeout starting SCL clock\n"); 73 return -ETIMEDOUT; 74 } 75 76 /* Clear FIFO */ 77 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); 78 79 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 80 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 81 4, 4, 0) != 0) { 82 DSSERR("Timeout clearing DDC fifo\n"); 83 return -ETIMEDOUT; 84 } 85 86 return 0; 87} 88 89static int hdmi_core_ddc_edid(struct hdmi_core_data *core, 90 u8 *pedid, int ext) 91{ 92 void __iomem *base = core->base; 93 u32 i; 94 char checksum; 95 u32 offset = 0; 96 97 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 98 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 99 4, 4, 0) != 0) { 100 DSSERR("Timeout waiting DDC to be ready\n"); 101 return -ETIMEDOUT; 102 } 103 104 if (ext % 2 != 0) 105 offset = 0x80; 106 107 /* Load Segment Address Register */ 108 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); 109 110 /* Load Slave Address Register */ 111 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); 112 113 /* Load Offset Address Register */ 114 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); 115 116 /* Load Byte Count */ 117 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); 118 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); 119 120 /* Set DDC_CMD */ 121 if (ext) 122 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); 123 else 124 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); 125 126 /* HDMI_CORE_DDC_STATUS_BUS_LOW */ 127 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { 128 DSSERR("I2C Bus Low?\n"); 129 return -EIO; 130 } 131 /* HDMI_CORE_DDC_STATUS_NO_ACK */ 132 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { 133 DSSERR("I2C No Ack\n"); 134 return -EIO; 135 } 136 137 for (i = 0; i < 0x80; ++i) { 138 int t; 139 140 /* IN_PROG */ 141 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { 142 DSSERR("operation stopped when reading edid\n"); 143 return -EIO; 144 } 145 146 t = 0; 147 /* FIFO_EMPTY */ 148 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { 149 if (t++ > 10000) { 150 DSSERR("timeout reading edid\n"); 151 return -ETIMEDOUT; 152 } 153 udelay(1); 154 } 155 156 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); 157 } 158 159 checksum = 0; 160 for (i = 0; i < 0x80; ++i) 161 checksum += pedid[i]; 162 163 if (checksum != 0) { 164 DSSERR("E-EDID checksum failed!!\n"); 165 return -EIO; 166 } 167 168 return 0; 169} 170 171int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) 172{ 173 int r, l; 174 175 if (len < 128) 176 return -EINVAL; 177 178 r = hdmi_core_ddc_init(core); 179 if (r) 180 return r; 181 182 r = hdmi_core_ddc_edid(core, edid, 0); 183 if (r) 184 return r; 185 186 l = 128; 187 188 if (len >= 128 * 2 && edid[0x7e] > 0) { 189 r = hdmi_core_ddc_edid(core, edid + 0x80, 1); 190 if (r) 191 return r; 192 l += 128; 193 } 194 195 return l; 196} 197 198static void hdmi_core_init(struct hdmi_core_video_config *video_cfg) 199{ 200 DSSDBG("Enter hdmi_core_init\n"); 201 202 /* video core */ 203 video_cfg->ip_bus_width = HDMI_INPUT_8BIT; 204 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; 205 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; 206 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; 207 video_cfg->hdmi_dvi = HDMI_DVI; 208 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; 209} 210 211static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) 212{ 213 DSSDBG("Enter hdmi_core_powerdown_disable\n"); 214 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); 215} 216 217static void hdmi_core_swreset_release(struct hdmi_core_data *core) 218{ 219 DSSDBG("Enter hdmi_core_swreset_release\n"); 220 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); 221} 222 223static void hdmi_core_swreset_assert(struct hdmi_core_data *core) 224{ 225 DSSDBG("Enter hdmi_core_swreset_assert\n"); 226 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); 227} 228 229/* HDMI_CORE_VIDEO_CONFIG */ 230static void hdmi_core_video_config(struct hdmi_core_data *core, 231 struct hdmi_core_video_config *cfg) 232{ 233 u32 r = 0; 234 void __iomem *core_sys_base = core->base; 235 void __iomem *core_av_base = hdmi_av_base(core); 236 237 /* sys_ctrl1 default configuration not tunable */ 238 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); 239 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); 240 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); 241 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); 242 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); 243 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); 244 245 REG_FLD_MOD(core_sys_base, 246 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); 247 248 /* Vid_Mode */ 249 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); 250 251 /* dither truncation configuration */ 252 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { 253 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); 254 r = FLD_MOD(r, 1, 5, 5); 255 } else { 256 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); 257 r = FLD_MOD(r, 0, 5, 5); 258 } 259 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); 260 261 /* HDMI_Ctrl */ 262 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); 263 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); 264 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); 265 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); 266 hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); 267 268 /* TMDS_CTRL */ 269 REG_FLD_MOD(core_sys_base, 270 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); 271} 272 273static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, 274 struct hdmi_avi_infoframe *frame) 275{ 276 void __iomem *av_base = hdmi_av_base(core); 277 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 278 int i; 279 280 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 281 282 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, 283 HDMI_INFOFRAME_SIZE(AVI), false); 284 285 for (i = 0; i < sizeof(data); ++i) { 286 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, 287 data[i]); 288 } 289} 290 291static void hdmi_core_av_packet_config(struct hdmi_core_data *core, 292 struct hdmi_core_packet_enable_repeat repeat_cfg) 293{ 294 /* enable/repeat the infoframe */ 295 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, 296 (repeat_cfg.audio_pkt << 5) | 297 (repeat_cfg.audio_pkt_repeat << 4) | 298 (repeat_cfg.avi_infoframe << 1) | 299 (repeat_cfg.avi_infoframe_repeat)); 300 301 /* enable/repeat the packet */ 302 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, 303 (repeat_cfg.gen_cntrl_pkt << 3) | 304 (repeat_cfg.gen_cntrl_pkt_repeat << 2) | 305 (repeat_cfg.generic_pkt << 1) | 306 (repeat_cfg.generic_pkt_repeat)); 307} 308 309void hdmi4_configure(struct hdmi_core_data *core, 310 struct hdmi_wp_data *wp, struct hdmi_config *cfg) 311{ 312 /* HDMI */ 313 struct omap_video_timings video_timing; 314 struct hdmi_video_format video_format; 315 /* HDMI core */ 316 struct hdmi_core_video_config v_core_cfg; 317 struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 }; 318 319 hdmi_core_init(&v_core_cfg); 320 321 hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); 322 323 hdmi_wp_video_config_timing(wp, &video_timing); 324 325 /* video config */ 326 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 327 328 hdmi_wp_video_config_format(wp, &video_format); 329 330 hdmi_wp_video_config_interface(wp, &video_timing); 331 332 /* 333 * configure core video part 334 * set software reset in the core 335 */ 336 hdmi_core_swreset_assert(core); 337 338 /* power down off */ 339 hdmi_core_powerdown_disable(core); 340 341 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; 342 v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode; 343 344 hdmi_core_video_config(core, &v_core_cfg); 345 346 /* release software reset in the core */ 347 hdmi_core_swreset_release(core); 348 349 if (cfg->hdmi_dvi_mode == HDMI_HDMI) { 350 hdmi_core_write_avi_infoframe(core, &cfg->infoframe); 351 352 /* enable/repeat the infoframe */ 353 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; 354 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; 355 /* wakeup */ 356 repeat_cfg.audio_pkt = HDMI_PACKETENABLE; 357 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; 358 } 359 360 hdmi_core_av_packet_config(core, repeat_cfg); 361} 362 363void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) 364{ 365 int i; 366 367#define CORE_REG(i, name) name(i) 368#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ 369 hdmi_read_reg(core->base, r)) 370#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ 371 hdmi_read_reg(hdmi_av_base(core), r)) 372#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ 373 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ 374 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) 375 376 DUMPCORE(HDMI_CORE_SYS_VND_IDL); 377 DUMPCORE(HDMI_CORE_SYS_DEV_IDL); 378 DUMPCORE(HDMI_CORE_SYS_DEV_IDH); 379 DUMPCORE(HDMI_CORE_SYS_DEV_REV); 380 DUMPCORE(HDMI_CORE_SYS_SRST); 381 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); 382 DUMPCORE(HDMI_CORE_SYS_SYS_STAT); 383 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); 384 DUMPCORE(HDMI_CORE_SYS_DE_DLY); 385 DUMPCORE(HDMI_CORE_SYS_DE_CTRL); 386 DUMPCORE(HDMI_CORE_SYS_DE_TOP); 387 DUMPCORE(HDMI_CORE_SYS_DE_CNTL); 388 DUMPCORE(HDMI_CORE_SYS_DE_CNTH); 389 DUMPCORE(HDMI_CORE_SYS_DE_LINL); 390 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); 391 DUMPCORE(HDMI_CORE_SYS_HRES_L); 392 DUMPCORE(HDMI_CORE_SYS_HRES_H); 393 DUMPCORE(HDMI_CORE_SYS_VRES_L); 394 DUMPCORE(HDMI_CORE_SYS_VRES_H); 395 DUMPCORE(HDMI_CORE_SYS_IADJUST); 396 DUMPCORE(HDMI_CORE_SYS_POLDETECT); 397 DUMPCORE(HDMI_CORE_SYS_HWIDTH1); 398 DUMPCORE(HDMI_CORE_SYS_HWIDTH2); 399 DUMPCORE(HDMI_CORE_SYS_VWIDTH); 400 DUMPCORE(HDMI_CORE_SYS_VID_CTRL); 401 DUMPCORE(HDMI_CORE_SYS_VID_ACEN); 402 DUMPCORE(HDMI_CORE_SYS_VID_MODE); 403 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 404 DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); 405 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 406 DUMPCORE(HDMI_CORE_SYS_DC_HEADER); 407 DUMPCORE(HDMI_CORE_SYS_VID_DITHER); 408 DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); 409 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); 410 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); 411 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); 412 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); 413 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); 414 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); 415 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); 416 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); 417 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); 418 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); 419 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); 420 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); 421 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); 422 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); 423 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); 424 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); 425 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); 426 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); 427 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); 428 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); 429 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); 430 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); 431 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); 432 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); 433 DUMPCORE(HDMI_CORE_SYS_INTR_STATE); 434 DUMPCORE(HDMI_CORE_SYS_INTR1); 435 DUMPCORE(HDMI_CORE_SYS_INTR2); 436 DUMPCORE(HDMI_CORE_SYS_INTR3); 437 DUMPCORE(HDMI_CORE_SYS_INTR4); 438 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); 439 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); 440 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); 441 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); 442 DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); 443 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); 444 445 DUMPCORE(HDMI_CORE_DDC_ADDR); 446 DUMPCORE(HDMI_CORE_DDC_SEGM); 447 DUMPCORE(HDMI_CORE_DDC_OFFSET); 448 DUMPCORE(HDMI_CORE_DDC_COUNT1); 449 DUMPCORE(HDMI_CORE_DDC_COUNT2); 450 DUMPCORE(HDMI_CORE_DDC_STATUS); 451 DUMPCORE(HDMI_CORE_DDC_CMD); 452 DUMPCORE(HDMI_CORE_DDC_DATA); 453 454 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); 455 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); 456 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1); 457 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2); 458 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3); 459 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1); 460 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2); 461 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3); 462 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1); 463 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2); 464 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3); 465 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE); 466 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL); 467 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS); 468 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S); 469 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH); 470 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP); 471 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL); 472 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0); 473 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1); 474 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2); 475 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4); 476 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5); 477 DUMPCOREAV(HDMI_CORE_AV_ASRC); 478 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN); 479 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); 480 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT); 481 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1); 482 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2); 483 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3); 484 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL); 485 DUMPCOREAV(HDMI_CORE_AV_DPD); 486 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); 487 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); 488 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); 489 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); 490 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); 491 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); 492 493 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) 494 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); 495 496 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); 497 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); 498 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); 499 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); 500 501 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) 502 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); 503 504 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); 505 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); 506 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); 507 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); 508 509 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) 510 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); 511 512 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); 513 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); 514 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); 515 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); 516 517 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) 518 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); 519 520 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) 521 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); 522 523 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); 524 525 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) 526 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); 527 528 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); 529} 530 531static void hdmi_core_audio_config(struct hdmi_core_data *core, 532 struct hdmi_core_audio_config *cfg) 533{ 534 u32 r; 535 void __iomem *av_base = hdmi_av_base(core); 536 537 /* 538 * Parameters for generation of Audio Clock Recovery packets 539 */ 540 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); 541 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); 542 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); 543 544 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { 545 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); 546 REG_FLD_MOD(av_base, 547 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); 548 REG_FLD_MOD(av_base, 549 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); 550 } else { 551 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, 552 cfg->aud_par_busclk, 7, 0); 553 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, 554 (cfg->aud_par_busclk >> 8), 7, 0); 555 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, 556 (cfg->aud_par_busclk >> 16), 7, 0); 557 } 558 559 /* Set ACR clock divisor */ 560 REG_FLD_MOD(av_base, 561 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); 562 563 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); 564 /* 565 * Use TMDS clock for ACR packets. For devices that use 566 * the MCLK, this is the first part of the MCLK initialization. 567 */ 568 r = FLD_MOD(r, 0, 2, 2); 569 570 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); 571 r = FLD_MOD(r, cfg->cts_mode, 0, 0); 572 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); 573 574 /* For devices using MCLK, this completes its initialization. */ 575 if (cfg->use_mclk) 576 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); 577 578 /* Override of SPDIF sample frequency with value in I2S_CHST4 */ 579 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, 580 cfg->fs_override, 1, 1); 581 582 /* 583 * Set IEC-60958-3 channel status word. It is passed to the IP 584 * just as it is received. The user of the driver is responsible 585 * for its contents. 586 */ 587 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0, 588 cfg->iec60958_cfg->status[0]); 589 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1, 590 cfg->iec60958_cfg->status[1]); 591 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2, 592 cfg->iec60958_cfg->status[2]); 593 /* yes, this is correct: status[3] goes to CHST4 register */ 594 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4, 595 cfg->iec60958_cfg->status[3]); 596 /* yes, this is correct: status[4] goes to CHST5 register */ 597 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, 598 cfg->iec60958_cfg->status[4]); 599 600 /* set I2S parameters */ 601 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); 602 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); 603 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); 604 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); 605 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); 606 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); 607 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); 608 609 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, 610 cfg->i2s_cfg.in_length_bits, 3, 0); 611 612 /* Audio channels and mode parameters */ 613 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); 614 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); 615 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); 616 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); 617 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); 618 r = FLD_MOD(r, cfg->en_spdif, 1, 1); 619 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); 620 621 /* Audio channel mappings */ 622 /* TODO: Make channel mapping dynamic. For now, map channels 623 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as 624 * HDMI speaker order is different. See CEA-861 Section 6.6.2. 625 */ 626 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78); 627 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); 628} 629 630static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, 631 struct snd_cea_861_aud_if *info_aud) 632{ 633 u8 sum = 0, checksum = 0; 634 void __iomem *av_base = hdmi_av_base(core); 635 636 /* 637 * Set audio info frame type, version and length as 638 * described in HDMI 1.4a Section 8.2.2 specification. 639 * Checksum calculation is defined in Section 5.3.5. 640 */ 641 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); 642 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); 643 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); 644 sum += 0x84 + 0x001 + 0x00a; 645 646 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), 647 info_aud->db1_ct_cc); 648 sum += info_aud->db1_ct_cc; 649 650 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), 651 info_aud->db2_sf_ss); 652 sum += info_aud->db2_sf_ss; 653 654 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); 655 sum += info_aud->db3; 656 657 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); 658 sum += info_aud->db4_ca; 659 660 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), 661 info_aud->db5_dminh_lsv); 662 sum += info_aud->db5_dminh_lsv; 663 664 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); 665 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); 666 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); 667 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); 668 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); 669 670 checksum = 0x100 - sum; 671 hdmi_write_reg(av_base, 672 HDMI_CORE_AV_AUDIO_CHSUM, checksum); 673 674 /* 675 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing 676 * is available. 677 */ 678} 679 680int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 681 struct omap_dss_audio *audio, u32 pclk) 682{ 683 struct hdmi_audio_format audio_format; 684 struct hdmi_audio_dma audio_dma; 685 struct hdmi_core_audio_config acore; 686 int err, n, cts, channel_count; 687 unsigned int fs_nr; 688 bool word_length_16b = false; 689 690 if (!audio || !audio->iec || !audio->cea || !core) 691 return -EINVAL; 692 693 acore.iec60958_cfg = audio->iec; 694 /* 695 * In the IEC-60958 status word, check if the audio sample word length 696 * is 16-bit as several optimizations can be performed in such case. 697 */ 698 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)) 699 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16) 700 word_length_16b = true; 701 702 /* I2S configuration. See Phillips' specification */ 703 if (word_length_16b) 704 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; 705 else 706 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 707 /* 708 * The I2S input word length is twice the lenght given in the IEC-60958 709 * status word. If the word size is greater than 710 * 20 bits, increment by one. 711 */ 712 acore.i2s_cfg.in_length_bits = audio->iec->status[4] 713 & IEC958_AES4_CON_WORDLEN; 714 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) 715 acore.i2s_cfg.in_length_bits++; 716 acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; 717 acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; 718 acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; 719 acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; 720 721 /* convert sample frequency to a number */ 722 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { 723 case IEC958_AES3_CON_FS_32000: 724 fs_nr = 32000; 725 break; 726 case IEC958_AES3_CON_FS_44100: 727 fs_nr = 44100; 728 break; 729 case IEC958_AES3_CON_FS_48000: 730 fs_nr = 48000; 731 break; 732 case IEC958_AES3_CON_FS_88200: 733 fs_nr = 88200; 734 break; 735 case IEC958_AES3_CON_FS_96000: 736 fs_nr = 96000; 737 break; 738 case IEC958_AES3_CON_FS_176400: 739 fs_nr = 176400; 740 break; 741 case IEC958_AES3_CON_FS_192000: 742 fs_nr = 192000; 743 break; 744 default: 745 return -EINVAL; 746 } 747 748 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); 749 750 /* Audio clock regeneration settings */ 751 acore.n = n; 752 acore.cts = cts; 753 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { 754 acore.aud_par_busclk = 0; 755 acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; 756 acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK); 757 } else { 758 acore.aud_par_busclk = (((128 * 31) - 1) << 8); 759 acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; 760 acore.use_mclk = true; 761 } 762 763 if (acore.use_mclk) 764 acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; 765 766 /* Audio channels settings */ 767 channel_count = (audio->cea->db1_ct_cc & 768 CEA861_AUDIO_INFOFRAME_DB1CC) + 1; 769 770 switch (channel_count) { 771 case 2: 772 audio_format.active_chnnls_msk = 0x03; 773 break; 774 case 3: 775 audio_format.active_chnnls_msk = 0x07; 776 break; 777 case 4: 778 audio_format.active_chnnls_msk = 0x0f; 779 break; 780 case 5: 781 audio_format.active_chnnls_msk = 0x1f; 782 break; 783 case 6: 784 audio_format.active_chnnls_msk = 0x3f; 785 break; 786 case 7: 787 audio_format.active_chnnls_msk = 0x7f; 788 break; 789 case 8: 790 audio_format.active_chnnls_msk = 0xff; 791 break; 792 default: 793 return -EINVAL; 794 } 795 796 /* 797 * the HDMI IP needs to enable four stereo channels when transmitting 798 * more than 2 audio channels 799 */ 800 if (channel_count == 2) { 801 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; 802 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; 803 acore.layout = HDMI_AUDIO_LAYOUT_2CH; 804 } else { 805 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; 806 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | 807 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | 808 HDMI_AUDIO_I2S_SD3_EN; 809 acore.layout = HDMI_AUDIO_LAYOUT_8CH; 810 } 811 812 acore.en_spdif = false; 813 /* use sample frequency from channel status word */ 814 acore.fs_override = true; 815 /* enable ACR packets */ 816 acore.en_acr_pkt = true; 817 /* disable direct streaming digital audio */ 818 acore.en_dsd_audio = false; 819 /* use parallel audio interface */ 820 acore.en_parallel_aud_input = true; 821 822 /* DMA settings */ 823 if (word_length_16b) 824 audio_dma.transfer_size = 0x10; 825 else 826 audio_dma.transfer_size = 0x20; 827 audio_dma.block_size = 0xC0; 828 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 829 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 830 831 /* audio FIFO format settings */ 832 if (word_length_16b) { 833 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; 834 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; 835 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; 836 } else { 837 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; 838 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; 839 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 840 } 841 audio_format.type = HDMI_AUDIO_TYPE_LPCM; 842 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 843 /* disable start/stop signals of IEC 60958 blocks */ 844 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; 845 846 /* configure DMA and audio FIFO format*/ 847 hdmi_wp_audio_config_dma(wp, &audio_dma); 848 hdmi_wp_audio_config_format(wp, &audio_format); 849 850 /* configure the core*/ 851 hdmi_core_audio_config(core, &acore); 852 853 /* configure CEA 861 audio infoframe*/ 854 hdmi_core_audio_infoframe_cfg(core, audio->cea); 855 856 return 0; 857} 858 859int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 860{ 861 REG_FLD_MOD(hdmi_av_base(core), 862 HDMI_CORE_AV_AUD_MODE, true, 0, 0); 863 864 hdmi_wp_audio_core_req_enable(wp, true); 865 866 return 0; 867} 868 869void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 870{ 871 REG_FLD_MOD(hdmi_av_base(core), 872 HDMI_CORE_AV_AUD_MODE, false, 0, 0); 873 874 hdmi_wp_audio_core_req_enable(wp, false); 875} 876 877int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) 878{ 879 struct resource *res; 880 881 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 882 if (!res) { 883 DSSERR("can't get CORE mem resource\n"); 884 return -EINVAL; 885 } 886 887 core->base = devm_ioremap_resource(&pdev->dev, res); 888 if (IS_ERR(core->base)) { 889 DSSERR("can't ioremap CORE\n"); 890 return PTR_ERR(core->base); 891 } 892 893 return 0; 894} 895