1/* 2 * HDMI driver definition for TI OMAP5 processors. 3 * 4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19#ifndef _HDMI5_CORE_H_ 20#define _HDMI5_CORE_H_ 21 22#include "hdmi.h" 23 24/* HDMI IP Core System */ 25 26/* HDMI Identification */ 27#define HDMI_CORE_DESIGN_ID 0x00000 28#define HDMI_CORE_REVISION_ID 0x00004 29#define HDMI_CORE_PRODUCT_ID0 0x00008 30#define HDMI_CORE_PRODUCT_ID1 0x0000C 31#define HDMI_CORE_CONFIG0_ID 0x00010 32#define HDMI_CORE_CONFIG1_ID 0x00014 33#define HDMI_CORE_CONFIG2_ID 0x00018 34#define HDMI_CORE_CONFIG3_ID 0x0001C 35 36/* HDMI Interrupt */ 37#define HDMI_CORE_IH_FC_STAT0 0x00400 38#define HDMI_CORE_IH_FC_STAT1 0x00404 39#define HDMI_CORE_IH_FC_STAT2 0x00408 40#define HDMI_CORE_IH_AS_STAT0 0x0040C 41#define HDMI_CORE_IH_PHY_STAT0 0x00410 42#define HDMI_CORE_IH_I2CM_STAT0 0x00414 43#define HDMI_CORE_IH_CEC_STAT0 0x00418 44#define HDMI_CORE_IH_VP_STAT0 0x0041C 45#define HDMI_CORE_IH_I2CMPHY_STAT0 0x00420 46#define HDMI_CORE_IH_MUTE 0x007FC 47 48/* HDMI Video Sampler */ 49#define HDMI_CORE_TX_INVID0 0x00800 50#define HDMI_CORE_TX_INSTUFFING 0x00804 51#define HDMI_CORE_TX_RGYDATA0 0x00808 52#define HDMI_CORE_TX_RGYDATA1 0x0080C 53#define HDMI_CORE_TX_RCRDATA0 0x00810 54#define HDMI_CORE_TX_RCRDATA1 0x00814 55#define HDMI_CORE_TX_BCBDATA0 0x00818 56#define HDMI_CORE_TX_BCBDATA1 0x0081C 57 58/* HDMI Video Packetizer */ 59#define HDMI_CORE_VP_STATUS 0x02000 60#define HDMI_CORE_VP_PR_CD 0x02004 61#define HDMI_CORE_VP_STUFF 0x02008 62#define HDMI_CORE_VP_REMAP 0x0200C 63#define HDMI_CORE_VP_CONF 0x02010 64#define HDMI_CORE_VP_STAT 0x02014 65#define HDMI_CORE_VP_INT 0x02018 66#define HDMI_CORE_VP_MASK 0x0201C 67#define HDMI_CORE_VP_POL 0x02020 68 69/* Frame Composer */ 70#define HDMI_CORE_FC_INVIDCONF 0x04000 71#define HDMI_CORE_FC_INHACTIV0 0x04004 72#define HDMI_CORE_FC_INHACTIV1 0x04008 73#define HDMI_CORE_FC_INHBLANK0 0x0400C 74#define HDMI_CORE_FC_INHBLANK1 0x04010 75#define HDMI_CORE_FC_INVACTIV0 0x04014 76#define HDMI_CORE_FC_INVACTIV1 0x04018 77#define HDMI_CORE_FC_INVBLANK 0x0401C 78#define HDMI_CORE_FC_HSYNCINDELAY0 0x04020 79#define HDMI_CORE_FC_HSYNCINDELAY1 0x04024 80#define HDMI_CORE_FC_HSYNCINWIDTH0 0x04028 81#define HDMI_CORE_FC_HSYNCINWIDTH1 0x0402C 82#define HDMI_CORE_FC_VSYNCINDELAY 0x04030 83#define HDMI_CORE_FC_VSYNCINWIDTH 0x04034 84#define HDMI_CORE_FC_INFREQ0 0x04038 85#define HDMI_CORE_FC_INFREQ1 0x0403C 86#define HDMI_CORE_FC_INFREQ2 0x04040 87#define HDMI_CORE_FC_CTRLDUR 0x04044 88#define HDMI_CORE_FC_EXCTRLDUR 0x04048 89#define HDMI_CORE_FC_EXCTRLSPAC 0x0404C 90#define HDMI_CORE_FC_CH0PREAM 0x04050 91#define HDMI_CORE_FC_CH1PREAM 0x04054 92#define HDMI_CORE_FC_CH2PREAM 0x04058 93#define HDMI_CORE_FC_AVICONF3 0x0405C 94#define HDMI_CORE_FC_GCP 0x04060 95#define HDMI_CORE_FC_AVICONF0 0x04064 96#define HDMI_CORE_FC_AVICONF1 0x04068 97#define HDMI_CORE_FC_AVICONF2 0x0406C 98#define HDMI_CORE_FC_AVIVID 0x04070 99#define HDMI_CORE_FC_AVIETB0 0x04074 100#define HDMI_CORE_FC_AVIETB1 0x04078 101#define HDMI_CORE_FC_AVISBB0 0x0407C 102#define HDMI_CORE_FC_AVISBB1 0x04080 103#define HDMI_CORE_FC_AVIELB0 0x04084 104#define HDMI_CORE_FC_AVIELB1 0x04088 105#define HDMI_CORE_FC_AVISRB0 0x0408C 106#define HDMI_CORE_FC_AVISRB1 0x04090 107#define HDMI_CORE_FC_AUDICONF0 0x04094 108#define HDMI_CORE_FC_AUDICONF1 0x04098 109#define HDMI_CORE_FC_AUDICONF2 0x0409C 110#define HDMI_CORE_FC_AUDICONF3 0x040A0 111#define HDMI_CORE_FC_VSDIEEEID0 0x040A4 112#define HDMI_CORE_FC_VSDSIZE 0x040A8 113#define HDMI_CORE_FC_VSDIEEEID1 0x040C0 114#define HDMI_CORE_FC_VSDIEEEID2 0x040C4 115#define HDMI_CORE_FC_VSDPAYLOAD(n) (n * 4 + 0x040C8) 116#define HDMI_CORE_FC_SPDVENDORNAME(n) (n * 4 + 0x04128) 117#define HDMI_CORE_FC_SPDPRODUCTNAME(n) (n * 4 + 0x04148) 118#define HDMI_CORE_FC_SPDDEVICEINF 0x04188 119#define HDMI_CORE_FC_AUDSCONF 0x0418C 120#define HDMI_CORE_FC_AUDSSTAT 0x04190 121#define HDMI_CORE_FC_AUDSV 0x04194 122#define HDMI_CORE_FC_AUDSU 0x04198 123#define HDMI_CORE_FC_AUDSCHNLS(n) (n * 4 + 0x0419C) 124#define HDMI_CORE_FC_CTRLQHIGH 0x041CC 125#define HDMI_CORE_FC_CTRLQLOW 0x041D0 126#define HDMI_CORE_FC_ACP0 0x041D4 127#define HDMI_CORE_FC_ACP(n) ((16-n) * 4 + 0x04208) 128#define HDMI_CORE_FC_ISCR1_0 0x04248 129#define HDMI_CORE_FC_ISCR1(n) ((16-n) * 4 + 0x0424C) 130#define HDMI_CORE_FC_ISCR2(n) ((15-n) * 4 + 0x0428C) 131#define HDMI_CORE_FC_DATAUTO0 0x042CC 132#define HDMI_CORE_FC_DATAUTO1 0x042D0 133#define HDMI_CORE_FC_DATAUTO2 0x042D4 134#define HDMI_CORE_FC_DATMAN 0x042D8 135#define HDMI_CORE_FC_DATAUTO3 0x042DC 136#define HDMI_CORE_FC_RDRB(n) (n * 4 + 0x042E0) 137#define HDMI_CORE_FC_STAT0 0x04340 138#define HDMI_CORE_FC_INT0 0x04344 139#define HDMI_CORE_FC_MASK0 0x04348 140#define HDMI_CORE_FC_POL0 0x0434C 141#define HDMI_CORE_FC_STAT1 0x04350 142#define HDMI_CORE_FC_INT1 0x04354 143#define HDMI_CORE_FC_MASK1 0x04358 144#define HDMI_CORE_FC_POL1 0x0435C 145#define HDMI_CORE_FC_STAT2 0x04360 146#define HDMI_CORE_FC_INT2 0x04364 147#define HDMI_CORE_FC_MASK2 0x04368 148#define HDMI_CORE_FC_POL2 0x0436C 149#define HDMI_CORE_FC_PRCONF 0x04380 150#define HDMI_CORE_FC_GMD_STAT 0x04400 151#define HDMI_CORE_FC_GMD_EN 0x04404 152#define HDMI_CORE_FC_GMD_UP 0x04408 153#define HDMI_CORE_FC_GMD_CONF 0x0440C 154#define HDMI_CORE_FC_GMD_HB 0x04410 155#define HDMI_CORE_FC_GMD_PB(n) (n * 4 + 0x04414) 156#define HDMI_CORE_FC_DBGFORCE 0x04800 157#define HDMI_CORE_FC_DBGAUD0CH0 0x04804 158#define HDMI_CORE_FC_DBGAUD1CH0 0x04808 159#define HDMI_CORE_FC_DBGAUD2CH0 0x0480C 160#define HDMI_CORE_FC_DBGAUD0CH1 0x04810 161#define HDMI_CORE_FC_DBGAUD1CH1 0x04814 162#define HDMI_CORE_FC_DBGAUD2CH1 0x04818 163#define HDMI_CORE_FC_DBGAUD0CH2 0x0481C 164#define HDMI_CORE_FC_DBGAUD1CH2 0x04820 165#define HDMI_CORE_FC_DBGAUD2CH2 0x04824 166#define HDMI_CORE_FC_DBGAUD0CH3 0x04828 167#define HDMI_CORE_FC_DBGAUD1CH3 0x0482C 168#define HDMI_CORE_FC_DBGAUD2CH3 0x04830 169#define HDMI_CORE_FC_DBGAUD0CH4 0x04834 170#define HDMI_CORE_FC_DBGAUD1CH4 0x04838 171#define HDMI_CORE_FC_DBGAUD2CH4 0x0483C 172#define HDMI_CORE_FC_DBGAUD0CH5 0x04840 173#define HDMI_CORE_FC_DBGAUD1CH5 0x04844 174#define HDMI_CORE_FC_DBGAUD2CH5 0x04848 175#define HDMI_CORE_FC_DBGAUD0CH6 0x0484C 176#define HDMI_CORE_FC_DBGAUD1CH6 0x04850 177#define HDMI_CORE_FC_DBGAUD2CH6 0x04854 178#define HDMI_CORE_FC_DBGAUD0CH7 0x04858 179#define HDMI_CORE_FC_DBGAUD1CH7 0x0485C 180#define HDMI_CORE_FC_DBGAUD2CH7 0x04860 181#define HDMI_CORE_FC_DBGTMDS0 0x04864 182#define HDMI_CORE_FC_DBGTMDS1 0x04868 183#define HDMI_CORE_FC_DBGTMDS2 0x0486C 184#define HDMI_CORE_PHY_MASK0 0x0C018 185#define HDMI_CORE_PHY_I2CM_INT_ADDR 0x0C09C 186#define HDMI_CORE_PHY_I2CM_CTLINT_ADDR 0x0C0A0 187 188/* HDMI Audio */ 189#define HDMI_CORE_AUD_CONF0 0x0C400 190#define HDMI_CORE_AUD_CONF1 0x0C404 191#define HDMI_CORE_AUD_INT 0x0C408 192#define HDMI_CORE_AUD_N1 0x0C800 193#define HDMI_CORE_AUD_N2 0x0C804 194#define HDMI_CORE_AUD_N3 0x0C808 195#define HDMI_CORE_AUD_CTS1 0x0C80C 196#define HDMI_CORE_AUD_CTS2 0x0C810 197#define HDMI_CORE_AUD_CTS3 0x0C814 198#define HDMI_CORE_AUD_INCLKFS 0x0C818 199#define HDMI_CORE_AUD_CC08 0x0CC08 200#define HDMI_CORE_AUD_GP_CONF0 0x0D400 201#define HDMI_CORE_AUD_GP_CONF1 0x0D404 202#define HDMI_CORE_AUD_GP_CONF2 0x0D408 203#define HDMI_CORE_AUD_D010 0x0D010 204#define HDMI_CORE_AUD_GP_STAT 0x0D40C 205#define HDMI_CORE_AUD_GP_INT 0x0D410 206#define HDMI_CORE_AUD_GP_POL 0x0D414 207#define HDMI_CORE_AUD_GP_MASK 0x0D418 208 209/* HDMI Main Controller */ 210#define HDMI_CORE_MC_CLKDIS 0x10004 211#define HDMI_CORE_MC_SWRSTZREQ 0x10008 212#define HDMI_CORE_MC_FLOWCTRL 0x10010 213#define HDMI_CORE_MC_PHYRSTZ 0x10014 214#define HDMI_CORE_MC_LOCKONCLOCK 0x10018 215 216/* HDMI COLOR SPACE CONVERTER */ 217#define HDMI_CORE_CSC_CFG 0x10400 218#define HDMI_CORE_CSC_SCALE 0x10404 219#define HDMI_CORE_CSC_COEF_A1_MSB 0x10408 220#define HDMI_CORE_CSC_COEF_A1_LSB 0x1040C 221#define HDMI_CORE_CSC_COEF_A2_MSB 0x10410 222#define HDMI_CORE_CSC_COEF_A2_LSB 0x10414 223#define HDMI_CORE_CSC_COEF_A3_MSB 0x10418 224#define HDMI_CORE_CSC_COEF_A3_LSB 0x1041C 225#define HDMI_CORE_CSC_COEF_A4_MSB 0x10420 226#define HDMI_CORE_CSC_COEF_A4_LSB 0x10424 227#define HDMI_CORE_CSC_COEF_B1_MSB 0x10428 228#define HDMI_CORE_CSC_COEF_B1_LSB 0x1042C 229#define HDMI_CORE_CSC_COEF_B2_MSB 0x10430 230#define HDMI_CORE_CSC_COEF_B2_LSB 0x10434 231#define HDMI_CORE_CSC_COEF_B3_MSB 0x10438 232#define HDMI_CORE_CSC_COEF_B3_LSB 0x1043C 233#define HDMI_CORE_CSC_COEF_B4_MSB 0x10440 234#define HDMI_CORE_CSC_COEF_B4_LSB 0x10444 235#define HDMI_CORE_CSC_COEF_C1_MSB 0x10448 236#define HDMI_CORE_CSC_COEF_C1_LSB 0x1044C 237#define HDMI_CORE_CSC_COEF_C2_MSB 0x10450 238#define HDMI_CORE_CSC_COEF_C2_LSB 0x10454 239#define HDMI_CORE_CSC_COEF_C3_MSB 0x10458 240#define HDMI_CORE_CSC_COEF_C3_LSB 0x1045C 241#define HDMI_CORE_CSC_COEF_C4_MSB 0x10460 242#define HDMI_CORE_CSC_COEF_C4_LSB 0x10464 243 244/* HDMI HDCP */ 245#define HDMI_CORE_HDCP_MASK 0x14020 246 247/* HDMI CEC */ 248#define HDMI_CORE_CEC_MASK 0x17408 249 250/* HDMI I2C Master */ 251#define HDMI_CORE_I2CM_SLAVE 0x157C8 252#define HDMI_CORE_I2CM_ADDRESS 0x157CC 253#define HDMI_CORE_I2CM_DATAO 0x157D0 254#define HDMI_CORE_I2CM_DATAI 0X157D4 255#define HDMI_CORE_I2CM_OPERATION 0x157D8 256#define HDMI_CORE_I2CM_INT 0x157DC 257#define HDMI_CORE_I2CM_CTLINT 0x157E0 258#define HDMI_CORE_I2CM_DIV 0x157E4 259#define HDMI_CORE_I2CM_SEGADDR 0x157E8 260#define HDMI_CORE_I2CM_SOFTRSTZ 0x157EC 261#define HDMI_CORE_I2CM_SEGPTR 0x157F0 262#define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR 0x157F4 263#define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR 0x157F8 264#define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR 0x157FC 265#define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR 0x15800 266#define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR 0x15804 267#define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR 0x15808 268#define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR 0x1580C 269#define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR 0x15810 270#define HDMI_CORE_I2CM_SDA_HOLD_ADDR 0x15814 271 272enum hdmi_core_packet_mode { 273 HDMI_PACKETMODERESERVEDVALUE = 0, 274 HDMI_PACKETMODE24BITPERPIXEL = 4, 275 HDMI_PACKETMODE30BITPERPIXEL = 5, 276 HDMI_PACKETMODE36BITPERPIXEL = 6, 277 HDMI_PACKETMODE48BITPERPIXEL = 7, 278}; 279 280struct hdmi_core_vid_config { 281 struct hdmi_config v_fc_config; 282 enum hdmi_core_packet_mode packet_mode; 283 int data_enable_pol; 284 int vblank_osc; 285 int hblank; 286 int vblank; 287}; 288 289struct csc_table { 290 u16 a1, a2, a3, a4; 291 u16 b1, b2, b3, b4; 292 u16 c1, c2, c3, c4; 293}; 294 295int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len); 296void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s); 297int hdmi5_core_handle_irqs(struct hdmi_core_data *core); 298void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 299 struct hdmi_config *cfg); 300int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core); 301 302int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 303 struct omap_dss_audio *audio, u32 pclk); 304#endif 305