1/*
2 * linux/drivers/video/sa1100fb.h
3 *    -- StrongARM 1100 LCD Controller Frame Buffer Device
4 *
5 *  Copyright (C) 1999 Eric A. Thomas
6 *   Based on acornfb.c Copyright (C) Russell King.
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License.  See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#define LCCR0           0x0000          /* LCD Control Reg. 0 */
14#define LCSR            0x0004          /* LCD Status Reg. */
15#define DBAR1           0x0010          /* LCD DMA Base Address Reg. channel 1 */
16#define DCAR1           0x0014          /* LCD DMA Current Address Reg. channel 1 */
17#define DBAR2           0x0018          /* LCD DMA Base Address Reg.  channel 2 */
18#define DCAR2           0x001C          /* LCD DMA Current Address Reg. channel 2 */
19#define LCCR1           0x0020          /* LCD Control Reg. 1 */
20#define LCCR2           0x0024          /* LCD Control Reg. 2 */
21#define LCCR3           0x0028          /* LCD Control Reg. 3 */
22
23/* Shadows for LCD controller registers */
24struct sa1100fb_lcd_reg {
25	unsigned long lccr0;
26	unsigned long lccr1;
27	unsigned long lccr2;
28	unsigned long lccr3;
29};
30
31struct sa1100fb_info {
32	struct fb_info		fb;
33	struct device		*dev;
34	const struct sa1100fb_rgb *rgb[NR_RGB];
35	void __iomem		*base;
36
37	/*
38	 * These are the addresses we mapped
39	 * the framebuffer memory region to.
40	 */
41	dma_addr_t		map_dma;
42	u_char *		map_cpu;
43	u_int			map_size;
44
45	u_char *		screen_cpu;
46	dma_addr_t		screen_dma;
47	u16 *			palette_cpu;
48	dma_addr_t		palette_dma;
49	u_int			palette_size;
50
51	dma_addr_t		dbar1;
52	dma_addr_t		dbar2;
53
54	u_int			reg_lccr0;
55	u_int			reg_lccr1;
56	u_int			reg_lccr2;
57	u_int			reg_lccr3;
58
59	volatile u_char		state;
60	volatile u_char		task_state;
61	struct mutex		ctrlr_lock;
62	wait_queue_head_t	ctrlr_wait;
63	struct work_struct	task;
64
65#ifdef CONFIG_CPU_FREQ
66	struct notifier_block	freq_transition;
67	struct notifier_block	freq_policy;
68#endif
69
70	const struct sa1100fb_mach_info *inf;
71	struct clk *clk;
72};
73
74#define TO_INF(ptr,member)	container_of(ptr,struct sa1100fb_info,member)
75
76#define SA1100_PALETTE_MODE_VAL(bpp)    (((bpp) & 0x018) << 9)
77
78/*
79 * These are the actions for set_ctrlr_state
80 */
81#define C_DISABLE		(0)
82#define C_ENABLE		(1)
83#define C_DISABLE_CLKCHANGE	(2)
84#define C_ENABLE_CLKCHANGE	(3)
85#define C_REENABLE		(4)
86#define C_DISABLE_PM		(5)
87#define C_ENABLE_PM		(6)
88#define C_STARTUP		(7)
89
90#define SA1100_NAME	"SA1100"
91
92/*
93 * Minimum X and Y resolutions
94 */
95#define MIN_XRES	64
96#define MIN_YRES	64
97
98