1/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARM_KVM_VGIC_H
20#define __ASM_ARM_KVM_VGIC_H
21
22#include <linux/kernel.h>
23#include <linux/kvm.h>
24#include <linux/irqreturn.h>
25#include <linux/spinlock.h>
26#include <linux/types.h>
27#include <kvm/iodev.h>
28
29#define VGIC_NR_IRQS_LEGACY	256
30#define VGIC_NR_SGIS		16
31#define VGIC_NR_PPIS		16
32#define VGIC_NR_PRIVATE_IRQS	(VGIC_NR_SGIS + VGIC_NR_PPIS)
33
34#define VGIC_V2_MAX_LRS		(1 << 6)
35#define VGIC_V3_MAX_LRS		16
36#define VGIC_MAX_IRQS		1024
37#define VGIC_V2_MAX_CPUS	8
38
39/* Sanity checks... */
40#if (KVM_MAX_VCPUS > 255)
41#error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now
42#endif
43
44#if (VGIC_NR_IRQS_LEGACY & 31)
45#error "VGIC_NR_IRQS must be a multiple of 32"
46#endif
47
48#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
49#error "VGIC_NR_IRQS must be <= 1024"
50#endif
51
52/*
53 * The GIC distributor registers describing interrupts have two parts:
54 * - 32 per-CPU interrupts (SGI + PPI)
55 * - a bunch of shared interrupts (SPI)
56 */
57struct vgic_bitmap {
58	/*
59	 * - One UL per VCPU for private interrupts (assumes UL is at
60	 *   least 32 bits)
61	 * - As many UL as necessary for shared interrupts.
62	 *
63	 * The private interrupts are accessed via the "private"
64	 * field, one UL per vcpu (the state for vcpu n is in
65	 * private[n]). The shared interrupts are accessed via the
66	 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
67	 */
68	unsigned long *private;
69	unsigned long *shared;
70};
71
72struct vgic_bytemap {
73	/*
74	 * - 8 u32 per VCPU for private interrupts
75	 * - As many u32 as necessary for shared interrupts.
76	 *
77	 * The private interrupts are accessed via the "private"
78	 * field, (the state for vcpu n is in private[n*8] to
79	 * private[n*8 + 7]). The shared interrupts are accessed via
80	 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
81	 * shared[(n-32)/4] word).
82	 */
83	u32 *private;
84	u32 *shared;
85};
86
87struct kvm_vcpu;
88
89enum vgic_type {
90	VGIC_V2,		/* Good ol' GICv2 */
91	VGIC_V3,		/* New fancy GICv3 */
92};
93
94#define LR_STATE_PENDING	(1 << 0)
95#define LR_STATE_ACTIVE		(1 << 1)
96#define LR_STATE_MASK		(3 << 0)
97#define LR_EOI_INT		(1 << 2)
98
99struct vgic_lr {
100	u16	irq;
101	u8	source;
102	u8	state;
103};
104
105struct vgic_vmcr {
106	u32	ctlr;
107	u32	abpr;
108	u32	bpr;
109	u32	pmr;
110};
111
112struct vgic_ops {
113	struct vgic_lr	(*get_lr)(const struct kvm_vcpu *, int);
114	void	(*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
115	void	(*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
116	u64	(*get_elrsr)(const struct kvm_vcpu *vcpu);
117	u64	(*get_eisr)(const struct kvm_vcpu *vcpu);
118	void	(*clear_eisr)(struct kvm_vcpu *vcpu);
119	u32	(*get_interrupt_status)(const struct kvm_vcpu *vcpu);
120	void	(*enable_underflow)(struct kvm_vcpu *vcpu);
121	void	(*disable_underflow)(struct kvm_vcpu *vcpu);
122	void	(*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
123	void	(*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
124	void	(*enable)(struct kvm_vcpu *vcpu);
125};
126
127struct vgic_params {
128	/* vgic type */
129	enum vgic_type	type;
130	/* Physical address of vgic virtual cpu interface */
131	phys_addr_t	vcpu_base;
132	/* Number of list registers */
133	u32		nr_lr;
134	/* Interrupt number */
135	unsigned int	maint_irq;
136	/* Virtual control interface base address */
137	void __iomem	*vctrl_base;
138	int		max_gic_vcpus;
139	/* Only needed for the legacy KVM_CREATE_IRQCHIP */
140	bool		can_emulate_gicv2;
141};
142
143struct vgic_vm_ops {
144	bool	(*queue_sgi)(struct kvm_vcpu *, int irq);
145	void	(*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
146	int	(*init_model)(struct kvm *);
147	int	(*map_resources)(struct kvm *, const struct vgic_params *);
148};
149
150struct vgic_io_device {
151	gpa_t addr;
152	int len;
153	const struct vgic_io_range *reg_ranges;
154	struct kvm_vcpu *redist_vcpu;
155	struct kvm_io_device dev;
156};
157
158struct vgic_dist {
159	spinlock_t		lock;
160	bool			in_kernel;
161	bool			ready;
162
163	/* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
164	u32			vgic_model;
165
166	int			nr_cpus;
167	int			nr_irqs;
168
169	/* Virtual control interface mapping */
170	void __iomem		*vctrl_base;
171
172	/* Distributor and vcpu interface mapping in the guest */
173	phys_addr_t		vgic_dist_base;
174	/* GICv2 and GICv3 use different mapped register blocks */
175	union {
176		phys_addr_t		vgic_cpu_base;
177		phys_addr_t		vgic_redist_base;
178	};
179
180	/* Distributor enabled */
181	u32			enabled;
182
183	/* Interrupt enabled (one bit per IRQ) */
184	struct vgic_bitmap	irq_enabled;
185
186	/* Level-triggered interrupt external input is asserted */
187	struct vgic_bitmap	irq_level;
188
189	/*
190	 * Interrupt state is pending on the distributor
191	 */
192	struct vgic_bitmap	irq_pending;
193
194	/*
195	 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
196	 * interrupts.  Essentially holds the state of the flip-flop in
197	 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
198	 * Once set, it is only cleared for level-triggered interrupts on
199	 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
200	 */
201	struct vgic_bitmap	irq_soft_pend;
202
203	/* Level-triggered interrupt queued on VCPU interface */
204	struct vgic_bitmap	irq_queued;
205
206	/* Interrupt was active when unqueue from VCPU interface */
207	struct vgic_bitmap	irq_active;
208
209	/* Interrupt priority. Not used yet. */
210	struct vgic_bytemap	irq_priority;
211
212	/* Level/edge triggered */
213	struct vgic_bitmap	irq_cfg;
214
215	/*
216	 * Source CPU per SGI and target CPU:
217	 *
218	 * Each byte represent a SGI observable on a VCPU, each bit of
219	 * this byte indicating if the corresponding VCPU has
220	 * generated this interrupt. This is a GICv2 feature only.
221	 *
222	 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
223	 * the SGIs observable on VCPUn.
224	 */
225	u8			*irq_sgi_sources;
226
227	/*
228	 * Target CPU for each SPI:
229	 *
230	 * Array of available SPI, each byte indicating the target
231	 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
232	 */
233	u8			*irq_spi_cpu;
234
235	/*
236	 * Reverse lookup of irq_spi_cpu for faster compute pending:
237	 *
238	 * Array of bitmaps, one per VCPU, describing if IRQn is
239	 * routed to a particular VCPU.
240	 */
241	struct vgic_bitmap	*irq_spi_target;
242
243	/* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
244	u32			*irq_spi_mpidr;
245
246	/* Bitmap indicating which CPU has something pending */
247	unsigned long		*irq_pending_on_cpu;
248
249	/* Bitmap indicating which CPU has active IRQs */
250	unsigned long		*irq_active_on_cpu;
251
252	struct vgic_vm_ops	vm_ops;
253	struct vgic_io_device	dist_iodev;
254	struct vgic_io_device	*redist_iodevs;
255};
256
257struct vgic_v2_cpu_if {
258	u32		vgic_hcr;
259	u32		vgic_vmcr;
260	u32		vgic_misr;	/* Saved only */
261	u64		vgic_eisr;	/* Saved only */
262	u64		vgic_elrsr;	/* Saved only */
263	u32		vgic_apr;
264	u32		vgic_lr[VGIC_V2_MAX_LRS];
265};
266
267struct vgic_v3_cpu_if {
268#ifdef CONFIG_ARM_GIC_V3
269	u32		vgic_hcr;
270	u32		vgic_vmcr;
271	u32		vgic_sre;	/* Restored only, change ignored */
272	u32		vgic_misr;	/* Saved only */
273	u32		vgic_eisr;	/* Saved only */
274	u32		vgic_elrsr;	/* Saved only */
275	u32		vgic_ap0r[4];
276	u32		vgic_ap1r[4];
277	u64		vgic_lr[VGIC_V3_MAX_LRS];
278#endif
279};
280
281struct vgic_cpu {
282	/* per IRQ to LR mapping */
283	u8		*vgic_irq_lr_map;
284
285	/* Pending/active/both interrupts on this VCPU */
286	DECLARE_BITMAP(	pending_percpu, VGIC_NR_PRIVATE_IRQS);
287	DECLARE_BITMAP(	active_percpu, VGIC_NR_PRIVATE_IRQS);
288	DECLARE_BITMAP(	pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
289
290	/* Pending/active/both shared interrupts, dynamically sized */
291	unsigned long	*pending_shared;
292	unsigned long   *active_shared;
293	unsigned long   *pend_act_shared;
294
295	/* Bitmap of used/free list registers */
296	DECLARE_BITMAP(	lr_used, VGIC_V2_MAX_LRS);
297
298	/* Number of list registers on this CPU */
299	int		nr_lr;
300
301	/* CPU vif control registers for world switch */
302	union {
303		struct vgic_v2_cpu_if	vgic_v2;
304		struct vgic_v3_cpu_if	vgic_v3;
305	};
306};
307
308#define LR_EMPTY	0xff
309
310#define INT_STATUS_EOI		(1 << 0)
311#define INT_STATUS_UNDERFLOW	(1 << 1)
312
313struct kvm;
314struct kvm_vcpu;
315
316int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
317int kvm_vgic_hyp_init(void);
318int kvm_vgic_map_resources(struct kvm *kvm);
319int kvm_vgic_get_max_vcpus(void);
320int kvm_vgic_create(struct kvm *kvm, u32 type);
321void kvm_vgic_destroy(struct kvm *kvm);
322void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
323void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
324void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
325int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
326			bool level);
327void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
328int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
329int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu);
330
331#define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
332#define vgic_initialized(k)	(!!((k)->arch.vgic.nr_cpus))
333#define vgic_ready(k)		((k)->arch.vgic.ready)
334
335int vgic_v2_probe(struct device_node *vgic_node,
336		  const struct vgic_ops **ops,
337		  const struct vgic_params **params);
338#ifdef CONFIG_ARM_GIC_V3
339int vgic_v3_probe(struct device_node *vgic_node,
340		  const struct vgic_ops **ops,
341		  const struct vgic_params **params);
342#else
343static inline int vgic_v3_probe(struct device_node *vgic_node,
344				const struct vgic_ops **ops,
345				const struct vgic_params **params)
346{
347	return -ENODEV;
348}
349#endif
350
351#endif
352